Address writing method and apparatus, and storage medium and chip

Abstract

An address writing method and apparatus, and a storage medium and a chip. The method comprises: determining data information of a received frame to be written and index information of said received frame (S202); writing the data information and the index information into an available cache area address to which target identifier information of an available cache area points, wherein the available cache area address is configured for storing the data information (S204); determining target index information data corresponding to the index information in a linked list bitmap, wherein the linked list bitmap comprises a plurality of pieces of sorted index information data, and each of the plurality of pieces of index information data comprises a valid identifier and an identifier information pointer (S206); and setting a valid identifier in the target index information data to a valid identifier value, and writing first identifier information in the target identifier information into an identifier information pointer in the target index information data (S208).

Description

Address writing method, device, storage medium and chip Technical Field

[0001] The present application relates to the field of communications, and in particular to an address writing method, device, storage medium, and chip. Background Art

[0002] In the reordering scenario during the design of Application-Specific Integrated Circuit (ASIC) chips, a linked list structure is generally used for reordering resource management. Since the sequence number (Num) of the received frame is a random value within a certain range, and the frame length of each frame is not fixed, the insertion operation of the intermediate node of the linked list is required when inserting the newly arrived received frame between two cached frames. When a general linked list structure implements the function of inserting the intermediate node of the linked list, it is necessary to read the data of each node one by one starting from the head of the linked list, and find two consecutive nodes, where the Num of the previous node is less than the Num of the received frame, and the Num of the next node is greater than the Num of the received frame. Then the pointer (next_pointer) pointing to the next node in the previous node points to the address assigned to the node, and the next_pointer of the node points to the address of the next node. The disadvantage of this method is that the efficiency of the linked list insertion operation is low, and it is not suitable for high-performance reordering scenarios. For the reordering of n received frames, its time complexity is O(n 2 ).

[0003] Regarding related technologies, the existing linked list structure reordering scheme has low efficiency in linked list insertion operations and is therefore not suitable for high-performance reordering scenarios. No effective solution has been proposed yet.

[0004] Therefore, it is necessary to improve the related technology to overcome the above-mentioned defects in the related technology.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide an address writing method, device, storage medium and chip to at least solve the problem that the linked list insertion operation of the existing linked list structure reordering scheme is inefficient and therefore not suitable for high-performance reordering scenarios.

[0007] According to an embodiment of the present application, an address writing method is provided, comprising: determining data information of a received frame to be written and index information of the received frame; writing the data information and the index information into an available cache address pointed to by target identification information of an available cache, wherein the available cache address is used to store the data information; determining target index information data corresponding to the index information in a linked list bitmap, wherein the linked list bitmap includes a plurality of index information data that have been sorted, wherein each index information data in the plurality of index information data includes: a valid identifier and an identifier information pointer; setting the valid identifier in the target index information data to a valid identifier value, and writing the first identifier information in the target identifier information into the identifier information pointer in the target index information data.

[0008] According to an embodiment of the present application, an address writing device is also provided, including: a first determination module, used to determine the data information of the received frame to be written and the index information of the received frame; a first writing module, used to write the data information and the index information into the available cache area address pointed to by the target identification information of the available cache area, wherein the available cache area address is used to store the data information; a second determination module, used to determine the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes a plurality of index information data that have been sorted, wherein each index information data in the plurality of index information data includes: a valid identifier and an identification information pointer; a second writing module, used to set the valid identifier in the target index information data to a valid identifier value, and write the first identification information in the target identification information into the identification information pointer in the target index information data.

[0009] According to an embodiment of the present application, a computer-readable storage medium is further provided, in which a computer program is stored. When the computer program is executed by a processor, the processor executes the address writing method according to the embodiment of the present application.

[0010] According to an embodiment of the present application, a chip is also provided, including the address writing device according to the embodiment of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The exemplary embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0012] FIG1 is a hardware structure block diagram of a chip for executing an address writing method according to an embodiment of the present application;

[0013] FIG2 is a flow chart of an address writing method according to an embodiment of the present application;

[0014] FIG3 is a schematic diagram of various structures according to an embodiment of the present application;

[0015] FIG4 is a flow chart of an embodiment of an address writing method according to an embodiment of the present application;

[0016] FIG5 is a schematic diagram of a specific embodiment of an address writing method according to an embodiment of the present application;

[0017] FIG6 is a schematic diagram of another specific embodiment of the address writing method according to an embodiment of the present application;

[0018] FIG7 is a schematic diagram of another specific embodiment of the address writing method according to an embodiment of the present application;

[0019] FIG8 is a structural block diagram of an address writing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0021] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0022] The method embodiments provided in the embodiments of the present application can be executed in a chip or a similar computing device to implement the reordering process of the received frames by the receiving-side hardware during the operation of the chip, wherein the chip may include but is not limited to: Wireless Fidelity (WIFI) chip, Ethernet switching chip, routing chip, etc.; the devices that can run the above chips include but are not limited to: WIFI devices, Ethernet switches, routers, general serial communication devices, etc., and the above chips are suitable for the field of network communications.

[0023] Taking running on a chip as an example, Figure 1 is a hardware structure block diagram of a chip for executing the address writing method according to an embodiment of the present application. As shown in Figure 1, the chip may include one or more (only one is shown in Figure 1) processors 102 (the processor 102 may include but is not limited to a microprocessor (Microprocessor Unit, abbreviated as MPU) or a programmable logic device (Programmable logic device, abbreviated as PLD)) and a memory 104 for storing data. In an exemplary embodiment, the above-mentioned chip may also include a transmission device 106 and an input and output device 108 for communication functions. It will be understood by those skilled in the art that the structure shown in Figure 1 is only for illustration and does not limit the structure of the above-mentioned chip. For example, the chip may also include more or fewer components than those shown in Figure 1, or have a different configuration with the same function as shown in Figure 1 or more functions than those shown in Figure 1.

[0024] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the chip corresponding to the address writing method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories can be connected to the chip via a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0025] The transmission device 106 is used to receive or send data via a network. Specific examples of the aforementioned network may include a wireless network provided by the chip's communications provider. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0026] FIG2 is a flow chart of an address writing method according to an embodiment of the present application. As shown in FIG2 , the steps of the method are applied to the above chip and include the following steps S202 to S208 .

[0027] In step S202, data information of a received frame to be written and index information of the received frame are determined.

[0028] In step S204, the data information and the index information are written into the available cache area address pointed to by the target identification information of the available cache area, wherein the available cache area address is used to store the data information.

[0029] In step S206, the target index information data corresponding to the index information in the linked list bitmap is determined, wherein the linked list bitmap includes a plurality of index information data that have been sorted, wherein each of the plurality of index information data includes: a valid identifier and an identifier information pointer.

[0030] In step S208, the valid flag in the target index information data is set to a valid flag value, and the first flag information in the target flag information is written into the flag information pointer in the target index information data.

[0031] The embodiment of the present application determines the data information of the received frame to be written and the index information of the received frame through the above steps; writes the data information and the index information into the available buffer address pointed to by the target identification information of the available buffer, wherein the available buffer address is used to store the data information; determines the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes a plurality of index information data that have been sorted, wherein each index information data in the plurality of index information data includes: a valid identifier and an identification information pointer; sets the valid identifier in the target index information data to a valid identifier value, and writes the first identification information in the target identification information into the identification information pointer in the target index information data. That is, when there is a received frame to be written, the data information of the received frame is written into the available buffer address, and the first identification information in the target identification information of the available buffer address is written into the index information data corresponding to the received frame in the plurality of index information data that have been sorted included in the linked list bitmap, thereby solving the technical problem that the linked list insertion operation of the existing linked list structure reordering scheme is low in efficiency and thus unsuitable for high-performance reordering scenarios.

[0032] In an exemplary embodiment, writing the data information and the index information into the available cache area address pointed to by the target identification information of the available cache area (i.e., step S204) specifically includes the following steps: determining the size relationship between the length value of the data information and the preset value; when the length value is less than the preset value, obtaining any identification information in the identification information queue as the target identification information, wherein the identification information queue records all identification information of the available cache area; writing the data information and the index information into the available cache area address pointed to by any identification information; when the length value is greater than or equal to the preset value, fragmenting the data information according to the length value to obtain multiple data information fragments; writing the multiple data information fragments and the index information into the available cache area address pointed to by the target identification information of the available cache area.

[0033] Optionally, the preset value can be selected as 2. In this case, when the length of the data information of the received frame to be written is less than 2, the data information can be written only to one available buffer address, and then any identification information is selected from the identification information queue as the target identification information, and the data information and the index information of the received frame to be written are written to the available buffer address pointed to by any identification information. "The identification information queue records all the identification information of the available buffer" means that the identification information queue records the identification information corresponding to the available buffer, and the available buffer corresponding to the available buffer address to which the data information and other data have been written can be understood as no longer available (in the absence of other operations: such as data information clearing operations, etc.), and the identification information queue does not include the identification information corresponding to the available buffer to which the data information has been written.

[0034] When the length of the data information is greater than or equal to 2, the data information is fragmented according to the actual length of the data information (i.e., the length value). For example, if the length value of the data information is 5, the data information is fragmented into 5 data information fragments. If the length of the data information is 8, the data information is fragmented into 8 data information fragments. The multiple data information fragments and index information obtained according to the length value are written to the available buffer area address pointed to by the target identification information obtained from the identification information queue.

[0035] It should be noted that in the embodiment of the present application, the preset value can be 2, but it is not used to limit the present application, that is, the preset value can be 3, 5, 6, etc. The preset value can be determined according to the memory and processing power of the device used to execute the address writing method in the embodiment of the present application. The preset value selection of 2 is only used to ensure that when the data information is written to the available cache address in fragments, the first written data information fragment has at least one identification information corresponding to the available cache address to which the next data information fragment may be written. It can be further clarified that if the preset value is selected as 3, then the second written data information fragment can be written to the available cache address. There is identification information corresponding to the available cache address to which the third written data information fragment will be written.

[0036] In an exemplary embodiment, writing multiple data information fragments and the index information into the available cache area address pointed to by the target identification information of the available cache area includes: for each data information fragment among the multiple data information fragments, determining the fragment number corresponding to the data information fragment according to the fragmentation order of the data information fragment among the multiple data information fragments; writing the data information fragment, the fragment number, and the index information into the available cache area address pointed to by the target identification information of the available cache area.

[0037] It is understandable that, in the process of fragmenting the data information, each of the multiple data information fragments has a corresponding fragment number, and the fragment number of each data information fragment is related to the order in which each data information fragment is fragmented. For example, the fragment number corresponding to the first data information fragment obtained in the fragmentation process is 1, the fragment number of the second data information fragment obtained is 2, and so on. It should be noted that the fragmentation of the data information is performed in order from beginning to end. The number of the data information is a character in a certain order, which can be Arabic numerals: such as 1, 2, 3, ..., or English letters: such as A, B, C, D ..., or a combination of numbers and letters, etc., and the embodiments of the present application do not limit this. Furthermore, in the process of actually writing each data information fragment to the available cache address, the information that needs to be written includes: data information fragment, fragment number, index information.

[0038] In an exemplary embodiment, after writing the data information and the index information into the available cache area address pointed to by any identification information, the method further includes: setting the shard field in the available cache area address to a first value, and setting the identification information field in the available cache area address to a null value, wherein the shard field is set to the first value to indicate that the data information shard written to the available cache area address is not a data information shard, or that the data information shard written to the available cache area address is the last data information shard.

[0039] It should be noted that the fragment field in the available cache address is used to indicate whether the data information fragment written to the current available cache address is a data information fragment based on the current value of the field; the identification information pointer is used to indicate: if the target data information fragment is written to the current available cache address, but the target data information fragment is not the last data information fragment among all data information fragments, the pointer to the identification information corresponding to the available cache address where the next target data information fragment should be written. In essence, it is a chain pointer that chains all data information fragments (equivalent to multiple data information fragments).

[0040] It can be understood that, when the preset value is 2, one available buffer area can meet the writing requirements of the data information. Therefore, any identification information is selected from the identification information of the available buffer area in the identification information queue, and the data information fragment is written to the available buffer area address pointed to by any identification information. After writing, the fragment field of the available buffer area address is set to a first value, which can be 0. In the embodiment of the present application, it is used to indicate that what is written to the available buffer area address is not a data information fragment, but a complete data information. The identification information field in the available buffer area address to which the complete data information is written does not need to point to the identification information where the next data information fragment is located, and is therefore set to a null value. For example, the null value can be replaced by 0.

[0041] Exemplarily, the write row format of data information and the like written to the available cache address is, for example: {0, 0, info[x]}, where the first "0" is used to indicate that what is written to the available cache address is not a data information fragment, but complete data information, and the second "0" is used to indicate that there is no identification information corresponding to the available cache area where the next data information fragment of the current data information fragment is written, which needs to be pointed to, "info" represents data information, and "x" represents index information.

[0042] Regarding the writing of data information fragments, in one embodiment, writing the data information fragment, the fragment number, and the index information into the available cache area address pointed to by the target identification information of the available cache area includes: obtaining m identification information from the identification information queue, and determining the m identification information as the target identification information, wherein each data information fragment in the multiple data information fragments corresponds one-to-one to each identification information in the m identification information, and m is an integer greater than 1; writing the data information fragment, the fragment number, and the index information into the available cache area address pointed to by the identification information corresponding to the data information fragment.

[0043] When data information is fragmented based on a length value, and the length value is m, m data information fragments will be generated. Accordingly, m identification information must be obtained from the identification information queue to store the m data information fragments in the available buffer addresses pointed to by the m identification information. These m identification information can then collectively serve as the target identification information. Generally speaking, data information only needs to be fragmented when the length value is greater than 1. Therefore, m is an integer greater than 1. After clarifying the composition of the target identification information, each data information fragment, its fragment number, and index information should be written to the available buffer address pointed to by the identification information corresponding to each data information fragment.

[0044] With respect to writing of data information fragments, in another embodiment, writing the data information fragment, the fragment number, and the index information into the available cache area address pointed to by the target identification information of the available cache area further includes: obtaining n identification information from the identification information queue, wherein the n identification information is used to ensure that in the process of writing the kth data information fragment among the multiple data information fragments into the kth available cache area address pointed to by the kth identification information among the n identification information, the n identification information contains identification information corresponding to the nth data information fragment in the identification information field that can be written to the kth available cache area address, wherein the identification information field is used to indicate the identification information corresponding to the next data information fragment of the kth data information fragment, and n is an integer greater than 1. And n is less than m, k=n-1; when the kth data information fragment has been written into the available cache area, determine whether the current length value is greater than or equal to the preset value, wherein the current length value is used to indicate the length value obtained by updating the length value after any data information fragment among the multiple data information fragments is written into the available cache area address pointed to by the target identification information; when the current length value is greater than or equal to the preset value, write the wth data information fragment, the fragment number corresponding to the wth data information fragment, and the index information into the available cache area address pointed to by any identification information, wherein the arbitrary identification information is any identification information that has not been obtained in the identification information queue, and the multiple data information fragments include the wth data information fragment, w=n+1.

[0045] In the case where there are m data information fragments, n identification information can also be preferentially obtained from the identification information queue, so that at least when the kth data information fragment among the m data information is written to the kth available cache address, there is the (k+1)th identification information corresponding to the (k+1)th data information fragment in the identification information field that can be written to the kth available cache address, so that in the subsequent reading process of the data information, under the guidance of the identification information field (equivalent to the identification information pointer), the data information fragments with the same fragment order can be read in sequence. For example, if there are 10 data information fragments, two identification information can be obtained first, and then when the first data information fragment is written to the available cache address pointed to by the first identification information, the identification information corresponding to the second data information fragment is written to the identification information field of the first available cache address.

[0046] It should be noted that, every time a data information segment is written into an available buffer address, the length value of the data information segment will be reduced by 1 accordingly. Furthermore, when there are 10 data information fragments and 2 identification information are obtained first, after the first data information fragment is written into the available cache area, the current length value = 10-1 = 9. If the preset value is 2, the length value is still greater than the preset value, and it is necessary to continue to select arbitrary identification information from the remaining identification information in the identification information queue, wherein the remaining identification information is the identification information remaining in the identification information queue after n identification information are taken away (in fact, it can be understood as the current identification information queue); the arbitrary identification information is used as the (n+1)th identification information to point to the (n+1)th available cache area address that should be written into the (n+1)th data information fragment, and is also used to be written into the identification information field of the nth available cache area address, so that in the subsequent reading process of the data information fragment, the (n+1)th available cache area address carrying the (n+1)th data information fragment can be found based on the nth available cache area address.

[0047] In an exemplary embodiment, after writing the data information fragment, the fragment number, and the index information into the available cache address pointed to by the target identification information of the available cache, the method further includes: determining whether the data information fragment is the last data information fragment; if the data information fragment is the last data information fragment, determining the target available cache address to which the data information fragment is written; setting the fragment field in the target available cache address to a first value, and setting the identification information field in the target available cache address to a null value, wherein the fragment field is set to the first value for indicating that the target available cache address is written. is not a data information fragment, or the data information fragment written by the target available cache area address is the last data information fragment; in the case that the data information fragment is not the last data information fragment, determine the target available cache area address to which the data information fragment is written; set the fragment field in the target available cache area address to a second value, and write the identification information field in the target available cache area address as the identification information of the available cache area to which the next data information fragment corresponding to the data information fragment is expected to be written, wherein the fragment field is set to the second value to indicate that the data information fragment written by the target available cache area address is not the last data information fragment.

[0048] It is understandable that, in the process of writing data information fragments into the available cache area address, there are two situations: the data information fragment currently being written is not the last one, and the data information fragment currently being written is the last one.

[0049] In the case where the last data information fragment is currently being written, the fragment field of the target available cache address being written is set to the second value, which is used to indicate that the last data information fragment is written in the target available cache address, and the identification information field of the target available cache is set to a null value, because the last data information does not have a next data information fragment to point to. For example, the field representation in the available cache address can be: {0, 0, info[x, y], the first "0" is used to represent the first value, that is, the current data information fragment is the last data information fragment, the second "0" indicates that when the last data information fragment is written in the target available cache address, there is no identification information corresponding to the available cache address to which the next data information fragment to point to is written, info represents data information, x represents index information, and y represents the fragment number corresponding to the last data information fragment.

[0050] In the case where the data information fragment currently being written is not the last data information fragment, the fragment field of the target available cache address being written is set to the first value, which is used to indicate that the data information fragment written to the target available cache address is not the last data information fragment, and the identification information field of the target available cache is written with the identification information of the available cache to which the next data information fragment corresponding to the data information fragment written to the target available cache is expected to be written. For example, the field representation format in the available cache address can be: {1, ID[n+1], info[x, y]}, where "1" is used to represent the second value, i.e., the current data information fragment is not the last data information fragment, ID[n+1] represents the identification information corresponding to the (n+1)th data information fragment when the nth data information fragment is written to the target available cache address, info represents the data information, x represents the index information, and y represents the fragment number corresponding to the nth data information fragment.

[0051] In an exemplary embodiment, writing the first identification information in the target identification information into the identification information pointer in the target index information data includes: when the length value is less than a preset value, determining any identification information as the first identification information and writing it into the identification information pointer in the target index information data; when the length value is greater than or equal to the preset value, determining the first obtained identification information in the target identification information as the first identification information and writing it into the identification information pointer in the target index information data.

[0052] It can be understood that if the data information does not need to be fragmented and is directly written into the address of the available cache area, then the identification information pointer in the index information data corresponding to the data information in the linked list bitmap only needs to point to the available cache area where the data information is written, and then the identification information pointer is written with any of the aforementioned identification information.

[0053] If the data information needs to be fragmented, the identification information pointer needs to point to the available buffer area where the first data information fragment is written. Since the identification information of the available buffer area may be obtained out of order, the identification information pointer needs to be written with the first obtained identification information.

[0054] Next, the address writing method will be further described in conjunction with the following optional embodiments.

[0055] An optional embodiment of the present application is directed to the front-end development and design of an ASIC chip, and is used to implement the function of reordering received frames by the receiving-side hardware in the operation of a Wireless Fidelity (WIFI) chip.

[0056] Various structures of optional embodiments of the present application are shown in FIG3 , which are composed of three storage units: a linked list bitmap (bitmap), an available buffer area (info_buffer), and an identification information queue (ID FIFO).

[0057] The valid flag (valid) of each data storage linked list corresponding node of the linked list bitmap bitmap and the linked list node (info_ptr) assigned to the descriptor (equivalent to the identification information pointer in the above embodiment), valid is 1, indicating that the data information (info) corresponding to the index information (Num) has been received, and at this time info_ptr is valid.

[0058] The available buffer area info_buffer stores data information info resource blocks. When the length of the data information info is unequal and requires multiple resource blocks to store, the chain information within the data information info is stored. Each buffer storage content consists of three parts: {next_vld, next_ID, info}, where next_vld is used to indicate whether it is the last data information fragment or whether it is a data information fragment; next_ID is used to indicate the identification information corresponding to the next data information fragment of the currently stored data information fragment; info can be the frame body of the received frame itself (equivalent to the data information or data information fragment in the above embodiment), or indicate related information stored in the received frame.

[0059] The ID information queue FIFO maintains the number and number of allocatable resource blocks (equivalent to the available buffer addresses in the above embodiment) in the available buffer area info_buffer. For example, in Figure 3, 0, 3, 6, and 8 in the ID information queue correspond to available buffer area addresses (addr) 0, 3, 6, and 8 in the available buffer area.

[0060] Optionally, next_vld, next_ID and info of the available buffer area info_buffer in an optional embodiment of the present application can be divided into three storage units.

[0061] An optional embodiment of the present application adopts the process shown in FIG4 , adopting a serial processing method, specifically including the following steps S401 to S410 .

[0062] In step S401, the identification information queue is initialized.

[0063] The identification information queue ID FIFO is initialized and written with 0, 1, 2... in sequence until it is full.

[0064] In step S402, data information info and index information Num are input. The input data information info and corresponding index information Num are received.

[0065] In step S403, it is determined whether the length value of the data information info is greater than or equal to 2. If it is greater than or equal to 2, step S404 is executed; if it is less than 2, step S405 is executed.

[0066] In step S404, two available identification information (ID[n], ID[n+1]) are requested from the identification information queue ID FIFO.

[0067] If the length of the data information info (info_length) is greater than or equal to two available buffer area info_buffer resource blocks, two available identification information buffer IDs are requested from the identification information queue ID FIFO, recorded as ID[n] and ID[n+1], and the process goes to step S406.

[0068] In step S405, one available identification information is requested from the identification information queue ID FIFO, and the process proceeds to step S408.

[0069] If the length of the data information info is one available buffer info_buffer resource block (ie, less than 2), only one available identification information buffer ID is requested. The first requested ID is ID_head.

[0070] In step S406, {1, ID[n+1], info[x, y]} is written into the available buffer address, and the length of the data information info, info_length, is reduced by 1, where n=n+1 and y=y+1.

[0071] Take the first resource block of the data information info and record it as info[x, y], where x represents the index Num of the data information info and y represents the fragment number within the data information info. Write the fields {1, ID[n+1], info[x, y]} to the ID[n] address of the available buffer area info_buffer. "1" indicates that the data information info is fragmented. At this point, ID[n+1] is valid, indicating the address of the next fragment (i.e., info[x, y+1]). After writing, the length of the data information info, info_length, is decremented by 1; y and n are incremented by 1, indicating that the next fragment of the data information info is ready.

[0072] In step S407, it is determined whether the length info_length of the data information info is greater than or equal to 2. If it is greater than or equal to 2, the process proceeds to step S409; if it is less than 2, the process proceeds to step S408.

[0073] If the length info_length is greater than or equal to 2, apply for 1 buffer ID (ID[n+1]) (ie, the next available identification information) from the identification information queue ID FIFO, and then repeat step S406; if the length info_length is less than 2, proceed to step S408.

[0074] In step S408, {0, 0, info[x, y]} is written into the available buffer address of the available buffer, and the process goes to step S410.

[0075] Write {0, 0, info[x, y]} into the ID[n] address of the available buffer area info_buffer, where the first "0" represents the fragment of the last data information info.

[0076] In step S409, the next available identification information is requested from the identification information queue ID FIFO.

[0077] In step S410, {1, first ID} (ie, ID_head) is written into the index information Num data in the linked list bitmap.

[0078] It should be noted that, in the above steps S401 to S410, if it is not explicitly stated that a step needs to be skipped, it needs to be executed in sequence.

[0079] The address of the index information Num of the linked list bitmap bitmap is written into {1, ID_head}, where "1" indicates that the index information Num has received the data information info, and ID_head is the first address of the data information info in the available buffer area info_buffer.

[0080] A specific embodiment is given below to explain the above embodiment. In the specific embodiment, the linked list structure receives data information info[0], info[4], info[2] with index information Num=0, Num=4, Num=2 in sequence, where the data information info[2] with index information Num=2 requires two available buffer area info_buffer resource blocks for storage.

[0081] Step 1: Receive the data information info[0] with index information Num=0, apply for an available identification information buffer ID(0) from the identification information queue ID FIFO, write the data information info[0] into the available buffer area info_buffer address 0, write data {0, 0, info[0]}, and write {1, 0} in bitmap[0], as shown in Figure 5.

[0082] Step 2: After receiving the data information info[4] with index information Num=4, apply for an available identification information buffer ID(3) from the identification information queue ID FIFO, write the data information info[4] into the available buffer area info_buffer address 3, write data {0, 0, info[4]}, and write {1, 3} into bitmap[4], as shown in Figure 6.

[0083] Step 3, after receiving the data information info[2] with index information Num=2, apply for two available identification information buffer IDs (6, 8) from the identification information queue ID FIFO, write the data information info[2, 0] into the available buffer area info_buffer address 6, and write the data as {1, 8, info[2, 0]}, "1" indicates that there is a fragment of the next data information info, and "8" indicates that the address of the next fragment is 8; write the data information info[2, 1] into the available buffer area info_buffer address 8, write the data as {0, 0, info[2, 1]}, and write {1, 6} in bitmap[2], as shown in Figure 7.

[0084] Based on the address writing method given in the above optional embodiment, the corresponding output process is: when the output condition is met, the linked list bitmap bitmap is shifted. If the removed field contains a valid indication, the data information info is read from the available buffer area info_buffer according to the corresponding available identification information ID for output. If the next_vld of the obtained data information info is 0, the linked list bitmap bitmap is continued to be shifted; if the next_vld of the obtained data information info is 1, the next fragment of the data information info is obtained according to the next ID, until the fragment of the obtained data information info has a tail indication (that is, next_vld is 0).

[0085] Furthermore, the method and apparatus for implementing fast insertion of a linked list structure provided in an optional embodiment of the present application meet the requirements for fast insertion of reordering services in ASIC front-end designs. Specifically, the embodiment of the present application adopts a linked list structure for scenarios with variable frame lengths. This improves reordering performance by inserting linked lists in the middle of a linked list rather than inserting nodes within a linked list. The delay of each insertion is fixed, and the time complexity for reordering n received frames is O(n).

[0086] Therefore, compared with the related art, the insertion delay of each received frame in the optional embodiment of the present application is a fixed value, which meets the requirements of the WIFI receiving side chip for the traffic and delay stability of the received frame reordering.

[0087] The present application also provides an address writing device for implementing the above-mentioned embodiments and implementation methods, which have been described and will not be repeated here. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementations using hardware, or a combination of software and hardware, are also possible and contemplated.

[0088] FIG8 is a block diagram of an address writing device according to an embodiment of the present application. As shown in FIG8 , the address writing device includes a first determining module 82 , a first writing module 84 , a second determining module 86 , and a second writing module 88 .

[0089] The first determining module 82 is used to determine the data information of the received frame to be written and the index information of the received frame.

[0090] The first writing module 84 is used to write the data information and the index information into the available cache area address pointed to by the target identification information of the available cache area, wherein the available cache area address is used to store the data information.

[0091] The second determination module 86 is used to determine the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes a plurality of index information data that have been sorted, wherein each index information data in the plurality of index information data includes: a valid identifier and an identifier information pointer.

[0092] The second writing module 88 is used to set the valid flag in the target index information data to a valid flag value, and write the first flag information in the target flag information into the flag information pointer in the target index information data.

[0093] The present application uses the above-mentioned module to determine the data information of the received frame to be written and the index information of the received frame; write the data information and the index information into the available buffer address pointed to by the target identification information of the available buffer, wherein the available buffer address is used to store the data information; determine the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes a plurality of index information data that have been sorted, wherein each index information data in the plurality of index information data includes: a valid identifier and an identifier information pointer; set the valid identifier in the target index information data to a valid identifier value, and write the first identifier information in the target identification information into the identifier information pointer in the target index information data. That is, when there is a received frame to be written, the data information of the received frame is written into the available buffer address, and the first identifier information in the target identification information of the available buffer address is written into the index information data corresponding to the received frame in the plurality of index information data that have been sorted included in the linked list bitmap, thereby solving the technical problem that the linked list insertion operation of the existing linked list structure reordering scheme is low in efficiency and thus unsuitable for high-performance reordering scenarios.

[0094] In an exemplary embodiment, the first writing module 84 is also used to determine the size relationship between the length value of the data information and a preset value; when the length value is less than the preset value, obtain any identification information in the identification information queue as the target identification information, wherein the identification information queue records all identification information of the available cache area; write the data information and the index information into the available cache area address pointed to by any identification information; when the length value is greater than or equal to the preset value, fragment the data information according to the length value to obtain multiple data information fragments; write the multiple data information fragments and the index information into the available cache area address pointed to by the target identification information of the available cache area.

[0095] In an exemplary embodiment, the first writing module 84 is also used to: for each data information fragment among the multiple data information fragments, determine the fragment number corresponding to the data information fragment according to the fragmentation order of the data information fragment among the multiple data information fragments; write the data information fragment, the fragment number, and the index information into the available cache area address pointed to by the target identification information of the available cache area.

[0096] In an exemplary embodiment, the above-mentioned device also includes a setting module for setting the fragment field in the available cache area address to a first value, and setting the identification information field in the available cache area address to a null value, wherein the fragment field is set to the first value to indicate that the data information fragment written to the available cache area address is not a data information fragment, or that the data information fragment written to the available cache area address is the last data information fragment.

[0097] In an exemplary embodiment, the first writing module 84 is also used to: obtain m identification information from the identification information queue, and determine the m identification information as the target identification information, wherein each data information fragment in the multiple data information fragments corresponds one-to-one to each identification information in the m identification information, and m is an integer greater than 1; write the data information fragment, the fragment number, and the index information into the available cache area address pointed to by the identification information corresponding to the data information fragment.

[0098] In an exemplary embodiment, the first writing module 84 is further used to: obtain n identification information from the identification information queue, wherein the n identification information is used to ensure that in the process of writing the kth data information fragment among the multiple data information fragments to the kth available cache area address pointed to by the kth identification information among the n identification information, there is identification information corresponding to the nth data information fragment in the identification information field that can be written to the kth available cache area address in the n identification information, wherein the identification information field is used to indicate the identification information corresponding to the next data information fragment of the kth data information fragment, n is an integer greater than 1, and n is less than m, k=n-1; when the kth data information fragment has been written In the case where the wth data information fragment is written to the available cache area, determine whether the current length value is greater than or equal to the preset value, wherein the current length value is used to indicate the length value obtained by updating the length value after any data information fragment among the multiple data information fragments is written to the available cache area address pointed to by the target identification information; in the case where the current length value is greater than or equal to the preset value, write the wth data information fragment, the fragment number corresponding to the wth data information fragment, and the index information into the available cache area address pointed to by any identification information, wherein the arbitrary identification information is any identification information that has not been obtained in the identification information queue, and the multiple data information fragments include the wth data information fragment, and w=n+1.

[0099] In an exemplary embodiment, the setting module is further used to: determine whether the data information fragment is the last data information fragment; if the data information fragment is the last data information fragment, determine the target available cache address to which the data information fragment is written; set the fragment field in the target available cache address to a first value, and set the identification information field in the target available cache address to a null value, wherein the fragment field is set to the first value to indicate that the data information fragment written to the target available cache address is not a data information fragment, or that the data information fragment written to the target available cache address is the last data information fragment; if the data information fragment is not the last data information fragment, determine the target available cache address to which the data information fragment is written; set the fragment field in the target available cache address to a second value, and write the identification information field in the target available cache address as identification information of the available cache area to which the next data information fragment corresponding to the data information fragment is expected to be written, wherein the fragment field is set to the second value to indicate that the data information fragment written to the target available cache address is not the last data information fragment.

[0100] In an exemplary embodiment, the second writing module 88 is also used to: when the length value is less than a preset value, determine any one of the identification information as the first identification information and write it into the identification information pointer in the target index information data; when the length value is greater than or equal to the preset value, determine the first obtained identification information in the target identification information as the first identification information and write it into the identification information pointer in the target index information data.

[0101] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, which is stored in a readable storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the method of each embodiment of the present application.

[0102] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0103] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0104] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0105] Optionally, in this embodiment, the processor may be configured to execute the following steps S1 to S4 through a computer program.

[0106] In step S1 , data information of a received frame to be written and index information of the received frame are determined.

[0107] In step S2, the data information and the index information are written into the available cache area address pointed to by the target identification information of the available cache area, wherein the available cache area address is used to store the data information.

[0108] In step S3, the target index information data corresponding to the index information in the linked list bitmap is determined, wherein the linked list bitmap includes a plurality of index information data that have been sorted, wherein each index information data in the plurality of index information data includes: a valid identifier and an identifier information pointer.

[0109] In step S4, the valid flag in the target index information data is set to a valid flag value, and the first flag information in the target flag information is written into the flag information pointer in the target index information data.

[0110] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0111] Optionally, in this embodiment, the electronic device may also be configured to execute steps S1 to S4 via a computer program.

[0112] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0113] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0114] The above description is merely an embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for writing an address, comprising: Determining data information of a received frame to be written and index information of the received frame; Writing the data information and the index information into an available cache address pointed to by the target identification information of the available cache, wherein the available cache address is used to store the data information; Determine the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes a plurality of index information data that have been sorted, wherein each of the plurality of index information data includes: a valid identifier and an identifier information pointer; The valid identification in the target index information data is set to a valid identification value, and the first identification information in the target identification information is written into the identification information pointer in the target index information data.

2. The address writing method according to claim 1, wherein: The address of the available cache area pointed to by the target identification information of writing the data information and the index information into the available cache area includes: Determine the size relationship between the length value of the data information and a preset value; When the length value is less than a preset value, obtaining any identification information in the identification information queue as the target identification information, wherein the identification information queue records all identification information of the available buffer area; writing the data information and the index information into the address of the available buffer area pointed to by any identification information; When the length value is greater than or equal to the preset value, the data information is segmented according to the length value to obtain multiple data information segments; the multiple data information segments and the index information are written into the available cache area address pointed to by the target identification information of the available cache area.

3. The address writing method according to claim 2, wherein: Writing the plurality of data information fragments and the index information into the available cache area address pointed to by the target identification information of the available cache area comprises: For each of the plurality of data information fragments, Determine a fragment number corresponding to the data information fragment according to a fragmentation order of the data information fragment among the multiple data information fragments; The data information fragment, the fragment number, and the index information are written into the available cache area address pointed to by the target identification information of the available cache area.

4. The address writing method according to claim 2, wherein: After writing the data information and the index information into the available cache address pointed to by any identification information, the method further includes: The fragment field in the available cache area address is set to a first value, and the identification information field in the available cache area address is set to a null value, wherein the fragment field is set to the first value to indicate that the data information fragment written to the available cache area address is not a data information fragment, or that the data information fragment written to the available cache area address is the last data information fragment.

5. The address writing method according to claim 3, wherein: Writing the data information fragment, the fragment number, and the index information into the available cache address pointed to by the target identification information of the available cache includes: Obtain m pieces of identification information from the identification information queue, and determine the m pieces of identification information as the target identification information, wherein each of the multiple data information fragments corresponds to each of the m pieces of identification information one by one, and m is an integer greater than 1; The data information segment, the segment number, and the index information are written into the available cache area address pointed to by the identification information corresponding to the data information segment.

6. The address writing method according to claim 3, wherein: Writing the data information fragment, the fragment number, and the index information into the available cache address pointed to by the target identification information of the available cache includes: Obtain n identification information from the identification information queue, wherein the n identification information The identification information is used to ensure that in the process of writing the kth data information fragment among the multiple data information fragments into the Kth available cache area address pointed to by the kth identification information among the n identification information, the n identification information contains the identification information corresponding to the nth data information fragment in the identification information field that can be written into the kth available cache area address, wherein the identification information field is used to indicate the identification information corresponding to the next data information fragment of the kth data information fragment, n is an integer greater than 1, and n is less than m, k=n-1; In the case where the kth data information fragment has been written into the available buffer area, determining whether the current length value is greater than or equal to the preset value, wherein the current length value is used to indicate a length value obtained by updating the length value after any data information fragment among the multiple data information fragments is written into the available buffer area address pointed to in the target identification information; When the current length value is greater than or equal to the preset value, the w-th data information fragment, the fragment number corresponding to the w-th data information fragment, and the index information are written into the available cache area address pointed to by any identification information, wherein the arbitrary identification information is any identification information that has not been acquired in the identification information queue, and the w-th data information fragment is included in multiple data information fragments, and w=n+1.

7. The address writing method according to claim 3, wherein: After writing the data information fragment, the fragment number, and the index information into the available cache area address pointed to by the target identification information of the available cache area, the method further includes: Determining whether the data information fragment is the last data information fragment; In the case where the data information fragment is the last data information fragment, determining a target available cache address to which the data information fragment is written; setting a fragment field in the target available cache address to a first value, and setting an identification information field in the target available cache address to a null value, wherein the fragment field is set to the first value to indicate that the target available cache address does not write a data information fragment, or that the data information fragment written by the target available cache address is the last data information fragment; In the case where the data information fragment is not the last data information fragment, Determine the target available cache address to which the data information fragment is written; set the fragment field in the target available cache address to a second value, and write the identification information field in the target available cache address as the identification information of the available cache area to which the next data information fragment corresponding to the data information fragment is expected to be written, wherein the fragment field is set to the second value to indicate that the data information fragment written by the target available cache address is not the last data information fragment.

8. The address writing method according to claim 2, wherein: Writing the first identification information in the target identification information into the identification information pointer in the target index information data comprises: In the case where the length value is less than a preset value, determining any one of the identification information as the first identification information and writing it into the identification information pointer in the target index information data; When the length value is greater than or equal to a preset value, the first identification information obtained in the target identification information is used as the first identification information and written into the identification information pointer in the target index information data.

9. An address writing device, comprising: A first determining module, used to determine data information of a received frame to be written and index information of the received frame; A first writing module, used for writing the data information and the index information into an available cache area address pointed to by the target identification information of the available cache area, wherein the available cache area address is used for storing the data information; A second determination module is used to determine the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes a plurality of index information data that have been sorted, wherein each of the plurality of index information data includes: a valid identifier and an identifier information pointer; The second writing module is used to set the valid identification in the target index information data to a valid identification value, and write the first identification information in the target identification information into the identification information pointer in the target index information data.

10. A computer-readable storage medium having a computer program stored thereon, wherein: When the computer program is executed by a processor, the processor is caused to perform the method as claimed in any one of claims 1 to 8.

11. A chip comprising the address writing device according to claim 9.

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