Method for manufacturing shielded gate trench device

Abstract

Provided is a method for manufacturing a shielded gate trench device, comprising: forming, in a trench, a first silicon oxide material layer and a first polycrystalline silicon material layer; etching the first polycrystalline silicon material layer, and forming a first polycrystalline silicon layer, a top end of the first polycrystalline silicon layer being lower than a top end of the first silicon oxide material layer; etching the first silicon oxide material layer, and forming a first silicon oxide layer, the trench above the first silicon oxide layer forming a recess space; forming, in the recess space, a second silicon oxide material layer and a second polycrystalline silicon material layer; and, at a preset temperature, recrystallizing the second polycrystalline silicon material layer. In the present invention, the first polycrystalline silicon material layer is etched and a nail head structure is removed, facilitating filling of the second polycrystalline silicon material layer, and by means of recrystallization, a defect in the second polycrystalline silicon material layer is repaired, improving the electrical reliability of the device. In addition, after the second polycrystalline silicon material layer is etched back and a gate polycrystalline silicon is formed, an interface void between gate oxide and the gate polycrystalline silicon is repaired by means of thermal oxidation, and the electrical reliability of the device is further improved.

Description

Method for manufacturing a shielded grid device Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a method for manufacturing a shielded gate device. Background Art

[0002] In shielded gate (SGT) devices, the trench needs to be filled with a gate oxide layer and a gate polysilicon layer. This process can easily create holes and gaps in the gate polysilicon, leading to defects. Furthermore, the presence of these holes and gaps can easily leave contaminants, such as etching byproducts, water vapor, or corrosive gases, in the subsequent implantation and etching processes. These residues can also cause defects, leading to product ID leakage and device electrical failure. Furthermore, as SGT products are increasingly targeted at lower voltages, the gate oxide layer is becoming thinner. The presence of post-etch byproducts and polysilicon stress on the gate polysilicon can cause voids to form at the interface between the gate polysilicon and the gate oxide layer, also causing leakage.

[0003] There are two main ways to improve gate polysilicon holes and gaps in existing manufacturing methods. The first is to optimize the morphology of the trench after etching, forming a trench with a larger top and smaller bottom to facilitate polysilicon filling. However, in actual applications, due to product design and machine capacity limitations, it is impossible to achieve a morphology with a larger top and smaller bottom. The second is to form the gate polysilicon through multiple etching and multiple deposition methods, but this is costly and complex. At the same time, the damage to the gate oxide layer during multiple etching and the thickness requirement of the etch stop layer in the non-trench area must also be considered. Although changing the gas ratio of the etching process can reduce etching damage, it is limited by the gas ratio of the etching machine. In addition, by changing the polysilicon deposition temperature to reduce the effect of stress on the gate oxide layer, the purpose of repairing interface voids can be achieved. However, due to the limitations of polysilicon resistance and polysilicon grain requirements, it may be limited in product application.

[0004] Therefore, how to provide a method for manufacturing a shielded gate device to improve the ID leakage of the shielded gate device, improve reliability, and reduce costs has become a technical problem that needs to be urgently solved by those skilled in the art.

[0005] Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for manufacturing a shielded gate device to solve the problems in the prior art of gaps and holes easily existing in the gate polysilicon and voids easily existing at the interface between the gate polysilicon and the gate oxide layer.

[0007] To achieve the above-mentioned and other related purposes, the present invention provides a method for manufacturing a shielded gate device, comprising the following steps:

[0008] Providing a substrate, wherein a trench is formed in the substrate, a first silicon oxide material layer is formed on the sidewall and bottom of the trench, and a first polysilicon material layer is formed in the trench;

[0009] Etching the first polysilicon material layer to form a first polysilicon layer, wherein a top of the first polysilicon layer is lower than a top of the first silicon oxide material layer, and a top of the first polysilicon layer is not lower than a top of the substrate;

[0010] Etching the first silicon oxide material layer to form a first silicon oxide layer, wherein a top of the first silicon oxide layer is lower than a top of the trench, wherein the trench above the first silicon oxide layer constitutes a recessed space;

[0011] forming a second silicon oxide material layer on the bottom and sidewalls of the groove space, and forming a second polysilicon material layer in the groove space;

[0012] The second polysilicon material layer is recrystallized at a preset temperature to repair defects in the second polysilicon material layer.

[0013] Optionally, the recrystallization temperature of the second polysilicon material layer ranges from 900° C. to 1100° C.

[0014] Optionally, after the second polysilicon material layer is recrystallized, the following steps are further included:

[0015] Etching the second polysilicon material layer to form gate polysilicon;

[0016] Oxygen is introduced into the cavity to partially oxidize the gate polysilicon at a preset temperature to repair the voids in the second silicon oxide material layer.

[0017] Optionally, the gate polysilicon oxidation temperature range is 1000-1100°C.

[0018] Optionally, after the gate polysilicon is partially oxidized, the thickness of the generated thermal oxide layer is in the range of

[0019] Optionally, the time interval between etching the second polysilicon material layer and thermally oxidizing the gate polysilicon is no more than 70 hours.

[0020] Optionally, before etching the first polysilicon material layer, the step of grinding the first polysilicon material layer using chemical mechanical grinding is also included to make the upper surface of the first polysilicon material layer flush with the upper surface of the first silicon oxide material layer, and then etching the first polysilicon material layer using dry etching to form the first polysilicon layer.

[0021] Optionally, the first silicon oxide material layer is etched by wet etching to form the first silicon oxide layer.

[0022] Optionally, the thickness of the first silicon oxide material layer is in the range of The thickness of the first polysilicon material layer is in the range of

[0023] Optionally, the thickness of the second silicon oxide material layer is in the range of

[0024] As described above, in the method for fabricating a shielded gate device of the present invention, etching the first polysilicon layer to remove the nail head structure facilitates the subsequent filling of the second polysilicon layer. After the second polysilicon layer is filled, the gap defects in the second polysilicon layer are repaired through recrystallization, thereby improving the electrical reliability of the device. Furthermore, after the second polysilicon layer is etched back to form the gate polysilicon, the interface voids between the gate oxide and the gate polysilicon are repaired through thermal oxidation, further improving the electrical reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a schematic diagram showing a method for manufacturing a shielded gate device according to a first embodiment of the present invention, wherein a first silicon oxide material layer and a first polysilicon material layer are formed in a trench.

[0026] FIG. 2 is a schematic diagram showing a method for manufacturing a shielded gate device according to a first embodiment of the present invention, wherein a chemical mechanical polishing method is used to polish a first polysilicon material layer.

[0027] FIG. 3 is a schematic diagram showing the process of etching a first silicon oxide layer to form a groove space in a method for manufacturing a shielded gate device according to the first embodiment of the present invention.

[0028] FIG. 4 is a schematic diagram showing filling a second silicon oxide material layer and a second polysilicon material layer in a groove space in a method for manufacturing a shielded gate device according to a first embodiment of the present invention.

[0029] FIG. 5 is a schematic diagram showing etching of a second polysilicon material layer in a method for manufacturing a shielded gate device according to the first embodiment of the present invention.

[0030] FIG6 is a flow chart showing a method for manufacturing a shielded gate device according to a second embodiment of the present invention.

[0031] FIG. 7 is a schematic diagram showing a first silicon oxide material layer and a first polysilicon material layer formed during trench filling according to a second embodiment of the present invention.

[0032] FIG. 8 is a schematic diagram showing a second embodiment of the present invention, wherein the first polysilicon material layer is polished using a chemical mechanical polishing method.

[0033] FIG. 9 is a schematic diagram showing etching of the first polysilicon material layer according to a second embodiment of the present invention.

[0034] FIG. 10 is a schematic diagram showing etching the first silicon oxide material layer to form a groove space according to a second embodiment of the present invention.

[0035] FIG. 11 is a schematic diagram showing a second silicon oxide material layer and a second polysilicon material layer formed in the groove space according to a second embodiment of the present invention.

[0036] FIG. 12 is a schematic diagram showing the recrystallization of the second polysilicon material layer according to the second embodiment of the present invention.

[0037] FIG. 13 is a schematic diagram showing etching the second polysilicon material layer to form gate polysilicon according to a second embodiment of the present invention.

[0038] FIG. 14 is a schematic diagram showing thermal oxidation of gate polysilicon according to a second embodiment of the present invention.

[0039] DESCRIPTION OF EMBODIMENTS 10 substrate 20 first silicon oxide layer 20a first silicon oxide layer 30 first polysilicon layer 30a first polysilicon layer 40 second silicon oxide layer 50 second polysilicon layer 50a gate polysilicon 60 thermal oxide layer S1-S5 steps DETAILED DESCRIPTION

[0040] The following describes the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components during actual implementation. During actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0041] 1 to 5 , which illustrate a method for fabricating a shielded gate device according to a first embodiment of the present invention, comprising the following steps: (1) as shown in FIG1 , a trench is formed by etching in a substrate 10, and a first silicon oxide material layer 20 and a first polysilicon material layer 30 are filled in the trench; (2) as shown in FIG2 , the first polysilicon material layer 30 above the first silicon oxide material layer 20 is removed by chemical mechanical polishing (CMP), and the top of the retained first polysilicon material layer 30 has a “nail head” structure; (3) as shown in FIG3 , the first silicon oxide material layer 20 is etched by wet etching to form a first silicon oxide layer 20 a, and the trench above the first silicon oxide layer 20 a constitutes a recessed space, wherein the bottom of the recessed space has a sharp corner and the top opening is small; (4) as shown in FIG4 , a second silicon oxide material layer 40 is formed on the bottom and sidewalls of the recessed space, and a second polysilicon material layer 50 is formed in the recessed space; (5) as shown in FIG5 , the second polysilicon material layer 50 is etched to form a gate polysilicon 50 a. In this embodiment, due to the irregular shape of the groove space, it is not conducive to the filling of the second silicon oxide material layer 40 and the second polysilicon material layer 50. Gaps and holes will be formed in the second polysilicon material layer 50, and the device is prone to leakage failure. In addition, the second silicon oxide material layer 40 is relatively thin as a gate oxide layer. Under the stress of the second polysilicon material layer 50, voids will be formed at the interface, which will also cause device leakage. Therefore, the present invention provides a second embodiment to improve the leakage problem of the shielded gate device. Please refer to Figures 6 to 14.

[0042] Please refer to FIG6 , which is a flow chart showing a method for manufacturing a shielded gate device according to a second embodiment of the present invention, comprising the following steps:

[0043] S1: providing a substrate, wherein a trench is formed in the substrate, a first silicon oxide material layer is formed on the sidewalls and bottom of the trench, and a first polysilicon material layer is formed in the trench;

[0044] S2: etching the first polysilicon material layer to form a first polysilicon layer, wherein a top of the first polysilicon layer is lower than a top of the first silicon oxide material layer, and a top of the first polysilicon layer is not lower than a top of the substrate;

[0045] S3: etching the first silicon oxide material layer to form a first silicon oxide layer, wherein a top of the first silicon oxide layer is lower than a top of the trench, wherein the trench above the first silicon oxide layer constitutes a recessed space;

[0046] S4: forming a second silicon oxide material layer on the bottom and sidewalls of the groove space, and forming a second polysilicon material layer in the groove space;

[0047] S5: Recrystallizing the second polysilicon material layer at a preset temperature to repair defects in the second polysilicon material layer.

[0048] First, referring to FIG. 7 and FIG. 8 , step S1 is performed: providing a substrate 10 , wherein a trench is formed in the substrate 10 , a first silicon oxide material layer 20 is formed on the sidewall and bottom of the trench, and a first polysilicon material layer 30 is formed in the trench.

[0049] As an example, the substrate 10 may be any suitable semiconductor substrate. In this embodiment, the substrate 10 is a silicon substrate.

[0050] As an example, the thickness of the first silicon oxide material layer 20 is in the range of The thickness of the first polysilicon material layer 30 is in the range of In which, the first silicon oxide material layer 20 is used as a shielding gate dielectric, and the first polysilicon material layer 30 is used as a shielding gate polysilicon; as shown in Figure 7, in the process of forming the first silicon oxide material layer 20 on the sidewall and bottom of the trench, the first silicon oxide material layer 20 is also formed on the upper surface of the substrate 10; in the process of forming the first polysilicon material layer 30 in the trench, the first polysilicon material layer 30 is also formed above the first silicon oxide material layer 20.

[0051] As an example, as shown in Figure 8, CMP grinding is used to remove the first polysilicon material layer 30 located above the first silicon oxide material layer 20, and the remaining first polysilicon material layer 30 is flush with the upper surface of the first silicon oxide material layer 20, wherein the top of the first polysilicon material layer 30 is a "nail head" structure.

[0052] 9 , step S2 is performed: etching the first polysilicon material layer 30 to form a first polysilicon layer 30a, wherein the top of the first polysilicon layer 30a is lower than the top of the first silicon oxide material layer 20 , and the top of the first polysilicon layer 30a is not lower than the top of the substrate 10 .

[0053] As an example, the first polysilicon material layer 30 is etched by dry etching to form the first polysilicon layer 30 a , wherein the “nail head” structure on the top of the first polysilicon material layer 30 is removed.

[0054] Next, referring to FIG10 , step S3 is performed: etching the first silicon oxide material layer 20 to form a first silicon oxide layer 20a, wherein the top of the first silicon oxide layer 20a is lower than the top of the trench, wherein the remaining portion of the trench above the first silicon oxide layer 20a constitutes a recess space.

[0055] As an example, the first silicon oxide material layer 20 is etched by wet etching to form the first silicon oxide layer 20a shown. Compared with the structure shown in Figure 3, in this embodiment, the "nail head" structure on the top of the first polysilicon material layer 30 is removed, and the top of the groove space is completely opened.

[0056] Next, referring to FIG. 11 , step S4 is performed: a second silicon oxide material layer 40 is formed on the bottom and sidewalls of the recess space, and a second polysilicon material layer 50 is formed in the recess space.

[0057] As an example, the second silicon oxide material layer 40 is used as gate oxide, and the second polysilicon material layer 50 is used as gate polysilicon. Since the top of the groove space is completely open, it is conducive to filling the groove space relative to the structure shown in Figure 3. Compared with the structure shown in Figure 4, defects such as gaps or holes in the second polysilicon material layer 50 in this embodiment are reduced.

[0058] As an example, although fully opening the top of the recessed space can reduce gaps or holes in the second polysilicon material layer 50, because the recessed space is formed using a wet etching process, the bottom of the recessed space is inclined, and the upper surface of the bottom of the second silicon oxide material layer 40 located at the bottom of the recessed space has a height difference, resulting in an irregular structure. Furthermore, the second polysilicon material layer 50 is formed using low-pressure furnace deposition. Deposition under low pressure will grow layer by layer along the morphology of the previous layer. Due to the irregular morphology of the second silicon oxide material layer 40 (as shown in Figures 11-14, the cross-section of the second silicon oxide material layer 40 has a height difference at the bottom), gaps and holes will still appear in the second polysilicon material layer 50 (as shown by the blank space and black dots in Figure 11).

[0059] As an example, the thickness of the second silicon oxide material layer 40 is in the range of The thinner the second silicon oxide material layer 40 is, the easier it is for voids to form at the interface between the second silicon oxide material layer 40 and the second polysilicon material layer 50 under the stress of the second polysilicon material layer 50 .

[0060] Next, referring to FIG. 12 , step S5 is performed: the second polysilicon material layer 50 is recrystallized at a predetermined temperature to repair defects in the second polysilicon material layer 50 .

[0061] As an example, the second polysilicon material layer 50 is recrystallized at a temperature of 900-1100° C. to repair the gaps and holes in the second polysilicon material layer 50 , and the polysilicon recrystallization does not affect the conductivity of the gate.

[0062] As an example, in other types of devices, when there are gap defects in polysilicon, the polysilicon gap defects can be repaired by using a recrystallization method.

[0063] As an example, please refer to Figure 13, the second polysilicon material layer 50 is etched back to form gate polysilicon 50a. Since the second polysilicon material layer 50 repairs the gaps and holes through the recrystallization process, it avoids electrical failure of the product caused by the existence of polysilicon holes and gaps, and avoids the pollutants in the holes and gaps releasing corrosive substances such as fluoride ions to corrode and damage the second silicon oxide material layer 40 during long-term storage.

[0064] As an example, referring to FIG. 14 , after forming gate polysilicon 50 a, oxygen is introduced into the chamber to oxidize the top of gate polysilicon 50 a at a predetermined temperature to repair interface voids between the second silicon oxide material layer 40 and gate polysilicon 50 a. In other trench power devices, particularly those with thin gate oxides, the thermal oxidation method of this embodiment can also be used to repair interface voids.

[0065] As an example, the temperature range of the thermal oxidation of the gate polysilicon 50a is 1000-1100°C, and the thickness range of the generated thermal oxide layer 60 is The thermal oxide layer 60 can ensure that the interface voids of the second silicon oxide material layer 40 are completely filled and repaired, and will not affect the subsequent etching / implantation process.

[0066] As an example, polysilicon is usually etched using a fluorine-containing gas. After the second polysilicon material layer 50 is etched back on the etching machine, it must undergo cleaning and drying steps to remove etching byproducts and residual corrosive substances such as fluorine ions. It is then placed on a deposition machine to thermally oxidize the gate polysilicon 50a. However, cleaning and drying cannot guarantee the complete removal of fluorine ions. Fluorine ion precipitation will corrode the second silicon oxide material layer 40, etc. In this embodiment, the time interval between the second polysilicon material layer 50 being etched back and the thermal oxidation of the gate polysilicon 50a does not exceed 70 hours to avoid fluorine ion corrosion of the second silicon oxide material layer 40, and the high temperature process of 1000-1100°C can remove corrosive substances. Specifically, in this embodiment, the time interval between the second polysilicon material layer 50 being etched back and the thermal oxidation of the gate polysilicon 50a is 50-60 hours.

[0067] In summary, in the method for manufacturing a shielded gate device of the present invention, etching the first polysilicon material layer to remove the nail head structure facilitates the subsequent filling of the second polysilicon material layer. After the second polysilicon material layer is filled, the gap defects in the second polysilicon material layer are repaired by recrystallization, thereby improving the electrical reliability of the device. In addition, after the second polysilicon material layer is etched back to form gate polysilicon, the interface voids between the gate oxide and the gate polysilicon are repaired by thermal oxidation, further improving the electrical reliability of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0068] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing a shielded gate device, characterized in that: The following steps are involved: Providing a substrate, wherein a trench is formed in the substrate, a first silicon oxide material layer is formed on the sidewall and bottom of the trench, and a first polysilicon material layer is formed in the trench; Etching the first polysilicon material layer to form a first polysilicon layer, wherein the top of the first polysilicon layer is lower than the top of the first silicon oxide material layer, and the top of the first polysilicon layer is not lower than the top of the substrate; Etching the first silicon oxide material layer to form a first silicon oxide layer, wherein a top of the first silicon oxide layer is lower than a top of the groove, wherein the groove above the first silicon oxide layer constitutes a recessed space; forming a second silicon oxide material layer at the bottom and sidewalls of the groove space, and forming a second polysilicon material layer in the groove space; The second polysilicon material layer is recrystallized at a preset temperature to repair defects in the second polysilicon material layer.

2. The method for manufacturing a shielded gate device according to claim 1, characterized in that: The temperature range of recrystallization of the second polysilicon material layer is 900-1100°C.

3. The method for manufacturing a shielded gate device according to claim 1, characterized in that: After the second polysilicon material layer is recrystallized, the method further comprises the following steps: Etching the second polysilicon material layer to form gate polysilicon; Oxygen is introduced into the cavity to partially oxidize the gate polysilicon at a preset temperature to repair the voids in the second silicon oxide material layer.

4. The method for manufacturing a shielded gate device according to claim 3, characterized in that: The temperature range of the gate polysilicon oxidation is 1000-1100°C.

5. The method for manufacturing a shielded gate device according to claim 3, characterized in that: After the gate polysilicon is partially oxidized, the thickness of the generated thermal oxide layer is in the range of 6. The method for manufacturing a shielded gate device according to claim 3, characterized in that: The time interval between etching the second polysilicon material layer and thermally oxidizing the gate polysilicon is no more than 70 hours.

7. The method for manufacturing a shielded gate device according to claim 1, characterized in that: Before etching the first polysilicon material layer, the method also includes the step of grinding the first polysilicon material layer using chemical mechanical grinding to make the upper surface of the first polysilicon material layer flush with the upper surface of the first silicon oxide material layer, and then etching the first polysilicon material layer using dry etching to form the first polysilicon layer.

8. The method for manufacturing a shielded gate device according to claim 1, characterized in that: The first silicon oxide material layer is etched by wet etching to form the first silicon oxide layer.

9. The method for manufacturing a shielded gate device according to claim 1, characterized in that: The thickness of the first silicon oxide material layer is in the range of The thickness of the first polysilicon material layer is in the range of 10. The method for manufacturing a shielded gate device according to claim 1, characterized in that: The thickness of the second silicon oxide material layer is in the range of 11. The method for manufacturing a shielded gate device according to claim 5, characterized in that: The thermal oxide layer is on top of the gate polysilicon.

12. The method for manufacturing a shielded gate device according to claim 7, characterized in that: After grinding the first polysilicon material layer, the top of the first polysilicon material layer presents a "nail head" structure.

13. The method for manufacturing a shielded gate device according to claim 12, characterized in that: After etching the first polysilicon material layer, the "nail head" structure is removed.

14. The method for manufacturing a shielded gate device according to claim 1, characterized in that: The second polysilicon material layer is formed by low-pressure furnace deposition.

15. The method for manufacturing a shielded gate device according to claim 1, characterized in that: The bottom of the groove space is in an inclined shape.

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