Direct-current arc fault detection method and apparatus, and electric power system

Abstract

A direct-current arc fault detection method and apparatus, and an electric power system. The method comprises: on the basis of a preset initial gain, performing signal processing on a pre-sampling signal, so as to obtain a corresponding first processing signal, wherein the pre-sampling signal is obtained by means of performing pre-sampling on an electrical signal of a direct-current line; on the basis of the first processing signal, determining an optimization gain; on the basis of the optimization gain, performing signal processing on a target sampling signal, so as to obtain a corresponding second processing signal, wherein the target sampling signal is obtained by means of performing target sampling on the electrical signal of the direct-current line; and on the basis of the second processing signal, determining whether there is an arc fault in the direct-current line.

Description

DC arc fault detection method, device and power system

[0001] Related applications

[0002] This application claims priority to Chinese patent application number 202311042193.2, filed on August 16, 2023, entitled “DC Arc Fault Detection Method, Device and Power System,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of power electronics technology, and in particular to a DC arc fault detection method, device, and power system. Background Art

[0004] Power electronics technology has been widely used in recent years, especially in photovoltaic power generation systems. However, when photovoltaic panels are aged or installed improperly, DC arc faults may occur. Since DC arcs do not have a zero crossing point and will not extinguish automatically, the arcs continue to accumulate energy during the burning process, which can easily cause damage to equipment and even fires, seriously affecting the safety of people's lives and property. In addition, since the location and time of arc generation are not fixed, it is difficult to perform more accurate detection, which can easily lead to false alarms or missed alarms. The relevant DC arc detection method mainly detects the electrical quantities of the DC line, including the current signal or voltage signal output by the DC power supply, such as the photovoltaic panel, and then extracts the feature quantities in the time domain or frequency domain. The feature quantities are judged with the help of a pre-established model to determine whether an arc fault exists.

[0005] Because DC arcs have little impact on the output characteristics of photovoltaic panels, the small amount of detected electrical energy affects the accuracy of A / D conversion, making it difficult to extract characteristic quantities. Therefore, to improve the accuracy of detection results, a signal amplification circuit is often used to amplify the detected electrical energy. However, the magnitude of the detected electrical energy varies in different situations, making it difficult to set the signal amplification gain. Using a fixed gain for amplification may result in ineffective signal amplification if the gain is set too low; however, setting the gain too high can lead to problems such as signal overflow.

[0006] Currently, no effective solution has been proposed to address the problems of unclear amplification effect or signal overflow that may result from using a fixed gain for signal amplification in related technologies.

[0007] Summary of the Invention

[0008] According to various embodiments of the present application, a DC arc fault detection method, device, and power system are provided.

[0009] In a first aspect, a DC arc fault detection method is provided in this embodiment, the method comprising:

[0010] Based on a preset initial gain, performing signal processing on a pre-sampled signal to obtain a corresponding first processed signal, wherein the pre-sampled signal is obtained by pre-sampling an electrical signal of the DC line;

[0011] determining an optimized gain based on the first processed signal;

[0012] Based on the optimized gain, signal processing is performed on a target sampling signal to obtain a corresponding second processed signal, wherein the target sampling signal is obtained by performing target sampling on an electrical signal of the DC link;

[0013] Based on the second processed signal, it is determined whether an arc fault exists in the DC line.

[0014] In some embodiments, the pre-sampling is performed multiple times, and determining the optimization gain based on the first processed signal includes:

[0015] Repeating the process of acquiring the first processed signal to obtain a plurality of first processed signals;

[0016] determining a maximum amplitude among a plurality of the first processed signals when the number of the first processed signals reaches a first number threshold;

[0017] Based on the maximum amplitude, the optimization gain is determined.

[0018] In some embodiments, the performing signal processing on the pre-sampled signal based on a preset initial gain to obtain a corresponding first processed signal includes:

[0019] filtering the pre-sampled signal;

[0020] amplifying the filtered pre-sampled signal based on the initial gain;

[0021] The amplified pre-sampled signal is subjected to A / D conversion to obtain the first processed signal.

[0022] In some embodiments, performing signal processing on the target sample signal based on the optimized gain to obtain a corresponding second processed signal includes:

[0023] filtering the target sampling signal;

[0024] amplifying the filtered target sampling signal based on the optimized gain;

[0025] The amplified target sampling signal is subjected to A / D conversion to obtain the second processed signal.

[0026] In some embodiments, the target sampling is performed multiple times, and determining whether an arc fault exists in the DC line based on the second processed signal includes:

[0027] Repeating the process of acquiring the second processed signal to obtain a plurality of second processed signals;

[0028] When the number of the second processed signals reaches a second number threshold, treating the plurality of second processed signals as a group of signals to be detected;

[0029] Based on the signal to be detected, it is determined whether an arc fault exists in the DC line.

[0030] In some embodiments, determining whether an arc fault exists in the DC line based on the signal to be detected includes:

[0031] Performing a fast Fourier transform on the signal to be detected to extract the corresponding frequency domain spatial feature quantity;

[0032] Inputting the frequency domain spatial feature quantity into an arc fault determination model to obtain a corresponding preliminary arc fault determination result;

[0033] Based on the preliminary arc fault determination result, it is determined whether an arc fault exists in the DC line.

[0034] In some embodiments, determining whether an arc fault occurs in the DC line based on the preliminary arc fault determination result includes:

[0035] Repeating the acquisition process of the signal to be detected to obtain multiple groups of the signal to be detected;

[0036] Based on the plurality of groups of signals to be detected, obtaining a plurality of preliminary arc fault determination results;

[0037] When the number of the preliminary arc fault determination results reaches a third number threshold, determining whether the number of the preliminary arc fault determination results indicating the presence of an arc fault reaches a fourth number threshold;

[0038] When the number of the preliminary arc fault determination results indicating the presence of an arc fault reaches a fourth number threshold, it is determined that an arc fault exists in the DC link.

[0039] In some embodiments, the arc fault determination model is a BP neural network model, which is trained based on frequency domain spatial feature quantities corresponding to sample signals, and the sample signals include sample signals with arc faults and sample signals without arc faults.

[0040] In a second aspect, a DC arc fault detection device is provided in this embodiment, the device comprising:

[0041] A signal sampling circuit, configured to obtain the pre-sampled signal based on pre-sampling of the electrical signal of the DC line; and further configured to obtain the target sampled signal based on target sampling of the electrical signal of the DC line;

[0042] a signal processing circuit configured to perform signal processing on the pre-sampled signal based on a preset initial gain to obtain a corresponding first processed signal; and to determine an optimized gain based on the first processed signal; and to perform signal processing on the target sampled signal based on the optimized gain to obtain a corresponding second processed signal;

[0043] A fault judgment circuit is used to determine whether an arc fault exists in the DC line based on the second processed signal.

[0044] In a third aspect, this embodiment provides a power system, which includes the DC arc fault detection device and a DC line as described in the second aspect.

[0045] The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0047] FIG1 is a schematic diagram of an application environment of a DC arc fault detection method according to some embodiments of the present application.

[0048] FIG2 is a flow chart of a DC arc fault detection method according to some embodiments of the present application.

[0049] FIG3 is a schematic diagram of DC arc fault detection in a photovoltaic system according to some embodiments of the present application.

[0050] FIG4 is a flowchart of determining an optimized gain based on a first processed signal according to some embodiments of the present application.

[0051] FIG5 is a flowchart of obtaining a first processed signal based on a pre-sampled signal in some embodiments of the present application.

[0052] FIG6 is a flowchart of obtaining a second processed signal based on a target sample signal in some embodiments of the present application.

[0053] FIG. 7 is a flowchart of determining an arc fault based on a second processed signal according to some embodiments of the present application.

[0054] FIG8 is a flowchart of determining an arc fault based on a signal to be detected according to some embodiments of the present application.

[0055] FIG9 is a flowchart of determining an arc fault based on a preliminary arc fault determination result according to some embodiments of the present application.

[0056] FIG10 is a flow chart of a DC arc fault detection method according to some optional embodiments of the present application.

[0057] FIG11 is a structural block diagram of a DC arc fault detection device according to some embodiments of the present application. DETAILED DESCRIPTION

[0058] In order to more clearly understand the purpose, technical solutions and advantages of this application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0059] Unless otherwise defined, the technical terms or scientific terms involved in this application should have the general meaning understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "an", "a", "the", "these" and the like in this application do not indicate quantitative restrictions, and they can be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application refers to two or more. "And / or" describes the relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. Generally, the character " / " indicates that the related objects are in an "or" relationship. The terms "first," "second," "third," etc. used in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0060] The DC arc fault detection method provided in the embodiments of the present application can be executed in a terminal, computer, or similar computing device, or in a controller of a power device. This controller can be a controller of a power device such as an inverter, optimizer, or circuit breaker in a photovoltaic system, or other controller in the photovoltaic system, without limitation in this embodiment. The controller, terminal, computer, etc. can receive, process, and transmit data related to electrical signals from the DC line.

[0061] When the method is applied to a terminal, a computer, or a similar computing device, FIG1 is a block diagram of the structure of the controller of the inverter that performs the DC arc fault detection method in some embodiments of the present application. As shown in FIG1 , the controller of the inverter may include one or more (only one is shown in FIG1 ) processors 102 and a memory 104 for storing data, wherein the processor 102 may include but is not limited to a digital signal processor DSP (Digital Signal Processing), a microprocessor MCU (Microcontroller Unit) or a programmable logic device FPGA (Field Programmable Gate Array) and other processing devices. The inverter can be a single-phase energy storage inverter, a three-phase energy storage inverter, a microinverter, a photovoltaic inverter, etc. The controller of the inverter may also include a transmission device 106 for communication functions, and the transmission device 106 can communicate with a host computer or the cloud. It will be understood by those skilled in the art that the structure shown in FIG1 is only for illustration and does not limit the structure of the controller. For example, the controller may also include more or fewer components than shown in FIG1 , or have a different configuration than shown in FIG1 .

[0062] The memory 104 can be used to store computer programs, such as software programs and modules of application software, such as the computer program corresponding to the DC arc fault detection method in this embodiment. The processor 102 executes the computer program stored in the memory 104 to execute various functional applications and data processing, thereby implementing the above-mentioned method. The memory 104 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some embodiments, the memory 104 may further include memory remotely located relative to the processor 102, and such remote memory may be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0063] In this embodiment, a DC arc fault detection method is provided. FIG2 is a flow chart of the DC arc fault detection method according to some embodiments of the present application. As shown in FIG2 , the flow chart includes the following steps:

[0064] Step S201 : Based on a preset initial gain, signal processing is performed on a pre-sampled signal to obtain a corresponding first processed signal, wherein the pre-sampled signal is obtained by pre-sampling an electrical signal of a DC line.

[0065] The DC line of this embodiment can be a DC line output by a photovoltaic panel in a photovoltaic system. Figure 3 is a schematic diagram of DC arc fault detection in a photovoltaic system in some embodiments of the present application. As shown in Figure 3, the DC power output by the photovoltaic panel PV is converted into AC power after being converted by an inverter. It will be understood by those skilled in the art that the structure shown in Figure 3 is only for illustration and does not limit the type of the above-mentioned DC line. The DC line can also be a line between a DC power supply and a power device in other power systems. The DC power supply can be a photovoltaic DC power supply, a fuel cell, or an energy storage battery. The power device can be an inverter, an optimizer, a circuit breaker, or other power devices.

[0066] The electrical signal of the DC line is pre-sampled to obtain a pre-sampled signal, and the pre-sampled signal is processed to obtain a first processed signal. The electrical signal may be a current signal or a voltage signal. The signal processing method may include filtering, amplification, A / D (Analog to Digital) conversion, and other processing methods. The signal amplification processing is performed based on an initial gain, which can be predetermined based on the approximate amplitude range of the pre-sampled signal and the input range of the A / D converter. The initial gain setting needs to avoid overflow of the amplified signal.

[0067] Step S202: determining an optimized gain based on the first processed signal.

[0068] The initial gain is adjusted to obtain an optimized gain, which can be determined according to the maximum amplitude of the first processed signal and the input range of the A / D converter.

[0069] Step S203 : Based on the optimized gain, signal processing is performed on the target sampling signal to obtain a corresponding second processed signal, where the target sampling signal is obtained by performing target sampling on the electrical signal of the DC line.

[0070] Target sampling is performed again on the electrical signal of the DC line to obtain a target sampled signal. The target sampling method can be the same as the pre-sampling method. The target sampled signal is processed to obtain a second processed signal. The signal processing method can include filtering, amplification, A / D conversion, and other processing methods. The signal amplification processing is performed based on the optimized gain.

[0071] Step S204: determining whether an arc fault exists in the DC line based on the second processed signal.

[0072] The second processed signal obtained by processing based on the optimized gain is used as data input for DC arc fault determination, and a determination result is obtained to determine whether an arc fault occurs in the DC line.

[0073] Through the above steps S201 to S204, the pre-sampled signal is processed based on a pre-set initial gain to obtain a corresponding first processed signal; the optimized gain is determined based on the first processed signal, and the initial gain is adjusted according to the amplitude of the first processed signal to obtain the optimized gain, thereby improving the matching degree between the gain coefficient and the sampled electrical signal; the target sampled signal is processed based on the optimized gain to obtain a corresponding second processed signal; and whether an arc fault exists in the DC line is determined based on the second processed signal, thereby improving the accuracy of arc fault judgment and solving the problems of signal overflow caused by excessive gain and weak signal and inaccurate detection caused by excessive gain.

[0074] In some embodiments, the number of pre-sampling is multiple times. FIG4 is a flow chart of determining the optimization gain based on the first processed signal in some embodiments of the present application. As shown in FIG4 , the flow chart includes the following steps:

[0075] Step S401 : Repeat the process of acquiring the first processed signal to obtain multiple first processed signals.

[0076] Step S201 can be repeated multiple times to pre-sample the electrical signal of the DC line multiple times to obtain multiple pre-sampled signals. Then, based on the initial gain, signal processing is performed on the multiple pre-sampled signals to obtain corresponding multiple first processed signals. Simultaneously, the number of pre-sampling times or the number of first processed signals is accumulated.

[0077] Step S402 : when the number of first processed signals reaches a first number threshold, determining a maximum amplitude among the plurality of first processed signals.

[0078] This embodiment does not limit the first quantity threshold, and can be set according to the requirements of detection accuracy. A maximum amplitude of a signal is determined from the plurality of first processed signals, and the maximum amplitude is obtained.

[0079] Step S403: determining the optimization gain based on the maximum amplitude.

[0080] An optimized gain is determined according to a maximum amplitude of the plurality of first processed signals and an input range of the A / D converter.

[0081] Through the above steps S401 to S403, by repeating the process of obtaining the first processed signal, multiple first processed signals are obtained, the maximum amplitude among the multiple first processed signals is determined, and based on the maximum amplitude, the optimized gain is determined, thereby improving the matching degree between the sampling signal of the DC link and the A / D converter, and improving the conversion accuracy of the A / D conversion of the sampling signal.

[0082] In some embodiments, FIG5 is a flow chart of obtaining a first processed signal based on a pre-sampled signal in some embodiments of the present application. As shown in FIG5 , the flow includes the following steps:

[0083] Step S501: filtering the pre-sampled signal.

[0084] In this embodiment, the pre-sampled signal obtained by pre-sampling can be filtered using a bandpass filter to retain electrical signals within a preset frequency range. The preset frequency range can be 21kHz-65kHz. Electrical signals in this frequency range contain a large amount of arc information. The bandpass filter can be composed of a high-pass filter and a low-pass filter.

[0085] Step S502 : amplifying the filtered pre-sampled signal based on the initial gain.

[0086] The filtered pre-sampled signal can be amplified by a signal amplifier, and the gain of the signal amplifier can be set according to the requirements. In this step, it is set as the initial gain.

[0087] Step S503 , performing A / D conversion on the amplified pre-sampled signal to obtain a first processed signal.

[0088] The amplified pre-sampled signal can be converted into a digital signal through an A / D converter, that is, a first processed signal is obtained, and the optimized gain is determined according to the amplitude of the first processed signal.

[0089] Through the above steps S501 to S503, the pre-sampled signal is filtered to retain the arc information in the pre-sampled signal and remove the noise in the pre-sampled signal; the filtered pre-sampled signal is amplified based on the initial gain to obtain an analog signal that can be A / D converted; and the amplified pre-sampled signal is A / D converted to obtain a first processed signal, which facilitates determining the optimized gain according to the amplitude of the first processed signal and improving the A / D conversion accuracy.

[0090] In some embodiments, FIG6 is a flow chart of obtaining a second processed signal based on a target sample signal in some embodiments of the present application. As shown in FIG6 , the flow includes the following steps:

[0091] Step S601: Filter the target sampling signal.

[0092] Similar to step S501, the target sampling signal obtained by the target sampling can be filtered by a bandpass filter to retain the electrical signal within a preset frequency range, which can be 21 kHz-65 kHz.

[0093] Step S602: amplify the filtered target sample signal based on the optimized gain.

[0094] Similar to step S502 , the filtered target sampled signal may be amplified by a signal amplifier, but in this step, the gain of the signal amplifier is set to an optimized gain.

[0095] Step S603 , performing A / D conversion on the amplified target sampling signal to obtain a second processed signal.

[0096] Similar to step S503, the amplified target sampling signal can be converted into a digital signal through an A / D converter, that is, a second processed signal is obtained, and the second processed signal is used as an input signal for DC arc fault determination for subsequent DC arc fault determination.

[0097] Through the above steps S601 to S603, the target sampling signal is filtered to retain the arc information in the target sampling signal and remove the noise in the target sampling signal; the filtered target sampling signal is amplified based on the optimized gain to obtain an analog signal that can be A / D converted, thereby improving the accuracy of subsequent A / D conversion; the amplified target sampling signal is A / D converted to obtain a second processed signal, which facilitates the subsequent extraction of time domain or frequency domain feature quantities of the second processed signal for DC arc fault judgment, thereby improving the accuracy of feature quantity extraction.

[0098] In some embodiments, the number of target sampling is multiple. FIG7 is a flow chart of determining an arc fault based on the second processed signal in some embodiments of the present application. As shown in FIG7 , the flow chart includes the following steps:

[0099] Step S701 : Repeat the process of acquiring the second processed signal to obtain multiple second processed signals.

[0100] Step S203 can be repeated multiple times to perform target sampling on the DC line electrical signal to obtain multiple target sampling signals. Signal processing is then performed on the multiple target sampling signals based on the optimized gain to obtain corresponding multiple second processed signals. The number of target samplings or the number of second processed signals is accumulated.

[0101] Step S702 : When the number of the second processed signals reaches a second number threshold, the plurality of second processed signals are taken as a group of signals to be detected.

[0102] This embodiment does not limit the second quantity threshold, and can be set according to the requirements of detection accuracy. The plurality of second processed signals are used as a group of signals to be detected, and as input signals for DC arc fault determination.

[0103] Step S703: Determine whether there is an arc fault in the DC line based on the signal to be detected.

[0104] It is possible to extract feature quantities in the time domain or frequency domain of the signal to be detected and determine whether an arc fault exists in the DC line based on the feature quantities.

[0105] Through the above steps S701 to S703, by repeating the process of obtaining the second processed signal, multiple second processed signals are obtained, and the multiple second processed signals are used as a group of signals to be detected, which facilitates the subsequent overall feature extraction; by determining whether there is an arc fault in the DC line based on the signals to be detected, and judging the arc fault based on the optimized processed signals, the accuracy of the DC arc fault judgment is improved.

[0106] In some embodiments, FIG8 is a flow chart of determining an arc fault based on a signal to be detected in some embodiments of the present application. As shown in FIG8 , the flow chart includes the following steps:

[0107] Step S801 : performing fast Fourier transform on the signal to be detected to extract the corresponding frequency domain spatial feature quantity.

[0108] Perform fast Fourier transform on a set of signals to be detected and extract feature quantities in the frequency domain.

[0109] Step S802 : Inputting the frequency domain spatial feature quantity into the arc fault determination model to obtain a corresponding preliminary arc fault determination result.

[0110] The frequency domain spatial feature quantities are input into an arc fault determination model. The arc fault determination model can be a binary classification model, and the output can be either 0 or 1, where 0 indicates that there is no arc fault on the DC line, and 1 indicates that there is an arc fault on the DC line. The arc fault determination model can be a neural network model or other deep learning model.

[0111] Step S803: Determine whether an arc fault exists in the DC line based on the preliminary arc fault determination result.

[0112] Through the above steps S801 to S803, by performing fast Fourier transform on the signal to be inspected, the corresponding frequency domain spatial feature quantity is extracted as the data basis for arc fault judgment; by inputting the frequency domain spatial feature quantity into the arc fault judgment model, the corresponding preliminary arc fault judgment result is obtained, and the arc fault judgment is performed through the deep learning model; by determining whether there is an arc fault in the DC line based on the preliminary arc fault judgment result, the accuracy of arc fault judgment is improved.

[0113] In some embodiments, FIG9 is a flow chart of determining an arc fault based on a preliminary arc fault determination result in some embodiments of the present application. As shown in FIG9 , the flow chart includes the following steps:

[0114] Step S901 , repeating the process of acquiring the signal to be detected to obtain multiple groups of signals to be detected.

[0115] After using the generated set of test signals as input signals for DC arc fault determination, the DC line electrical signals can be sampled and processed to generate multiple sets of test signals. Alternatively, multiple sampling and signal processing steps can be performed continuously to generate multiple sets of test signals before DC arc fault determination.

[0116] The process of obtaining a set of signals to be detected is to perform multiple pre-sampling and multiple target sampling, reset the gain of the signal amplifier to the initial gain during pre-sampling to obtain multiple first processed signals; determine the optimized gain based on the maximum amplitude of the first processed signal; and set the gain of the signal amplifier to the optimized gain during target sampling to obtain multiple second processed signals as a set of signals to be detected.

[0117] Step S902 : obtaining a plurality of preliminary arc fault determination results based on a plurality of groups of signals to be detected.

[0118] Multiple sets of test signals are sequentially input into the arc fault determination model to obtain corresponding preliminary arc fault determination results. The preliminary arc fault determination results can be 0 or 1, where 0 indicates a preliminary determination that no arc fault exists on the DC line, and 1 indicates a preliminary determination that an arc fault exists on the DC line. The number of preliminary arc fault determination results of 1 and the total number of determinations are accumulated.

[0119] Step S903 : When the number of preliminary arc fault determination results reaches the third number threshold, it is determined whether the number of preliminary arc fault determination results indicating the presence of an arc fault reaches a fourth number threshold.

[0120] The third number threshold may be preset as M, the fourth number threshold may be preset as N, and N may be smaller than M. When the total number of preliminary arc fault determinations reaches M, it is determined whether the number of determination results of 1 reaches N.

[0121] Step S904 : When the number of preliminary arc fault determination results indicating the presence of an arc fault reaches a fourth number threshold, it is determined that an arc fault exists in the DC line.

[0122] If the number of determination results that are 1 reaches N, it is finally determined that an arc fault exists in the DC line.

[0123] Through the above steps S901 to S904, multiple groups of signals to be detected are obtained by repeating the process of obtaining the signals to be detected, and the number of signals to be detected is increased through multiple sampling and signal processing, thereby expanding the feature quantity used as the model input; multiple preliminary arc fault determination results are obtained based on the multiple groups of signals to be detected, and the accuracy of the arc fault determination is improved by increasing the number of determinations; when the number of preliminary arc fault determination results reaches a third quantity threshold, it is determined whether the number of preliminary arc fault determination results indicating the existence of an arc fault reaches a fourth quantity threshold, thereby obtaining the occurrence rate of true determination results; when the number of preliminary arc fault determination results indicating the existence of an arc fault reaches a fourth quantity threshold, it is determined that an arc fault exists in the DC line, and when the occurrence rate reaches a predetermined threshold, it is determined that the fault exists, thereby improving the accuracy of the fault determination.

[0124] In some embodiments, after determining whether an arc fault exists on the DC line based on the second processed signal, the DC arc fault detection method further includes:

[0125] When it is determined that an arc fault exists in the DC line, a fault alarm is issued; or when it is determined that no arc fault exists in the DC line, arc fault detection of the DC line is continued.

[0126] When it is determined that there is an arc fault in the DC line, relevant personnel are informed through a fault warning to eliminate the DC arc fault; when it is determined that there is no arc fault in the DC line, the DC arc fault detection process of the above embodiment can be repeated, and detection can be continuously performed while the DC power supply is outputting DC power.

[0127] The DC arc fault detection method of this embodiment, when it is determined that an arc fault exists in the DC line, issues a fault alarm to remind relevant personnel to perform troubleshooting; when it is determined that no arc fault exists in the DC line, it continues to perform arc fault detection on the DC line, and continuously performs arc fault detection during the operation of the photovoltaic system, thereby improving the safety and stability of the photovoltaic system operation.

[0128] In some embodiments, the arc fault determination model is a BP (back propagation) neural network model, which is trained based on frequency domain spatial feature quantities corresponding to sample signals, and the sample signals include sample signals with arc faults and sample signals without arc faults.

[0129] A BP neural network model is used as the arc fault judgment model. The model can be supervised trained through sample signals. The frequency domain spatial feature quantities extracted from sample signals with arc faults and sample signals without arc faults are used as input data to train the model to obtain an arc fault judgment model, thereby improving the training speed of the arc fault judgment model and the accuracy of the judgment results.

[0130] This embodiment is described and illustrated below using alternative embodiments. The DC arc fault detection device of this embodiment includes a signal sampling circuit, a signal processing circuit, and a fault determination circuit. The signal sampling circuit samples a DC electrical signal and transmits the sampled electrical signal to the signal processing circuit. Specifically, the signal sampling circuit can use a transformer to sample the DC electrical signal.

[0131] The signal processing circuit processes the sampled DC electrical signal. The signal processing circuit includes a bandpass filter, a signal amplifier, an A / D converter, and a gain setting circuit. The gain setting circuit is used to adaptively set the gain of the signal amplifier.

[0132] The fault judgment circuit performs fast Fourier transform on each group of detected signals and obtains characteristic quantities, and judges arc faults through the arc fault BP neural network model. When it is judged that an arc fault occurs, an alarm message is sent to the user.

[0133] FIG10 is a flow chart of a DC arc fault detection method according to some optional embodiments of the present application. As shown in FIG10 , the flow chart includes the following steps:

[0134] Step S1001: The signal sampling circuit pre-samples the electrical signal of the DC line;

[0135] Step S1002: the signal processing circuit filters the pre-sampled signal through a bandpass filter;

[0136] Step S1003: the signal amplifier amplifies the filtered pre-sampled signal based on the initial gain;

[0137] Step S1004, performing A / D conversion on the amplified pre-sampled signal through an A / D converter to obtain a first processed signal;

[0138] Step S1005, determining whether the number i of the first processed signals reaches a first number threshold; if the result is "no", continue looping through steps S1001 to S1005; if the result is "yes", proceed to step S1006;

[0139] In step S1006, the gain setting circuit groups the received first processing signals, a first threshold number of which is received, into a group, detects a maximum amplitude therefrom, sets an optimized gain of the signal amplifier based on the maximum amplitude and the input range of the A / D converter, and resets the number i of the first processing signals to 0.

[0140] Step S1007: the signal sampling circuit performs target sampling on the electrical signal of the DC line;

[0141] Step S1008: the signal processing circuit filters the target sampled signal through a bandpass filter;

[0142] Step S1009: the signal amplifier amplifies the filtered target sample signal based on the optimized gain;

[0143] Step S1010, the amplified target sampling signal is A / D converted by an A / D converter to obtain a second processed signal;

[0144] Step S1011: The gain setting circuit determines whether the number s of the second processed signals reaches a second number threshold; if the result is "no", the steps S1007 to S1011 are looped; if the result is "yes", the circuit goes to step S1012;

[0145] Step S1012: The second processed signals of the second threshold number are input as a group of electrical signals to be detected to the fault judgment circuit; the gain setting circuit resets the gain of the signal amplifier to the initial gain; and resets the signal numbers i and s to 0; and the above steps S1001 to S1012 are repeated;

[0146] Step S1013: the fault judgment circuit performs FFT (fast Fourier transform) analysis on the received set of electrical signals to be detected;

[0147] Step S1014, extracting feature quantities in the frequency domain;

[0148] Step S1015: Input the characteristic value into the arc fault BP neural network model for preliminary judgment. The output result can be 0 or 1, where 0 indicates that the arc fault has not occurred and 1 indicates that the arc fault has occurred;

[0149] Step S1016, counting the number of preliminary arc fault judgment results m; setting a fault flag n, and executing an auto-increment algorithm on the fault flag n when the preliminary judgment result of the arc fault BP neural network model is that an arc fault exists;

[0150] Step S1017, setting a third threshold M and a fourth threshold N, wherein the fourth threshold N is smaller than the third threshold M. When the number of determinations m reaches the third threshold M, determining whether the fault flag n reaches the fourth threshold N;

[0151] Step S1018: If the fault flag n reaches the fourth threshold N, it is finally determined that an arc fault has occurred;

[0152] Step S1019: the fault judgment circuit issues a fault alarm signal;

[0153] Step S1020: If the fault flag n does not reach the fourth threshold N, it is finally determined that no arc fault has occurred;

[0154] Step S1021 : setting the DC arc fault determination times m and the fault flag n to 0, and re-performing the DC arc fault detection.

[0155] Through the above steps S1001 to S1021, multiple instantaneous electrical quantities of the DC line are obtained through multiple sampling and processing, thereby improving the integrity and effectiveness of the pre-sampling signal and the target sampling signal; the size of the initial gain is adjusted by the first processing signal to obtain the optimized gain, thereby improving the matching degree between the sampling signal of the DC line and the A / D converter, solving the problems of exceeding the A / D converter range due to excessive gain and poor A / D conversion accuracy and inaccurate detection due to excessive gain, thereby improving the detection accuracy; by extracting the frequency domain spatial feature quantity corresponding to the signal to be detected as the data basis for arc fault judgment; by increasing the number of judgments on the signal to be detected, the accuracy of arc fault judgment is improved.

[0156] It should be noted that the steps shown in the above process or the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0157] In some embodiments, the present application further provides a DC arc fault detection device. In some embodiments, FIG11 is a structural block diagram of the DC arc fault detection device of this embodiment. As shown in FIG11 , the device includes:

[0158] The signal sampling circuit 1101 is configured to obtain a pre-sampled signal based on pre-sampling of the electrical signal of the DC line; and further configured to obtain a target sampled signal based on target sampling of the electrical signal of the DC line;

[0159] The signal processing circuit 1102 is configured to perform signal processing on the pre-sampled signal based on a preset initial gain to obtain a corresponding first processed signal; determine an optimized gain based on the first processed signal; and further perform signal processing on the target sampled signal based on the optimized gain to obtain a corresponding second processed signal;

[0160] The fault judgment circuit 1103 is configured to determine whether an arc fault exists in the DC line based on the second processed signal.

[0161] The DC arc fault detection device of this embodiment pre-samples the electrical signal of the DC line through the signal sampling circuit 1101 to obtain a pre-sampled signal, and obtains a target sampled signal through target sampling. The signal processing circuit 1102 performs signal processing on the pre-sampled signal based on the initial gain to obtain a first processed signal, determines the optimized gain based on the first processed signal, and performs signal processing on the target sampled signal based on the optimized gain to obtain a second processed signal. The initial gain is adjusted according to the amplitude of the first processed signal to obtain the optimized gain, thereby improving the matching degree between the gain coefficient and the sampled electrical signal, and solving the problems of signal overflow caused by excessive gain and weak signal and inaccurate detection caused by excessive gain. The fault judgment circuit 1103 determines whether there is an arc fault in the DC line based on the second processed signal, thereby improving the accuracy of arc fault judgment.

[0162] In some embodiments, the signal processing circuit includes a filter, a signal amplifier, and an A / D converter. The filter is used to filter the pre-sampled signal or the target sampling signal; the signal amplifier is used to amplify the pre-sampled signal based on an initial gain, or to amplify the target sampling signal based on an optimized gain; and the A / D converter is used to perform A / D conversion on the amplified pre-sampled signal or the target sampling signal.

[0163] The DC arc fault detection device of this embodiment retains arc information in the pre-sampled signal through a filter and removes noise in the pre-sampled signal; obtains an analog signal that can be A / D converted through a signal amplifier; and obtains a digital electrical signal through an A / D converter, which facilitates the subsequent extraction of time domain or frequency domain feature quantities for DC arc fault judgment, thereby improving the accuracy of feature quantity extraction.

[0164] In some embodiments, the signal processing circuit further includes a gain setting circuit, which is configured to determine a maximum amplitude among the plurality of first processed signals when the number of the first processed signals reaches a first number threshold, and determine an optimized gain based on the maximum amplitude.

[0165] The DC arc fault detection device of this embodiment determines the maximum amplitude among multiple first processed signals through a gain setting circuit, thereby improving the accuracy of the maximum amplitude of the signal; improving the matching degree between the sampling signal of the DC line and the A / D converter, and improving the conversion accuracy of the A / D conversion of the sampling signal.

[0166] In some embodiments, the fault judgment circuit includes a feature extraction circuit and a fault judgment circuit. The feature extraction circuit is used to perform fast Fourier transform on the signal to be detected to extract the corresponding frequency domain spatial feature; the fault judgment circuit is used to input the frequency domain spatial feature into the arc fault judgment model to obtain the corresponding preliminary arc fault judgment result.

[0167] The DC arc fault detection device of this embodiment performs fast Fourier transform on the signal to be detected through a feature extraction circuit to extract the corresponding frequency domain spatial feature as the data basis for arc fault judgment; the fault judgment circuit performs arc fault judgment through a deep learning model, thereby improving the accuracy of arc fault judgment.

[0168] In some embodiments, the present application further provides a power system, which includes the DC arc fault detection device and a DC line according to the above embodiment.

[0169] The power system of this embodiment provides DC power to power equipment through a DC line, detects whether there is an arc fault in the DC line through a DC arc fault detection device, and continuously performs arc fault detection during the operation of the power system, thereby improving the safety and stability of the power system operation.

[0170] In addition, in conjunction with the DC arc fault detection method provided in the above embodiments, a readable storage medium may be provided in this embodiment to implement the method. The readable storage medium stores a program that, when executed by a processor, implements any of the DC arc fault detection methods in the above embodiments.

[0171] It should be noted that, for specific examples in this embodiment, reference may be made to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0172] It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0173] Obviously, the accompanying drawings are merely examples or embodiments of the present application. A person skilled in the art can also apply the present application to other similar situations based on these drawings without inventive effort. Furthermore, it is understandable that, although the work involved in this development process may be complex and lengthy, certain design, manufacturing, or production changes based on the technical content disclosed in this application are merely routine technical means for a person skilled in the art and should not be considered to constitute a deficiency in the disclosure of the present application.

[0174] The term "embodiment" as used in this application refers to specific features, structures, or characteristics described in conjunction with the embodiment that can be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily mean that the embodiment is the same, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is understood, either explicitly or implicitly, by those skilled in the art that the embodiments described in this application can be combined with other embodiments when there is no conflict.

[0175] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of patent protection. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A DC arc fault detection method, characterized in that: The method comprises: Based on a preset initial gain, performing signal processing on a pre-sampled signal to obtain a corresponding first processed signal, wherein the pre-sampled signal is obtained by pre-sampling an electrical signal of a DC line; determining an optimized gain based on the first processed signal; Based on the optimized gain, signal processing is performed on a target sampling signal to obtain a corresponding second processed signal, wherein the target sampling signal is obtained based on target sampling of an electrical signal of the DC line; Based on the second processed signal, it is determined whether an arc fault exists in the DC line.

2. The method according to claim 1, wherein: The number of pre-sampling is multiple times, and the determining of the optimization gain based on the first processed signal includes: Repeating the process of acquiring the first processed signal to obtain a plurality of the first processed signals; In the case where the number of the first processed signals reaches a first number threshold, determining a maximum amplitude among the plurality of the first processed signals; Based on the maximum amplitude, the optimization gain is determined.

3. The method according to claim 1, wherein: The performing signal processing on the pre-sampled signal based on the preset initial gain to obtain the corresponding first processed signal includes: filtering the pre-sampled signal; Amplifying the filtered pre-sampled signal based on the initial gain; The amplified pre-sampled signal is A / D converted to obtain the first processed signal.

4. The method according to claim 1, wherein: The performing signal processing on the target sampled signal based on the optimized gain to obtain a corresponding second processed signal comprises: filtering the target sampling signal; Based on the optimized gain, amplifying the filtered target sampling signal; The amplified target sampling signal is subjected to A / D conversion to obtain the second processed signal.

5. The method according to claim 1, wherein: The target sampling times are multiple times, and the determining whether there is an arc fault in the DC line based on the second processed signal includes: Repeating the process of acquiring the second processed signal to obtain a plurality of the second processed signals; When the number of the second processed signals reaches a second number threshold, taking the plurality of second processed signals as a group of signals to be detected; Based on the signal to be detected, it is determined whether an arc fault exists in the DC line.

6. The method according to claim 5, wherein: The determining whether there is an arc fault in the DC line based on the signal to be detected includes: Performing a fast Fourier transform on the signal to be detected to extract the corresponding frequency domain spatial feature quantity; Inputting the frequency domain spatial feature quantity into an arc fault determination model to obtain a corresponding preliminary arc fault determination result; Based on the preliminary arc fault determination result, it is determined whether an arc fault exists in the DC line.

7. The method according to claim 6, wherein: The determining whether there is an arc fault in the DC line based on the preliminary arc fault determination result includes: Repeating the process of acquiring the signal to be detected to obtain multiple groups of the signal to be detected; Based on the plurality of groups of the signals to be detected, a plurality of preliminary arc fault determination results are obtained; In the case where the number of the preliminary arc fault determination results reaches a third number threshold, determining whether the number of the preliminary arc fault determination results with a result of the presence of an arc fault reaches a fourth number threshold; When the number of the preliminary arc fault determination results indicating the presence of an arc fault reaches a fourth number threshold, it is determined that an arc fault exists in the DC line.

8. The method according to claim 6, wherein: The arc fault determination model is a BP neural network model, which is obtained by training based on frequency domain spatial feature quantities corresponding to sample signals, and the sample signals include sample signals with arc faults and sample signals without arc faults.

9. A DC arc fault detection device, characterized in that: The device comprises: A signal sampling circuit, used for obtaining the pre-sampling signal based on pre-sampling the electrical signal of the DC line; and also used for obtaining the target sampling signal based on target sampling of the electrical signal of the DC line; A signal processing circuit, configured to perform signal processing on the pre-sampled signal based on a preset initial gain to obtain a corresponding first processed signal; and to determine an optimized gain based on the first processed signal; and to perform signal processing on the target sampled signal based on the optimized gain to obtain a corresponding second processed signal; A fault judgment circuit is used to determine whether there is an arc fault in the DC line based on the second processed signal.

10. A power system, characterized in that: The power system comprises the DC arc fault detection device as claimed in claim 9 and a DC line.

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