Display having selectable drive-current level for pixels

Abstract

A micro-LED display including a plurality of current sources is disclosed. Each pixel includes a plurality of switches coupled to the plurality of current sources which can be selectively connected in parallel to supply a drive current at different levels to the pixels to make the light emitted by the micro-LED display more uniform.

Description

DISPLAY HAVING SELECTABLE DRIVE-CURRENT LEVEL FOR PIXELSCROSS-REFERENCE TO RELATED APPLICATION

[0001] The application claims the benefit of U.S. Provisional Application No. 63 / 519,015 filed on August 11, 2023, which is hereby incorporated by reference in its entirety.FIELD OF THE DISCLOSURE

[0002] The present disclosure relates to a display including micron-sized, light-emitting diodes (micro-LEDs) used as pixels and more specifically to adjusting the drive current used to drive the micro-LEDs to illuminate.BACKGROUND

[0003] A micro-LED display includes pixels that have a switch for toggling the illumination ON / OFF at a high rate to encode a grayscale level onto the light emitted by the pixel. The pixel may further include a static random-access memory cell (i.e., SRAM) for each pixel that can hold the state of the switch to maintain the illumination of the pixel between the toggling. One current source can be used by all the pixels to supply the drive current conducted by the switch for the illumination.SUMMARY

[0004] Variations in the micro-LED performance can lead to intensity (i.e., brightness) variations between pixels. The present disclosure describes a display that includes a selectable drive-current level to compensate for the variations in the intensity between pixels.

[0005] In some aspects, the techniques described herein relate to a display including: a pixel array, wherein a plurality of pixels in the pixel array include: a micro light emitting diode (micro-LED) configured to radiate a light based on a drive current; and a plurality of switches coupled between a plurality of current sources and the micro-LED and configured according to a switch configuration to receive a pulse width modulation signal (PWM-signal) or an OFF-signal, wherein a level of the drive current for a pixel is determined by the switch configuration for the pixel.

[0006] In some aspects, the techniques described herein relate to a method for controlling a display, the method including; determining a level of a drive current for a plurality of pixels in the display; determining a switch configuration for a plurality of switches within each pixel of the plurality of pixels based on the level of the drive current; coupling an OFF-signal or a pulse width modulation signal (PWM-signal) to the plurality of switches based on the switch configuration for each pixel; and driving each pixel of the plurality of pixels to illuminate light, the drive current for each pixel having a level selected from a plurality of possible levels based on the switch configuration for each pixel.

[0007] In some aspects, the techniques described herein relate to a pixel for a display including: a micro light emitting diode (micro-LED); a first switch coupled between the microLED and a first current source; a second switch coupled between the micro-LED and a second current source; a first bit-line coupled to a first static random access memory (SRAM), the first SRAM coupled between the first bit-line and a first controlling terminal of the first switch; and a second bit-line coupled to a second SRAM, the second SRAM coupled between the second bit- line and a second controlling terminal of the second switch, wherein a drive current on the micro-LED is determined based on a switch configuration of the first switch and the second switch.

[0008] The foregoing illustrative summary, as well as other exemplary objectives and / or advantages of the disclosure, and the manner in which the same are accomplished, are further explained within the following detailed description and its accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. l is a micro-LED display according to a possible implementation of the present disclosure.

[0010] FIG. 2 is a schematic of a portion of a pixel for a micro-LED display according to a possible implementation of the present disclosure.

[0011] FIG. 3 is a histogram illustrating a possible variation in brightness of pixels in a micro-LED display.

[0012] FIG. 4 is a chart illustrating drive current levels to compensate for the possible variation in brightness shown in FIG. 3.

[0013] FIG. 5 is a schematic of a pixel with a selectable drive current according to a possible implementation of the present disclosure.

[0014] FIG. 6A is a table illustrating switch configurations and drive currents of a pixel having two switches according to a possible implementation of the present disclosure.

[0015] FIG. 6B illustrates a PWM signal according to a possible implementation of the present disclosure.

[0016] FIG. 7 illustrates a switch-configuration encoder according to a possible implementation of the present disclosure.

[0017] FIG. 8 is a flowchart of a method for controlling a display according to a possible implementation of the present disclosure.

[0018] The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.DETAILED DESCRIPTION

[0019] A micro-LED display may include millions of pixels, each having dimensions that are a few micrometers (e.g., < 10 microns). The display may include pixels that are all configured to radiate light of the same color (e.g., red) or may include pixels (e.g., subpixels) that are configured to radiate light in the principal components of white light (e.g., red, blue, green). In any case, the light emitted by each pixel can be generated by a light emitting diode (LED). The light is radiated at a brightness that ideally is uniform (i.e., constant) over the entire area of the pixel array. When the brightness is uniform, then the pixels may be modulated ON / OFF according to a pulse-width modulation (PWM) signal so that the pixels may faithfully represent the gray levels of an image for display.

[0020] A technical problem facing the micro-LED is that variations in the micro-LEDs of the display may cause variations in the brightness, which can lead to errors in this gray scale representation. These variations (i.e., process corners) may result from fabrication variations, circuit variations (e.g., location in the pixel array), and / or environmental variations (e.g., temperature). Adjusting the drive current to compensate for the brightness variations may be problematic when one current source is used to supply the current to all the pixels. For example, increasing the drive current to brighten darker pixels may result in overdriving brighter pixels. The light illuminated by pixels that are over driven may be shifted (e.g., decreased) inwavelength. As a result, this compensation approach has the technical problem of exchanging brightness variations with wavelength (i.e., color) variations. The present disclosure describes a display to address these technical problems. The disclosed display includes a selectable drive current for each pixel so that (i) the brightness of the pixels can be within an acceptable brightness range and (ii) the color of the pixels can be within an acceptable wavelength range.

[0021] FIG. 1 is a schematic block diagram of a display according to a possible implementation of the present disclosure. The display 100 includes a plurality of pixels arranged in a 2D grid (i.e., pixel array 130). Each pixel 200 may be configured to generate light while conducting a drive current from a drive current module 140, which as will be discussed, can include multiple current sources. Each pixel includes at least one memory cell (e.g., static random-access memory (SRAM)).

[0022] A state of the SRAM corresponds to the illumination state of the LED. The state of an SRAM for a pixel may be controlled (i.e., set / reset) by a signal (e.g., PWM signal) transmitted on a bit line coupled to the SRAM. Each pixel may include multiple SRAMs each having a corresponding bit line. When multiple SRAMs of the pixel receive the PWM signal, the states are controlled identically.

[0023] As shown in FIG. 1, the display 100 further includes a word-line driver 110 configured to transmit a word-line signal to a word-line (i.e., row) of the pixel array 130. The word-line signal can activate a row so that each pixel in the activated row is coupled to its respective bit line(s).

[0024] As shown in FIG. 1, the display 100 further includes a bit-line driver 120 configured to transmit bit-line signals to the bit-lines of the pixels in an activated row. The bit line signals may change or maintain the state of the SRAM(s) of each pixel in the activated row. In a possible implementation, a bit-line signal is a differential signal. In this case, each bit-line may include a positive bit-line (BL+) configured to carry a positive bit-line signal and a negative bit- line configured to carry a negative bit-line signal (BL-). In this differential configuration, the positive bit-line and the negative bit-line may be referred to collectively as a bit line. Each pixel may include multiple bit-lines (e.g., one for each SRAM). Each of the multiple bit-lines may be in this differential configuration.

[0025] The display 100 further includes a controller 101 configured to control the operation of the word-line driver 110 and the bit-line driver 120. The controller may be configured tocontrol the operation to display content (i.e., images, frames, cells) on a frame-by-frame basis. Each frame may be rendered on the pixel array 130 on a row-by-row basis, and the memory cell(s) (i.e., SRAM(s)) for each pixel may hold the pixels of a row ON (illuminated) or OFF (not illuminated) while the other rows of the frame are rendered.

[0026] The controller 101 may be further configured to receive content for display and to generate a PWM signal for each pixel based on the content. A PWM signal can be transmitted to the bit line of a particular pixel using the row / column selection described above. When the particular pixel includes multiple bit lines, then a switch encoder 150 may be used to route the PWM signal to the appropriate bit lines of the particular pixel. The appropriate bit lines may be determined based on a switch configuration for the particular pixel.

[0027] As shown in FIG. 1, the display 100 may further include a memory 160. The memory 160 may be configured to store a switch configuration for each pixel. A switch configuration, recalled (i.e., read) from the memory 160, can configure the switch encoder 150 to route a PWM-signal to the active switches (i.e., SRAM(s)) of a pixel. The inactive active switches can receive no signal or an OFF-signal to maintain their inactive state. Accordingly, the switch encoder 150 may be configured to route an OFF-signal to inactive switches (i.e., SRAM(s)) of the pixel)

[0028] The switch encoder 150 may be implemented variously. For example, the switch encoder 150 may be implemented as a logic circuit external to the controller 101 or as a software program executed by (i.e., internal to) the controller 101.

[0029] In an alternate implementation, each pixel can include a local memory (e.g., SRAM) to store its switch configuration and a local switch encoder (e.g., logic circuit) to route signals on a bit-line to the appropriate switches within a pixel. An advantage of this implementation is that each pixel only requires one bit line, while a disadvantage of this implementation is that the size of the pixel must accommodate the added local memory and local switch encoder. For pixels that are less than 10 microns in length and width, the multiple bit-line implementation may be preferred.

[0030] FIG. 2 is a schematic of a portion of a pixel for a micro-LED display according to a possible implementation of the present disclosure. To simplify the discussion, the portion includes one switch and one SRAM (i.e., one switch / SRAM pair). The disclosed pixel, however,can include multiple switch / SRAM pairs that each operate as described with the single switch / SRAM pair implementation shown in FIG. 2.

[0031] As shown in FIG. 2, the pixel 200 includes a switch 220 coupled between a microLED 210 and a current source 221. The current source 221 may be part of the drive current module 140 shown in FIG. 1. The switch 220 can be in a short circuit state (i.e., ON-condition) so that the micro-LED 210 is illuminated (i.e., generates light) by the current of the current source 221. Alternatively, the switch 220 can be in an open circuit state (i.e., OFF-condition) so that the micro-LED 210 is dark because it receives no current.

[0032] As shown in FIG. 2, the switch 220 can be controlled ON or OFF according to the state (i.e., the stored value) of a static random-access memory (SRAM 250) cell. The SRAM 250 receives power for operation from a power supply 211 which is coupled to each pixel of the pixel array 130. The SRAM 250 may be configured to output a HIGH voltage (e.g., VDD) while in a HIGH state (i.e., ON-state) or output a LOW voltage (e.g., ground) while in a LOW state (i.e., OFF-state). An advantage of using an SRAM 250 to control the switch 220 is that while the SRAM 250 is in the HIGH-state (i.e., ON-state) or the LOW-state (i.e., OFF-state) it consumes very little current (e.g., approximately zero current) from the power supply 211. The SRAM 250 draws most of its current (e.g., approximately all of its current) as it transitions (i.e., is flipped) between states (i.e., during a write process).

[0033] As shown in FIG. 2, the SRAM 250 includes two inverters (i.e., a pair of inverters) coupled in parallel with their polarities reversed (i.e., coupled output to input). The pair of inverters function as a digital latch circuit (i.e., latch 213). A write process (i.e., write operation) configures latch 213 into one of two states: an ON-state to output a signal corresponding to a logical HIGH (i.e., 1) and an OFF-state to output a signal corresponding to a logical LOW (i.e., 0).

[0034] As shown in FIG. 2, the pixel 200 further includes a bit line 215, and the state of the SRAM 250 may be flipped by bit-line signals (BL+, BL-) applied to the bit line 215. During the write process, the signals (BL+, BL-) are set to assert the desired state onto the latch 213. Once the desired state is set, the output of the latch 213 is stable and the signals (BL+, BL-) may be removed.

[0035] As shown in FIG. 2, the pixel 200 further includes a word line 214. During the write process, the latch circuit is coupled to the positive / negative signals of the bit line 215 by switchescontrolled by a signal (WL) transmitted on a word line 214. For example, a first level (e.g., HIGH) on the word line 214 turns the switches ON to couple the input / output of latch 213 to respective positive / negative lines of the bit line 215. A second level (e.g., LOW) on the word line 214 turns the switches OFF to decouple the input / output of the latch 213 from the bit-line drivers so that the state is stored. The state of the SRAM 250 appears as a voltage at the output of one of the inverters of the latch 213.

[0036] Changing the state of the latch (i.e., flipping the latch) can include changing the ON / OFF condition of the transistors. While the transistors are changing their condition (i.e., transitioning), a low-resistance path to ground 212 may be created, and a shoot-through current may flow from the power supply 211 to the SRAM 250 until the transition is completed. This shoot-through current may be relatively large and corresponds to a power loss associated with the write process. Limiting the current can avoid wasted power during the writing process (i.e., write mode), which can reduce an overall power consumed by the SRAM cell over time. For a memory including many SRAM cells (e.g., 2 million) the cumulative reduction in power can be significant.

[0037] The pixel 200 can include a current-limiting transistor 275 to limit the current drawn by the SRAM during a write process. The current-limiting transistor 275 is biased according to the power supply 211 (VDD) and a bias voltage (VBIAS) to be in a partially-ON (i.e., partially- OFF) condition during the write process to clamp the current drawn by the SRAM 250. In a partially-ON condition, the current-limiting transistor 275 conducts current at a limited level (Iw) between a short circuit level (i.e., fully-ON) and an open circuit level (i.e., fully-OFF). The conduction condition of the current-limiting transistor 275 is based on the gate-source voltage (VGS), as shown in FIG. 2. Accordingly, the limited level (Iw) drawn by the SRAM 250 is related to a bias voltage (VBIAS) applied to a controlling terminal of the current-limiting transistor 275.

[0038] The current-limiting transistor 275 may be implemented as a p-type metal oxide semiconductor transistor (i.e., PMOS transistor) that has a source terminal coupled to the power supply 211, a drain terminal coupled to the SRAM 250, and a gate terminal coupled to a driver. The driver may serve the entire pixel array. For each pixel, the driver can output a bias voltage (VBIAS) to configure the current-limiting transistor 275 in a partially-ON condition to limit the current drawn by the SRAM 250 during a writing period of the SRAM 250.

[0039] FIG. 3 illustrates a histogram of the pixel brightness for pixels in a pixel array 130 that are driven at the same current level (Io). While the pixel 200 is in an ON-condition, a brightness (i.e., intensity, nits, lumens) of the light generated by the micro-LED 210 (i.e., the pixel brightness) is set by a level of the current source 221.

[0040] Pixels in a pixel array 130 are designed to radiate light at a nominal brightness 301 (Bo) when driven by a current source at a current level (Io). In practice, the actual brightness of the pixels will vary so that some pixels will radiate in a range of brightnesses that is higher than the nominal brightness (Bo) and some pixels will radiate in a range of brightnesses that is less than the nominal brightness (Bo).

[0041] As shown in FIG. 3, the brightness of the pixels can form a distribution (e.g., normal distribution) around the nominal brightness 301 (Bo). As shown, some pixels will radiate light that is below a minimum brightness threshold (BMIN). The minimum brightness threshold (BMIN) may be based on a noticeable error (e.g., grayscale error) in the displayed image. Simply, increasing (i.e., boosting) the drive current (e.g., Io + Al) for all pixels in the pixel array can raise all the pixels above the minimum brightness threshold (BMIN) but could force some pixels above a maximum brightness threshold (BMAX).

[0042] The maximum brightness threshold (BMAX) may be based on an overdrive condition of the micro-LED 210. When overdriven, the light emitted by a micro-LED may shift from its nominal color (i.e., nominal wavelength). For example, a red pixel that is overdriven with too much drive current may appear as orange. In other words, the wavelength(s) of the pixel may shift when it is overdriven so that the color of the pixel is outside an acceptable wavelength range. These changes in color can create noticeable color errors in a displayed image.

[0043] To avoid brightness errors and color errors in displayed content, all pixels of the display may be driven so that they radiate light at a wavelength (i.e., color) that is within an acceptable wavelength range. Accordingly, it may be necessary to increase the drive current of pixels in a low-brightness range 321 but not increase the drive current for pixels in a high- brightness range 323.

[0044] What is more, some pixels may have the drive current decreased (e.g., Io - Al) so that the variation in brightness may be further reduced. In other words, control of the drive current at the pixel level can drive the pixels so that they all have a brightness within an acceptable brightness range 322.

[0045] With reference to FIG. 3, the drive current of a first group of pixels in the low- brightness range 321 may be increased (e.g., Io + Al) so that the first group of pixels radiate within the acceptable brightness range 322. The drive current of a second group of pixels in the high-brightness range 323 can be reduced (e.g., Io - Al) so that the second group of pixels radiate within the acceptable brightness range 322. After these adjustments all micro-LEDs of the pixel array 130 are configured to radiate light at brightnesses within an acceptable brightness range 322. Further, because the adjustments do not over drive the micro-LEDs, all pixels radiate light at wavelengths (i.e., colors) that are within an acceptable wavelength range.

[0046] The acceptable wavelength range and the acceptable brightness range 322 may be determined empirically or in simulation. For example, the acceptable ranges may be based on a user’s perception of errors in a set of test images displayed on the display during a process (i.e., calibration process) for the display. This process may be performed prior to the display being used by a user.

[0047] FIG. 4 is a chart illustrating drive current levels to compensate for the possible variation in brightness shown in FIG. 3. As shown, a first group of pixels 421 may require a high drive current level (HIGH) for compensation. The high drive current level is higher than the design (i.e., nominal) current level (DESIGN) due to the pixels in the first group having brightnesses that are in the low-brightness range 321. A second group of pixels 423 may require a low drive current level (LOW) for compensation. The low drive current level is lower than the design current level (DESIGN) due to the pixels in this group having brightnesses that are in the high-brightness range 323. A third group of pixels 422 may require the design current level (DESIGN) because the pixels in the third group radiate at brightnesses that are within the acceptable brightness range 322

[0048] As shown in FIG. 4, adjusting the brightness levels of the pixel array 130 can include selecting a current level for a pixel from a plurality of discrete current levels. As shown, three current levels may be used for adjusting the brightness levels of pixels in a pixel array 130. The discrete levels may be related (e.g., scale values) or may be unrelated. As shown in FIG. 4, the HIGH level and the LOW level may deviate from the DESIGN level by different amounts.

[0049] The three drive current levels may be generated using two current sources. In a possible implementation, the drive current module 140 includes two current sources: a first current source (Ii) and a second current source (E). In a possible implementation, the levels ofthe two current sources are different. The low drive current level (LOW) for a pixel may be generated by coupling the pixel to the first current source (Ii). The design drive current level (DESIGN) for a pixel may be generated by coupling the pixel to the second current source (I2). The high drive current level (HIGH) may be generated by coupling both the first current source (Ii) and the second current source (I2) to the pixel (i.e., I1+I2). No current (i.e., OFF-condition) may be considered a fourth drive current level. The fourth drive current level for a pixel may be generated by decoupling both the first current source (Ii) and the second current source (I2) from the pixel.

[0050] FIG. 5 is a schematic of a pixel with a selectable drive current according to a possible implementation of the present disclosure. The pixel 500 may be a pixel in a pixel array for a display. In a possible implementation, each pixel of the pixel array is the substantially same as the pixel shown in FIG 5. Alternatively, a portion of the pixels (e g., red pixels) in the pixel array may be the same as the pixel 500 shown in FIG. 5.

[0051] As shown, a pixel 500 includes a micro-LED 510 coupled between a drive node 523 and a ground 530. The micro-LED is configured to radiate light at an intensity and a color (i.e., wavelength) based on a drive current (IDRIVE). The plurality of current sources may be coupled in a parallel connection between the power supply 520 and the drive node 523 by a plurality of switches. As shown, the pixel 500 further includes a pair of switches coupled between a pair of current sources and drive node 523 of the micro-LED 510. A first switch 511 is configured to couple a first current source 521 to the drive node 523 (i.e., the micro-LED) and a second switch 512 is configured to couple a second current source 522 to the drive node 523 (i.e., micro-LED). When both current sources are coupled, the currents from each current source combine (i.e., add, sum) at the drive node 523.

[0052] The pixel 500 further includes an SRAM cell (i.e., SRAM) for each switch and a bit line for each SRAM. As shown, the pixel 500 includes two SRAMs and two bit lines. The pixel 500 includes a first SRAM 501 coupled between a first bit-line 531 and the first switch 511. The pixel 500 further includes a second SRAM 502 coupled between a second bit-line 532 and the second switch 512. When enabled by a word-line signal (WL) on a word line 514, the first SRAM 501 is configured to receive a first bit-line signal (BL1) from the first bit-line 531, and the second SRAM 502 is configured to receive a second bit-line signal (BL2) from the second bit-line 532. The first bit-line signal and the second bit-line signal can determine a switchconfiguration for the pixel. The level of the drive current (IDRIVE) is selected based on the switch configuration.

[0053] The first bit-line signal (BL1) and the second bit-line signal (BL2) can be an OFF- signal. The OFF-signal received at the first bit -line 531 can configure the first switch 511 in an OFF condition so that the drive current (IDRIVE) does not include current from the first current source 521. The OFF-signal received at the second bit-line 532 can configure the second switch 512 in the OFF condition so that the drive current (IDRIVE) does not include current from the second current source 522.

[0054] The first bit-line signal (BL1) and the second bit-line signal (BL2) can be a PWM- signal. The PWM-signal toggles between an ON-state and an OFF-state (i.e., ON / OFF) each cycle of the PWM-signal. The PWM-signal received at the first bit-line 531 can toggle the first switch 511 ON / OFF so that the drive current (IDRIVE) while in the ON condition includes current from the first current source 521. The PWM-signal received at the second bit-line 532 can toggle the second switch 512 ON / OFF so that the drive current (IDRIVE) while in the ON condition includes current from the second current source 522. When each bit line receives the PWM-signal, then the switches may be toggled in unison according to the PWM-signal.

[0055] FIG. 6A is a table illustrating switch configurations and drive current levels of a pixel having two switches according to a possible implementation of the present disclosure. The switch configuration for the two-switch implementation may be represented as a 2 -bit binary string, where each bit corresponds to a switch being active (i.e., 1) or inactive (i.e., 0). In a first switch configuration (i.e., 10) the first switch receives the PWM-signal (i.e., ON / OFF) and the second switch receives the OFF-signal (i.e., OFF). In the first switch configuration (i.e., 10) the drive current (in the ON condition) is the current (Ii) from the first current source 521. In a second switch configuration (i.e., 01) the second switch receives the PWM-signal (i.e., ON / OFF) and the first switch receives the OFF-signal (i.e., OFF). In the second switch configuration (i.e., 01) the drive current (in the ON condition) is the current (b) from the second current source 522. In a third switch configuration (i.e., 11) the first switch receives the PWM-signal (i.e., ON / OFF) and the second switch receives the PWM-signal (i.e., ON / OFF). In the third switch configuration (i.e., 11) the drive current (in the ON condition) is the sum of currents from the first current source 521 and the second current source 522 (i.e., Ii+b).

[0056] The switch configuration (e.g., 10, 01, 1 1) for a pixel may be determined using a calibration process. The calibration process may include driving the pixel at a current level to generate an illumination (i.e., generate light). The calibration process may further include measuring a brightness of the illumination and comparing the brightness to an acceptable brightness range, and based on this comparison, the switch configuration for the pixel may be determined. The calibration process may include storing the switch configurations for each pixel in a memory. The calibration process may be performed (e.g., at a factory) prior to use of the display (e.g., by a user). The switch configuration for a pixel may be recalled from the memory (e.g., during use) and used to route the PWM signals to the appropriate switch (or switches) of the pixel.

[0057] FIG. 6B illustrates a PWM signal according to a possible implementation of the present disclosure. The PWM signal may alternate between a HIGH level (i.e., high voltage) and a LOW level (i.e. low voltage) during a PWM cycle 601. The HIGH level may correspond to an ON-state of an SRAM (i.e., switch) and the LOW level may correspond to an OFF-state of the SRAM (i.e., switch). The PWM signal has an ON period 602 and an OFF period 603. An average intensity of the light from the pixel may correspond to the duty cycle of a PWM cycle 601. The duty cycle may be the ratio of the ON period 602 to the overall period of the PWM cycle 601.

[0058] FIG. 7 illustrates a switch-configuration encoder according to a possible implementation of the present disclosure. As mentioned, the display 100 may include a switch encoder 150 configured to generate the bit-line signals for a pixel according to a switch configuration of the pixel. The switch encoder 150 may include a logic circuit (or equivalent software) to route a PWM signal from a controller to the bit lines of a pixel.

[0059] For the two-switch configuration discussed in FIG. 5, two AND gates may be used in the switch encoder 150. A first input of each AND gate may receive a bit of the switch configuration (e.g., from the memory 160). A second input of each AND gate may receive a PWM signal (e.g., from the controller 101). As shown, a possible switch configuration of 10 results in the first bit-line 531 receiving the PWM signal and the second bit-line 532 receiving the OFF signal.

[0060] FIG. 8 is a flowchart of a method for controlling a display according to a possible implementation of the present disclosure. The method 800 includes determining 810 drivecurrent levels suitable (e.g., required) for the pixels in a display to radiate light within and acceptable range (e.g., brightness range and / or wavelength range). There may be a plurality of current sources that can be used by each pixel. As a result, the determination may include selecting which current sources will be used by the pixel to generate the appropriate drive current level. The method 800 further includes determining 820 a switch configuration for each pixel based on its drive current level. For example, each pixel includes a plurality of switches coupled to the plurality of current sources and each switch configuration is the combination of active and inactive switches in the pixel. The method further includes coupling 830 an OFF-signal to inactive switches and a PWM-signal to active switches of each pixel based on its switch configuration so that the micro-LED of the pixel receives current from the active switches. The method 800 further includes driving 840 each pixel to illuminate light that is in an acceptable range using a drive current provided by the active switches.

[0061] Any of the steps in the method may be implemented, at least in part, by software. These implementations can include a non-transitory computer-readable storage medium comprising instructions stored thereon that, when executed by at least one processor, are configured to cause a computing system to perform any of the methods described above. Example implementations can include an apparatus including means for performing any of the methods described above. Example implementations can include an apparatus including at least one processor and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to perform any of the methods described above.

[0062] Various implementations of the systems and techniques described here can be realized in digital electronic circuitry, integrated circuitry, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0063] These computer programs (also known as programs, software, software applications or code) include machine instructions for a programmable processor, and can be implemented ina high-level procedural and / or object-oriented programming language, and / or in assembly / machine language. As used herein, the terms “machine-readable medium” “computer- readable medium” refers to any computer program product, apparatus and / or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term “machine- readable signal” refers to any signal used to provide machine instructions and / or data to a programmable processor.

[0064] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (a LED (light-emitting diode), or OLED (organic LED), or LCD (liquid crystal display) monitor / screen) for displaying information to the user and a keyboard and a pointing device (e g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0065] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (“LAN”), a wide area network (“WAN”), and the Internet.

[0066] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0067] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the specification.

[0068] In addition, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desirable results. In addition, other steps may be provided, or steps may be eliminated, from the described flows, and other components may be added to, or removed from, the described systems. Accordingly, other implementations are within the scope of the following claims.

[0069] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and / or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and / or subcombinations of the functions, components and / or features of the different implementations described.

[0070] While example implementations may include various modifications and alternative forms, implementations thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example implementations to the particular forms disclosed, but on the contrary, example implementations are to cover all modifications, equivalents, and alternatives falling within the scope of the claims. Like numbers refer to like elements throughout the description of the figures.

[0071] Some of the above example implementations are described as processes or methods depicted as flowcharts. Although the flowcharts describe the operations as sequential processes, many of the operations may be performed in parallel, concurrently or simultaneously. In addition, the order of operations may be re-arranged. The processes may be terminated when their operations are completed, but may also have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, subprograms, etc.

[0072] Methods discussed above, some of which are illustrated by the flow charts, may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine or computer readable medium such as a storage medium. A processor(s) may perform the necessary tasks.

[0073] Specific structural and functional details disclosed herein are merely representative for purposes of describing example implementations. Example implementations, however, be embodied in many alternate forms and should not be construed as limited to only the implementations set forth herein.

[0074] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example implementations. As used herein, the term and / or includes any and all combinations of one or more of the associated listed items.

[0075] It will be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., between versus directly between, adjacent versus directly adjacent, etc.).

[0076] The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting of example implementations. As used herein, the singular forms a, an and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes and / or including, when used herein, specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0077] It should also be noted that in some alternative implementations, the functions / acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed concurrently or may sometimes be executed in the reverse order, depending upon the functionality / acts involved.

[0078] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example implementations belong. It will be further understood that terms, e.g., those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0079] Portions of the above example implementations and corresponding detailed description are presented in terms of software, or algorithms and symbolic representations of operation on data bits within a computer memory. These descriptions and representations are the ones by which those of ordinary skill in the art effectively convey the substance of their work to others of ordinary skill in the art. An algorithm, as the term is used here, and as it is used generally, is conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of optical, electrical, or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0080] In the above illustrative implementations, reference to acts and symbolic representations of operations (e.g., in the form of flowcharts) that may be implemented as program modules or functional processes include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types and may be described and / or implemented using existing hardware at existing structural elements. Such existing hardware may include one or more Central Processing Units (CPUs), digital signal processors (DSPs), application-specific-integrated-circuits, field programmable gate arrays (FPGAs) computers or the like.

[0081] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied tothese quantities. Unless specifically stated otherwise, or as is apparent from the discussion, terms such as processing or computing or calculating or determining of displaying or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical, electronic quantities within the computer system’s registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

[0082] Note also that the software implemented aspects of the example implementations are typically encoded on some form of non-transitory program storage medium or implemented over some type of transmission medium. The program storage medium may be magnetic (e.g., a floppy disk or a hard drive) or optical (e.g., a compact disk read only memory, or CD ROM), and may be read only or random access. Similarly, the transmission medium may be twisted wire pairs, coaxial cable, optical fiber, or some other suitable transmission medium known to the art. The example implementations are not limited by these aspects of any given implementation.

[0083] Lastly, it should also be noted that whilst the accompanying claims set out particular combinations of features described herein, the scope of the present disclosure is not limited to the particular combinations hereafter claimed, but instead extends to encompass any combination of features or implementations herein disclosed irrespective of whether or not that particular combination has been specifically enumerated in the accompanying claims at this time.

Claims

CLAIMS1. A display comprising: a pixel array, wherein a plurality of pixels in the pixel array include: a micro light emitting diode (micro-LED) configured to radiate a light based on a drive current; and a plurality of switches coupled between a plurality of current sources and the micro- LED and configured according to a switch configuration to receive a pulse width modulation signal (PWM-signal) or an OFF-signal, wherein a level of the drive current for a pixel is determined by the switch configuration for the pixel.

2. The display according to claim 1, wherein the drive current for the pixel configures the micro-LED to radiate the light that is at a brightness that is within an acceptable brightness range and that is at a color that is within an acceptable wavelength range.

3. The display according to claim 1, further comprising a memory configured to store the switch configuration, wherein the memory is external to the pixel array and stores switch configurations for the plurality of pixels in the pixel array.

4. The display according to claim 1, wherein the plurality of pixels further include a local memory, the local memory of a particular pixel configured to store the switch configuration for the particular pixel.

5. The display according to claim 1, further comprising: a plurality of bit-lines coupled to each pixel of the plurality of pixels, the plurality of bitlines configured to conduct the PWM-signal or the OFF-signal to the plurality of switches.

6. The display according to claim 5, further comprising a switch encoder coupled to each of the plurality of bit-lines, the switch encoder configured to: receive the PWM-signal; receive the switch configuration; and output the PWM-signal or the OFF-signal to each bit-line according to the switch configuration.

7. The display according to claim 5, wherein: each of the plurality of pixels further include a plurality of static random access memory (SRAM) cells; and each SRAM cell of the plurality of SRAM cells is coupled between a switch and a bit-line.

8. The display according to claim 1, wherein the micro-LED has a dimension that is less than 10 microns.

9. The display according to claim 1, wherein: the plurality of switches is a first switch and a second switch; and the switch configuration for each of the plurality of pixels is one of: a first switch configuration that includes the first switch receiving the PWM-signal and the second switch receiving the OFF-signal; a second switch configuration that includes the first switch receiving the OFF-signal and the second switch receiving the PWM-signal; and a third switch configuration that includes the first switch receiving the PWM-signal and the second switch receiving the PWM-signal.

10. The display according to claim 9, wherein: the plurality of current sources is a first current source and a second current source; and the level of the drive current for each pixel of the plurality of pixels is one of: a first current level that is the first current source; a second current level that is the second current source; anda third current level that is a sum of the first current source and the second current source.

11. The display according to claim 1, wherein the plurality of current sources are at different current levels.

12. The display according to claim 1, wherein the plurality of current sources are coupled to the micro-LED in a parallel connection.

13. The display according to claim 1, wherein the plurality of current sources are coupled to each pixel of the plurality of pixels.

14. A method for controlling a display, the method comprising; determining a level of a drive current for a plurality of pixels in the display; determining a switch configuration for a plurality of switches within each pixel of the plurality of pixels based on the level of the drive current; coupling an OFF-signal or a pulse width modulation signal (PWM-signal) to the plurality of switches based on the switch configuration for each pixel; and driving each pixel of the plurality of pixels to illuminate light, the drive current for each pixel having a level selected from a plurality of possible levels based on the switch configuration for each pixel.

15. The method for controlling the display according to claim 14, wherein determining the level of the drive current for each pixel of the plurality of pixels is part of a calibration process, the calibration process performed on the display prior to use by a user.

16. The method for controlling the display according to claim 15, wherein the calibration process includes: driving a pixel at a current level generate an illumination; measuring a brightness of the illumination; comparing the brightness to an acceptable brightness range to generate a comparison; determining the switch configuration for the pixel based on the comparison; and storing the switch configuration for the pixel in a memory.

17. The method for controlling the display according to claim 14, wherein coupling the OFF- signal or the PWM-signal to the plurality of switches based on the switch configuration includes: toggling a static random access memory (SRAM) between an ON-state and an OFF-state, the SRAM coupled between a bit-line and a switch that is configured to receive the PWM-signal.

18. A pixel for a display comprising: a micro light emitting diode (micro-LED); a first switch coupled between the micro-LED and a first current source; a second switch coupled between the micro-LED and a second current source; a first bit-line coupled to a first static random access memory (SRAM), the first SRAM coupled between the first bit-line and a first controlling terminal of the first switch; and a second bit-line coupled to a second SRAM, the second SRAM coupled between the second bit-line and a second controlling terminal of the second switch, wherein a drive current on the micro-LED is determined based on a switch configuration of the first switch and the second switch.

19. The pixel for the display according to claim 18, wherein the switch configuration is one of: a first switch configuration in which the first switch conducts a first current and the second switch is OFF, the drive current in the first switch configuration being the first current;a second switch configuration in which the first switch is OFF and the second switch conducts a second current, the drive current in the second switch configuration being the second current; and a third switch configuration in which the first switch conducts the first current and the second switch conducts the second current, the drive current being a sum of the first current and the second current.

20. The pixel for the display according to claim 19, wherein the switch configuration is selected based on a brightness and a color the pixel.

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