Proximity doping for silicon structures

Abstract

Methods for fabricating a polysilicon doped structure include forming a first multilayer structure by growth / deposition of an oxide layer on a first substrate and disposing amorphous silicon on the oxide layer. The methods further include forming a second multilayer structure by disposing a spin-on-dopant on a second substrate. The methods further include creating a stack by placing the second multilayer structure on the first multilayer structure so that the spin-on-dopant is near the amorphous silicon. And the methods include applying heat to the stack to cause the first multilayer structure to transform into the polysilicon doped structure.

Description

070439.01838 (2023-104) PROXIMITY DOPING FOR SILICON STRUCTURES CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 519,706, filed August 15, 2023. This disclosure of this application is hereby incorporated by reference in its entirety. BACKGROUND Description of the Related Art

[0002] Conventional solutions for forming doped polysilicon-junctions in photovoltaic (PV) industries employ low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), and plasma enhanced chemical vapor deposition (PECVD) to deposit layers of amorphous silicon (a-Si:H) on substrates. Silane, along with hydrogen (H2) or other gases, is the main precursor for a-Si:H formation. The deposited a-Si:H layers then go through dopant diffusion in a thermal furnace using POCl3, BBr3, etc., as precursors and annealed in the thermal furnace. The other way is inclusion of the dopant gases (e.g., PH3, BH3, etc.) along with SiH4and H2, during the a-Si layer formation and subsequent annealing in a thermal furnace or rapid thermal annealing (RTA). Above solutions suffer from certain drawbacks. For example, the used dopant precursors are toxic, hazardous, expensive and require mandatory safety control and careful handling for health- and safety-related concerns. Moreover, masking or etching of one side of the wafer is always required in poly-Si passivating contacts on c-Si solar cells (e.g., in case where dopant diffusion occur in a thermal furnace after the formation of a-Si:H). Ion implantation is another technique used widely in the photovoltaic (PV) industry for a doping process wherein required dopants (i.e., P or B atoms) implanted in material followed by furnace / rapid thermal annealing, but a very high cost of equipment results in the significantly increased cost of the final product.

[0003] Conventional solutions for homogeneously diffused junctions employ diffusion processes similar to doped polysilicon-junctions, but without the step of forming a-Si:H layers either in APCVD, LPCVD or PECVD. 1 144830243070439.01838 (2023-104)

[0004] Spin-on-dopants (SOD) are the better alternatives to those doping or diffusion methods, as they are cost-effective, commercially viable, can form similar diffusion or doping junctions to those formed by aforementioned conventional techniques. However, SODs are not without its own limitations, as SODs are a mixture of organic components and dopant sources. Traditionally, SODs are spun directly onto the semiconductor substrate surface, followed by annealing to dope impurities in the substrates. In case of direct SOD process, a residual, soft, and carbon rich film is frequently left after doping, which is in-soluble in deglaze solution (i.e., diluted HF solution) and not able to remove completely. Organic residues prevent the effective passivation of defects or dangling bonds on the semiconductor surface by passivation materials, as those residues remained on the surface are hard to be removed and increases the process costs notably due to the need to include additional removal steps. Proximity doping proposed herein for photovoltaic (PV) cells circumvents the drawbacks of directly spinning SOD on substrate surface, while taking advantages of the benefits of SODs to other doping or diffusion methods. SUMMARY

[0005] Aspects of the present disclosure relate to fabricating polysilicon doped structure s. Issues associated with prior solutions are addressed by the subject matter of the independent claims included in this document. Additional advantageous aspects are included in the dependent claims.

[0006] In one aspect, the present disclosure provides a method for fabricating a polysilicon doped structure. The method includes forming a first multilayer structure by growth / deposition of an oxide layer on a first substrate and disposing amorphous silicon on the oxide layer. The method further includes forming a second multilayer structure by disposing a spin-on-dopant on a second substrate. The method further includes creating a stack by placing the second multilayer structure on the first multilayer structure so that the spin-on-dopant is near the amorphous silicon. And the method includes applying heat to the stack to cause the first multilayer structure to transform into the polysilicon doped structure.

[0007] Implementations of the disclosure may include one or more of the following optional features. In some examples, at least one of the first substrate and the second substrate includes a silicon wafer. The oxide layer may be grown on the first substrate using an ozone dissolved de- 2 144830243070439.01838 (2023-104) ionized water. The amorphous silicon may be deposited on the oxide layer using PECVD reactor. The second multilayer structure may be formed by disposing the spin-on-dopant on the second substrate and prebaking it at given temperature for a given time. The method may further include disposing one or more spacers between first and second multilayer structures prior to disposing the second multilayer structure on the first multilayer structure. The one or more spacers may include quartz and / or silicon. The heat may be applied to the stack using a heat source of a box furnace. In some examples, the method further includes removing the second multilayer structure from the polysilicon doped structure. The method may further include removing a top layer of residue from a doped polysilicon layer of the polysilicon doped structure. The doped polysilicon layer may have a uniform sheet resistance and hence doping, thereacross.

[0008] In another aspect, the present disclosure provides a method for fabricating a diffused homojunction. The method includes obtaining a first substrate and forming a multilayer structure by disposing a spin-on-dopant on a second substrate. The method further includes creating a stack by placing the multilayer structure on the first substrate and applying heat to the stack to cause the first substrate to transform into the diffused homojunction.

[0009] Implementations of the disclosure may include one or more of the following optional features. In some examples, at least one of the first substrate and the second substrate includes a silicon wafer. The multilayer structure may be formed by disposing the spin-on-dopant on the second substrate and prebaking it at given temperature for a given time. The heat may be applied to the stack using a heat source of a box furnace. In some examples, the method further includes removing the multilayer structure from the diffused homojunction. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present solution will be described with reference to the following drawing figures, in which like numerals represent like items throughout the figures.

[0011] FIG.1 provide illustrations that are useful for understanding a doped polysilicon- junction process and a diffused homo-junction process of the present solution.

[0012] FIG.2 is an illustration of a method for fabricating a doped polysilicon structure. 3 144830243070439.01838 (2023-104)

[0013] FIG.3 is an illustration of a substrate.

[0014] FIG.4 provides an illustration of an oxide layer and an amorphous silicon layer disposed on the substrate of FIG.3 to form a multi-layer structure.

[0015] FIG.5 provides an illustration of another substrate.

[0016] FIG.6 provides an illustration of a spin-on-dopant (SOD) layer disposed on the substrate of FIG.5 to form a multi-layer structure and prebake for a particular time.

[0017] FIG.7 provides an illustration of optional spacers placed on the SOD layer of FIG.6.

[0018] FIG.8 provides an illustration showing the multi-layer structure of FIG.6 placed on the multi-layer structure of FIG.4 (with the optional spaces located therebetween).

[0019] FIG.9 provides illustrations showing the stacked multi-layer structures disposed in a box furnace.

[0020] FIG.10 provides illustrations of heat being applied to the stacked multi-layer structures.

[0021] FIG.11 provides illustrations showing the resulting structure inside the box furnace after the heat is no longer being applied.

[0022] FIG.12 provides an illustration showing the resulting structure removed from the box furnace.

[0023] FIG.13 provides an illustration showing the multi-layer structure of FIG.6 and / or spacers of FIG.7 removed from the resulting structure.

[0024] FIG.14 provides an illustration showing a residue layer removed from the resulting structure to form a polysilicon doped structure.

[0025] FIG.15 provides an illustration that is useful for understanding long-term passivation stability of Phosphorus-doped polysilicon samples.

[0026] FIG.16 is an illustration of a method for fabricating diffused homogeneous junction silicon solar cells. 4 144830243070439.01838 (2023-104) DETAILED DESCRIPTION

[0027] It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended figures could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0028] The present solution may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the present solution is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0029] Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present solution should be or are in any single embodiment of the present solution. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present solution. Thus, discussions of the features and advantages, and similar language, throughout the specification may, but do not necessarily, refer to the same embodiment.

[0030] Furthermore, the described features, advantages and characteristics of the present solution may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the present solution can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present solution. 5 144830243070439.01838 (2023-104)

[0031] Reference throughout this specification to “one embodiment”, “an embodiment”, or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present solution. Thus, the phrases “in one embodiment”, “in an embodiment”, and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0032] As used in this document, the singular form “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art. As used in this document, the term “comprising” means “including, but not limited to”.

[0033] The present solution relates to implementing systems and methods for producing doped polysilicon-junction and / or diffused homo-junction for PV cells. Illustrations are provided in FIG.1 that are useful for understanding the methods for producing the doped polysilicon-junction and the diffused homo-junction. Besides, the present solution offers the unmatched flexibility to dope or diffuse on front and rear surfaces of PV cells or devices requiring opposite or same polarity (i.e., phosphorus or boron) doping or diffusion. The present solution also reduces the process steps of forming doped or diffused junctions with opposite or same polarities on front and rear sides through co-annealing—rather than annealing doped or diffused junctions one at a time—which reduces the annealing process by half. The process is feasible in a small box furnace instead using a full thermal furnace, which needs keep running all times and have more maintenance cost. The present solution can be implemented with no changes or relatively minimal changes to existing PV industry equipment.

[0034] The present solution also reduces the number of equipment required to form doped or diffused junctions in PV industry to a minimum as shown by the following TABLE 1 and TABLE 2. 6 144830243070439.01838 (2023-104) TABLE 1 1) Diffused Polysilicon-Junction Existing Solution Present Solution Comments n al r t7 144830243070439.01838 (2023-104) TABLE 2 2) Diffused Homo-Junction r tlong-term passivation stability, good thickness and uniformity, low contact resistivity, is low- cost, fast, and can be applied in PV industries.

[0035] In some scenarios, a box furnace is used to produce the doped polysilicon-junction and / or diffused homo-junction. The polysilicon surface is very hydrophobic without any blistering. The result is a cleaner and hydrophobic wafer with more uniform doping across the substrate layer while using a safer and less wasteful process.

[0036] The doping of the a-Si is carried out using a SOD-made diffusion source. It can be applied to anything that requires a doped substrate layer and can be implemented with no changes or relatively minimal changes to existing industry equipment. The present solution can also concurrently dope two sides of the substrate, thereby eliminating the need for masking particularly for the doped-polysilicon process. 8 144830243070439.01838 (2023-104)

[0037] The present solution concerns implementing systems and methods for fabricating a doped polysilicon structure. The methods comprise forming a first multi-layer structure by growth / deposition of an oxide layer on a first substrate (e.g., a silicon wafer) and disposing amorphous silicon on the oxide layer. The growth / deposition of the oxide layer can be done via thermal / chemical route and amorphous silicon can be achieved via a physical vapor deposition (PVD) process and / or a chemical vapor deposition (CVD) process.

[0038] The methods also comprise: forming a second multi-layer structure by disposing an SOD on a second substrate (e.g., a silicon wafer); creating a stack by placing the second multi- layer structure on the first multi-layer structure so that the SOD is near the amorphous silicon; applying heat to the stack to cause the first multi-layer structure to transform into the polysilicon doped structure; removing the second multi-layer structure from the polysilicon doped structure; and / or removing a top layer of residue from a doped polysilicon layer of the doped polysilicon doped. The heat may be applied to the stack using a heat source such as furnace. The doped polysilicon layer has a uniform thickness and a uniform amount of dopant thereacross.

[0039] In some scenarios, spacers may be employed. Accordingly, the methods may further comprise disposing at least one silicon-compatible structure on the SOD prior to placing the second multi-layer structure on the first multi-layer structure. The silicon-compatible structure(s) comprise(s) quartz, and / or silicon or any compatible material. In other embodiment, the optional spacers are omitted.

[0040] The present solution can be used in various applications. The applications include, but are not limited to, semiconductor wafer applications, solar cell applications (e.g., passivated contact (or TOPCon) solar cells, poly-Si on oxide (POLO) junction solar cells, and / or interdigitated back contact (IBC) solar cells), passive emitter poly-Si cell applications, electronic device applications (e.g., transistors), consumer electronic good applications (e.g., tablets, smart phones, laptops, smart TVs, etc.), integrated circuit applications, and / or aerospace applications.

[0041] Referring now to FIG.2, there is provided a flow diagram of an illustrative method 200 for fabricating a doped polysilicon structure. Method 200 begins with 202 and continues with 204 where a first substrate is obtained. The first substrate can include, but is not limited to, 9 144830243070439.01838 (2023-104) a silicon substrate or silicon wafer. An illustration of a first substrate 300 is provided in FIG.3. The first substrate is used in 206 to form a first multi-layer structure. The operations of 206 involve growing / disposing an oxide layer, for example 1-2 nm, on the first substrate and disposing a layer of amorphous silicon on the oxide layer, for example 60 nm, 90 nm, 120 nm, etc. The oxide layer can be grown / deposited via thermal / chemical methods and amorphous silicon layer can be disposed using a PVD process and / or a CVD process. An illustration showing a first multi-layer structure 400 is shown in FIG.3 with an oxide layer 402 and an amorphous silicon layer 404.

[0042] Next in 208, a second substrate is obtained. The second substrate can include, but is not limited to, a silicon substrate or silicon wafer. An illustration of a second substrate 500 is provided in FIG.5. The second substrate is used in 210 to form a second multi-layer structure. The second multi-layer structure is formed by disposing an SOD layer on the second substrate and prebaking it at a particular temperature for a given duration (e.g., 200 °C for 30 min). The use of the second multi-layer structure has many advantages such as a decreased chance of contamination from the dopant in the final product and / or co-doping of front and backside at the same time. An illustration showing a second multi-layer structure 600 is provided in FIG.6. The multi-layer structure 600 comprises a SOD layer 602 disposed on the second substrate 500.

[0043] In some scenarios, spacers are employed. Accordingly, method 200 includes an optional step 212 in which one or more silicon-compatible structures are disposed on the SOD layer. The silicon-compatible structures provide the spacers on the second multi-layer structure. The silicon-compatible structure(s) can include, but are not limited to, quartz structure(s), structure(s), and / or silicon structure(s). An illustration showing spacer(s) 702, 704 disposed on the SOD layer 602 is provided in FIG.7. Although two spacers are shown in FIG.7, the present solution is not limited in this regard. Any number of spacers can be used in accordance with a given application, and, in some embodiments, no spacers are used.

[0044] In 214, the second multi-layer structure is disposed on the first multi-layer structure. This can involve arranging the two structures relative to each other such that (i) the SOD layer is near or adjacent to the amorphous silicon layer or (ii) any optional spacer(s) reside between the 10 144830243070439.01838 (2023-104) SOD layer and the amorphous silicon layer. The arrangement of (i) is shown in the top illustration of FIG.8, while the arrangement of (ii) is shown in bottom illustration of FIG.8.

[0045] In 216, the stacked multi-layer structures are placed in a furnace (either box or tube). Any known or to be known furnace can be used here. An illustration showing the stacked multiplayer structures disposed in a box furnace 900 is provided in FIG.9. The top illustration of FIG.9 does not include any spacers, while the bottom illustration in FIG.9 includes spacers.

[0046] Next in 218, a heat source of the furnace is activated, where ambient (N2, O2) is optional. The heat source can include, but is not limited to, a light source. An internal temperature of the furnace is increased in block 220 to a given temperature. The given temperature can include, but is not limited to, 700 °C, 1000 °C, any temperature between 700 °C and 1000 °C, any temperature between 800 °C and 950 °C, any temperature between 850 °C and 900 °C, any temperature between 875 °C and 900 °C, and / or any temperature between 850 °C and 875 °C. Once the internal temperature of the furnace has reached the given temperature, the system waits a pre-defined period of time (for example, thirty to sixty minutes or depends on application requirements), as shown by 222. The top illustration of FIG.10 shows heat being applied to the stacked multi-layer structures without spacers, and while the bottom illustration of FIG.10 shown heat being applied to the stacked multi-layer structures with spacers disposed therebetween.

[0047] Upon expiration of this period of time, the heat source of the furnace is deactivated in 224. The internal temperature of the furnace is allowed to cool for a pre-defined duration, as shown by 226. The internal temperature is allowed to decrease to 500 °C, room temperature, or any value between 500 °C and room temperature. The pre-defined duration can include, but is not limited to, sixty minutes depends on system used. The top illustration of FIG.11 shows heat no longer being applied to the multi-layer structure 1110 without spacers, and while the bottom illustration of FIG.11 shows heat no longer being applied to the multi-layer structure 1120 with spacers disposed therebetween. It should be noted that the first multi-layer structure 400 has been changed via the application of heat to now comprise a doped polysilicon layer 1102 and a residual layer 1100. This resulting structure is referred to herein as a doped polysilicon structure. 11 144830243070439.01838 (2023-104)

[0048] Next in 228, both multi-layer structures are removed from the furnace. An illustration is provided in FIG.12 showing the multi-layer structures removed from the furnace. The second multi-layer structure is removed from the doped polysilicon (first multiplayer) structure in 230. An illustration is provided in FIG.13 showing the second multi-layer structure 1202 and optional spacer(s) 702, 704 removed from the doped polysilicon structure 1200.

[0049] As noted above, the doped polysilicon structure comprises a doped polysilicon layer and a residual layer. The residual layer 1100 is removed from the doped polysilicon structure in 232 via, for example, a wet etching process. Wet etching processes are well known. An illustration showing the doped polysilicon structure without the residual layer is provided in FIG.14. Subsequently, 234 is performed where method 200 ends or other operations or performed.

[0050] Preliminary results show very low contact resistivity (ρc), demonstrating the quality of the proximity doping technique. In particular, ρcof n_p-Si was measured in the range of 0.28- 4.25 mΩcm2.3D device simulation verifies that resistivity in this range is consistent with developing high efficiency (e.g., > 24%) polysilicon passivated contact solar cells.

[0051] Using ozone oxide (DI-O3) as a tunnel oxide for the doped polysilicon, the thickness of DI-O3can be adjusted by varying growth time, ozone concentration, and / or temperature. Wafers with a diameter of 100 mm were grown using DI-O3and found to have less than 4% variation in thickness from an average value. For example, one wafer had thicknesses between 1.31 and 1.41 nm and another had thicknesses between 1.728 and 1.824 nm.

[0052] In other results, the average measured sheet resistance of the doped polysilicon formed via box furnace annealing is 9.25 Ω / □. FIG .15A Photoluminescence (PL) images of doped polysilicon samples passivated by SiNx / AlOx showed doping and passivation uniformity. Photo conductive decay (PCD) measurement results of the same passivated samples showed typical lifetime and saturation current density (J0) as 1.1~1.5 ms and 21~29 fA / cm2respectively. Referring to Fig.15, Phosphorus-doped polysilicon samples also demonstrate the good long-term passivation stability, which is highly important for the commercially viable option. 12 144830243070439.01838 (2023-104)

[0053] FIG.16 is an illustration of a method 1600 for fabricating a diffused homogeneous junction silicon solar cell. Method 1600 begins with 1602 and continues with 1604 where a first substrate is obtained. The first substrate can include, but is not limited to, a silicon substrate or silicon wafer. An illustration of a first substrate 100 is provided in FIG.1.

[0054] Next in 1606, a second substrate is obtained. The second substrate can include, but is not limited to, a silicon substrate or silicon wafer. An illustration of a second substrate 102 is provided in FIG.1. The second substrate is used in 1608 to form a multi-layer structure. The multi-layer structure is formed by disposing an SOD layer on the second substrate and prebaking it at a particular temperature for a given duration (e.g., 200 °C for 30 min). The use of the multi- layer structure has many advantages such as a decreased chance of contamination from the dopant in the final product and / or co-doping of front and backside at the same time. An illustration showing a multi-layer structure 106 is provided in FIG.1. The multi-layer structure 600 comprises a SOD layer 108 disposed on the second substrate 102.

[0055] In some scenarios, spacers are employed. Accordingly, method 1600 includes an optional step 1610 in which one or more silicon-compatible structures are disposed on the SOD layer. The silicon-compatible structures provide the spacers on the multi-layer structure. The silicon-compatible structure(s) can include, but are not limited to, quartz structure(s), structure(s), and / or silicon structure(s). An illustration showing spacer(s) 110 between the SOD layer 108 and the first substrate 100 is provided in FIG.1. Although two spacers are shown in FIG.1, the present solution is not limited in this regard. Any number of spacers can be used in accordance with a given application.

[0056] In 1612, the multi-layer structure is disposed on the first substrate. The stacked structures are placed in a furnace (either box or tube) in 1614. Any known or to be known furnace can be used here. Next in 1616, a heat source of the furnace is activated, where ambient (N2, O2) is optional. The heat source can include, but is not limited to, a light source. An internal temperature of the furnace is increased in block 1618 to a given temperature. The given temperature can include, but is not limited to, 700 °C, 1000 °C, any temperature between 700 °C and 1000 °C, any temperature between 800 °C and 950 °C, any temperature between 850 °C and 900 °C, any temperature between 875 °C and 900 °C, and / or any temperature between 850 °C 13 144830243070439.01838 (2023-104) and 875 °C. Once the internal temperature of the furnace has reached the given temperature, the system waits a pre-defined period of time (for example, thirty to sixty minutes or depends on application requirements), as shown by 1620.

[0057] Upon expiration of this period of time, the heat source of the furnace is deactivated in 1622. The internal temperature of the furnace is allowed to cool for a pre-defined duration, as shown by 1624. The internal temperature is allowed to decrease to 500 °C, room temperature, or any value between 500 °C and room temperature. The pre-defined duration can include, but is not limited to, sixty minutes depends on system used.

[0058] Next in 1626, the structures are removed from the furnace. The multi-layer structure is then removed from the homogenous (first substrate) structure as shown by 1628. Wet etching is performed in 1630 to remove the residue from the first substrate to obtain diffused homogeneous (first substrate) structure. Subsequently, 1632 is performed where method 1600 ends or other operations or performed.

[0059] Although the present solution has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In addition, while a particular feature of the present solution may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Thus, the breadth and scope of the present solution should not be limited by any of the above-described embodiments. Rather, the scope of the present solution should be defined in accordance with the following claims and their equivalents. 14 144830243

Claims

070439.01838 (2023-104) CLAIMS What is claimed is:

1. A method for fabricating a polysilicon doped structure, comprising: forming a first multilayer structure by growth / deposition of an oxide layer on a first substrate and disposing amorphous silicon on the oxide layer; forming a second multilayer structure by disposing a spin-on-dopant on a second substrate; creating a stack by placing the second multilayer structure on the first multilayer structure so that the spin-on-dopant is near the amorphous silicon; and applying heat to the stack to cause the first multilayer structure to transform into the polysilicon doped structure.

2. The method according to claim 1, wherein at least one of the first substrate and the second substrate comprises a silicon wafer.

3. The method according to claim 1, wherein the oxide layer is grown on the first substrate using an ozone dissolved de-ionized water.

4. The method according to claim 1, wherein the amorphous silicon is deposited on the oxide layer using PECVD reactor.

5. The method according to claim 1, wherein the second multilayer structure is formed by disposing the spin-on-dopant on the second substrate and prebaking it at given temperature for a given time.

6. The method according to claim 5, further comprising disposing one or more spacers between first and second multilayer structures prior to disposing the second multilayer structure on the first multilayer structure.

7. The method according to claim 6, wherein the one or more spacers comprise quartz and / or silicon. 15 144830243070439.01838 (2023-104) 8. The method according to claim 1, wherein the heat is applied to the stack using a heat source of a box furnace.

9. The method according to claim 1, further comprising removing the second multilayer structure from the polysilicon doped structure.

10. The method according to claim 9, further comprising removing a top layer of residue from a doped polysilicon layer of the polysilicon doped structure.

11. The method according to claim 10, wherein the doped polysilicon layer has a uniform sheet resistance and hence doping, thereacross.

12. A method for fabricating a diffused homojunction, comprising: obtaining a first substrate; forming a multilayer structure by disposing a spin-on-dopant on a second substrate; creating a stack by placing the multilayer structure on the first substrate; and applying heat to the stack to cause the first substrate to transform into the diffused homojunction.

13. The method according to claim 12, wherein at least one of the first substrate and the second substrate comprises a silicon wafer.

14. The method according to claim 12, wherein the multilayer structure is formed by disposing the spin-on-dopant on the second substrate and prebaking it at given temperature for a given time.

15. The method according to claim 12, wherein the heat is applied to the stack using a heat source of a box furnace.

16. The method according to claim 12, further comprising removing the multilayer structure from the diffused homojunction. 16 144830243

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