Semiconductor device, optical device, and manufacturing method for semiconductor structure

Abstract

Disclosed in embodiments of the present application are a semiconductor device, an optical device, and a manufacturing method for a semiconductor structure. The manufacturing method comprises: forming a stack structure on a substrate, wherein the stack structure comprises functional layers and sacrificial layers which are alternately stacked, the functional layers and the sacrificial layers are made of the same material, the sacrificial layers are doped with n-type or p-type impurities, and the doping concentration of the sacrificial layers is greater than that of the functional layers; and selectively removing the sacrificial layers from the stack structure.

Description

Semiconductor device, optical device and method for manufacturing semiconductor structure Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a method for manufacturing a semiconductor device, an optical device, and a semiconductor structure. Background Art

[0002] With the continued advancement of Moore's Law and the advancement of semiconductor processes to the 3nm node, gate-all-around (GAA) transistors are considered a viable alternative to fin field-effect transistors (FinFETs). Highly selective etching of the horizontally stacked nanosheets of the sacrificial layer is crucial in GAA manufacturing. The industry typically forms n-type GAA-FETs by selectively removing SiGe from a multilayer Si and SiGe stack to create vertically stacked Si nanowires.

[0003] However, due to the large difference in lattice constants between Si and SiGe, as the number of stacked Si and SiGe layers increases, internal stress will continue to accumulate. When the number of stacked Si and SiGe layers reaches a certain level, it will cause the wafer to warp, and in severe cases, it will even cause the wafer to break, thus limiting the number of stacked Si and SiGe layers. In addition, due to the lattice mismatch between the Si and SiGe layers, the dislocation defects of the Si layer epitaxially grown on the SiGe layer will increase. Since the Si layer will serve as the channel of the GAA-FET, the dislocation defects in the Si layer will also reduce the performance of the GAA-FET.

[0004] Summary of the Invention

[0005] The embodiments of the present application disclose a method for manufacturing a semiconductor device, an optical device, and a semiconductor structure to solve the problem in the related art that the number of stacked layers is not high and dislocation defects are easily generated.

[0006] In order to solve the above technical problems, according to a first aspect, an embodiment of the present application discloses a method for manufacturing a semiconductor structure, comprising: forming a stacked structure on a substrate, the stacked structure comprising alternatingly stacked functional layers and sacrificial layers, the functional layers and the sacrificial layers being composed of the same material, the sacrificial layers being doped with n-type or p-type impurities, and the doping concentration of the sacrificial layers being greater than the doping concentration of the functional layers; and selectively removing the sacrificial layers from the stacked structure.

[0007] In some embodiments, there are multiple functional layers and multiple sacrificial layers, at least a portion of at least one of the functional layers is curved or bent; and / or at least a portion of at least one of the sacrificial layers is curved or bent.

[0008] In some embodiments, the substrate is a plane and the stacked structure is formed on the plane; or the substrate includes a wavy surface and the stacked structure is adaptively formed on the wavy surface; or the substrate includes a protruding structure protruding from the surface of the substrate body, and the stacked structure is adaptively formed on the surface of the substrate body and the protruding structure.

[0009] In some embodiments, the raised structure includes: a first raised portion, located on the substrate body; a second raised portion, located on the first raised portion, the projection area of ​​the second raised portion on the plane where the substrate body is located is larger than the projection area of ​​the first raised portion on the plane where the substrate body is located, and the projection of the first raised portion on the plane where the substrate body is located is located within the projection of the second raised portion on the plane where the substrate body is located.

[0010] In some embodiments, selectively removing the sacrificial layer from the stacked structure includes: performing anisotropic etching on the stacked structure to retain the stacked structure directly below the second protrusion; and selectively removing the sacrificial layer from the retained stacked structure.

[0011] In some embodiments, the functional layer is a non-doped layer; or the doping concentration of the functional layer is less than 5×10 14 cm -3 ; or the doping concentration of the sacrificial layer is greater than 5×10 14 cm -3 ; or the doping concentration of the sacrificial layer is 6×10 14 cm -3 to 5×10 21 cm -3 .

[0012] In some embodiments, forming the stacked structure on the substrate includes: using a chemical vapor deposition process to alternately epitaxially grow the functional layer and the sacrificial layer on the substrate.

[0013] In some embodiments, the material of the functional layer and the sacrificial layer is silicon; the step of epitaxially growing the functional layer includes: introducing silicon-containing gas into the process chamber; the step of epitaxially growing the sacrificial layer includes: introducing the silicon-containing gas and the gas containing impurity elements into the process chamber.

[0014] In some embodiments, the silicon-containing gas includes at least one of SiH4, Si2H6, and SiH2Cl2; the gas containing impurity elements includes B2H6, or the gas containing impurity elements includes at least one of PH3, AsH3, SbH3, and BiH3.

[0015] In some embodiments, the epitaxial growth temperature is 400°C to 750°C.

[0016] In some embodiments, selectively removing the sacrificial layer from the stacked structure includes: performing isotropic plasma etching on the stacked structure using a process gas.

[0017] In some embodiments, the functional layer and the sacrificial layer are made of silicon; and the process gas includes at least one of a chlorine-containing gas and a bromine-containing gas.

[0018] In some embodiments, the chlorine-containing gas includes at least one of Cl2 and HCl; the bromine-containing gas includes at least one of Br2 and HBr; and the process gas further includes at least one of N2, He, and Ar.

[0019] In some embodiments, after selectively removing the sacrificial layer from the stacked structure, the method further includes: performing oxidation treatment on the functional layer; and removing the oxide layer on the surface of the functional layer.

[0020] According to the second aspect, an embodiment of the present application discloses a semiconductor device, comprising: a substrate; at least one functional layer, arranged on the substrate, at least one of the functional layers being spaced apart in the vertical direction, and at least a portion of at least one of the functional layers being curved or bent; a gate structure, arranged around each of the functional layers; and source / drain regions, respectively arranged on both sides of the functional layers and connected to the functional layers.

[0021] According to the third aspect, an embodiment of the present application discloses a semiconductor device, comprising: a substrate; at least one functional layer, arranged on the substrate, at least one of the functional layers being spaced apart in the vertical direction, and the functional layers being obtained by the manufacturing method of the semiconductor structure described in the first aspect above; a gate structure, arranged around each of the functional layers; and source / drain regions, respectively arranged on both sides of the functional layers and connected to the functional layers.

[0022] According to a fourth aspect, an embodiment of the present application discloses an optical device, comprising: at least one functional layer for transmitting an optical signal, wherein the functional layer is obtained by the manufacturing method of the semiconductor structure described in the first aspect above.

[0023] In the manufacturing method of the semiconductor device, optical device and semiconductor structure of the embodiment of the present application, the functional layer and the sacrificial layer are composed of the same material, and only the doping concentration is different. There is almost no difference in the lattice constant of the functional layer and the sacrificial layer. No stress will appear at the interface between the functional layer and the sacrificial layer due to lattice mismatch, and no dislocation defects will be introduced in the functional layer. Moreover, compared with the related technology using a gradient sacrificial layer, the thickness of the sacrificial layer of the embodiment of the present application can be made very thin, and the manufacturing process is simple, the number of stacking layers is high and the production capacity is large. The number of stacking layers of the stacked structure of the embodiment of the present application can reach hundreds of layers, and there will be no phenomenon of wafer warping or even cracking. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG1 is a schematic diagram showing a Si / SiGe stacked structure in the related art;

[0025] FIG2 shows a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application;

[0026] FIG3 shows another flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application;

[0027] 4 to 10 are schematic structural diagrams showing steps of a method for manufacturing a semiconductor structure according to an embodiment of the present application;

[0028] FIG11 shows a schematic diagram of the lattice of SiGe material;

[0029] FIG12 shows a schematic diagram of the lattice of Si material doped with P element;

[0030] 13 and 14 are schematic structural diagrams showing steps of a method for manufacturing an exemplary semiconductor structure according to an embodiment of the present application;

[0031] 15 and 16 are schematic structural diagrams showing steps of a method for manufacturing an exemplary semiconductor structure according to an embodiment of the present application;

[0032] FIG17 is a schematic diagram showing another example of a protrusion structure in an embodiment of the present application;

[0033] 18 to 20 are schematic structural diagrams showing steps of a method for manufacturing an exemplary semiconductor structure according to an embodiment of the present application;

[0034] FIG21 shows a schematic diagram of a semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0036] It should be understood by those skilled in the art that the embodiments of the present application are merely illustrations of the structures and methods for which the present application may be implemented in various forms. In addition, each example provided in conjunction with the various embodiments is intended to be illustrative, not restrictive. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show the details of specific components. Therefore, the specific structural and functional details in the embodiments of the present application should not be interpreted as restrictive, but merely as a representative basis for teaching those skilled in the art to adopt the methods and structures of the embodiments of the present application in different ways. It should also be noted that identical and corresponding elements are represented by the same reference numerals.

[0037] In the following description, many specific details are set forth, such as specific structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it should be understood by those skilled in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0038] For the purposes of the following description, the terms "upper," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall relate to the orientation of the structures and methods disclosed in the drawings of the specification. It will be understood that when an element as a layer, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements between the two. It will also be understood that when an element is referred to as being "under" another element, the element can be directly under the other element or intervening elements may be present. Conversely, when an element is referred to as being "directly under" another element, there are no intervening elements between the two.

[0039] As mentioned above, due to the lattice mismatch between the Si layer and the SiGe layer, on the one hand, the number of stacked layers of the Si layer and the SiGe layer is limited, and on the other hand, dislocation defects are introduced into the Si layer, resulting in poor performance of the manufactured GAA-FET. In order to solve this technical problem, a solution is provided in the related art. As shown in Figure 1, when the SiGe layer 2 is epitaxially grown on the surface of the substrate 1, the Ge concentration in the SiGe layer 2 needs to be gradually changed, that is, the Ge concentration is first gradually increased as the thickness of the SiGe layer 2 grows, and then the Ge concentration is gradually reduced as the thickness of the SiGe layer 2 grows, so that the lattice constants on both sides of the SiGe layer 2 in contact with the Si layer 3 are close to those of the Si layer 3, so as to avoid or reduce the stress between the Si layer and the SiGe layer caused by the lattice mismatch and the introduction of dislocation defects in the Si layer. However, since this solution requires continuous adjustment of the Ge concentration during the epitaxial growth of the SiGe layer 2, the process complexity is high and the manufacturing cost is high; on the other hand, since a thicker SiGe layer 2 needs to be formed to achieve the gradient buffer effect, the number of stacked layers is still not high and the production capacity is low.

[0040] To solve the above technical problems, an embodiment of the present application provides a method for manufacturing a semiconductor structure, as shown in FIG2 . The method may include the following steps:

[0041] S110. Form a stacked structure on a substrate.

[0042] As shown in Figures 4 and 5, Figure 4 shows a schematic top view of the semiconductor structure of an embodiment of the present application, and Figure 5 is a schematic cross-sectional view along line AA in Figure 1. A stacked structure 200 is formed on a substrate 100, and the stacked structure 200 includes alternating functional layers 201 and sacrificial layers 202. Among them, the functional layer 201 is used to realize the function of the semiconductor structure. For example, when the semiconductor structure is used for GAA-FET, the functional layer 201 serves as the channel of the GAA-FET, and the sacrificial layer 202 is removed in subsequent processes. It should be understood by those skilled in the art that the present application is not limited to this. The functional layer 201 can also realize other functions in different application scenarios, such as acting as a waveguide in active or passive optical devices.

[0043] The functional layer 201 and the sacrificial layer 202 are made of the same material, for example, both are made of Si. Those skilled in the art should understand that the functional layer 201 and the sacrificial layer 202 can also be made of other materials, for example, they can also be made of materials such as Ge, SiGe, GaAs, InSb, GaP, GaN, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. It should be noted that when the functional layer 201 and the sacrificial layer 202 are made of compound materials, the "same material" in the embodiments of the present application means that the compound material contains the same type of elements, and the proportion of each element is the same, and only the doping concentration is different. There is a clear definition of n-type or p-type impurities in the art. By adding a small amount of n-type or p-type impurities to the semiconductor material, the main element composition of the semiconductor material will not be changed. Its purpose is usually to change the concentration of free electrons or free holes in the semiconductor material to change the electrical properties of the semiconductor material. Those skilled in the art will understand that since the doping concentration of conventional semiconductor doping processes is extremely small relative to the content of the main element, different doping concentrations will hardly change the lattice constants of the functional layer 201 and the sacrificial layer 202. This "same material" with different doping concentrations makes the lattice constants of the functional layer 201 and the sacrificial layer 202 almost the same. For example, if the functional layer 201 and the sacrificial layer 202 are both made of Si x Ge y If the composition is different, then the "same material" in the embodiments of the present application refers to SiGe with the same proportion of Si and Ge, that is, the values ​​of x and y are the same, and only the doping concentration is different. If the proportions of the elements constituting the compound material are different, even if the compound materials of the functional layer 201 and the sacrificial layer 202 contain the same type of elements, it will lead to a large difference in the lattice constants of the functional layer 201 and the sacrificial layer 202. Therefore, when the compound materials of the functional layer 201 and the sacrificial layer 202 have different proportions of each element, it is still impossible to solve the problem of stress between the Si layer and the SiGe layer and the introduction of dislocation defects in the Si layer caused by lattice mismatch in the related art. It should be understood by those skilled in the art that compound materials with the same constituent elements but different proportions of each element should not be considered as the "same material" referred to in the embodiments of the present application. In some embodiments of the embodiments of the present application, the sacrificial layer 202 can be doped with n-type or p-type impurities, and the functional layer 201 can be undoped. For example, the functional layer 201 is an intrinsic semiconductor. In this case, the doping concentration of the sacrificial layer 202 must be greater than the doping concentration of the functional layer 201 (i.e., no doping). In some other implementations of the embodiments of the present application, the functional layer 201 may also be doped, for example, the functional layer 201 is doped with n-type or p-type impurities, and the doping concentration of the sacrificial layer 202 is greater than the doping concentration of the functional layer 201 .

[0044] In some embodiments of the present application, the functional layer 201 may be an undoped layer or a lightly doped layer, and the sacrificial layer 202 may be a heavily doped layer. Due to the difference in doping concentration between the functional layer 201 and the sacrificial layer 202, the sacrificial layer 202 can be selectively etched from the stacked structure 200 in a subsequent etching process. In some embodiments, the functional layer 201 may be made of an intrinsic semiconductor material, or the doping concentration of the functional layer 201 may be less than 5×10 14 cm -3 , the doping concentration of the sacrificial layer 202 may be greater than 5×10 14 cm -3 The inventors of this application found that the doping concentration of 5×10 14 cm -3 is a cut-off point. Taking n-type doped Si material as an example, the doping concentration is greater than 5×10 14 cm -3 The doping concentration of the doping layer is less than 5×10 14 cm -3 The doped layer or the undoped layer has a good etching selectivity. Furthermore, the doping concentration of the sacrificial layer 202 is not suitable to be too high. When the doping concentration of the sacrificial layer 202 is too high, the difference between the lattice constants of the functional layer 201 and the sacrificial layer 202 will increase. In some embodiments, the doping concentration of the sacrificial layer 202 is 6×10 14 cm -3 to 5×10 21 cm -3 , more preferably 1×10 15 cm -3 to 5×10 21 cm -3 .

[0045] The substrate 100 includes a single crystal semiconductor layer on at least a portion of its surface. The substrate 100 may include a single crystal semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaN, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the substrate 100 may be made of crystalline Si. Other layers may be present between the substrate 100 and the stacked structure 200. The materials of the substrate 100 and the functional layer 201 or the sacrificial layer 202 may be the same or different. When the materials of the substrate 100 and the functional layer 201 or the sacrificial layer 202 are different, a buffer layer may be present between the substrate 100 and the stacked structure 200. The buffer layer may be used to gradually shift the lattice constant from that of the substrate 100 to that of the functional layer 201 or the sacrificial layer 202.

[0046] In the SiGe layer of the related art, the Ge content is on the order of 20% to 50%, as shown in Figure 11. This results in a significant difference between the lattice constant of SiGe and that of Si. Therefore, as the number of stacked Si and SiGe layers increases, internal stress accumulates. When the number of stacked Si and SiGe layers reaches a certain level, it can cause wafer warping and, in severe cases, even wafer cracking, thus limiting the number of stacked Si and SiGe layers. In contrast, the functional layer 201 and the sacrificial layer 202 of the embodiment of the present application are made of the same material, differing only in doping concentration. The difference in lattice constant between the functional layer 201 and the sacrificial layer 202 is minimal. Taking the functional layer 201 and the sacrificial layer 202 as an example, when a Group V element such as P is doped into the sacrificial layer 202, the P atoms replace a small number of Si atoms in the Si crystal and occupy positions on the lattice. The doping concentration of conventional semiconductor doping processes is extremely low compared to the Ge content in the SiGe layer. As shown in FIG12 , the lattice constant of the sacrificial layer 202 is barely altered. Therefore, the lattice constants of the functional layer 201 and the sacrificial layer 202 are almost identical. Stress accumulation due to lattice mismatch does not occur at the interface between the functional layer 201 and the sacrificial layer 202, nor does dislocation defects introduce into the functional layer 201. Compared to the related art shown in FIG1 , the thickness of the sacrificial layer 202 of the stacked structure of the embodiment of the present application can be made very thin, for example, consistent with the thickness of the functional layer. This allows for a simple process, a high number of stacked layers, and high production capacity. The stacked layers of the stacked structure of the embodiment of the present application can reach hundreds of layers without causing wafer warpage or cracking, and without introducing dislocation defects due to lattice mismatch into the functional layer 201.

[0047] In some implementations of the embodiments of the present application, the above step S110 may include: using a chemical vapor deposition process to alternately epitaxially grow the functional layer 201 and the sacrificial layer 202 on the substrate 100.

[0048] In the example of Figure 5, the sacrificial layer 202 is first epitaxially grown on the substrate 100, and then the functional layer 201 is epitaxially grown. However, the present application is not limited to this. The functional layer 201 can also be epitaxially grown first, and then the sacrificial layer 202 can be epitaxially grown, and other layers can also exist between the functional layer 201 and the sacrificial layer 202.

[0049] Still taking the functional layer 201 and the sacrificial layer 202 as an example, the step of epitaxially growing the functional layer 201 includes: introducing a silicon-containing gas into the process chamber; the step of epitaxially growing the sacrificial layer 202 includes: introducing a silicon-containing gas and a gas containing an impurity element into the process chamber. More specifically, the process chamber is a chemical vapor deposition (CVD) process chamber, and the silicon-containing gas may include at least one of SiH4, Si2H6, and SiH2Cl2. During the step of epitaxially growing the functional layer 201, the silicon-containing gas is thermally decomposed, and Si atoms are deposited on the substrate surface to form a film. During the step of epitaxially growing the sacrificial layer 202, the silicon-containing gas and the gas containing an impurity element are thermally decomposed, and Si atoms and impurity atoms are deposited on the substrate surface to form a film, i.e., in-situ doping to form a doped semiconductor layer. When n-type doping is required, the impurity-containing gas may include, for example, at least one of PH3, AsH3, SbH3, and BiH3. When p-type doping is required, the impurity-containing gas may include, for example, B2H6. In some embodiments, the sacrificial layer 202 is doped with an impurity element having a large atomic weight, such as As, Sb, or Bi. Accordingly, the impurity-containing gas used in the epitaxial growth of the sacrificial layer 202 may include AsH3, SbH3, or BiH3. Impurity elements having a large atomic weight are less likely to diffuse into the functional layer, thereby preventing a reduction in the doping concentration difference between the sacrificial layer 202 and the functional layer 201 and improving the etch selectivity of the sacrificial layer 202 relative to the functional layer 201.

[0050] In some implementations of the present application, the epitaxial growth temperature is 400° C. to 750° C. The epitaxial growth temperature should not be too high. If the epitaxial growth temperature is too high, some impurity atoms in the sacrificial layer 202 may diffuse into the functional layer 201, which will reduce the doping concentration difference between the sacrificial layer 202 and the functional layer 201, thereby reducing the etching selectivity of the sacrificial layer 202 relative to the functional layer 201 in the subsequent selective etching process.

[0051] S120. Selectively remove the sacrificial layer from the stacked structure.

[0052] As shown in FIG9 , which is a schematic cross-sectional view taken along line AA in FIG1 , the sacrificial layer 202 is selectively removed from the stacked structure 200, leaving only the functional layer 201. In some implementations of the present application, the functional layer 201 can, for example, serve as a channel for a GAA-FET, and in subsequent steps, a gate structure is formed around the functional layer 201.

[0053] In some implementations of the embodiments of the present application, as shown in FIG3 , after step S110 and before step S120, the following steps may be further included:

[0054] S111 . Remove the sacrificial layer 202 of a predetermined thickness.

[0055] As shown in FIG6 , FIG6 is a schematic cross-sectional view along line BB in FIG4 . In the direction along line BB, both sides of the sacrificial layer 202 are removed by a predetermined thickness, which is about 3 nm to 10 nm, more preferably about 5 nm.

[0056] S112 . Fill the space formed after the sacrificial layer 202 is removed by a predetermined thickness with the insulating layer 203 .

[0057] As shown in FIG. 7 , the insulating layer 203 may be silicon nitride, for example, and may be formed by an atomic layer deposition (ALD) process. The insulating layer 203 may be used to prevent a subsequently formed gate structure from being conductive with a source region or a drain region.

[0058] S113 . Epitaxially grow an epitaxial layer 204 on the side of the functional layer 201 .

[0059] As shown in Figure 8 , the epitaxial layer 204 can serve as the source and drain regions of a GAA-FET. Due to the support of the epitaxial layer 204 , after removing the sacrificial layer 202 , multiple functional layers 201 spaced apart from each other can be formed as shown in Figure 9 .

[0060] In some implementations of the embodiments of the present application, the step S120 may include: performing isotropic plasma etching on the stacked structure 200 using a process gas.

[0061] Since the sacrificial layer 202 needs to be laterally etched, isotropic plasma etching is required. During the etching process, the power of the bottom electrode of the process chamber is 0, or a low power bottom electrode power is applied.

[0062] To improve the etch selectivity of the sacrificial layer 202 relative to the functional layer 201, enabling complete removal of the sacrificial layer 202 while leaving the functional layer 201 undamaged or minimally damaged, the inventors of this application have discovered that using a chlorine-containing gas and / or a bromine-containing gas as the main etch gas exhibits excellent selectivity for the highly doped sacrificial layer 202. The chlorine-containing gas may, for example, include at least one of Cl2 and HCl, and the bromine-containing gas may include at least one of Br2 and HBr. To further enhance the etch profile, the process gas may also include an auxiliary etch gas, which may include at least one of N2, He, or Ar. Furthermore, the flow ratio of the auxiliary etch gas to the main etch gas in the process gas may be 3 to 2500, with the main etch gas flow rate ranging from 20 sccm to 1000 sccm and the auxiliary etch gas flow rate ranging from 3 slm to 50 slm. Testing has shown that the isotropic plasma etching method of the embodiments of this application can achieve lateral etching of tens of microns with excellent etch selectivity.

[0063] In some implementations of the embodiments of the present application, after step S120, the following steps may be further included:

[0064] S121 . Perform oxidation treatment on the functional layer 201 .

[0065] The functional layer 201 may contain residual impurity elements due to various factors. For example, in the process of forming the functional layer 201 by epitaxial growth, some impurity atoms in the heavily doped sacrificial layer 202 may diffuse into the functional layer 201, or after the selective etching of the sacrificial layer 202 in step S120 is completed, a small amount of sacrificial layer 202 may still remain on the surface of the functional layer 201. In some application scenarios, the impurity elements remaining in the functional layer 201 may have an adverse effect. For example, when the functional layer 201 serves as the channel of a GAA-FET, the residual impurity elements may make it difficult to completely shut off the channel. In order to remove these impurities, the functional layer 201 can be oxidized to form an oxide layer on the surface of the functional layer 201. When the functional layer 201 is made of Si material, the oxide layer is, for example, a silicon oxide layer. The oxide layer can enrich the impurity atoms near the surface of the functional layer 201 in the oxide layer.

[0066] S122. Remove the oxide layer on the surface of the functional layer 201.

[0067] Since the impurity elements are concentrated in the oxide layer, after removing the oxide layer generated by oxidation on the surface of the functional layer 201 , the impurity elements remaining in the functional layer 201 can be removed.

[0068] After the above steps S121 and S122, not only can the impurity elements remaining in the functional layer 201 be removed, but the surface of the functional layer 201 can also be made smoother. Since the burrs protruding from the surface of the functional layer 201 are more easily oxidized, after the oxide layer on the surface of the functional layer 201 is selectively removed, the burrs on the surface of the functional layer 201 can be removed, thereby further improving the performance of the subsequently manufactured devices. In some embodiments, since the above steps S121 and S122 will remove a certain thickness of the functional layer, the thickness of the functional layer can be made slightly larger than the predetermined thickness during the epitaxial growth of the functional layer, so that the thickness of the functional layer can be exactly equal to the predetermined thickness after steps S121 and S122.

[0069] In order to form a semiconductor device, in some implementations of the embodiments of the present application, after step S120, the following steps may be further included:

[0070] S130. Form a gate structure around the functional layer.

[0071] As shown in FIG10 , a gate structure is formed around the functional layer 201, so that the functional layer 201 serves as a channel of the semiconductor device, and the gate structure is disposed around the channel. The gate structure may include a gate dielectric layer 205 and a gate electrode layer 206 disposed around the functional layer 201. The gate dielectric layer 205 may, for example, include one or more layers of dielectric material, such as a high-k dielectric material such as HfO2; and the gate electrode layer 206 may include one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, alloys thereof, other suitable materials, and / or combinations thereof.

[0072] Accordingly, when the functional layer serves as a channel of a semiconductor device, embodiments of the present application further provide a semiconductor device, as shown in Figures 3 to 10 . The semiconductor device may include a substrate 100; at least one functional layer 201 disposed on the substrate 100, with at least one functional layer 201 spaced apart in the vertical direction, and the functional layers 201 are obtained by the semiconductor structure manufacturing method described above; a gate structure disposed around each functional layer 201; and source / drain regions 204 disposed on either side of and connected to the functional layer 201. Preferably, there are multiple functional layers 201. More specifically, the semiconductor device may be, for example, a 3D DRAM.

[0073] When the functional layer is used as a waveguide for an optical device, an embodiment of the present application further provides an optical device comprising at least one functional layer 201 for transmitting optical signals, the functional layer 201 being obtained by the semiconductor structure manufacturing method described above. Preferably, there are multiple functional layers 201.

[0074] Since the layers in the stacked structure of the embodiment of the present application are made of the same material, the lattice constant difference between the layers is extremely small. During the epitaxial growth process, stress will not be accumulated to cause the wafer to warp or even crack, and dislocation defects will not be introduced into the functional layer. Therefore, the stacked structure of the embodiment of the present application can be formed not only on a plane, but also adaptably formed on various complex surfaces to meet the needs of different application scenarios. In this case, at least a portion of at least one of the functional layers of the stacked structure is curved or bent, and / or at least a portion of at least one of the sacrificial layers of the stacked structure is curved or bent. However, the Si / SiGe stacked structure in the conventional solution introduces greater stress at the bends or bends, making it impossible to manufacture a stacked structure with a curved or bent shape. The following will describe in detail the stacked structure with a curved or bent shape of the embodiment of the present application through several examples. Those skilled in the art should understand that the examples below are not exhaustive. Since there is almost no lattice constant difference between the functional layer and the sacrificial layer of the stacked structure implemented in the present application, those skilled in the art can design other stacked structures with a curved or bent shape according to actual conditions.

[0075] In one example of an embodiment of the present application, as shown in Figures 13 and 14, the substrate 110 includes a wavy surface. Those skilled in the art will appreciate that the substrate 110 does not have to be entirely wavy, and may be only partially wavy. A stacked structure 210 is adaptively formed on the wavy surface of the substrate 110. The stacked structure 210 includes alternating functional layers 211 and sacrificial layers 212. Similarly, the functional layers 211 and sacrificial layers 212 may be alternately epitaxially grown on the substrate 110 using a chemical vapor deposition process. After the sacrificial layers 212 are selectively removed from the stacked structure 210, a plurality of mutually spaced wavy functional layers 211 are formed as shown in Figure 14. For further details on the steps of forming the stacked structure on the substrate and selectively removing the sacrificial layers from the stacked structure, reference may be made to the corresponding description above and will not be repeated here.

[0076] In another example of an embodiment of the present application, as shown in Figures 15 and 16, a substrate 120 includes a protruding structure 122 protruding from the surface of a substrate body 121. A stacked structure 220 is adaptively formed on the surfaces of the substrate body 121 and the protruding structure 122. The stacked structure 220 includes alternating functional layers 221 and sacrificial layers 222. After the sacrificial layers 222 are selectively removed from the stacked structure 220, a plurality of mutually spaced functional layers 221 shaped like the character Ω are formed as shown in Figure 16. In the examples of Figures 15 and 16, the cross-section of the protruding structure 122 is rectangular, however, the present application is not limited thereto, and the protruding structure may also have other shapes. As shown in Figure 17, the protruding structure may be a sawtooth-shaped protruding structure 123 or a trapezoidal-shaped protruding structure 124, etc. In the examples of Figures 15 and 16 , the top and side surfaces of the raised structure 122 are both planar. However, the present application is not limited to this. The surface of the raised structure may be entirely curved, such as the raised structure 125 in Figure 17 , or partially curved, such as the raised structure 126 in Figure 17 . Those skilled in the art will also appreciate that the upper surface of the substrate body 121 is not limited to being planar, but may also include a curved or bent surface. Further details regarding the steps of forming the stacked structure on the substrate and selectively removing the sacrificial layer from the stacked structure can be found in the corresponding description above and will not be repeated here.

[0077] In another example of the present application, as shown in Figures 18 to 20, the substrate 130 has a raised structure protruding from the surface of the substrate body 131. The raised structure may include a first raised portion 132 and a second raised portion 133, wherein the first raised portion 132 is located on the substrate body 131, and the second raised portion 133 is located on the first raised portion 132. The projected area of ​​the second raised portion 133 on the plane of the substrate body 131 is larger than the projected area of ​​the first raised portion 132 on the plane of the substrate body 131, and the projection of the first raised portion 132 on the plane of the substrate body 131 is located within the projection of the second raised portion 133 on the plane of the substrate body 131. A stacked structure 230 is adaptively formed on the surfaces of the substrate body 131 and the raised structure. The stacked structure 230 includes alternating functional layers 231 and sacrificial layers 232. Further details of the steps of forming the stacked structure on the substrate can be found in the corresponding description above and will not be repeated here.

[0078] Furthermore, the step of selectively removing the sacrificial layer 232 from the stacked structure 230 may include:

[0079] S120a. Perform anisotropic etching on the stacked structure 230.

[0080] In this step, lower electrode power can be applied to the process chamber to achieve anisotropic plasma etching. During this anisotropic etching process, the substrate body 131 and the second raised portion 133 have a high etching selectivity relative to the functional layer 231 and the sacrificial layer 232. That is, the second raised portion 133 acts as an etching mask, and the stacked structure 230 except for the portion directly below the second raised portion 133 is etched, leaving only the stacked structure 230 directly below the second raised portion 133, as shown in FIG19 .

[0081] S120 b . Selectively remove the sacrificial layer 232 from the remaining stacked structure 230 .

[0082] As shown in Figure 20, after the sacrificial layer 232 is selectively removed from the stacked structure 230, a plurality of mutually spaced functional layers 221 are formed, similar to square brackets. Further details on the step of selectively removing the sacrificial layer from the stacked structure can be found in the corresponding description above and will not be repeated here.

[0083] In the examples shown in Figures 13 to 20, the formation of a stacked structure on substrates of various morphologies is described as an example. The functional layer and sacrificial layer in the stacked structure are adaptively formed on the substrate to form a curved or bent shape, and the sacrificial layer is selectively removed from the stacked structure to obtain functional layers of different morphologies that are spaced apart from each other. These functional layers of different morphologies can meet the needs of different application scenarios. For example, when the semiconductor structure is used for GAA-FET, the functional layer in the embodiment of the present application is curved or bent. Compared with the straight channel in the conventional GAA-FET, when a gate structure is formed around the functional layer of the embodiment of the present application, its gate width is wider, which can better suppress the short channel effect and achieve better control of leakage current. When the semiconductor structure is used for active or passive optical devices, the functional layer in the embodiment of the present application can act as a waveguide, which can realize the propagation of optical signals between endpoints in different scenarios.

[0084] Accordingly, an embodiment of the present application further provides a semiconductor device, as shown in FIG21 . The semiconductor device may include: a substrate 110; at least one functional layer 211 disposed on the substrate, the at least one functional layer 211 being spaced apart in the vertical direction, and at least a portion of at least one of the functional layers 211 being curved; a gate structure disposed around each functional layer 211; and source / drain regions (not shown) disposed on either side of the plurality of functional layers 211 and connected to the functional layers 211. In this embodiment, the gate structure may include a gate dielectric layer 215 and a gate electrode layer 216 disposed around the functional layers 211. Because the functional layers of the semiconductor device of the embodiment of the present application are curved or bent, the gate width of the semiconductor device of the embodiment of the present application is wider than that of a conventional straight channel, thereby better suppressing the short channel effect and achieving better control of leakage current. Preferably, there are multiple functional layers 211. More specifically, the semiconductor device may be, for example, a 3D DRAM.

[0085] In the example of FIG21 , all functional layers 211 are curved. Those skilled in the art will appreciate that only some of the functional layers 211 may be curved. Furthermore, a functional layer 211 need not be entirely curved; only a portion of a functional layer 211 may be curved. Those skilled in the art will appreciate that a functional layer may also be zigzag, such as the zigzag shown in FIG15 to FIG20 . Similarly, not all functional layers need be zigzag; only some of the functional layers 211 may be zigzag. Furthermore, a functional layer need not be entirely zigzag; only a portion of a functional layer may be zigzag. Those skilled in the art will appreciate that in the semiconductor device of the embodiments of the present application, some functional layers may include curved sections or all may be curved, some functional layers may include curved sections or all may be zigzag, or a functional layer may include both curved and zigzag sections. This application does not impose any limitations on this.

[0086] The above embodiments of this application focus on the differences between the various embodiments. As long as the different optimization features between the various embodiments are not contradictory, they can be combined to form a better embodiment. Considering the simplicity of the text, they will not be repeated here.

[0087] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, Comprising: Forming a stacked structure on a substrate, the stacked structure including alternately stacked functional layers and sacrificial layers, the functional layers and the sacrificial layers being composed of the same material, the sacrificial layers being doped with n-type or p-type impurities, and the doping concentration of the sacrificial layers being greater than the doping concentration of the functional layers; Selectively removing the sacrificial layers from the stacked structure.

2. The manufacturing method according to claim 1, wherein, There are multiple functional layers and sacrificial layers, and at least a part of at least one of the functional layers is curved or bent; and / or At least a part of at least one of the sacrificial layers is curved or bent.

3. The manufacturing method according to claim 1, characterized in that, The substrate is planar, and the stacked structure is formed on the plane; or The substrate includes a wavy surface, and the stacked structure is adaptively formed on the wavy surface; or The substrate includes a convex structure protruding from the surface of the substrate body, and the stacked structure is adaptively formed on the surfaces of the substrate body and the convex structure.

4. The manufacturing method according to claim 3, characterized in that, The convex structure includes: A first convex portion located on the substrate body; A second convex portion located on the first convex portion, the projection area of the second convex portion on the plane where the substrate body is located being greater than the projection area of the first convex portion on the plane where the substrate body is located, and the projection of the first convex portion on the plane where the substrate body is located being within the projection of the second convex portion on the plane where the substrate body is located.

5. The manufacturing method according to claim 4, characterized in that, Selectively removing the sacrificial layers from the stacked structure includes: Performing anisotropic etching on the stacked structure to retain the stacked structure directly below the second convex portion; Selectively removing the sacrificial layers from the retained stacked structure.

6. The manufacturing method according to claim 1, characterized in that, The functional layer is an undoped layer; or the doping concentration of the functional layer is less than 5×10 14 cm -3 ; or The doping concentration of the sacrificial layer is greater than 5×10 14 cm -3 ; or The doping concentration of the sacrificial layer is 6×10 14 cm -3 to 5×10 21 cm -3 .

7. The manufacturing method according to any one of claims 1 to 6, characterized in that, Forming the stacked structure on the substrate includes: Using a chemical vapor deposition process to alternately epitaxially grow the functional layers and the sacrificial layers on the substrate.

8. The manufacturing method according to claim 7, characterized in that, The materials of the functional layers and the sacrificial layers are silicon; The step of epitaxially growing the functional layers includes introducing a silicon-containing gas into the process chamber; The step of epitaxially growing the sacrificial layers includes introducing the silicon-containing gas and a gas containing an impurity element into the process chamber.

9. The manufacturing method according to claim 8, wherein The silicon-containing gas includes at least one of SiH4, Si2H6, and SiH2Cl2; The gas containing an impurity element includes B2H6, or the gas containing an impurity element includes at least one of PH3, AsH3, SbH3, and BiH3.

10. The manufacturing method according to claim 7, characterized in that, The temperature of the epitaxial growth is 400°C to 750°C.

11. The manufacturing method according to any one of claims 1 to 6, characterized in that, Selectively removing the sacrificial layers from the stacked structure includes: Performing isotropic plasma etching on the stacked structure using a process gas.

12. The manufacturing method according to claim 11, characterized in that, The materials of the functional layers and the sacrificial layers are silicon; The process gas includes at least one of a chlorine-containing gas and a bromine-containing gas.

13. The manufacturing method according to claim 12, wherein, The chlorine-containing gas includes at least one of Cl2 and HCl; The bromine-containing gas includes at least one of Br2 and HBr; The process gas further includes at least one of N2, He, and Ar.

14. The manufacturing method according to any one of claims 1 to 6, characterized in that, After selectively removing the sacrificial layers from the stacked structure, it further includes: Performing an oxidation treatment on the functional layers; Removing the oxide layer on the surface of the functional layers.

15. A semiconductor device, characterized in that, Comprising: A substrate; At least one functional layer is disposed on the substrate, at least one of the functional layers is spaced apart in the vertical direction, and at least a part of at least one of the functional layers is curved or bent; A gate structure is disposed around each of the functional layers; Source / drain regions are respectively disposed on both sides of the functional layer and are connected to the functional layer.

16. A semiconductor device, characterized in that, Comprising: A substrate; At least one functional layer is disposed on the substrate, at least one of the functional layers is spaced apart in the vertical direction, and the functional layer is obtained by the manufacturing method of the semiconductor structure according to any one of claims 1 to 14; A gate structure is disposed around each of the functional layers; Source / drain regions are respectively disposed on both sides of the functional layer and are connected to the functional layer.

17. An optical device, characterized in that, Comprising: At least one functional layer for transmitting an optical signal, and the functional layer is obtained by the manufacturing method of the semiconductor structure according to any one of claims 1 to 14.

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