Storage computing unit, array, macro module, and upper-level macro module

Abstract

The present invention relates to the field of mixed-signal compute-in-memory, and relates to a storage computing unit, comprising a 1-bit multiplication unit, a capacitor, an accumulation bus, and a control line, and further comprising a differential capacitor and a differential accumulation bus. The storage computing unit makes the use of an approximation standard 6T SRAM storage unit possible, thereby improving the energy efficiency, computing area efficiency, and storage density. Further provided are a storage computing array comprising a plurality of storage computing units and a plurality of 1-bit SAR logic units, a storage computing macro module comprising the storage computing array and a plurality of comparators, and a storage computing upper-level macro module comprising the storage computing macro module and a plurality of dynamic comparator clock generating units. According to the storage computing array and corresponding SAR logic units and dynamic comparator clock generating units of the present invention, the wiring is simplified, the interconnection parasitics are reduced, the energy efficiency is improved, and the number of metal layers for interconnection is reduced, thereby reducing costs.

Description

A storage computing unit, array, macro module and upper macro module Technical Field

[0001] The present invention belongs to the field of mixed signal storage and computing integration, and relates to a storage computing unit, an array, a macro module and an upper-layer macro module. Background Art

[0002] To address the energy efficiency and computational power challenges of neural network accelerators, integrated memory and compute architectures that transcend the von Neumann paradigm have garnered significant attention in recent years. Integrated memory and compute macromodules based on static random access memory (SRAM) can be categorized as digital memory and compute and mixed-signal memory and compute, depending on the signal representation of multiplication and addition operations. Digital memory and compute, such as TSMC's design, often suffer from excessive area, primarily because digital circuits other than the SRAM cells, such as the adder tree, occupy a significant area, resulting in low storage density. In contrast, mixed-signal memory and compute can perform accumulation on a single metal line placed above the SRAM cells, potentially significantly reducing the need for additional circuitry beyond the SRAM cells. Digital memory and compute boast the inherent numerical / physical equivalence inherent in digital circuits—that is, the chip output is equivalent to the result of the numerical calculation—a characteristic typically lacked by mixed-signal circuits. In addition to the inherent susceptibility of mixed-signal circuits to various non-ideal characteristics, such as comparator input mismatch, comparator noise, capacitor mismatch, and power / ground jitter, the microarchitecture of existing mixed-signal integrated memory and compute macromodules also leads to a lack of computational equivalence. This is primarily due to the mismatch between the dot product dimension and the A / D conversion precision. In the TSMC architecture shown in Figure 1, in a vector-matrix multiplication of 64-dimensional 4-bit activations and 4-bit weights, the full-precision output is 14 bits, yet the A / D conversion directly truncates the output to only 4 bits. Chen Ran, before being input to the next neural network layer, the activations must ultimately be quantized to only 4 bits. However, as Google's quantization algorithm demonstrates, such random truncation is unacceptable to maintain high model inference accuracy. Second, there is a mismatch between the LSB of the dot product operation and the LSB of the A / D conversion. In the Princeton University architecture shown in Figure 2, assuming an accumulation dimension of 2n and an A / D converter precision of n bits, theoretically, each digital output value of the A / D converter has a one-to-one correspondence with each discrete analog value accumulated. However, in physical implementation, the physical devices used for point multiplication and accumulation are different from those used for analog-to-digital conversion, which causes LSB mismatch between the two. In this case, the digital output of the analog-to-digital conversion is more susceptible to interference from non-ideal characteristics such as noise.

[0003] The mixed-signal storage and computing architecture proposed in US Patent US20220276835A1 can solve the above-mentioned problems, but this architecture has some other disadvantages. The most obvious disadvantages include:

[0004] (1) As shown in Figure 1b of U.S. Patent No. 20220276835A1, the 6T cell used is not a standard 6T cell. In addition to its own layout area being larger than that of the standard 6T, the write assist circuit required at normal power supply voltage will increase the macromodule area and power consumption, and is not conducive to normal operation at low power supply voltage. At the same time, the layout itself is more complex than the standard 6T, resulting in increased parasitic capacitance and reduced energy efficiency;

[0005] (2) The SAR analog-to-digital converter has too many control lines for its own DAC. Excessive control lines squeezed into the narrow SRAM column width increase parasitic capacitance and reduce energy efficiency, and the excessive number of metal layers required for connection increases cost.

[0006] Therefore, a new microarchitecture is urgently needed to solve these problems.

[0007] Summary of the Invention

[0008] In view of this, an object of the present invention is to provide a storage computing unit, a storage computing array, a storage computing macro module and a storage computing upper-layer macro module.

[0009] In order to achieve the above object, the present invention provides the following technical solutions:

[0010] In a first aspect of the present invention, there is provided a storage calculation unit comprising a 1-bit multiplication unit, a capacitor, an accumulation bus, and a control line;

[0011] The 1-bit multiplication unit implements 1-bit multiplication, that is, mul=a×w, where a is the activation value provided by the signal A connected to the first input terminal of the 1-bit multiplication unit; w is the weight stored inside the 1-bit multiplication unit; mul or the inverse of mul n mul is provided as a calculation result to the output end of the 1-bit multiplication unit; the bottom plate of the capacitor is connected to the output end of the 1-bit multiplication unit, and the top plate of the capacitor is connected to the accumulation bus; the control line is connected to the second input end of the 1-bit multiplication unit.

[0012] In a second aspect of the present invention, there is provided a storage calculation unit comprising a 1-bit multiplication unit, a capacitor, an accumulation bus, a differential capacitor, a differential accumulation bus, and a control line;

[0013] The 1-bit multiplication unit implements 1-bit multiplication, i.e., mul=a×w, where a is an activation value provided by a signal A connected to a first input terminal of the 1-bit multiplication unit; and w is a weight stored inside the 1-bit multiplication unit.

[0014] mul is the calculation result and is provided to the output of the 1-bit multiplication unit. Correspondingly, mul is negated. n mul is used as the calculation result and provided to the differential output terminal of the 1-bit multiplication unit; or, mul is used as the calculation result and provided to the differential output terminal of the 1-bit multiplication unit, correspondingly, the inversion of mul n mul is the calculation result and is provided to the output of the 1-bit multiplication unit;

[0015] The bottom plate of the capacitor is connected to the output end of the 1-bit multiplication unit, and the top plate is connected to the accumulation bus; the bottom plate of the differential capacitor is connected to the differential output end of the 1-bit multiplication unit, and the top plate is connected to the differential accumulation bus; the control line is connected to the second input end of the 1-bit multiplication unit.

[0016] Furthermore, in the storage computing unit described in the first aspect or the second aspect, the output of the 1-bit multiplication unit is mul, and the 1-bit multiplication unit includes a plurality of SRAM storage cells and a control module, and the plurality of SRAM storage cells share a local bit line and an inverted bit line;

[0017] The control module includes a first inverter, a first PMOS transistor, and a second inverter; the source of the first PMOS transistor is connected to Vdd, the gate is connected to the input signal A as the first input of the 1-bit multiplication unit, and the drain is connected to the source of the PMOS transistor of the first inverter; the drain of the PMOS transistor of the first inverter is connected to the drain of the NMOS transistor, and the source of the NMOS transistor is connected to GND; the input of the first inverter is connected to the control line as the second input of the 1-bit multiplication unit, and the output is connected to the local bit line shared by the multiple SRAM storage cells; the input of the second inverter is connected to the local bit line, and the output of the second inverter serves as the output of the 1-bit multiplication unit.

[0018] Furthermore, the SRAM memory cell is a 6T SRAM memory cell;

[0019] The 6T SRAM memory cell includes a third inverter, a fourth inverter, a first gated access switch, a second gated access switch, a storage word line, and a storage calculation word line; the input of the third inverter is connected to the output of the fourth inverter, and the input of the fourth inverter is connected to the output of the third inverter; the drain of the first gated access switch is connected to the output of the third inverter to store the weight w; the drain of the second gated access switch is connected to the output of the fourth inverter to store the weight inversion nw; the source of the first gated access switch is connected to the inverted bit line, and the source of the second gated access switch is connected to the local bit line; the gate of the first gated access switch is connected to the storage word line, and the gate of the second gated access switch is connected to the storage calculation word line.

[0020] Furthermore, in the storage computing unit described in the first aspect or the second aspect, the output of the 1-bit multiplication unit is n mul, a 1-bit multiplication unit comprising a plurality of SRAM storage cells and a control module, wherein the plurality of SRAM storage cells share a local bit line and an inverted bit line;

[0021] The control module includes a fifth inverter and a second PMOS transistor; the source of the second PMOS transistor is connected to Vdd, the gate is connected to the input signal A as the first input of the 1-bit multiplication unit, and the drain is connected to the source of the PMOS transistor of the fifth inverter; the drain of the PMOS transistor of the fifth inverter is connected to the drain of the NMOS transistor, and the source of the NMOS transistor is connected to GND; the input of the fifth inverter is connected to the control line as the second input of the 1-bit multiplication unit, and the output is connected to the local bit line shared by the multiple SRAM storage cells; the local bit line also serves as the output of the 1-bit multiplication unit.

[0022] Furthermore, the SRAM memory cell is a 6T SRAM memory cell;

[0023] The 6T SRAM memory cell includes a third inverter, a fourth inverter, a first gated access switch, a second gated access switch, a storage word line, and a storage calculation word line; the input of the third inverter is connected to the output of the fourth inverter, and the input of the fourth inverter is connected to the output of the third inverter; the drain of the first gated access switch is connected to the output of the third inverter to store the weight w; the drain of the second gated access switch is connected to the output of the fourth inverter to store the weight inversion nw; the source of the first gated access switch is connected to the inverted bit line, and the source of the second gated access switch is connected to the local bit line; the gate of the first gated access switch is connected to the storage word line, and the gate of the second gated access switch is connected to the storage calculation word line.

[0024] In a third aspect of the present invention, a storage computing array is provided, comprising a plurality of storage computing units as described in the first aspect and a plurality of 1-bit SAR logic units;

[0025] The plurality of storage computing units form a two-dimensional array, wherein the top plates of the capacitors in all the storage computing units in each column of the two-dimensional array are connected to the same accumulation bus; the storage computing units in each column of the two-dimensional array are divided into a plurality of groups, and the storage computing units in the same group share the same control line, which is controlled by a 1-bit SAR logic unit adjacent to the group of storage computing units;

[0026] or,

[0027] comprising a plurality of storage and computing units as described in the second aspect and a plurality of 1-bit SAR logic units;

[0028] Multiple storage computing units form a two-dimensional array, the top plates of the capacitors in all the storage computing units in each column of the two-dimensional array are connected to the same accumulation bus, and the top plates of the differential capacitors in all the storage computing units in each column are connected to the same differential accumulation bus; all the storage computing units in each column of the two-dimensional array are divided into several groups, and the storage computing units in the same group share the same control line, which is controlled by a 1-bit SAR logic unit adjacent to the group of storage computing units.

[0029] Furthermore, the number of storage computing units in each column of the storage computing array is 2 k+1 , k is an integer greater than or equal to 0; all storage calculation units in each column are sequentially divided by 2 k , 2 k-1 ,…,2 1 , 2 0 , 2 0 are divided into k+2 groups; each column has k+1 1-bit SAR logic units, and these k+1 1-bit SAR logic units control the first k+1 groups of storage and calculation units respectively; the control lines of the k+2th group of storage and calculation units are controlled by the storage / calculation logic unit.

[0030] Furthermore, the 1-bit SAR logic unit includes a first NAND gate, a second NAND gate, a third NAND gate, and a first latch;

[0031] The first input end of the first NAND gate is connected to one bit of the first sparse coding signal of the 1-bit activation value vector, and the second input end is connected to one bit of the second sparse coding signal of the 1-bit weight vector; the first input end of the second NAND gate is connected to the storage enable signal, and the second input end is connected to the output end of the first NAND gate; the data input end of the first latch is connected to the output result of the comparator for comparing the voltages on the accumulation bus and the differential accumulation bus, the enable end is connected to the output end of the second NAND gate, and the reset end is connected to the reset signal; the first input end of the third NAND gate is connected to the inverting output end of the first latch, the second input end is connected to the output end of the first NAND gate, and the output end is connected to the control signal.

[0032] Furthermore, the output results of the comparators in each column of the storage and calculation array are divided into several segments by adding a gating unit at the 1-bit SAR logic unit;

[0033] The first input end of the gating unit is connected to the output signal of the gating unit in the previous level 1-bit SAR logic unit or the output result of the ungated comparator, and is also connected to the data input end of the first latch in the current level 1-bit SAR logic unit. The second input end of the gating unit is connected to the gating signal. The output end signal of the gating unit is connected to the first input end of the gating unit in the next level 1-bit SAR logic unit, and is also connected to the data input end of the first latch in the next level 1-bit SAR logic unit.

[0034] Furthermore, the 1-bit SAR logic unit includes a fourth NAND gate, a fifth NAND gate, a sixth inverter, and a second latch;

[0035] The first input end of the fourth NAND gate is connected to one bit of the first sparse coding signal of the 1-bit activation value vector, and the second input end is connected to the third sparsity signal that integrates the sparsity of the 1-bit activation value vector and the sparsity of the 1-bit weight vector; the input end of the sixth inverter is connected to the output end of the fourth NAND gate; the data input end of the second latch is connected to the output result of the comparator for comparing the voltages on the accumulation bus and the differential accumulation bus, the enable end is connected to the output end of the sixth inverter, and the reset end is connected to the reset signal; the first input end of the fifth NAND gate is connected to the inverting output end of the second latch, the second input end is connected to the output end of the fourth NAND gate, and the output end is connected to the control signal.

[0036] Furthermore, the output results of the comparators in each column of the storage and calculation array are added to the gate control unit at each 1-bit SAR logic unit and divided into several segments;

[0037] The first input end of the gating unit is connected to the output signal of the gating unit in the previous level 1-bit SAR logic unit or the output result of the ungated comparator, and is also connected to the data input end of the first latch in the current level 1-bit SAR logic unit. The second input end of the gating unit is connected to the gating signal. The output end signal of the gating unit is connected to the first input end of the gating unit in the next level 1-bit SAR logic unit, and is also connected to the data input end of the first latch in the next level 1-bit SAR logic unit.

[0038] Furthermore, the third sparsity signal in each column of the storage and calculation array is added to a gate control unit at each 1-bit SAR logic unit and is divided into a plurality of segments;

[0039] The first input end of the gating unit is connected to the output signal of the gating unit in the previous level 1-bit SAR logic unit or the ungated third sparsity signal, and is also connected to the second input end of the fourth NAND gate in the current level 1-bit SAR logic unit. The second input end of the gating unit is connected to the gating signal. The output end signal of the gating unit is connected to the first input end of the gating unit in the next level 1-bit SAR logic unit, and is also connected to the second input end of the fourth NAND gate in the next level 1-bit SAR logic unit.

[0040] In a fourth aspect of the present invention, a storage computing macro module is provided, comprising the storage computing array as described in the third aspect and a plurality of comparators;

[0041] Each column in the storage and calculation array corresponds to a comparator; the first input end of each comparator is connected to the accumulation bus of the corresponding column, and the second input end is connected to the reference voltage; alternatively, the first input end of each comparator is connected to the accumulation bus of the corresponding column, and the second input end is connected to the differential accumulation bus of the corresponding column; the output result of the comparator serves as the input of all 1-bit SAR logic units in the corresponding column.

[0042] Furthermore, the comparator is a dynamic comparator.

[0043] In a fifth aspect of the present invention, a storage calculation upper layer macro module is provided, comprising the storage calculation macro module as described above and a plurality of dynamic comparator clock generation units;

[0044] The clock of the dynamic comparator in the storage calculation macromodule is provided by the dynamic comparator clock generating unit; one dynamic comparator corresponds to one dynamic comparator clock generating unit.

[0045] Further, the dynamic comparator clock generation unit includes k+2 selection switches and an AND gate;

[0046] The source of one of the k+2 selection switches is connected to the ground, and the sources of the remaining selection switches are respectively connected to one bit of the fourth sparse coding signal of the 1-bit activation value vector; the gates of the k+2 selection switches are respectively connected to one bit of the fifth sparse coding signal of the 1-bit weight vector; the drains of the k+2 selection switches are connected together to obtain a third sparsity signal that combines the sparsity of the 1-bit activation value vector and the sparsity of the 1-bit weight vector; the first input end of the AND gate is connected to the third sparsity signal, the second input end is connected to the system clock signal, and the output end is the dynamic comparator clock signal provided to the corresponding dynamic comparator.

[0047] The beneficial effects of the present invention are as follows: the storage computing unit of the present invention, due to its innovative topological structure, enables the use of approximately standard 6T SRAM storage cells, thereby resolving many of the aforementioned problems, such as: the large storage cell layout area and complex wiring, which result in reduced energy efficiency, computing area efficiency, and storage density; the requirement for write-assist circuitry at the nominal power supply voltage of a certain process node, which makes low-power supply voltage operation unfriendly; and the increased power consumption and area caused by additional write-assist circuitry. The innovative storage computing array structure of the present invention, as well as the corresponding SAR logic and dynamic comparator clock signal generation circuit, significantly reduce the number of connections in each column, simplify routing, and reduce wiring parasitics, thereby improving energy efficiency and reducing the number of metal layers used for routing, thereby reducing costs.

[0048] Other advantages, objects, and features of the present invention will be described in part in the following description and, in part, will be apparent to those skilled in the art upon examination of the following description or may be learned from practice of the present invention. The objects and other advantages of the present invention may be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below with reference to the accompanying drawings, in which:

[0050] Figure 1 shows TSMC's mixed-signal storage and computing architecture;

[0051] Figure 2 shows Princeton University's mixed-signal storage and computing architecture.

[0052] FIG3 is a schematic diagram of the structure of the storage computing unit according to the first embodiment;

[0053] FIG4 is a schematic structural diagram of a 1-bit multiplication unit when the output is mul according to the first embodiment;

[0054] FIG5 is a diagram of the embodiment 1 when the output is n Schematic diagram of the structure of a 1-bit multiplication unit in mul;

[0055] FIG6 is a schematic diagram of the structure of the storage computing unit according to the second embodiment;

[0056] FIG7 is a schematic structural diagram of a 1-bit multiplication unit according to the second embodiment;

[0057] FIG8 is a schematic diagram of the structure of the improved SRAM storage unit according to the third embodiment;

[0058] FIG9 is a schematic diagram of the overall structure of the storage computing array according to the fourth embodiment;

[0059] FIG10 is a schematic diagram of the structure of a single column in the storage and computing array according to the fourth embodiment;

[0060] FIG11 is a schematic diagram of the structure of a 1-bit SAR logic unit according to the first preferred embodiment of the fourth embodiment;

[0061] FIG12 is a schematic diagram of the optimized structure of a 1-bit SAR logic unit according to the first preferred embodiment of the fourth embodiment;

[0062] FIG13 is a schematic diagram of the structure of a 1-bit SAR logic unit according to the second preferred embodiment of the fourth embodiment;

[0063] FIG14 is a schematic diagram of the optimized structure of a 1-bit SAR logic unit according to the second preferred embodiment of the fourth embodiment;

[0064] FIG15 is a schematic structural diagram of a dynamic comparator clock generating unit according to the fifth embodiment. DETAILED DESCRIPTION

[0065] The following describes the embodiments of the present invention by means of specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0066] Among them, the accompanying drawings are only for illustrative purposes and represent only schematic diagrams rather than actual pictures, and should not be understood as limiting the present invention. In order to better illustrate the embodiments of the present invention, some parts of the accompanying drawings may be omitted, enlarged or reduced, and do not represent the dimensions of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions may be omitted in the accompanying drawings.

[0067] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "back", etc. indicating directions or positional relationships, they are based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0068] Example 1:

[0069] This embodiment provides a storage computing unit, as shown in FIG3 , which includes a 1-bit multiplication unit, a capacitor, an accumulation bus V topp , a control line Ctrl, where the 1-bit multiplication unit is used to implement 1-bit multiplication, that is, mul = a × w, where a is the activation value provided by the signal A connected to the first input terminal of the 1-bit multiplication unit, and w is the weight stored inside the 1-bit multiplication unit. mul or the inverse of mul n mul is provided as the calculation result to the output of the 1-bit multiplication unit; the bottom plate of the capacitor is connected to the output of the 1-bit multiplication unit, and the top plate of the capacitor is connected to the accumulation bus V topp ; The control line Ctrl is connected to the second input terminal of the 1-bit multiplication unit.

[0070] Optionally, the 1-bit multiplication unit includes a plurality of SRAM storage cells and a control module, wherein the plurality of SRAM storage cells share a local bit line BL and an inverted bit line nBL.

[0071] As shown in FIG4 , when the output of the 1-bit multiplication unit is mul, the control module includes a first inverter, a first PMOS transistor, and a second inverter; wherein the source of the first PMOS transistor is connected to Vdd, the gate is connected to the input signal A as the first input of the 1-bit multiplication unit, and the drain is connected to the source of the PMOS transistor of the first inverter; the drain of the PMOS transistor of the first inverter is connected to the drain of the NMOS transistor, and the source of the NMOS transistor is connected to GND; the input of the first inverter is connected to the control line Ctrl as the second input of the 1-bit multiplication unit, and the output of the first inverter is connected to the local bit line BL shared by multiple SRAM storage cells; the input of the second inverter is connected to BL, and the output of the second inverter serves as the output of the 1-bit multiplication unit. The calculation result of the second inverter is the result output by the output of the 1-bit multiplication unit.

[0072] When performing 1-bit multiplication, the Ctrl signal is always 0; when the 1-bit input activation value is 0, the A signal is 0, and all SRAM cells are disconnected from the BL; the BL is charged to a high level at this time, and the output of the second inverter is a low level, that is, the output result mul is 0; when the 1-bit input activation value is 1, the A signal is 1, and the SRAM cell involved in the operation is connected to the BL; if the w value stored in this SRAM cell is 0, then its inverted value, that is, 1, will be transmitted to the BL, and after inversion by the second inverter, the output result mul is 0; if the w value stored in this SRAM cell is 1, then its inverted value, that is, 0, will be transmitted to the BL, and after inversion by the second inverter, the output result mul is 1.

[0073] As shown in Figure 5, when the output of the 1-bit multiplication unit is n When mul is used, the control module only includes the first inverter and the first PMOS transistor. Their connection relationship is the same as when the output of the 1-bit multiplication unit is mul. The second inverter is not included. Instead, the local bit line BL shared by multiple SRAM storage cells is directly output from the output end of the 1-bit multiplication unit as the result of the 1-bit multiplication unit. When performing 1-bit multiplication calculation, the Ctrl signal is always 0; when the 1-bit input activation value is 0, the A signal is 0, and all SRAM cells are disconnected from BL; BL is now charged to a high level, that is, the output result n mul is 1; when the 1-bit input activation value is 1, the A signal is 1, and the SRAM unit involved in the operation is connected to BL; if the w value stored in this SRAM unit is 0, then its inverse value, that is, 1, will be transmitted to BL, that is, the output result n mul is 1; if the w value stored in this SRAM unit is 1, then its inverse value, that is, 0, will be transmitted to BL, that is, the output result n mul is 0.

[0074] Example 2:

[0075] This embodiment provides a storage calculation unit, as shown in FIG6 . Compared with the first embodiment, the storage calculation unit is different in that it further includes a differential capacitor and a differential accumulation bus V topn , where the bottom plate of the differential capacitor is connected to the differential output of the 1-bit multiplication unit, and the top plate is connected to the differential accumulation bus V topn In this embodiment, mul is output as the calculation result from the output terminal of the 1-bit multiplication unit. Correspondingly, the inversion of mul n mul is output from the differential output of the 1-bit multiplication unit as the calculation result; or mul can be output from the differential output of the 1-bit multiplication unit as the calculation result, and correspondingly, the inversion of mul n mul is output as a calculation result from the output terminal of the 1-bit multiplication unit.

[0076] In this embodiment, the 1-bit multiplication unit can provide both the multiplication result and the inversion of the multiplication result, as shown in Figure 7. When performing 1-bit multiplication calculation, the Ctrl signal is always 0; when the 1-bit input activation value is 0, the A signal is 0, and all SRAM cells are disconnected from BL; BL is charged to a high level at this time, and the output of the second inverter is a low level, that is, the output result mul is 0, and after passing through the differential second inverter, the output result nmul is 1; when the 1-bit input activation value is 1, the A signal is 1, and the SRAM unit involved in the operation is connected to BL; if the w value stored in this SRAM unit is 0, then its inverted value, that is, 1, will be transmitted to BL, and after being inverted by the second inverter, the output result mul is 0. At the same time, after passing through the differential second inverter, the output result n mul is 1; if the w value stored in this SRAM unit is 1, then its inverted value, that is, 0, will be transmitted to BL, and after being inverted by the second inverter, the output result mul is 1. At the same time, after passing through the differential second inverter, the output result n mul is 0.

[0077] Example 3:

[0078] In this embodiment, an improved SRAM memory cell is provided as the SRAM memory cell in Embodiments 1 and 2. As shown in FIG8 , the SRAM memory cell in this embodiment is a 6T SRAM memory cell, which includes a third inverter, a fourth inverter, a first gated access switch, and a second gated access switch. The input of the third inverter is connected to the output of the fourth inverter, and the input of the fourth inverter is connected to the output of the third inverter; the drain of the first gated access switch is connected to the output of the third inverter, storing a weight w; the drain of the second gated access switch is connected to the output of the fourth inverter, storing a weight nw; the source of the first gated access switch is connected to the inverted bit line nBL, and the source of the second gated access switch is connected to the local bit line BL; the gate of the first gated access switch is connected to the storage word line WL, and the gate of the second gated access switch is connected to the storage / calculation word line WL / A.

[0079] When the SRAM memory cells in the 1-bit multiplication unit of Example 2 utilize the 6T SRAM memory cells of this embodiment, these 6T SRAM memory cells participate in the operation in a time-division multiplexed manner. When writing to a memory cell, the WL and WL / A bits of that memory cell are high, signal A is low, and the content written is controlled by Ctrl. If nw is low, nBL is high and Ctrl is high; if nw is high, nBL is low and Ctrl is low. During analog-to-digital conversion, the WL and WL / A bits of all memory cells are low, signal A is low, and Ctrl is controlled by SAR logic. During 1-bit multiplication, Ctrl is low. If the activation value is low, the WL / A bits of the 6T SRAM memory cells in Figure 8 are low, and signal A in Figure 6 is low, resulting in a multiplication result of mul being 0. If the activation value is high, regardless of whether Ctrl is high or low at the end of the analog-to-digital conversion phase, Ctrl immediately becomes low upon entering the calculation phase. After a short delay, A transitions from low to high to ensure that BL is charged to a high level. After a short delay, WL / A changes from low to high. If the weight w is low, BL remains at a high level, and the multiplication result mul is 0; if the weight w is high, BL is discharged to a low level, and the multiplication result mul is 1.

[0080] Example 4:

[0081] This embodiment provides a storage computing array, which is composed of a plurality of storage computing units and a plurality of 1-bit SAR logic units in the first embodiment. The plurality of storage computing units form a two-dimensional array, and the top plates of the capacitors in all storage computing units in each column of the two-dimensional array are connected to the same accumulation bus. The accumulation bus to which the top plates of the capacitors in the storage computing units in the jth column of the storage computing array are connected is represented by V topp_j All storage computing units in each column of the two-dimensional array are divided into several groups from top to bottom. The storage computing units in the same group share the same control line. The control line that the storage computing units in the g-th group of the j-th column in the storage computing array are connected to is represented by Ctrl gj , and the control line Ctrl gj Controlled by a 1-bit SAR logic unit adjacent to the group of storage and calculation units.

[0082] Optionally, the storage computing array provided in this embodiment may also be composed of a plurality of storage computing units and a plurality of 1-bit SAR logic units in the second embodiment, with the difference being that: in a two-dimensional array composed of a plurality of storage computing units, the top plates of the differential capacitors in all storage computing units in each column are connected to the same differential accumulation bus, and the accumulation bus to which the top plates of the differential capacitors in the storage computing units in the j-th column of the storage computing array are commonly connected is represented by V topn_j .

[0083] Optionally, as shown in Figures 9-10, the number of storage computing units in each column of the storage computing array is 2 k+1 , k is an integer greater than or equal to 0; all storage calculation units in each column are 2 from top to bottom k , 2 k-1 ,…,2 1 , 2 0 , 2 0 The first k+1 groups are each connected to a 1-bit SAR logic unit adjacent to it. During analog-to-digital conversion, the output of the comparator is used as the input of this 1-bit SAR logic. Each column has k+1 1-bit SAR logic units. These k+1 1-bit SAR logic units control the first k+1 groups of storage and calculation units from top to bottom. The control line of the k+2 group of storage and calculation units at the bottom is controlled by the storage / calculation logic unit. The advantage of this architecture is that one control line only passes through one group of calculation units, and there is only one D line carrying the comparator result. cmp The lines pass through, so that there are at most two lines related to SAR logic control passing through each group of computing units.

[0084] As a preferred solution of this embodiment, the 1-bit SAR logic unit includes a first NAND gate, a second NAND gate, a third NAND gate, and a first latch; as shown in FIG11 , taking the 1-bit SAR logic unit connected to the j-th column and the g-th group of storage calculation units in the storage calculation array as an example, the first input end of the first NAND gate is connected to the first sparse coding signal A of the 1-bit activation value vector sparsity The g-th A in sparsity_g The second input terminal is connected to the second sparse coding signal W of the j-th column 1-bit weight vector sparsity_j The g-th W in sparsity_gj The first input terminal of the second NAND gate is connected to the storage enable signal nen write The gth nen in write_g , the second input end is connected to the output end of the first NAND gate; the data input end (D end) of the first latch is connected to the output result D of the comparator corresponding to the jth column cmp_j The enable terminal (E terminal) is connected to the output terminal of the second NAND gate, and the reset terminal (R terminal) is connected to the reset signal rst; the first input terminal of the third NAND gate is connected to the inverting output terminal (nQ terminal) of the first latch, the second input terminal is connected to the output terminal of the first NAND gate, and the output terminal is connected to the control signal Ctrl gj .

[0085] The sparsity is measured by the number of 1s in a single-bit weight vector or a single-bit activation value vector. The more 1s there are, the lower the sparsity is, and the fewer 1s there are, the higher the sparsity is. sparsity_j and A sparsityBoth are represented in binary and are encoded in thermometer code; storage enable signal nen write Also expressed in binary; if the dot product dimension is 2 k+1 , then W sparsity_j 、A sparsity and nen write Both have k+1 bits.

[0086] W sparsity_j The value of each bit is stored in the SRAM cell adjacent to its corresponding 1-bit SAR logic. In FIG7 of the second embodiment, as many SRAM storage cells are used for time division multiplexing in each storage calculation unit, the number of SRAM storage cells required for each group of calculation units sharing the 1-bit SAR logic is the same as that required to store W. sparsity_gj value.

[0087] A sparsity The 1 in the SAR analog-to-digital conversion phase appears as a single-cycle high pulse. These pulses appear in sequence according to the conversion process from high to low in the SAR analog-to-digital conversion. After the calculation phase, the analog-to-digital conversion phase begins. In the first conversion cycle, A sparsity The bit where the high pulse appears is the first non-zero bit from the highest bit to the lowest bit; in the subsequent conversion cycle, high pulses appear in sequence from the second non-zero bit to the lowest bit until the last bit in A sparsity_1 A high pulse appears on the sparsity If all 0s are present, the calculation of the input activation value vector and the analog-to-digital conversion phase are completely skipped, and the next A is calculated directly. sparsity The input activation value vector that is not all zeros.

[0088] 2 in a column of the storage calculation array k+1 The number of 1s stored in the storage units involved in the calculation in the storage calculation unit N W_1 and k+1 bits W sparsity_j The corresponding relationship between the values ​​of k+1 The number of 1s in the N-dimensional input activation value vector A_1 and k+1 bits A sparsity The corresponding relationship of the values ​​is as follows:

[0089] N W_1 is 0, W sparsity_j The values ​​of k+1 bits are all 0; N A_1 is 0, A sparsity The k+1 bits of are all 0;

[0090] N W_1 The range is 2 i to 2 i+1 -1, 0≤i≤k-1, W sparsity_jThe value of the lowest i+1 bits is 1, and the values ​​of other bits are 0; N A_1 The range is 2 i to 2 i+1 -1, 0≤i≤k-1, A sparsity The value of the lowest i+1 bits is 1, and the values ​​of the other bits are 0;

[0091] N W_1 The range is 2 k to 2 k+1 , W sparsity_j The values ​​of k+1 bits are all 1; N A_1 The range is 2 k to 2 k+1 , A sparsity The values ​​of the k+1 bits are all 1.

[0092] nen write It is low when writing to the storage unit, and high in other stages, such as calculation and analog-to-digital conversion stages; in the write operation stage, nen write All bits can be low, or one bit can be low. write_g When the storage unit in the corresponding storage computing unit group is written, nen write_g becomes low.

[0093] When writing to a memory cell, D cmp_j The value of is equal to the value of the written weight W; at this time A sparsity_g is low, W sparsity_gj High or low, nen write_g The driving line of the control line is Ctrl. gj Equal to D cmp_j , it can be inferred from the circuits of FIG7 and FIG8 that the stored value of w is equal to the value of W.

[0094] During the 1-bit multiplication calculation stage, A sparsity_g is low, and the first latch in Figure 11 is also reset, so the inverting output terminal nQ value is high, so Ctrl gj Is low.

[0095] During the analog-to-digital conversion phase, nen write_g According to the sparsity of the corresponding weight and input activation value vector, whenever A sparsity_g or W sparsity_gj is low, then Ctrl gj Maintaining it low indicates that the capacitors of this group of computing units do not participate in the flip, thus saving energy. sparsity_gj is high, and in a certain conversion cycle A sparsity_g Also for High, Ctrl gjIf high, the step of guessing bit value in SAR algorithm is performed. After the comparison result is obtained, D cmp_j The value of A sparsity_g After going low, it is retained in the first latch, Ctrl gj The value is equal to the saved D cmp_j value.

[0096] Optionally, as shown in FIG12 , the D in each column of the storage calculation array is cmp_j The signal is divided into several segments by adding a gate control unit at the 1-bit SAR logic unit; the gate control unit is the first AND gate, and the first input end of the first AND gate is connected to the output signal D of the gate control unit in the previous 1-bit SAR logic unit. cmp_gj , or connect the output result of the ungated comparator, and also connect the data input terminal (D terminal) of the first latch in this level of 1-bit SAR logic unit, and the second input terminal of the first AND gate is connected to the gating signal en gate_g , output signal D cmp_(g+1)j Connect to the first input terminal of the gate control unit in the next level 1-bit SAR logic unit, and also connect to the data input terminal (D terminal) of the first latch in the next level 1-bit SAR logic unit. cmp_gj Is the value on the D transmitted to the next segment? cmp_(g+1)j By signalen gate_g During the conversion process, if the capacitance of the highest bit (k+1) of the analog-to-digital conversion needs to be flipped, then en gate_1 Until the kth gate signal en gate_k Should be 1. If the conversion cycle reaches the lowest bit, then en gate All bits of should be 0. The same is true for other cases. The gate unit in the k+1th group of 1-bit SAR logic, that is, the gate unit with D cmp_kj The gating unit for the input can be omitted.

[0097] As another preferred solution of this embodiment, the structure of a 1-bit SAR logic unit is shown in FIG13 , which includes a fourth NAND gate, a fifth NAND gate, a sixth inverter, and a second latch; the first input end of the fourth NAND gate is connected to a bit A in the first sparse coding signal of the 1-bit activation value vector. sparsity_g The second input terminal is connected to the third sparsity signal en which combines the sparsity of the 1-bit activation value vector and the sparsity of the 1-bit weight vector. conv_j The input of the sixth inverter is connected to the output of the fourth NAND gate; the data input of the second latch (D terminal) is connected to the output of the comparator corresponding to the jth column D cmp_j, the enable terminal (E terminal) is connected to the output terminal of the sixth inverter, and the reset terminal (R terminal) is connected to the reset signal rst; the first input terminal of the fifth NAND gate is connected to the inverting output terminal (nQ terminal) of the second latch, the second input terminal is connected to the output terminal of the fourth NAND gate, and the output terminal is connected to the control signal Ctrl gj In write mode, conv_j The signal carries the weight value W, the second latch is placed in the reset state, and the output of nQ is always 1. sparsity When it is also 1, Ctrl gj The value of is equal to the value of W written into the storage calculation unit. This solution can save the 1-bit SAR logic in the previous solution because of the storage W sparsity_gj The value of the SRAM memory cell is required to store the additional memory.

[0098] Optionally, as shown in FIG14 , the D in each column of the storage calculation array is cmp_j The signal is added to the gate control unit at each 1-bit SAR logic unit and is divided into several segments, thereby saving energy consumption; the gate control unit includes a second AND gate, the first input end of the second AND gate is connected to the output signal D of the gate control unit in the previous 1-bit SAR logic unit cmp_gj , or connect the output result of the ungated comparator, and also connect the data input terminal (D terminal) of the second latch in this level 1-bit SAR logic unit, and the second input terminal of the second AND gate is connected to the gating signal en gate_g , output signal D cmp_(g+1)j It is connected to the first input terminal of the gate control unit in the next stage 1-bit SAR logic unit, and is also connected to the data input terminal (D terminal) of the second latch in the next stage 1-bit SAR logic unit.

[0099] In Figure 14, the en in each column of the storage calculation array conv_j The signal is also added to the gate control unit at each 1-bit SAR logic unit and is divided into several segments; the gate control unit includes a third AND gate, and the first input end of the third AND gate is connected to the output signal en of the gate control unit in the previous 1-bit SAR logic unit. conv_gj , or connected to the third sparse signal that is not gated, and also connected to the second input of the fourth NAND gate in this level of 1-bit SAR logic unit, and the second input of the third AND gate is connected to the gate signal en gate_g The output signal enconv_(g+1)j is connected to the first input of the gate control unit in the next-stage 1-bit SAR logic unit, and is also connected to the second input of the fourth NAND gate in the next-stage 1-bit SAR logic unit.

[0100] Embodiment 5:

[0101] This embodiment provides a storage calculation macro module, including the storage calculation array and a plurality of comparators as described in the fourth embodiment; each column in the storage calculation array corresponds to a comparator; the first input terminal of each comparator is connected to the accumulation bus V of the corresponding column topp_j , the second input terminal is connected to the reference voltage; or the first input terminal of each comparator is connected to the accumulation bus V of the corresponding column topp_j The second input terminal is connected to the differential accumulation bus V of the corresponding column topn_j The output of the comparator is used as the input of all 1-bit SAR logic units in the corresponding column. cmp_j .

[0102] In addition to the Ctrl gj Signal-controlled capacitor arrays use data sparsity to reduce flipping, thereby saving energy and increasing throughput. Dynamic comparators can also use data sparsity to reduce the number of comparisons. Normally, in a k+1-bit analog-to-digital conversion, the comparator needs to compare k+1 times. However, considering sparsity, the number of comparisons can be reduced to A. sparsity With W sparsity_j The one with the least number of 1s will prevail. sparsity There are a 1s in W sparsity_j If there are b 1s in , then the number of comparisons by the comparator is min(a, b), where min(a, b) represents the minimum value of a and b, and 0≤a,b≤k+1. Therefore, as a preferred solution of this embodiment, the comparator is a dynamic comparator. Combining a storage computing macromodule with several dynamic comparator clock generation units yields a storage computing upper-layer macromodule, where the clock for the dynamic comparator in the storage computing macromodule is provided by the dynamic comparator clock generation unit; one dynamic comparator corresponds to one dynamic comparator clock generation unit.

[0103] Optionally, as shown in FIG15 , the dynamic comparator clock generation unit includes k+2 selection switches and a fourth AND gate; one source of the k+2 selection switches is connected to the ground, and the remaining sources are respectively connected to one bit A in the fourth sparse coding signal of the 1-bit activation value vector. PWM_sparsity_g The gates of the k+2 selection switches are respectively connected to one bit W in the fifth sparse coding signal of the 1-bit weight vector OH_sparsity_gj The drains of the k+2 selection switches are connected together to obtain a third sparsity signal en that combines the sparsity of the 1-bit activation value vector and the sparsity of the 1-bit weight vector conv_j The first input terminal of the fourth AND gate is connected to the third sparsity signal en conv_j The second input terminal is connected to the system clock signal clk, and the output terminal is the dynamic comparator clock signal clk provided to the corresponding dynamic comparator cmp_j. In this possibility, the third sparsity signal en conv_j is generated during the process of generating a gating clock for the dynamic comparator. Specifically, the signal before the AND gate of clk cmp_j is regarded as en conv_j .

[0104] For the first signal line to the k+1 signal line, the names of the signals carried are A PWM_sparsity_1 , A PWM_sparsity_2 , …, A PWM_sparsity_k , A PWM_sparsity_(k+1) , which are shared by all columns of the entire memory computing array; these k+1 signal lines may have high-level periods only during the analog-to-digital conversion stage in the computing mode and are all at low level during the computing stage; during the analog-to-digital conversion stage, the total number of conversion periods is the number of bits with value 1 in A sparsity ; if this number N A_1 = 0, then the entire computing and analog-to-digital conversion stages of this 2 k+1 -dimensional input activation value vector can be skipped and the next N A_1 ≠0 input activation value vector can be directly calculated; if this number is 1≤N A_1 ≤k+1, then the waveform of A sparsity_(k+1-j) is that for 0≤j≤(k+1-N A_1 ), it is high in all N A_1 cycles, and for (k+1-N A_1 )<j≤k, it is high in the k+1-j cycles before the end of the analog-to-digital conversion stage;

[0105] W OH_sparsity_j has a total of k+2 bits, and the relationship between the number N k+1 of stored units with value 1 in the stored units participating in the operation in the second stored computing unit in the j-th column of the memory computing array and the value of the k+2-bit W W_1 is as follows: OH_sparsity_j When N

[0106] is 0, the lowest bit of the k+2 bits of W W_1 is 1, and the values of the other bits are 0; OH_sparsity_j When the range of N

[0107] is 2 i to 2 i+1 -1, 0≤i≤k-1, the (i+2)-th bit from the lowest bit of W OH_sparsity_j is 1, and the values of the other bits are 0; W_1 When the range of N

[0108] is 2 k to 2 k+1 , W OH_sparsity_j ​​The most significant bit of the k+2 bits is 1, and the values ​​of the other bits are 0.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, which should all be included in the scope of the claims of the present invention.

Claims

1. A storage computing unit, characterized in that: It includes a 1-bit multiplication unit, a capacitor, an accumulation bus, and a control line; The 1-bit multiplication unit implements 1-bit multiplication, that is, mul=a×w, where a is an activation value provided by a signal A connected to a first input terminal of the 1-bit multiplication unit; w is a weight stored inside the 1-bit multiplication unit; mul or the negation of mul nmul is provided as the calculation result to the output end of the 1-bit multiplication unit; the bottom plate of the capacitor is connected to the output end of the 1-bit multiplication unit, and the top plate of the capacitor is connected to the accumulation bus; The control line is connected to the second input terminal of the 1-bit multiplication unit.

2. A storage computing unit, characterized in that: including a 1-bit multiplication unit, a capacitor, an accumulation bus, a differential capacitor, a differential accumulation bus, and a control line; The 1-bit multiplication unit implements 1-bit multiplication, that is, mul=a×w, where a is an activation value provided by a signal A connected to a first input terminal of the 1-bit multiplication unit; w is a weight stored inside the 1-bit multiplication unit; mul is used as the calculation result and provided to the output end of the 1-bit multiplication unit. Correspondingly, the inverse of mul, nmul, is used as the calculation result and provided to the differential output end of the 1-bit multiplication unit. Alternatively, mul is provided as a calculation result to the differential output terminal of the 1-bit multiplication unit, and correspondingly, the negation of mul, nmul, is provided as a calculation result to the output terminal of the 1-bit multiplication unit; The bottom plate of the capacitor is connected to the output end of the 1-bit multiplication unit, and the top plate is connected to the accumulation bus; The bottom plate of the differential capacitor is connected to the differential output terminal of the 1-bit multiplication unit, and the top plate is connected to the differential accumulation bus; The control line is connected to the second input terminal of the 1-bit multiplication unit.

3. The storage computing unit according to claim 1 or 2, characterized in that: The output of the 1-bit multiplication unit is mul, and the 1-bit multiplication unit includes a plurality of SRAM storage units and a control module, and the plurality of SRAM storage units share a local bit line and an inverted bit line; The control module includes a first inverter, a first PMOS tube and a second inverter; the source of the first PMOS tube is connected to Vdd, the gate is connected to the input signal A as the first input of the 1-bit multiplication unit, and the drain is connected to the source of the PMOS tube of the first inverter; the drain of the PMOS tube of the first inverter is connected to the drain of the NMOS tube, and the source of the NMOS tube is connected to GND, the input end of the first inverter is connected to the control line as the second input end of the 1-bit multiplication unit, and the output end is connected to the local bit line shared by the multiple SRAM storage units; the input end of the second inverter is connected to the local bit line, and the output end of the second inverter is used as the output end of the 1-bit multiplication unit.

4. The storage computing unit according to claim 3, characterized in that: The SRAM storage unit is a 6T SRAM storage unit; The 6T SRAM storage cell includes a third inverter, a fourth inverter, a first gate access switch, a second gate access switches, storage word lines, and storage computation word lines; The input of the third inverter is connected to the output of the fourth inverter, and the input of the fourth inverter is connected to the output of the third inverter; the drain of the first gated access switch is connected to the output of the third inverter to store the weight w; the drain of the second gated access switch is connected to the output of the fourth inverter to store the inverted weight nw; the source of the first gated access switch is connected to the inverted bit line, and the source of the second gated access switch is connected to the local bit line; the gate of the first gated access switch is connected to the storage word line, and the gate of the second gated access switch is connected to the storage calculation word line.

5. The storage computing unit according to claim 1 or 2, characterized in that: The output of the 1-bit multiplication unit is n mul, the 1-bit multiplication unit includes a plurality of SRAM storage cells and a control module, the plurality of SRAM storage cells share a local bit line and an inverted bit line; The control module includes a fifth inverter and a second PMOS tube; the source of the second PMOS tube is connected to Vdd, the gate is connected to the input signal A as the first input end of the 1-bit multiplication unit, and the drain is connected to the source of the PMOS tube of the fifth inverter; the drain of the PMOS tube of the fifth inverter is connected to the drain of the NMOS tube, and the source of the NMOS tube is connected to GND, the input of the fifth inverter is connected to the control line as the second input end of the 1-bit multiplication unit, and the output end is connected to the local bit line shared by the multiple SRAM storage units; the local bit line also serves as the output end of the 1-bit multiplication unit.

6. A storage computing array, characterized in that: comprising a plurality of storage computing units as claimed in claim 1 and a plurality of 1-bit SAR logic units; A plurality of storage computing units form a two-dimensional array, and the top plates of the capacitors in all the storage computing units in each column of the two-dimensional array are connected to the same accumulation bus; all the storage computing units in each column of the two-dimensional array are divided into a plurality of groups, and the storage computing units in the same group share the same control line, and the control line is controlled by a 1-bit SAR logic unit adjacent to the group of storage computing units; or, comprising a plurality of storage computing units as claimed in claim 2 and a plurality of 1-bit SAR logic units; The plurality of storage computing units form a two-dimensional array, the top plates of the capacitors in all the storage computing units in each column of the two-dimensional array are connected to the same accumulation bus, and the top plates of the differential capacitors in all the storage computing units in each column are connected to the same differential accumulation bus; All storage computing units in each column of the two-dimensional array are divided into several groups. The storage computing units in the same group share the same control line, and the control line is controlled by a 1-bit SAR logic unit adjacent to the group of storage computing units.

7. The storage computing array according to claim 6, characterized in that: The number of storage computing units in each column of the storage computing array is 2 k+1 , k is an integer greater than or equal to 0; all storage computing units in each column are sequentially divided by 2 k , 2 k-1 , …, 2 1 , 2 0 , 2 0 are divided into k+2 groups; each column has k+1 1-bit SAR logic units, and these k+1 1-bit SAR logic units control the first k+1 groups of storage and calculation units respectively; the control lines of the k+2th group of storage and calculation units are controlled by the storage / calculation logic unit.

8. The storage computing array according to claim 6, characterized in that: The 1-bit SAR logic unit includes a first NAND gate, a second NAND gate, a third NAND gate and a first latch; A first input end of the first NAND gate is connected to one bit of a first sparse coding signal of a 1-bit activation value vector, and a second input end is connected to one bit of a second sparse coding signal of a 1-bit weight vector; The first input terminal of the second NAND gate is connected to the storage enable signal, and the second input terminal is connected to the output terminal of the first NAND gate; the data input terminal of the first latch is connected to the output result of the comparator used to compare the voltages on the accumulation bus and the differential accumulation bus, the enable terminal is connected to the output terminal of the second NAND gate, and the reset terminal is connected to the reset signal; the first input terminal of the third NAND gate is connected to the inverting output terminal of the first latch, the second input terminal is connected to the output terminal of the first NAND gate, and the output terminal is connected to the control signal.

9. The storage computing array according to claim 8, characterized in that: The output results of the comparators in each column of the storage calculation array are divided into several segments by adding a gating unit at the 1-bit SAR logic unit; The first input end of the gating unit is connected to the output signal of the gating unit in the previous level 1-bit SAR logic unit or the output result of the non-gated comparator, and is also connected to the data input end of the first latch in the 1-bit SAR logic unit of this level. The second input end of the gating unit is connected to the gating signal. The output end signal of the gating unit is connected to the first input end of the gating unit in the next level 1-bit SAR logic unit, and is also connected to the data input end of the first latch in the next level 1-bit SAR logic unit.

10. The storage computing array according to claim 6, characterized in that: The 1-bit SAR logic unit includes a fourth NAND gate, a fifth NAND gate, a sixth inverter and a second latch; The first input of the fourth NAND gate is connected to one bit of the first sparse coding signal of the 1-bit activation value vector, and the second input is connected to the third sparsity signal that integrates the sparsity of the 1-bit activation value vector and the sparsity of the 1-bit weight vector; the input of the sixth inverter is connected to the output of the fourth NAND gate; the data input of the second latch is connected to the output result of the comparator used to compare the voltages on the accumulation bus and the differential accumulation bus, the enable terminal is connected to the output of the sixth inverter, and the reset terminal is connected to the reset signal; the first input of the fifth NAND gate is connected to the inverting output of the second latch, the second input is connected to the output of the fourth NAND gate, and the output is connected to the control signal.

11. The storage computing array according to claim 10, characterized in that: The output results of the comparators in each column of the storage calculation array are added to the gating unit at each 1-bit SAR logic unit and divided into several segments; The first input end of the gating unit is connected to the output signal of the gating unit in the previous 1-bit SAR logic unit or the output result of the ungated comparator, and is also connected to the first latch of the 1-bit SAR logic unit of this level. The data input terminal, the second input terminal of the gating unit is connected to the gating signal, and the output terminal signal of the gating unit is connected to the first input terminal of the gating unit in the next level 1-bit SAR logic unit, and is also connected to the data input terminal of the first latch in the next level 1-bit SAR logic unit.

12. The storage computing array according to claim 10, characterized in that: The third sparse signal in each column of the storage calculation array is added to the gating unit at each 1-bit SAR logic unit and is divided into a plurality of segments; The first input end of the gating unit is connected to the output signal of the gating unit in the previous level 1-bit SAR logic unit or the third sparse signal that is not gated, and is also connected to the second input end of the fourth NAND gate in the 1-bit SAR logic unit of this level. The second input end of the gating unit is connected to the gating signal. The output end signal of the gating unit is connected to the first input end of the gating unit in the next level 1-bit SAR logic unit, and is also connected to the second input end of the fourth NAND gate in the next level 1-bit SAR logic unit.

13. A storage computing macro module, characterized in that: comprising the storage computing array as claimed in claim 6 and a plurality of comparators; Each column in the storage calculation array corresponds to a comparator; the first input end of each comparator is connected to the accumulation bus of the corresponding column, and the second input end is connected to the reference voltage; or the first input end of each comparator is connected to the accumulation bus of the corresponding column, and the second input end is connected to the differential accumulation bus of the corresponding column; The output of the comparator is used as the input of all 1-bit SAR logic cells in the corresponding column.

14. The storage computing macro module according to claim 13, characterized in that: The comparator is a dynamic comparator.

15. A storage and calculation upper layer macromodule, characterized in that: It comprises the storage computing macromodule as claimed in claim 14 and a plurality of dynamic comparator clock generating units; The clock of the dynamic comparator in the storage calculation macromodule is provided by the dynamic comparator clock generating unit; one dynamic comparator corresponds to one dynamic comparator clock generating unit.

16. The storage and calculation upper layer macromodule according to claim 15, characterized in that: The dynamic comparator clock generation unit includes k+2 selection switches and an AND gate; The source of one of the k+2 selection switches is connected to the ground, and the sources of the other selection switches are respectively connected to one bit of the fourth sparse coding signal of the 1-bit activation value vector; the gates of the k+2 selection switches are respectively connected to one bit of the fifth sparse coding signal of the 1-bit weight vector; the drains of the k+2 selection switches are connected together to obtain a third sparsity signal that combines the sparsity of the 1-bit activation value vector and the sparsity of the 1-bit weight vector; the first input terminal of the AND gate is connected to the third sparsity signal, the second input terminal is connected to the system clock signal, and the output terminal is the dynamic comparator clock signal provided to the corresponding dynamic comparator.

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