Code vectorization method and apparatus

Abstract

Embodiments of the present application relate to the technical field of computers, and provide a code vectorization method and apparatus. The method comprises: acquiring attribute information of a multi-dimensional cyclic code comprising a plurality of single-layer cyclic codes, and on the basis of the attribute information, determining a hardware logic layer corresponding to each layer of target cyclic code in the multi-dimensional cyclic code, wherein one layer of target cyclic code is a single-layer cyclic code to be vectorized; on the basis of an upper limit of the length of each hardware logic layer corresponding to each layer of target cyclic code, splitting a target cyclic code to obtain a plurality of code blocks, and on the basis of a hierarchical relation between the hardware logic layers corresponding to the plurality of code blocks, combining the plurality of code blocks into a plurality of multi-dimensional cyclic sub-codes; and on the basis of the plurality of multi-dimensional cyclic sub-codes and the attribute information, updating the multi-dimensional cyclic code into a vector instruction for a vector computing unit to perform vector computation. The embodiments of the present application can vectorize the multi-dimensional cyclic code without being limited by the form of an upper cyclic bound, so as to improve the computing efficiency.

Description

Code vectorization method and device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 30, 2023, with application number 202311128725.4 and invention name “Code Vectorization Method and Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of computer technology, and in particular to a code vectorization method and device. Background Art

[0003] In computationally intensive applications such as magnetic field simulation, voice interaction, and computer vision, the code used to implement the application can be vectorized to improve computational efficiency. Vectorization can include converting scalars in the code into vectors during code compilation. This allows the vector computing unit in hardware with vector computing capabilities (such as artificial intelligence (AI) chips) to compute multiple scalars in parallel within a single tick (e.g., a clock cycle), thereby improving computational efficiency.

[0004] In related technologies, loop codes in code are often the source of a large amount of calculations, and the loop codes can be vectorized as described above. For example, some chips support vectorization of multi-dimensional loop codes, i.e., nested loops: after determining that the loop upper bound (a value that expresses the upper limit of the loop range, and the number of loops can be calculated by the loop upper bound) of each layer of loop in the multi-dimensional loop code is a constant, i.e., the multi-dimensional loop code is a static shape loop, and the number of loops of each layer of loop meets the length upper limit of the vector calculation unit, vector instructions can be generated based on the interval step of the memory address accessed by the calculation in the loop code and the mask of the loop code, and the loop code can be directly replaced with vector instructions so that the vector calculation unit can perform vector calculations.

[0005] However, in real-world applications, most multidimensional loop codes are dynamic-shape loops. The upper bound of each loop layer is not a constant, causing the aforementioned chip to abandon vectorization for dynamic-shape loops. Furthermore, if the number of iterations of one or more layers in some static-shape loops exceeds the upper limit of the vector computation unit, the chip will also abandon vectorization for static-shape loops. This can easily lead to vectorization failures.

[0006] Summary of the Invention

[0007] To address the above technical issues, the present application provides a code vectorization method and apparatus. In this code vectorization method, multidimensional loop codes are segmented and combined to obtain multidimensional sub-loop codes that can be processed by a vector computing unit. This allows for vectorization of loop codes of any number of loops, avoids vectorization failures caused by length limitations, and improves computational efficiency.

[0008] In a first aspect, an embodiment of the present application provides a code vectorization method, the method comprising: obtaining attribute information of a multidimensional loop code; wherein the multidimensional loop code includes multiple single-layer loop codes, each single-layer loop code in the multiple single-layer loop codes is used to implement one layer of the multi-layer loop; determining, based on the attribute information, a hardware logic layer corresponding to each layer of target loop code in the multidimensional loop code; wherein each layer of target loop code is a single-layer loop code to be vectorized in the multiple single-layer loop codes; the multiple hardware logic layers are used to indicate the multi-level memory access rules of a vector computing unit, each hardware logic layer corresponding to one layer of the multi-level memory access rules; dividing the target loop code according to the upper limit of the length of each hardware logic layer corresponding to each layer of the target loop code to obtain multiple code blocks, and combining the multiple code blocks into multiple multidimensional sub-loop codes according to the hierarchical relationship between the hardware logic layers corresponding to the multiple code blocks; updating the multidimensional loop code into vector instructions based on the multiple multidimensional sub-loop codes and the attribute information; wherein the vector instructions are used by the vector computing unit to perform vector calculations.

[0009] In an embodiment of the present application, each layer of loop code in a multidimensional loop code is divided into multiple code blocks according to the length upper limit of the hardware logic layer in the vector computing unit, and the multiple code blocks are combined into multiple multidimensional sub-loops according to the hierarchical relationship of the hardware logic layer in the vector computing unit, thereby ensuring that the dimension and length of each multidimensional sub-loop code meet the processing conditions of the hardware logic layer. On this basis, the multidimensional loop code can be updated to a vector instruction. In this way, the vectorization of the multidimensional loop code is not restricted by static or dynamic shape, nor by the length of any layer of loop, thereby avoiding the problem of vectorization failure and improving computing efficiency.

[0010] According to the first aspect, the attribute information includes a hierarchical relationship between multiple single-layer loop codes; based on the attribute information, the hardware logic layer corresponding to each layer of target loop code in the multidimensional loop code is determined, including: based on the hierarchical relationship between the multiple single-layer loop codes, the multiple single-layer loop codes in the multidimensional loop code are determined; the mapping parameters set by the user in the preset interface are read; wherein the mapping parameters are used to indicate the hardware logic layer used by each layer of target loop code; based on the mapping parameters and the multiple single-layer loop codes, the hardware logic layer is allocated to each layer of target loop code in the multidimensional loop code.

[0011] In an embodiment of the present application, users can control the mapping relationship between the target loop code and the hardware logic layer in the multi-dimensional loop code through a preset interface to achieve priority vectorization of long loops, thereby increasing the amount of data calculated by each vector instruction and improving computing performance. In other words, users can determine a more accurate mapping relationship based on their perception of the number of loops in the business code, that is, select a loop matching method with better computing performance, and solve the problem of potential performance optimization loss caused by the inability to perceive the number of loops due to dynamic shapes during the compilation process. Even with dynamic shapes, users may have some room for length, thereby avoiding placing short loops in the inner layer of the loop or participating in vectorization.

[0012] According to the first aspect, or any implementation method of the first aspect above, the attribute information includes the loop upper bound of each single-layer loop code and the hierarchical relationship between multiple single-layer loop codes; based on the attribute information, the hardware logic layer corresponding to each layer of target loop code in the multidimensional loop code is determined, including: based on the hierarchical relationship between the multiple single-layer loop codes, the multiple single-layer loop codes are determined; based on the loop upper bound of each single-layer loop code and the length upper limit of each hardware logic layer and the multiple single-layer loop codes, a hardware logic layer is allocated to each layer of target loop code with a constant loop upper bound in the multiple single-layer loop codes; based on the loop hierarchical relationship between the multiple single-layer loop codes and the hierarchical relationship between the multiple hardware logic layers, a hardware logic layer is allocated to each layer of target loop code with a variable loop upper bound in the multiple single-layer loop codes with the loop hierarchical relationship between the multiple single-layer loop codes and the hierarchical relationship between the multiple hardware logic layers, with the loop hierarchy of the target loop code matching the hierarchy of the hardware logic layer as an allocation rule.

[0013] In an embodiment of the present application, for scenarios where the user has not set the mapping relationship between the target loop code and the hardware logic layer, the mapping relationship between the target loop code and the hardware logic layer is determined based on different situations where the loop upper bound of the loop implemented by the target loop code is a constant or a variable, combined with the limitations of the hardware logic layer, thereby further expanding the scope of application, reducing the problem of vectorization failure, and improving computing efficiency.

[0014] According to the first aspect, or any implementation of the first aspect above, based on the hierarchical relationship between the hardware logic layers corresponding to the multiple code blocks, the multiple code blocks are combined into multiple multidimensional sub-loop codes, including: according to a combination rule that matches the loop level in the multidimensional sub-loop implemented by each multidimensional sub-loop code in the multidimensional sub-loop code with the hierarchical relationship between the hardware logic layers corresponding to the multidimensional sub-loop code, one code block from the multiple code blocks corresponding to each layer of the target loop code is combined into a multidimensional sub-loop code, until the multiple code blocks corresponding to each layer of the target loop code are all combined to obtain the multidimensional sub-loop code.

[0015] In the embodiment of the present application, according to the hierarchical relationship of the hardware logic layers corresponding to the code blocks, one code block is taken from any target loop layer and combined into a multi-dimensional sub-loop code, until the combination of all code blocks is completed, and multiple multi-dimensional sub-loop codes are obtained. The code blocks of the remaining target loop layers can be avoided. The combination does not conform to the original loop structure and there are too many combination results, thereby ensuring the loop correctness of the multi-dimensional sub-loop obtained by the combination and theoretically the minimum number of sub-loops and the minimum vector instructions, further improving the computing efficiency.

[0016] According to the first aspect, or any implementation of the first aspect above, the attribute information includes the interval step size of each single-layer loop code memory access; based on multiple multidimensional sub-loop codes and attribute information, the multidimensional loop code is updated to a vector instruction, including: for each multidimensional sub-loop code in the multiple multidimensional sub-loop codes, the following operations are performed to generate a vector instruction of the multidimensional sub-loop code: according to the length upper limit of the hardware logic layer corresponding to the innermost sub-loop code in the multidimensional sub-loop code and the number of loops implemented by the innermost sub-loop code, a mask of the innermost sub-loop code is generated; starting from the outermost sub-loop code of the innermost sub-loop code in the multidimensional sub-loop code, based on the length upper limit of the hardware logic layer corresponding to the innermost sub-loop code, the number of loops implemented by the innermost sub-loop code, the mask of the innermost sub-loop code is generated. The upper limit of the length of the hardware logic layer corresponding to the layer sub-loop code, the mask of the inner layer sub-loop code, and the number of loops of the layer sub-loop code are used to generate a mask for the layer sub-loop code until the mask of each sub-loop code in the multidimensional sub-loop code is generated to obtain the mask of the multidimensional sub-loop code; wherein the mask of the multidimensional sub-loop code is used to indicate the attribute information of the sub-loop code in the multidimensional sub-loop code whose number of loops is less than the upper limit length of the hardware logic layer corresponding to the multidimensional sub-loop code; according to the interval step of each target loop code corresponding to the multidimensional sub-loop code and the mask of the multidimensional sub-loop code, a vector instruction of the multidimensional sub-loop code is generated; and the multidimensional loop code is replaced by using the vector instruction of each multidimensional sub-loop code in the plurality of multidimensional sub-loop codes.

[0017] In the embodiments of this application, a mask is in the form of a register. By setting a mask, the non-vectorized portion can be shielded, preventing computational anomalies caused by incorrect memory modifications. This solves the problem of tail block correctness in the vectorization of dynamic shape multi-dimensional loops. Furthermore, for multi-dimensional loop code scenarios, masks can be quickly generated by extending from the inner layer to the outer layer and filling in the inner layer mask according to the number of loops in that layer, further improving computational efficiency.

[0018] According to the first aspect, or any implementation of the first aspect above, the target loop code is divided according to the upper limit of the length of the hardware logic layer corresponding to each layer of the target loop code to obtain multiple code blocks, including: dividing the target loop code into non-tail blocks whose number of loops is an integer multiple of the upper limit of the length of the corresponding hardware logic layer, and tail blocks whose number of loops is less than the upper limit of the length of the corresponding hardware logic layer, respectively, according to the upper limit of the length of the hardware logic layer corresponding to each layer of the target loop code.

[0019] In an embodiment of the present application, the multi-dimensional loop code is segmented according to the length upper limit of the hardware logic layer, thereby ensuring that the multi-dimensional sub-loops obtained based on the subsequent combination of the segmentation results can be processed by the vector computing unit, avoiding the problem of vectorization failure.

[0020] In a second aspect, an embodiment of the present application provides a code vectorization device, the device comprising: a parsing and mapping module for obtaining attribute information of a multidimensional loop code; wherein the multidimensional loop code comprises multiple single-layer loop codes, each of the multiple single-layer loop codes being used to implement one layer of loop in a multi-layer loop; determining, based on the attribute information, a hardware logic layer corresponding to each layer of target loop code in the multidimensional loop code; wherein each layer of target loop code is a single-layer loop code to be vectorized in the multiple single-layer loop codes; the multiple hardware logic layers are used to indicate multi-level memory access rules of a vector computing unit, each hardware logic layer corresponding to one layer of memory access rules in the multi-level memory access; a loop segmentation module for segmenting the target loop code according to the length upper limit of each hardware logic layer corresponding to each layer of target loop code, obtaining multiple code blocks, and combining the multiple code blocks into multiple multidimensional sub-loop codes according to the hierarchical relationship between the hardware logic layers corresponding to the multiple code blocks;

[0021] The instruction replacement module is used to update the multi-dimensional loop code into a vector instruction based on multiple multi-dimensional sub-loop codes and attribute information; wherein the vector instruction is used for the vector calculation unit to perform vector calculation.

[0022] According to the second aspect, the attribute information includes a hierarchical relationship between multiple single-layer loop codes; a parsing mapping module is specifically used to: determine multiple single-layer loop codes in a multidimensional loop code based on the hierarchical relationship between the multiple single-layer loop codes; read the mapping parameters set by the user in a preset interface; wherein the mapping parameters are used to indicate the hardware logic layer used by each layer of target loop code; and allocate a hardware logic layer to each layer of target loop code in the multidimensional loop code based on the mapping parameters and the multiple single-layer loop codes.

[0023] According to the second aspect, or any implementation of the second aspect above, the attribute information includes the loop upper bound of each single-layer loop code and the hierarchical relationship between multiple single-layer loop codes; the parsing mapping module is specifically used to: determine multiple single-layer loop codes in the multidimensional loop code based on the hierarchical relationship between multiple single-layer loop codes; allocate a hardware logic layer to each layer of target loop code with a constant loop upper bound in the multiple single-layer loop codes based on the loop upper bound of each single-layer loop code and the upper limit of the length of each hardware logic layer and multiple single-layer loop codes; allocate a hardware logic layer to each layer of target loop code with a variable loop upper bound in the multiple single-layer loop codes based on the loop hierarchical relationship between multiple single-layer loop codes and the hierarchical relationship between multiple hardware logic layers, with the loop hierarchy of the target loop code matching the hierarchy of the hardware logic layer as the allocation rule.

[0024] According to the second aspect, or any implementation of the second aspect above, the loop segmentation module is specifically used to: according to a combination rule that matches the loop level in the multidimensional sub-loop implemented by each multidimensional sub-loop code in the multidimensional sub-loop code with the hierarchical relationship of each hardware logic layer corresponding to the multidimensional sub-loop code, combine one code block from the multiple code blocks corresponding to each layer of the target loop code into a multidimensional sub-loop code, until all the multiple code blocks corresponding to each layer of the target loop code are combined to obtain the multidimensional sub-loop code.

[0025] According to the second aspect, or any implementation of the second aspect above, the attribute information includes the interval step size of each single-layer loop code memory access; the instruction replacement module is specifically used to: for each multidimensional sub-loop code in the multiple multidimensional sub-loop codes, perform the following operations to generate a vector instruction of the multidimensional sub-loop code: according to the length upper limit of the hardware logic layer corresponding to the innermost sub-loop code in the multidimensional sub-loop code and the number of loops implemented by the innermost sub-loop code, generate a mask for the innermost sub-loop code; starting from the outermost sub-loop code of the innermost sub-loop code in the multidimensional sub-loop code, based on the length upper limit of the hardware logic layer corresponding to the innermost sub-loop code and the number of loops of the hardware logic layer corresponding to the sub-loop code of this layer ... The mask of the sub-loop code of the current layer is generated by using the upper limit of the length of the logical layer, the mask of the sub-loop code of the inner layer, and the number of loops of the sub-loop code of the current layer, until the mask of each sub-loop code in the multidimensional sub-loop code is generated, thereby obtaining the mask of the multidimensional sub-loop code; wherein the mask of the multidimensional sub-loop code is used to indicate the attribute information of the sub-loop code in the multidimensional sub-loop code whose number of loops is less than the upper limit length of the hardware logical layer corresponding to the multidimensional sub-loop code; according to the interval step of each target loop code corresponding to the multidimensional sub-loop code and the mask of the multidimensional sub-loop code, a vector instruction of the multidimensional sub-loop code is generated; and the multidimensional loop code is replaced by using the vector instruction of each multidimensional sub-loop code in the plurality of multidimensional sub-loop codes.

[0026] According to the second aspect, or any implementation of the second aspect above, the loop splitting module is specifically used to: split the target loop code into non-tail blocks whose number of loops is an integer multiple of the upper limit of the length of the corresponding hardware logic layer, and tail blocks whose number of loops is less than the upper limit of the length of the corresponding hardware logic layer, respectively according to the upper limit of the length of the hardware logic layer corresponding to each layer of the target loop code.

[0027] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here.

[0028] In a third aspect, an embodiment of the present application provides an electronic device comprising: a processor and a memory; the processor and the memory are connected; the memory is used to store one or more programs; when the one or more programs are executed by one or more processors, the one or more processors implement a method as in the first aspect and any one of the implementation methods of the first aspect.

[0029] In a fourth aspect, an embodiment of the present application provides a computer-readable medium for storing a computer program, wherein the computer program includes instructions for executing the method in the first aspect or any possible implementation of the first aspect.

[0030] In a fifth aspect, an embodiment of the present application provides a computer program comprising instructions for executing the method in the first aspect or any possible implementation of the first aspect.

[0031] In a sixth aspect, embodiments of the present application provide a chip comprising a processing circuit and transceiver pins. The transceiver pins and the processing circuit communicate with each other via an internal connection path, and the processing circuit executes the method of the first aspect or any possible implementation of the first aspect to control the receive pin to receive a signal and to control the transmit pin to send a signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] FIG1 is a schematic block diagram of an application scenario provided by an embodiment of the present application;

[0034] FIG2 is a block diagram of a compiler provided in an embodiment of the present application;

[0035] FIG3 is a flow chart of a code vectorization method according to an embodiment of the present application;

[0036] FIG4 is a flow chart of a code vectorization method according to an embodiment of the present application;

[0037] FIG5 is an example diagram of a mask structure of a multi-dimensional sub-loop code in a code vectorization method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0039] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0040] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0041] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0042] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0043] To facilitate understanding of this embodiment, some technical terms and background technologies involved in this embodiment are first introduced:

[0044] Multi-dimensional loop: A loop structure formed by nesting multiple loops. The calculation, memory access and other operations in the multi-dimensional loop can be related to the iteration position of any layer or layers of the multi-dimensional loop.

[0045] Automatic vectorization: An optimization method that integrates scalar calculations in the code into vector calculations, calling the chip's vector calculation unit to calculate multiple scalar data within a single beat (such as a clock cycle), equivalent to performing batch calculations within a beat. Scalar calculation refers to performing a single calculation within a beat.

[0046] Dynamic shape: The shape of the input object is a dynamic variable and is unknown at compile time. This describes the variables in loops that represent the loop upper bound and the number of iterations.

[0047] Vector Instructions: Some platforms, such as computers, feature a comprehensive vector operation instruction set. The fundamental operation object of vector instructions is a vector, an ordered set of numbers. If an instruction is a vector operation, it specifies the address of the vector operand (main memory starting address or vector register number) and explicitly or implicitly specifies other vector parameters such as the increment and vector length. Vector instructions specify that the processor processes all components of a vector using the same operation, effectively increasing computer processing speed.

[0048] Loop upper bound: A value that expresses the upper limit of the loop range. The loop upper bound can be used to calculate the number of loops, etc.

[0049] Intermediate representation (IR): Also known as intermediate code. The front-end module of the compiler performs lexical analysis, syntax analysis, and semantic analysis on the input program to generate an intermediate representation, also known as the intermediate representation. The back-end module of the compiler optimizes the IR (such as Java bytecode) to generate target code (such as machine code).

[0050] A bit mask (also known as a mask) is a string of binary digits in computer science that, through bitwise operations on a target number, masks specific bits. A bit mask uses numerical values ​​to record states. For example, each bit of a number can have two values, 0 and 1, with each bit representing a state. Using a bit mask, a rich set of states can be expressed with minimal resources. Based on this, masks in vectorization are used to indicate which data must be included in vector calculations. Bits with a value of 0 in the mask exclude the corresponding data from the calculation, while bits with a value of 1 indicate that the corresponding data is included.

[0051] The loop code used to implement loop logic in the business code can be one-dimensional or multi-dimensional. For example, a one-dimensional loop code, i.e., a layer of loop code, can be the code shown in Table 1-1 below:

[0052] If the computations in the loop code access continuous memory addresses, i.e., continuous memory access, the one-dimensional loop code can be directly segmented based on the upper limit of the vector compute unit length (e.g., LIMIT). Each segment of the loop code after segmentation meets the hardware vector compute unit length, except for the last segment, which can be smaller than this length, i.e., the tail block. For example, the one-dimensional loop code of length n in Table 1-1 can be segmented into n = x × LIMIT + y. Here, x × LIMIT is the loop length x, and y is the tail block. Each iteration is the data for calculating the LIMIT length in the loop, and this calculation of the LIMIT length can be converted into vector instructions, i.e., vectorized. In this way, the loop upper limit n can be a dynamic variable, allowing it to be processed by the vector compute unit even if it exceeds the upper limit of the hardware vector compute unit length. Based on this, for multidimensional loop code, if the computations and memory accesses of the multidimensional loop code are continuous, the multidimensional loop code can be collapsed into a one-dimensional loop code, and then vectorized using the processing method described above for the one-dimensional loop code.

[0053] However, in specific business scenarios, the vast majority of loop codes are multidimensional and not completely continuous, making them impossible to collapse. Therefore, the aforementioned collapse-and-splitting approach is still susceptible to vectorization failure, resulting in minimal performance improvement. In the case of multidimensional loop codes, if the number of iterations of the innermost loop of the multidimensional loop code is less than the upper limit of the vector computation unit length, vectorization computation is limited, and the performance loss is even more significant.

[0054] For example, the multi-dimensional loop code, i.e., the multi-layer loop code, may be the code shown in Table 1-2 below:

[0055] If the multidimensional loop code has a completely static shape, that is, the upper bound of each loop layer must be a constant known to the compiler, such as in[0…8) shown in Table 1-2, and the length of each loop layer in the multidimensional loop code meets the upper limit of the vector computing unit, and the vector computing unit supports vectorization of nested loops, vectorization can be achieved by directly replacing the loop with vector instructions without making any changes to the loop itself.

[0056] However, in real-world applications, the vast majority of loops are dynamic-shape loops. The vectorization method used in the examples in Table 1-2 can only optimize static-shape loops, forgoing optimization of dynamic-shape loops. Furthermore, not all static-shape loops can be optimized: vectorization is only possible when the length of each loop layer does not exceed the length limit of the corresponding hardware vector compute unit dimension. If the number of loops in one or more layers exceeds the limit, vectorization is abandoned for the entire loop. These two reasons result in very few loops in business code being vectorized, leading to vectorization failures and limited computing performance improvements.

[0057] The embodiment of the present application provides a code vectorization method to solve the above problems. The method divides each layer of loop code in the multidimensional loop code into multiple code blocks according to the upper limit of the length of the hardware logic layer in the vector calculation unit, and combines the multiple code blocks into multiple multidimensional sub-loops according to the hierarchical relationship of the hardware logic layer in the vector calculation unit, thereby ensuring that the dimension and length of each multidimensional sub-loop code meet the processing conditions of the hardware logic layer. On this basis, the multidimensional loop code can be updated to a vector instruction. In this way, the vectorization of the multidimensional loop is not limited by the static or dynamic shape, and the length of any layer of loop, thereby avoiding the problem of vectorization failure and improving computing efficiency.

[0058] Before describing the technical solutions of the embodiments of the present application, the application scenarios of the code vectorization methods of the embodiments of the present application are first described with reference to the accompanying drawings. The embodiments of the present application can be applied to business scenarios such as AI and HPC (high-performance computing) with high real-time requirements, as well as business scenarios such as meteorological analysis and magnetic field simulation calculations with large-scale data computing requirements. The code vectorization methods provided by the embodiments of the present application can be applied to any logic involving a large number of multi-dimensional loop calculations in the calculation. During specific implementation, the embodiments of the present application can be applied to compilers and hardware with multi-dimensional vector computing capabilities. For example, the compiler can be an independent software product without being embedded in the hardware module. During runtime, the compiler program code can run in the host memory of the server, and the compiled binary can be executed in the processor memory. Hardware with multi-dimensional vector computing capabilities can be, for example, various chips such as GPUs and CPUs. In one example, the above chip can support multi-dimensional interval memory access. Alternatively, in one example, the hardware can be a computer, server, computing cluster composed of multiple servers, or other electronic devices that include a chip with a vector computing unit with multi-dimensional vector computing capabilities and hardware instructions that support multi-dimensional interval, i.e., discontinuous memory access.

[0059] For example, Figure 1 is a schematic block diagram of an application scenario provided by an embodiment of the present application. As shown in Figure 1 , the embodiment of the present application can be applied to a computing platform, which can include: a compiler 101 and hardware 102.

[0060] Compiler 101 is configured to obtain source code written by a developer and compile it to generate a binary file executable by hardware 102. Compiler 101 may specifically include a vectorization module group 1011, which is configured to vectorize nested loops in the source code through a parsing and mapping module 1101, a loop splitting module 1102, and an instruction replacement module 1103 before compiler 101 generates a binary file.

[0061] The compiler 101 can also be used to obtain attribute information of nested loops in the source code, ie, the business code.

[0062] The parsing and mapping module 1101 is used to establish a mapping relationship between code loops and hardware instruction loops.

[0063] The loop segmentation module 1102 is used to segment the loop and construct a loop that meets the limitations of the hardware 102.

[0064] The instruction replacement module 1103 is used to replace loops that meet the limitations of the hardware 102 with hardware vector instructions.

[0065] The hardware 102 specifically processes vector instructions through the vector calculation unit 1021. The hardware 102 limits the length of the vector calculation unit 1021. It is understood that in specific applications, the compiler 101 can convert vector instructions into binary files, and the hardware 102 processes the binary vector instructions.

[0066] In one example, FIG2 is a block diagram of a compiler provided by an embodiment of the present application. As shown in FIG2 , the compiler may include: a language front end 1104 , a parsing and mapping module 1101 , a loop segmentation module 1102 , and an instruction replacement module 1103 .

[0067] The language front end 1104 is used to obtain attribute information of a multi-dimensional loop code in a business code for implementing a multi-layer loop; wherein the multi-dimensional loop code includes multiple single-layer loop codes, each of which is used to implement a layer of loop in the multi-layer loop.

[0068] The parsing mapping module 1101 is used to determine the hardware logic layer corresponding to each layer of the target loop code in the multi-layer target loop code based on the attribute information; wherein the multi-layer target loop code includes multiple single-layer loop codes to be vectorized in the multi-dimensional loop code; multiple hardware logic layers are used to indicate the multi-level memory access rules of the vector computing unit, and each hardware logic layer corresponds to one layer of memory access rules in the multi-level memory access.

[0069] The loop segmentation module 1102 is configured to segment the target loop code according to the upper limit of the length of each hardware logic layer corresponding to each layer of the target loop code to obtain multiple code blocks, and combine the multiple code blocks into multiple multi-dimensional sub-loop codes according to the hierarchical relationship between the hardware logic layers corresponding to the multiple code blocks;

[0070] The instruction replacement module 1103 is configured to update the multi-dimensional loop code into a vector instruction based on the multiple multi-dimensional sub-loop codes and the attribute information.

[0071] Specifically, the language front-end 1104 converts source code into intermediate code, which is equivalent to the front-end of the compiler. The processing of the intermediate code by the parsing and mapping module 1101 and the loop segmentation module 1102 is equivalent to the mid-end optimization of the compiler. The processing of the output of the loop segmentation module 1102 by the instruction replacement module 1103 is equivalent to the back-end optimization of the compiler.

[0072] To facilitate understanding and reasonable layout, the code vectorization method provided in the embodiment of the present application is specifically described below with reference to Figures 3 to 5.

[0073] FIG3 is a flow chart of a code vectorization method provided in an embodiment of the present application. As shown in FIG3 , taking the application of the code vectorization method to a compiler as an example, the method may include but is not limited to the following steps:

[0074] S301, acquiring attribute information of a multi-dimensional cyclic code; wherein the multi-dimensional cyclic code includes a plurality of single-layer cyclic codes, and each of the plurality of single-layer cyclic codes is used to implement a layer of cyclic in a multi-layer cyclic.

[0075] The compiler can read the business code from the storage device, convert the business code into an intermediate code, and obtain the structural information of the multidimensional loop written by the developer in the business code from the intermediate code through the functional functions and interfaces in the compiler. In one example, the compiler can also obtain the memory access information of the multidimensional loop. The attribute information of the multidimensional loop code used to implement multi-layer loops may include at least the structural information of the multidimensional loop, and may also include memory access information. For example, the structural information may include the parent-child relationship between each layer of loops in the multidimensional loop, that is, the hierarchical relationship and the number of executions of each layer of loops, that is, the number of loops. The memory access information may include the memory access interval of each layer of loops. The memory access interval may include the interval distance or step length between the memory addresses accessed by the calculations in each layer of loops.

[0076] For example, the multi-dimensional loop code in the service code of the embodiment of the present application may be the code shown in the following Table 2-1:

[0077] For the multi-dimensional loop code in Table 2-1, the structural information includes three layers of loops: the innermost loop is loop k, its parent loop is loop j, and its parent loop is loop i, the outermost loop. The lengths of these three loops are p, n, and m, respectively. Based on the loop structure, the memory access index calculated in the loop is index = k + j × p + i × n × p. This indicates that the memory access interval calculated in the loop is 1 for the innermost loop, p for the second loop, and n × p for the third loop.

[0078] S302, based on the attribute information, determine the hardware logic layer corresponding to each layer of target loop code in the multi-dimensional loop code; wherein each layer of target loop code is a single layer of loop code to be vectorized among multiple single layer loop codes; multiple hardware logic layers are used to indicate the multi-level memory access rules of the vector computing unit, and each hardware logic layer corresponds to one layer of memory access rules in the multi-level memory access.

[0079] After obtaining the attribute information of the multi-dimensional loop code, the compiler can determine the hardware logic layer corresponding to each layer of the target loop code in the multi-dimensional loop code based on the attribute information. It can be understood that each layer of memory access rules in the multi-level memory access rules includes rules such as the memory access interval and length upper limit adopted by the memory access at that level. Each hardware logic layer corresponds to one layer of memory access rules in the multi-level memory access. The memory access interval of the hardware logic layer is the interval between the memory addresses corresponding to the operands and the calculation results in each iterative change when the vector calculation unit performs vector calculations through the hardware logic layer. The length upper limit of the hardware logic layer is the upper limit of the number of scalar calculations performed in parallel in the vector calculation when the vector calculation unit performs vector calculations through the hardware logic layer. In other words, the vector calculation unit can perform multi-level vector calculations according to the multi-level memory access rules.

[0080] Exemplarily, the attribute information of a multi-dimensional loop code may indicate the hierarchical relationship and loop upper bound between single-layer loop codes in the multi-dimensional loop code. The single-layer loop codes in Table 2-1 may include k-loops, j-loops, and i-loops. A single-layer loop code may implement one layer of loop, i.e., one iteration change, for the calculation "A[k+j*p+i*n*p]=B[k+j*p+i*n*p]+C[k+j*p+i*n*p]". The loop upper bound of any loop code refers to the maximum number of iterations for the calculation. Based on the attribute information, the compiler may determine the hardware logic layer corresponding to each layer of target loop code in the multi-dimensional loop code, i.e., establish a mapping relationship between the target loop code and the hardware logic layer. In this mapping relationship, one target loop code may correspond to one or more hardware logic layers, and one hardware logic layer may correspond to one target loop code.

[0081] In an optional embodiment, FIG4 is a flowchart of a code vectorization method provided in an embodiment of the present application. As shown in FIG4 , in the code vectorization method provided in an embodiment of the present application, S302 shown in FIG3 above, when the user sets mapping parameters, may specifically include:

[0082] S3021, determining a plurality of single-layer loop codes in the multidimensional loop code according to a hierarchical relationship between the plurality of single-layer loop codes;

[0083] S3022, reading the mapping parameters set by the user in the preset interface; wherein the mapping parameters are used to indicate the hardware logic layer used by each layer of the target loop code;

[0084] S3023 , allocating a hardware logic layer to each layer of target loop code in the multi-dimensional loop code according to the mapping parameters and the multiple single-layer loop codes.

[0085] For example, as shown in Table 2-1 above, the compiler can determine multiple single-layer loop codes in the multidimensional loop code based on the hierarchical relationship between multiple single-layer loop codes: the innermost loop is the k loop, the parent loop of the k loop is the j loop, and the parent loop of the j loop is the outermost loop, the i loop. The preset interface can be vectorhint(). The number of parameters in vectorhint is used to indicate the number of hardware logic layers, and the order of the parameter arrangement is used to indicate the hierarchical relationship between multiple hardware logic layers. For example, in vectorhint(0,1,1), the number of parameters is 3, which means that the vector calculation unit supports three-layer loop expression, that is, it contains three layers of hardware logic layers; the parameters are arranged from left to right, which means that the hierarchical relationship of the three layers of hardware logic layers is from inner to outer. In an optional example, the arrangement of parameters from left to right can represent that the hierarchical relationship of the three layers of hardware logic layers is from outer to inner. The numerical value of the parameter represents different single-layer loop codes in the multidimensional loop code. For example, in vectorhint(0,1,1), 0 represents the innermost layer, that is, the first layer of single-layer loop code, and the numerical value of the parameter increases toward the outer layer, that is, 1 represents the second layer of single-layer loop code from the inner to the outer, and 2 represents the third layer of single-layer loop code from the inner to the outer.

[0086] Assume that the vector computation unit (VCU) contains three layers of hardware logic. From inner to outer, the layers are MAXSIMD, MAXBANK, and MAXREPEAT. The upper limits of the three layers are MAXSIMD, MAXBANK, and MAXREPEAT, respectively. Considering the multiple single-layer loop codes determined by the compiler, and assuming that the parameters are arranged from left to right to represent the hierarchy of the three hardware logic layers, from inner to outer, the mapping parameters in the default interface vectorhint(0,1,1) shown in Table 2-1 indicate that the first target loop code, loop k, uses the VCU's MAXSIMD layer for vector calculations; the second target loop code, loop j, uses the MAXBANK and MAXREPEAT layers for vector calculations. If the value "2" is not present in this mapping parameter, loop i, or the third loop, is not a target loop code and does not use hardware logic layers, thus not participating in vectorization. Subsequent loop segmentation and reassembly are unnecessary. The information provided by the interface also indicates that the user intends to vectorize only the two innermost loops.

[0087] Additionally, the target loop code's level within the multi-dimensional loop can be different from the hardware logic level used by the target loop code. For example, vectorhint(1,1,0) indicates that the second-level target loop code uses MAXSIMD and MAXBANK, while the innermost target loop code uses MAXREPEAT.

[0088] It should be understood that the above mapping parameter format is merely an example, and any mapping parameter that can indicate the hardware logic layer used by each target loop code layer can be used in this application, and this embodiment does not impose any restrictions thereto. When the above S302 is executed and the above mapping relationship is obtained, the mapping relationship can be saved. For example, the compiler can save the above mapping relationship in the form of a map (mapping container, a data structure).

[0089] In an embodiment of the present application, the user can control the mapping relationship between the target loop code and the hardware logic layer in the multi-dimensional loop code through a preset interface to achieve priority vectorization of long loops, thereby increasing the amount of data calculated by each vector instruction and improving computing performance. In other words, the user can determine a more accurate mapping relationship based on the perception of the number of loops in the business code, that is, select a loop matching method with better computing performance, and solve the problem of potential performance optimization loss caused by the inability to perceive the number of loops due to the dynamic shape during the compilation process. Even with a dynamic shape, the user may have some value space for the length, thereby avoiding placing short loops in the inner layer of the loop or participating in vectorization. Table 2-1 is a dynamic shape multi-dimensional loop, in which the length of each dimension is a variable. Automatic vectorization of this loop in the compiler can greatly reduce the execution time of this loop.

[0090] For example, the multi-dimensional loop code in the service code of the embodiment of the present application may be the code shown in the following Table 2-2:

[0091] Table 2-2 is similar to the multi-dimensional loop code shown in Table 2-1, except that in Table 2-2 the user does not set mapping parameters through the preset interface.

[0092] In an optional embodiment, the attribute information includes the loop upper bound of the loop implemented by each layer of the target loop code; accordingly, still referring to FIG. 4 , S302 shown in FIG. 3 above, when the user does not set the mapping parameters, may specifically include:

[0093] S3024 , allocating a hardware logic layer to each target loop code layer with a constant loop upper bound in the multiple single-layer loop codes according to the loop upper bound of each single-layer loop code and the hierarchical relationship between the multiple hardware logic layers and the multiple single-layer loop codes.

[0094] For example, the compiler can determine multiple single-layer loop codes in a multidimensional loop code based on the hierarchical relationship between the multiple single-layer loop codes: the innermost loop is the k-loop, the parent loop of the k-loop is the j-loop, and the parent loop of the j-loop is the outermost loop, the i-loop. If the user does not set mapping parameters through a preset interface, one or more of the multiple single-layer loop codes can be used as the target loop code. This depends on specific application scenario constraints such as the loop upper bound of each single-layer loop code, the hierarchical relationship between the multiple single-layer loop codes, and the hierarchical relationship between the hardware loop layers. This is not limited in this embodiment. If the loop upper bound of a single-layer loop code is a constant, hardware logic layers can be allocated based on whether the upper limit of the hardware logic layer length is divisible by the constant of the single-layer loop code, i.e., the loop upper bound. In this way, a single-layer loop code with a number of allocated hardware logic layers greater than 0 is the target loop code. A target loop code can be allocated multiple hardware logic layers, and a hardware logic layer can only be allocated to one target loop code.

[0095] In one example, when the loop upper bound of a single-layer loop code is a constant, the compiler can allocate hardware logic layers to the target loop code based on the upper limit of the length of the hardware logic layer and the upper limit of the loop of the target loop code, with the constraint that the tail blocks of each target loop code are the least and the memory access interval corresponding to the target loop code conforms to the memory access interval of the hardware logic layer. In this way, the single-layer loop code with a number of allocated hardware logic layers greater than 0 is the target loop code. Among them, the tail block refers to the code block in the target loop code whose number of loops is the remainder of the upper limit of the length of the allocated hardware logic layer. This reduces the part of the target code that cannot be vectorized and avoids the exception caused by the memory access interval of the target loop code not matching the memory access interval of the allocated hardware logic layer, which is conducive to further improving computing efficiency. In other words, different hardware structures, that is, vector computing unit structures, can have different mapping relationships, which are generally related to the number of loop iterations. In this example, the level of the target loop code may not match the level of the hardware logic layer.

[0096] S3025, according to the loop hierarchy relationship between multiple single-layer loop codes and the hierarchy relationship between multiple hardware logic layers, with the loop hierarchy of the target loop code matching the hierarchy of the hardware logic layer as the allocation rule, allocate a hardware logic layer to each layer of target loop code in the multiple single-layer loop codes whose loop upper bound is a variable.

[0097] Based on the hierarchical relationships between the multiple single-layer loop codes, the compiler can determine the multiple single-layer loop codes within the multidimensional loop code: the innermost loop is the k-loop, the parent of the k-loop is the j-loop, and the parent of the j-loop is the outermost loop, the i-loop. If the user does not set mapping parameters through the preset interface, one or more of the multiple single-layer loop codes can be used as the target loop code. This depends on specific application scenario constraints, such as the loop upper bound of each single-layer loop code, the hierarchical relationships between the multiple single-layer loop codes, and the hierarchical relationships between the hardware loop layers. This is not restricted in this embodiment. Because the user does not specify the mapping relationship through the interface in this step, the mapping relationship is established at compile time. In the case of dynamic shape, i.e., when the loop upper bound of the single-layer loop code is a variable, the number of loop iterations is unknown at compile time. Therefore, it can be directly allocated based on the hierarchy of the hardware logic layer and the loop hierarchy of the target loop code. Taking the three-layer loop in Table 2-2 as an example, the three layers of loops can be mapped to the three-layer loop structure of the hardware. The vectorization scope is three-level loops, where the i loop corresponds to the MAXREPEAT level, the j loop corresponds to the MAXBANK level, and the k loop corresponds to the MAXSIMD level. This determines the mapping relationship and can be saved in the compiler as a map.

[0098] In an optional example, when the number of levels between multiple single-layer loop codes (such as two-layer loops) is less than the number of levels between hardware loop layers (such as three-layer loops), allocation can also be combined with the rule that there are no remaining hardware loop layers on the basis of matching the levels of the two. For example, the multi-dimensional loop code includes a first-level single-layer loop code r-loop and a second-level single-layer loop code s-loop. The r-loop can correspond to two hardware loop layers and the s-loop can correspond to one hardware loop layer, or the r-loop can correspond to one hardware loop layer and the s-loop can correspond to two hardware loop layers. In this way, for the case where the upper bound of the loop is a variable, the single-layer loop code with the number of allocated hardware logic layers greater than 0 is the target loop code.

[0099] In an optional example, when the number of levels between multiple single-layer loop codes (such as three-layer loops) is greater than the number of levels between each hardware loop layer (such as two-layer loops), on the basis of matching the levels of the two, the rule of not vectorizing single-layer loop codes with the difference between the two levels can be combined to allocate them. For example, a multidimensional loop code includes a first-level single-layer loop code r loop, a second-level single-layer loop code s loop, and a third-level single-layer loop code q loop. Two of the single-layer loop codes can be allocated hardware loop layers of corresponding levels, and the remaining one is not vectorized. The specific selection of the target loop code depends on the application requirements. For example, the target loop code can be determined as the single-layer loop code with the number of levels between each hardware loop layer from the inner layer to the outer layer. This is not limited in this embodiment. In this way, when the upper bound of the loop is a variable, the single-layer loop code with the number of allocated hardware logic layers greater than 0 is the target loop code.

[0100] The embodiments of the present application can be applied to scenarios where the user has not set the mapping relationship between the mapping target loop code and the hardware logic layer, which can further expand the scope of application, reduce the problem of vectorization failure, and improve computing efficiency.

[0101] S303, split the target loop code according to the upper limit of the length of each hardware logic layer corresponding to each layer of the target loop code to obtain multiple code blocks, and combine the multiple code blocks into multiple multi-dimensional sub-loop codes according to the hierarchical relationship between the hardware logic layers corresponding to the multiple code blocks.

[0102] After determining the hardware logic layer corresponding to each target loop layer in the multi-layer target loop code, the compiler can split the target loop code into multiple code blocks based on the upper limit of the length of each hardware logic layer corresponding to each target loop layer. Each code block can be used to perform at least one iteration of the calculation in the multi-dimensional loop, and the specific number of iterations depends on a multiple of the upper limit of the length of the hardware logic layer corresponding to the code block.

[0103] In an optional implementation, the target loop code is divided according to the upper limit of the length of the hardware logic layer corresponding to each layer of the target loop code to obtain multiple code blocks, which may specifically include:

[0104] According to the upper limit of the length of the hardware logic layer corresponding to each layer of the target loop code, the target loop code is divided into non-tail blocks whose number of loops is an integer multiple of the upper limit of the length of the corresponding hardware logic layer, and tail blocks whose number of loops is less than the upper limit of the length of the corresponding hardware logic layer.

[0105] Exemplarily, according to the mapping relationship, a single-layer loop, ie, the target loop code, is split into q+1 blocks, where q is the number of hardware logic layers mapped to this layer of loop code.

[0106] Based on the mapping relationship in Table 2-1, the two-layer loop can be expressed as follows:

[0107] j loop: n = x × (MAXBANK × MAXREPEAT) + y × (MAXBANK) + z = part1 + part2 + part3;

[0108] k loop: p = (MAXSIMD) × a + b = part4 + part5.

[0109] These two expressions are the basis for loop segmentation: the j loop is split into three parts, part1 to part3, because it maps to two hardware loops; the k loop is split into two parts, part4 to part5, because it maps to one hardware loop. For the sub-loop code j loop, which uses two hardware loop layers, the MAXBANK layer and the MAXREPEAT layer, the meanings of the parameters in the above expressions are as follows:

[0110] MAXBANK × MAXREPEAT is the benchmark split length used to obtain the first-level non-tail block and the first-level tail block. It represents the number of scalar calculation operations performed in parallel in a vector calculation in these two hardware logic layers (MAXBANK layer and MAXREPEAT layer). The split length of the first-level non-tail block is x times the benchmark split length. The number of loops of the first-level tail block is less than the above benchmark split length. In other words, the split length of the first-level tail block is the number of loops of the target loop code modulo the above benchmark length.

[0111] MAXBANK is used to obtain the benchmark segmentation length of the second-level non-tail block and the second-level tail block. The second-level non-tail block and the second-level tail block are code blocks obtained by segmenting the first-level tail block, that is, the second-level segmentation. MAXBANK is used as the benchmark segmentation length for the second-level segmentation because the MAXBANK layer is the inner layer of the MAXREPEAT layer. The segmentation length of the second-level non-tail block is y times the benchmark segmentation length of the second-level segmentation. The number of loops of the second-level tail block is less than the benchmark segmentation length of the second-level segmentation. In other words, the segmentation length of the second-level tail block is the number of loops of the first-level tail block modulo the benchmark length of the second-level segmentation; the number of loops of the second-level tail block is z, which represents the number of scalar calculation operations performed in parallel in the second-level tail block.

[0112] Similarly, for the sub-loop code k loop that uses one hardware loop MAXSIMD layer, there is only one level of splitting to obtain non-tail blocks and level tail blocks. The benchmark split length is MAXSIMD, and the split length of the non-tail block is a times the benchmark split length; the number of loops of the tail block is b, which represents the remainder of the number of loops of k loop to MAXSIMD, that is, the number of scalar calculation operations performed in parallel in the tail block.

[0113] Taking the mapping relationship in Table 2-2 as an example, the three-layer loop can be expressed as follows:

[0114] m=x×MAXREPEAT+y=part1+part2;

[0115] n=z×MAXBANK+w=part3+part4;

[0116] p=a×MAXSIMD+b=part5+part6.

[0117] These three expressions form the basis for loop segmentation: the i-loop, j-loop, and k-loop are all split into two parts because they each map to a single hardware loop layer. The meaning of the parameters in each part is similar to the explanation of segmentation using the mapping relationship in Table 2-1. The difference lies in the specific sub-loop code and hardware logic layer. The common parts are not repeated here. For details, see the explanation of segmentation using the mapping relationship in Table 2-1.

[0118] In an embodiment of the present application, the multi-dimensional loop code is segmented according to the length upper limit of the hardware logic layer, thereby ensuring that the multi-dimensional sub-loops obtained based on the subsequent combination of the segmentation results can be processed by the vector computing unit, avoiding the problem of vectorization failure.

[0119] In an optional embodiment, the multiple code blocks are combined into multiple multi-dimensional sub-loop codes according to the hierarchical relationship between the hardware logic layers corresponding to the multiple code blocks, which may specifically include:

[0120] According to the combination rule that the loop level in the multidimensional sub-loop implemented by each multidimensional sub-loop code in the multidimensional sub-loop code matches the hierarchical relationship of each hardware logic layer corresponding to the multidimensional sub-loop code, one code block from the multiple code blocks corresponding to each layer of target loop code is combined into a multidimensional sub-loop code until the multiple code blocks corresponding to each layer of target loop code are combined to obtain a multidimensional sub-loop code.

[0121] In other words, the compiler takes one code block from the multiple code blocks corresponding to each target loop layer, and combines them according to the hierarchical relationship of the hardware logic layers corresponding to the combination result, thereby obtaining a multi-dimensional sub-loop code. This is repeated until all code blocks corresponding to each target loop layer are combined, thereby obtaining multiple multi-dimensional sub-loop codes. For example, the user sets the mapping parameters through the preset interface, that is, the segmentation result in Table 2-1 above:

[0122] Assume that the first target loop code is the outermost target loop code, and the corresponding multiple code blocks include part1, part2 and part3; then each layer of target loop code except the first target loop code is the second layer of target loop code, and the corresponding code blocks include part4 and part5.

[0123] The loop hierarchy within the resulting multidimensional sub-loop code depends on the hierarchy of the corresponding hardware logic layers. This means that there is only one bit-level relationship between the code blocks in the resulting combination, and there are no variations in the resulting combination due to multiple hierarchical relationships. Therefore, the number of multidimensional sub-loop codes is the product of the number of code blocks corresponding to each target loop code layer, for example, 3×2=6 or 2×3=6. Specifically, this includes: part1 combined with part4, part1 combined with part5; part2 combined with part4, part2 combined with part5; part3 combined with part4, and part3 combined with part5.

[0124] In other words, the blocks of the two-layer loop, k and j, are combined in pairs to form six nested sub-loops. The nested sub-loops are adjusted to adapt to the hardware format. That is, x, y, and a represent the number of times the hardware logic layer executes the calculation corresponding to the upper limit of their length. Therefore, the sub-loops of length x, y, and a are placed on the outermost. Taking the combination of part 1 and part 5 as an example, the resulting multi-dimensional sub-loop code is shown in Table 3-1:

[0125] In the code shown in the embodiment of this application, "*" represents multiplication. Similarly, compared with the example in Table 3-1 above, the combination of part 1 and part 4 has an additional sub-loop corresponding to a. "a" represents the sub-loop assigned to the MAXSIMD hardware logic layer to execute a times. The sub-loop corresponding to "a" is placed in the outer layer, as shown in Table 3-2 below:

[0126] It can be understood that the hierarchical relationship between the sub-loop corresponding to a and the sub-loop corresponding to x can be arbitrary. For example, the sub-loop corresponding to a in the above Table 3-2 can be in the inner layer of the sub-loop corresponding to x, or the sub-loop corresponding to a can be in the outer layer of the sub-loop corresponding to x.

[0127] Similarly, the combination of part 2 and part 5 has one less sub-loop corresponding to MAXREPEAT than the example in Table 3-1 above, as shown in Table 3-3 below:

[0128] For example, the user does not set the mapping parameters through the preset interface, that is, the segmentation result in Table 2-2 above is used as an example:

[0129] The multiple code blocks corresponding to the outermost target loop code may include part1 and part2; the second-level target loop code corresponds to code blocks part3 and part4; and the third-level target loop code corresponds to code blocks part5 and part6. Based on this, the number of multidimensional sub-loop codes is the product of the number of code blocks corresponding to each level of target loop code, for example, 2×2×2=8. Specifically, these codes may include: a combination of part1, part3, and part5; a combination of part1, part4, and part5; a combination of part1, part3, and part6; a combination of part1, part4, and part6; a combination of part2, part3, and part5; a combination of part2, part4, and part5; a combination of part2, part3, and part6; and a combination of part2, part4, and part6.

[0130] In other words, the three-layer loop segmentation results in Table 2-2 are combined to form eight nested sub-loops. The nested sub-loops are adjusted to adapt to the hardware format, that is, the loops of lengths x, z, and a are placed on the outermost layer. Taking the combination of part 1, part 4, and part 5 as an example, the resulting multi-dimensional sub-loop code is shown in Table 3-4:

[0131] In the embodiment of the present application, according to the hierarchical relationship of the hardware logic layers corresponding to the code blocks, one code block is taken from each target loop layer and combined into a multi-dimensional sub-loop code, until the combination of all code blocks is completed, and multiple multi-dimensional sub-loop codes are obtained. This can avoid combinations that do not conform to the original loop structure and excessive combination results, thereby ensuring the loop correctness of the multi-dimensional sub-loop obtained by the combination and theoretically minimizing the number of sub-loops and vector instructions, thereby further improving computing efficiency.

[0132] S304 , based on the multiple multidimensional sub-loop codes and the attribute information, the multidimensional loop code is updated into a vector instruction; wherein the vector instruction is used by a vector computing unit to perform vector computing.

[0133] After obtaining the multiple multidimensional sub-loop codes, the compiler can update the multidimensional loop codes into vector instructions based on the multiple multidimensional sub-loop codes and attribute information. The vector instructions are used by the vector computing unit to perform vector calculations. In this way, the compiler completes the vectorization of the multidimensional loop code by simply obtaining the vector instructions for the multidimensional loop code.

[0134] In an optional embodiment, the attribute information includes an interval step length of memory access of each layer of target loop code;

[0135] Accordingly, the above-mentioned updating of the multi-dimensional loop code into a vector instruction based on the multiple multi-dimensional sub-loop codes and attribute information may specifically include:

[0136] For each multi-dimensional sub-loop code in the plurality of multi-dimensional sub-loop codes, the following operations are performed to generate vector instructions of the multi-dimensional sub-loop code:

[0137] Generate a mask for the innermost sub-loop code according to the upper limit of the length of the hardware logic layer corresponding to the innermost sub-loop code in the multi-dimensional sub-loop code and the number of cycles of the loop implemented by the innermost sub-loop code;

[0138] Starting from the outermost sub-loop code of the innermost sub-loop code in the multidimensional sub-loop code, a mask of the sub-loop code of the current layer is generated based on the upper limit of the length of the hardware logic layer corresponding to the inner sub-loop code, the upper limit of the length of the hardware logic layer corresponding to the sub-loop code of the current layer, the mask of the inner sub-loop code, and the number of loops of the sub-loop code of the current layer, until a mask of each sub-loop code in the multidimensional sub-loop code is generated, thereby obtaining a mask of the multidimensional sub-loop code; wherein the mask of the multidimensional sub-loop code is used to indicate attribute information of a sub-loop code in the multidimensional sub-loop code whose number of loops is less than the upper limit of the length of the hardware logic layer corresponding to the multidimensional sub-loop code;

[0139] Generate a vector instruction of the multi-dimensional sub-loop code according to the interval step corresponding to the multi-dimensional sub-loop code and the mask of the multi-dimensional sub-loop code;

[0140] The multi-dimensional loop code is replaced by utilizing a vector instruction of each of the plurality of multi-dimensional sub-loop codes.

[0141] Exemplarily, the attribute information of a sub-loop code in a multidimensional sub-loop code whose number of loops is less than the upper limit length of the hardware logic layer corresponding to the multidimensional sub-loop code, that is, the attribute information of the tail block in the multidimensional sub-loop code, can include the number, length, and position of the tail blocks in the multidimensional sub-loop. The position refers to the memory address accessed by the calculation in the loop implemented by the tail block. It is understood that within the same multidimensional sub-loop code, there may be gaps in the memory access locations corresponding to the tail blocks in different sub-loop codes, that is, memory access may not be continuous.

[0142] This embodiment determines a mask for each sub-loop code in each multidimensional sub-loop code. The mask for a single sub-loop code can be determined one by one, working from the innermost layer toward the outermost layer: the upper limit of the hardware logic layer length corresponding to the innermost sub-loop code is used as the number of bits in the mask. Starting from the lowest bit of the mask, the number of mask bits corresponding to the number of iterations of the innermost sub-loop code is set to 1, i.e., the valid bit, to serve as the mask for that layer. When determining the mask for the outermost layer, the position that is an integer multiple of the upper limit of the hardware logic layer length corresponding to the innermost sub-loop code is used as the starting bit of the layer. The valid bits of the innermost mask are set n times, where n is the number of iterations of the layer, and so on, until the masks for all sub-loop codes in the multidimensional sub-loop code are determined. In other words, if the upper limit of the hardware length corresponding to the innermost sub-loop code is MAXSIMD and the number of iterations of the sub-loop code is b, then the mask of the innermost sub-loop code, also referred to as mask1, has a total length of MAXSIMD, with b bits of mask1 set to 1, and the remaining bits set to 0, starting from the starting bit. When it comes to the outer layer adjacent to the innermost layer, that is, the length limit of the hardware logic layer corresponding to the innermost sub-loop code is MAXBANK, so the total length of the mask of this layer, which can also be called mask2, is MAXBANK×MAXSIMD; the number of loop iterations of this layer is MAXBANK, so mask1 is placed starting from 0×MAXSIMD, 1×MAXSIMD...(the number of loop iterations of this layer - 1)×MAXSIMD, that is, mask1 is placed the number of times the loop iterations of this layer are repeated.

[0143] For example, Figure 5 is an example diagram of the mask structure of the multidimensional sub-loop code in the code vectorization method provided by an embodiment of the present application. As shown in Figure 5, the innermost layer is the first-layer sub-loop code, the corresponding hardware logic layer length upper limit is MAXSIMD=4, the number of iterations of the first-layer sub-loop code b=3, and the mask of the first-layer sub-loop code mask1=0111. The outer layer of the first-layer sub-loop code is the second-layer sub-loop code, the corresponding hardware logic layer length upper limit is MAXBANK=3, the number of iterations of the second-layer sub-loop code is 2, and only 6 of the MAXBANK*MAXSIMD=12 bits of the mask of the second-layer sub-loop code are set to 1, that is, "0111" is placed twice starting from bit 0, and finally mask2=000001110111 is obtained.

[0144] In the embodiments of this application, a mask is implemented in the form of a register, with each bit in the mask corresponding to a bit in the register. By setting the mask, the non-vectorized portion can be shielded, preventing computational anomalies caused by incorrect memory modifications. This solves the problem of tail block correctness in the vectorization of dynamic-shape multidimensional loops. Furthermore, for multidimensional loop code scenarios, masks can be quickly generated by extending from the innermost layer to the outermost layer and filling in valid bits, further improving computational efficiency.

[0145] In one example, a hardware unit that supports multidimensional vectors, namely a vector calculation unit, needs to fill in information such as the input / output memory starting position, namely the memory access start bit, and the memory access interval calculated in the multi-layer loop. The attribute information of the multidimensional loop code contains this information. After segmentation, the attribute information of the multidimensional loop code can be divided according to the number of loops after segmentation to obtain the memory access start bit of the multidimensional sub-loop and the memory access interval calculated in the multi-layer loop. In this way, the compiler can generate vector instructions for the multidimensional sub-loop code based on the interval step size of each target loop code corresponding to the multidimensional sub-loop code and the mask of the multidimensional sub-loop code, and then use the vector instructions of each multidimensional sub-loop code in the multiple multidimensional sub-loop codes to replace the multidimensional loop code. In other words, in the embodiment of the present application, the compiler replaces all multidimensional loops in the business code with vector instructions of the multidimensional sub-loop code corresponding to the multidimensional loop, which is equivalent to replacing the multidimensional loop in the business code with vector instructions. The compiler then sends the vector instructions to the vector calculation unit, and the vector calculation unit executes the received vector instructions to implement the vector calculation calculated in the multidimensional loop in the business code: parallel calculation of multiple data.

[0146] In an embodiment of the present application, each layer of loop code in a multidimensional loop code is divided into multiple code blocks according to the length upper limit of the hardware logic layer in the vector computing unit, and the multiple code blocks are combined into multiple multidimensional sub-loops according to the hierarchical relationship of the hardware logic layer in the vector computing unit, thereby ensuring that the dimension and length of each multidimensional sub-loop code meet the processing conditions of the hardware logic layer. On this basis, the multidimensional loop code can be updated to a vector instruction. In this way, the vectorization of the multidimensional loop is not restricted by static or dynamic shape, nor by the length of any layer of loop, thereby avoiding the problem of vectorization failure and improving computing efficiency.

[0147] In addition, the platform shown in FIG1 of the present application and the compiler shown in FIG2 include hardware and / or software modules that perform the corresponding functions in order to implement the functions of the code vectorization method in the above-mentioned embodiments of the present application. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to be beyond the scope of this application.

[0148] This embodiment further provides a computer storage medium, in which computer instructions are stored. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the code vectorization method in the above-mentioned embodiment.

[0149] This embodiment further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the code vectorization method in the above-mentioned embodiment.

[0150] Among them, the electronic device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here.

[0151] Any content of each embodiment of this application, as well as any content of the same embodiment, can be freely combined. Any combination of the above content is within the scope of this application.

[0152] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0153] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A code vectorization method, characterized in that: The method comprises: Acquire attribute information of a multidimensional cyclic code; wherein the multidimensional cyclic code includes a plurality of single-layer cyclic codes, each of the plurality of single-layer cyclic codes being used to implement a layer of cyclic in a multi-layer cyclic; Determine, according to the attribute information, a hardware logic layer corresponding to each layer of target loop code in the multi-dimensional loop code; wherein each layer of target loop code is a single layer of loop code to be vectorized among the multiple single layers of loop codes; the multiple hardware logic layers are used to indicate multi-level memory access rules of a vector computing unit, and each hardware logic layer corresponds to a layer of memory access rules among the multiple levels of memory access; According to the upper limits of the lengths of the hardware logic layers corresponding to each layer of the target loop code, the target loop code is divided to obtain a plurality of code blocks, and according to the hierarchical relationships between the hardware logic layers corresponding to the plurality of code blocks, the plurality of code blocks are combined into a plurality of multi-dimensional sub-loop codes; Based on the multiple multi-dimensional sub-loop codes and the attribute information, the multi-dimensional loop code is updated to a vector instruction; wherein the vector instruction is used by the vector computing unit to perform vector computing.

2. The method according to claim 1, characterized in that The attribute information includes a hierarchical relationship between the plurality of single-layer loop codes; Determining the hardware logic layer corresponding to each layer of target loop code in the multidimensional loop code according to the attribute information includes: Determining a plurality of single-layer cyclic codes in the multidimensional cyclic code according to a hierarchical relationship between the plurality of single-layer cyclic codes; Reading a mapping parameter set by a user in a preset interface; wherein the mapping parameter is used to indicate a hardware logic layer used by each layer of the target loop code; According to the mapping parameters and the plurality of single-layer loop codes, a hardware logic layer is allocated to each layer of target loop code in the multi-dimensional loop code.

3. The method according to claim 1, characterized in that The attribute information includes the loop upper bound of each single-layer loop code and the hierarchical relationship between the multiple single-layer loop codes; Determining the hardware logic layer corresponding to each layer of target loop code in the multidimensional loop code according to the attribute information includes: Determining a plurality of single-layer cyclic codes in the multidimensional cyclic code according to a hierarchical relationship between the plurality of single-layer cyclic codes; Allocate a hardware logic layer to each layer of target loop code in the multiple single-layer loop codes whose loop upper bound is a constant according to the loop upper bound of each single-layer loop code, the length upper bound of each hardware logic layer, and the multiple single-layer loop codes; According to the loop hierarchy relationship between the multiple single-layer loop codes and the hierarchy relationship between the multiple hardware logic layers, a hardware logic layer is allocated to each layer of target loop code in the multiple single-layer loop codes whose loop upper bound is a variable, with the loop hierarchy of the target loop code matching the hierarchy of the hardware logic layer as an allocation rule.

4. The method according to any one of claims 1 to 3, characterized in that Combining the multiple code blocks into multiple multi-dimensional sub-loop codes according to the hierarchical relationship between the hardware logic layers corresponding to the multiple code blocks includes: According to the combination rule that the loop level in the multidimensional sub-loop implemented by each multidimensional sub-loop code in the multidimensional sub-loop code matches the hierarchical relationship of each hardware logic layer corresponding to the multidimensional sub-loop code, one code block among the multiple code blocks corresponding to each layer of the target loop code is combined into a multidimensional sub-loop code until the multiple code blocks corresponding to each layer of the target loop code are combined to obtain a multidimensional sub-loop code.

5. The method according to any one of claims 1 to 4, characterized in that The attribute information includes the interval step length of each single-layer loop code memory access; The updating of the multidimensional loop code into a vector instruction based on the plurality of multidimensional sub-loop codes and the attribute information comprises: For each multi-dimensional sub-loop code in the plurality of multi-dimensional sub-loop codes, the following operations are performed to generate a vector instruction of the multi-dimensional sub-loop code: Generate a mask of the innermost sub-loop code according to the upper limit of the length of the hardware logic layer corresponding to the innermost sub-loop code in the multi-dimensional sub-loop code and the number of loops implemented by the innermost sub-loop code; Starting from the outermost sub-loop code of the innermost sub-loop code in the multi-dimensional sub-loop code, based on the upper limit of the length of the hardware logic layer corresponding to the inner sub-loop code, the upper limit of the length of the hardware logic layer corresponding to the sub-loop code of the current layer, the mask of the inner sub-loop code, and the number of loops of the sub-loop code of the current layer, the mask of the sub-loop code of the current layer is generated, until the mask of each sub-loop code in the multi-dimensional sub-loop code is generated, and the mask of the multi-dimensional sub-loop code is obtained; wherein the mask of the multi-dimensional sub-loop code is used to indicate the Attribute information of a sub-loop code in the multi-dimensional sub-loop code whose loop times are less than the upper limit length of the hardware logic layer corresponding to the multi-dimensional sub-loop code; Generate a vector instruction of the multidimensional sub-loop code according to the interval step of each target loop code corresponding to the multidimensional sub-loop code and the mask of the multidimensional sub-loop code; The multi-dimensional loop code is replaced by a vector instruction of each multi-dimensional sub-loop code of the plurality of multi-dimensional sub-loop codes.

6. The method according to any one of claims 1 to 5, characterized in that The target loop code is divided according to the upper limit of the length of the hardware logic layer corresponding to each layer of the target loop code to obtain multiple code blocks, including: According to the upper limit of the length of the hardware logic layer corresponding to each layer of the target loop code, the target loop code is divided into non-tail blocks whose number of loops is an integer multiple of the upper limit of the length of the corresponding hardware logic layer, and tail blocks whose number of loops is less than the upper limit of the length of the corresponding hardware logic layer.

7. A code vectorization device, characterized in that: The device comprises: A parsing mapping module, used for obtaining attribute information of a multidimensional loop code; wherein the multidimensional loop code includes a plurality of single-layer loop codes, each of the plurality of single-layer loop codes is used to implement a layer of loops in a multi-layer loop; according to the attribute information, determining a hardware logic layer corresponding to each layer of target loop code in the multidimensional loop code; wherein each layer of target loop code is a single-layer loop code to be vectorized in the plurality of single-layer loop codes; the plurality of hardware logic layers are used to indicate a multi-level memory access rule of a vector computing unit, each hardware logic layer corresponds to a layer of memory access rule in the multi-level memory access; A loop segmentation module, used to segment the target loop code according to the upper limit of the length of each hardware logic layer corresponding to each layer of the target loop code, to obtain multiple code blocks, and combine the multiple code blocks into multiple multi-dimensional sub-loop codes according to the hierarchical relationship between the hardware logic layers corresponding to the multiple code blocks; An instruction replacement module is used to update the multidimensional loop code into a vector instruction based on the multiple multidimensional sub-loop codes and the attribute information; wherein the vector instruction is used for the vector computing unit to perform vector computing.

8. The device according to claim 7, characterized in that The attribute information includes a hierarchical relationship between the plurality of single-layer loop codes; The parsing and mapping module is specifically used for: Determining a plurality of single-layer cyclic codes in the multidimensional cyclic code according to a hierarchical relationship between the plurality of single-layer cyclic codes; Reading a mapping parameter set by a user in a preset interface; wherein the mapping parameter is used to indicate a hardware logic layer used by each layer of the target loop code; According to the mapping parameters and the plurality of single-layer loop codes, a hardware logic layer is allocated to each layer of target loop code in the multi-dimensional loop code.

9. The device according to claim 7, characterized in that The attribute information includes the loop upper bound of each single-layer loop code and the hierarchical relationship between the multiple single-layer loop codes; The parsing and mapping module is specifically used for: Determining a plurality of single-layer cyclic codes in the multidimensional cyclic code according to a hierarchical relationship between the plurality of single-layer cyclic codes; Allocate a hardware logic layer to each layer of target loop code in the multiple single-layer loop codes whose loop upper bound is a constant according to the loop upper bound of each single-layer loop code, the length upper bound of each hardware logic layer, and the multiple single-layer loop codes; According to the loop hierarchy relationship between the multiple single-layer loop codes and the hierarchy relationship between the multiple hardware logic layers, a hardware logic layer is allocated to each layer of target loop code in the multiple single-layer loop codes whose loop upper bound is a variable, with the loop hierarchy of the target loop code matching the hierarchy of the hardware logic layer as an allocation rule.

10. The device according to any one of claims 7 to 9, characterized in that: The loop segmentation module is specifically used for: According to the combination rule that the loop level in the multidimensional sub-loop implemented by each multidimensional sub-loop code in the multidimensional sub-loop code matches the hierarchical relationship of each hardware logic layer corresponding to the multidimensional sub-loop code, one code block among the multiple code blocks corresponding to each layer of the target loop code is combined into a multidimensional sub-loop code until the multiple code blocks corresponding to each layer of the target loop code are combined to obtain a multidimensional sub-loop code.

11. The device according to any one of claims 7 to 10, characterized in that The attribute information includes the interval step length of each single-layer loop code memory access; The instruction replacement module is specifically used for: For each multidimensional sub-loop code in the plurality of multidimensional sub-loop codes, the following operations are performed to generate the multidimensional sub-loop code: Vector instructions: Generate a mask of the innermost sub-loop code according to the upper limit of the length of the hardware logic layer corresponding to the innermost sub-loop code in the multi-dimensional sub-loop code and the number of loops implemented by the innermost sub-loop code; Starting from the outermost sub-loop code of the innermost sub-loop code in the multidimensional sub-loop code, based on the length upper limit of the hardware logic layer corresponding to the inner sub-loop code, the length upper limit of the hardware logic layer corresponding to the sub-loop code of the current layer, the mask of the inner sub-loop code, and the number of loops of the sub-loop code of the current layer, the mask of the sub-loop code of the current layer is generated, until the mask of each sub-loop code in the multidimensional sub-loop code is generated to obtain the mask of the multidimensional sub-loop code; wherein the mask of the multidimensional sub-loop code is used to indicate the attribute information of the sub-loop code in the multidimensional sub-loop code whose number of loops is less than the upper limit length of the hardware logic layer corresponding to the multidimensional sub-loop code; Generate a vector instruction of the multidimensional sub-loop code according to the interval step of each target loop code corresponding to the multidimensional sub-loop code and the mask of the multidimensional sub-loop code; The multi-dimensional loop code is replaced by a vector instruction of each multi-dimensional sub-loop code of the plurality of multi-dimensional sub-loop codes.

12. The device according to any one of claims 7 to 11, characterized in that The loop segmentation module is specifically used for: According to the upper limit of the length of the hardware logic layer corresponding to each layer of the target loop code, the target loop code is divided into non-tail blocks whose number of loops is an integer multiple of the upper limit of the length of the corresponding hardware logic layer, and tail blocks whose number of loops is less than the upper limit of the length of the corresponding hardware logic layer.

13. An electronic device, characterized in that: include: Processor and memory; The processor is connected to the memory; The memory is used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that: The method comprises a computer program, wherein when the computer program is run on an electronic device, the electronic device executes the method according to any one of claims 1 to 6.

15. A chip, characterized in that: It comprises one or more interface circuits and one or more processors; the interface circuit is used to receive a signal from a memory of an electronic device and send the signal to the processor, the signal comprising a computer instruction stored in the memory; when the processor executes the computer instruction, the electronic device executes the method described in any one of claims 1 to 6.

16. A computer program product, characterized in that The invention comprises a computer program, which, when executed by an electronic device, enables the electronic device to execute the method according to any one of claims 1 to 6.

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