Chip and preparation method therefor, and electronic device

Abstract

The present application relates to the field of semiconductors, and provides a chip and a preparation method therefor, and an electronic device, capable of using a stress applying layer to generate a large tensile stress, effectively suppressing the size change of a ferroelectric layer due to phase change, reducing the thermal budget, and reducing the damage to the ferroelectric layer caused by a high temperature annealing process. The chip comprises a substrate, and a first electrode, a ferroelectric layer, and a second electrode which are sequentially stacked on the substrate. The surface of the ferroelectric layer facing the second electrode is a first surface, the second electrode covers a portion of the first surface, and the portion of the first surface not covered by the second electrode is a first sub-surface. The chip further comprises a stress applying layer made of a dielectric material, the coefficient of thermal expansion of the stress applying layer is smaller than the coefficient of thermal expansion of the second electrode, and the stress applying layer extends from the first sub-surface to a side wall of the second electrode.

Description

Chip and preparation method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 29, 2023, with application number 202311103485.2 and application name “Chip and its preparation method, electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductors, and in particular to a chip and a method for preparing the same, and electronic equipment. Background Art

[0003] The core part of ferroelectric memory includes a ferroelectric capacitor, which includes a first electrode, a ferroelectric layer, and a second electrode stacked in sequence. The ferroelectric layer undergoes polarization reversal under electric fields in different directions, causing the capacitor to charge and discharge, thereby realizing the storage state of "0" or "1".

[0004] The coefficient of thermal expansion (CTE) of the materials used for the first and second electrodes significantly influences the remnant polarization (Pr) of the ferroelectric layer. Excessively large CTEs hinder the formation of the ferroelectric orthorhombic phase (O) in the ferroelectric layer. Insufficient stress prevents the volume change of the ferroelectric layer due to phase transitions, hindering effective ferroelectric performance improvement. Consequently, a higher annealing temperature is required to compensate for the insufficient stress, which can easily damage the ferroelectric layer during the annealing process.

[0005] Summary of the Invention

[0006] In order to solve the above technical problems, the present application provides a chip and its preparation method, and an electronic device, which can use a stress application layer to generate a large tensile stress to inhibit the formation of a dielectric M phase, increase the proportion of a ferroelectric O phase, effectively inhibit the volume change of the ferroelectric layer due to phase change, and also reduce the thermal budget and reduce the damage to the ferroelectric layer caused by the high-temperature annealing process.

[0007] In a first aspect, the present application provides a chip comprising a substrate, a first electrode, a ferroelectric layer, and a second electrode stacked sequentially on the substrate. The surface of the ferroelectric layer facing the second electrode is a first surface, the second electrode partially covers the first surface, and the portion of the first surface not covered by the second electrode is a first sub-surface. The chip also includes a stressor layer composed of a dielectric material, the stressor layer having a thermal expansion coefficient less than that of the second electrode, and the stressor layer extending from the first sub-surface to the sidewalls of the second electrode.

[0008] In the present application, by reducing the size of the second electrode to cover the first sub-surface with a stress applying layer, since the thermal expansion coefficient of the stress applying layer is smaller than that of the second electrode, the deformation of the stress applying layer is smaller than that of the second electrode in a high temperature environment, and a stronger chemical bond can be formed. For example, when preparing the stress applying layer and the second electrode, the stress applying layer and the second electrode are annealed separately, and the deformation of the stress applying layer is smaller than that of the second electrode. In this way, although the ferroelectric layer is prone to deformation in a high temperature environment, because the stress applying layer is in contact with the first sub-surface, the stress applying layer with a smaller deformation can be used to provide in-plane tensile stress to the ferroelectric layer that is prone to deformation, thereby reducing the lateral deformation of the ferroelectric layer. Furthermore, the stress applying layer also extends to the side wall of the second electrode, so the stress applying layer can also be used to provide longitudinal tensile stress to the ferroelectric layer, thereby reducing the longitudinal deformation of the ferroelectric layer. It can also be said that the stress-applying layer with a smaller thermal expansion coefficient can generate a larger tensile stress during the cooling process. The tensile stress can inhibit the formation of the dielectric M phase, increase the proportion of the ferroelectric O phase, and effectively inhibit the volume change of the ferroelectric layer due to phase change, thereby effectively improving the ferroelectric performance.

[0009] On this basis, because the stressor layer has a smaller coefficient of thermal expansion than the second electrode, and the combined tensile stress applied to the ferroelectric layer by the stressor layer and the second electrode increases, a higher annealing temperature is not required to compensate for the stress deficiency. Therefore, during the preparation of the stressor layer, the high-temperature annealing temperature required for the stressor layer is relatively low, thereby reducing the thermal budget. Compared to related technologies, the high-temperature annealing process for the stressor layer in this application causes less damage to the ferroelectric layer.

[0010] In some possible implementations, the stress applying layer surrounds the second electrode, so that the stress applying layer can provide a greater stress around the edge of the ferroelectric layer.

[0011] In some possible implementations, along the second direction, the first electrode, the ferroelectric layer, and the second electrode are sequentially disposed on the substrate. In this case, the first electrode is a bottom electrode, and the second electrode is a top electrode.

[0012] In some possible implementations, a surface of the ferroelectric layer facing the first electrode is a second surface, the first electrode partially covers the second surface, and a portion of the second surface not covered by the first electrode is a second sub-surface. The stressor layer has a coefficient of thermal expansion that is less than the coefficient of thermal expansion of the first electrode, and the stressor layer further extends from the second sub-surface to a sidewall of the first electrode.

[0013] By reducing the size of the first electrode to cover the second surface of the sub-sub ... It can also be said that the stress-applying layer with a smaller thermal expansion coefficient can generate a larger tensile stress during the cooling process. The tensile stress can inhibit the formation of the dielectric M phase, increase the proportion of the ferroelectric O phase, and effectively inhibit the volume change of the ferroelectric layer due to phase change, thereby effectively improving the ferroelectric performance.

[0014] On this basis, because the stressor layer has a smaller coefficient of thermal expansion than the first electrode, and the stressor layer and the second electrode exert a greater overall tensile stress on the ferroelectric layer, a higher annealing temperature is not required to compensate for the stress deficiency. Therefore, during the preparation of the stressor layer, the high-temperature annealing temperature required for the stressor layer is lower, thereby reducing the thermal budget. Compared to related technologies, the high-temperature annealing process of the stressor layer in this application causes less damage to the ferroelectric layer.

[0015] In some possible implementations, the stressor layer completely covers the sidewalls of the first and second electrodes. And / or, the stressor layer completely covers the first and second subsurfaces. The stressor layer completely covers the first and second subsurfaces to maximize in-plane tensile stress in the ferroelectric layer and reduce lateral deformation in the portion of the ferroelectric layer that contacts the stressor layer.

[0016] In some possible implementations, tungsten has a relatively low coefficient of thermal expansion for conductive materials and is relatively common. Therefore, the coefficient of thermal expansion of the stressor layer is smaller than that of tungsten. This allows the stressor layer to be formed by removing a portion of the second electrode (or the first and second electrodes), thereby providing the ferroelectric layer with tensile stress that the second electrode (or the first and second electrodes) cannot provide. For example, the material of the stressor layer includes at least one of silicon dioxide, quartz, graphite, hexagonal boron nitride, silicon nitride, silicon, silicon germanium, and silicon carbide.

[0017] In a second aspect, the present application provides a chip comprising a substrate and a three-dimensional ferroelectric capacitor disposed on the substrate, the three-dimensional ferroelectric capacitor comprising a first electrode, a ferroelectric layer, multiple layers of second electrodes, and multiple layers of dielectric layers. The multiple layers of second electrodes and the multiple layers of dielectric layers are alternately disposed along the substrate toward the three-dimensional capacitor, the ferroelectric layer and the first electrode intersecting the multiple layers of second electrodes and the multiple layers of dielectric layers; the ferroelectric layer is disposed between the multiple layers of second electrodes and the first electrode. The chip also comprises a stressor layer composed of a dielectric material, the stressor layer having a thermal expansion coefficient less than that of the dielectric layer; the stressor layer extends from between the adjacent second electrode and the dielectric layer to between the second electrode and the ferroelectric layer.

[0018] In the present application, since the thermal expansion coefficient of the stress applying layer is smaller than that of the dielectric layer, the deformation of the stress applying layer is smaller than that of the dielectric layer in a high temperature environment, and a stronger chemical bond can be formed. For example, when preparing the first electrode, the first electrode is subjected to an annealing process to form a stress applying layer with a smaller deformation. In this way, although the ferroelectric layer is prone to deformation in a high temperature environment, since the stress applying layer is in contact with the ferroelectric layer, the stress applying layer with a smaller deformation can be used to provide in-plane tensile stress to the ferroelectric layer that is prone to deformation, thereby reducing the lateral deformation of the ferroelectric layer. Furthermore, the stress applying layer also extends between the adjacent second electrode and the dielectric layer. Therefore, on the basis of the second electrode providing tensile stress to the ferroelectric layer, the stress applying layer can also be used to provide longitudinal tensile stress to the ferroelectric layer, thereby reducing the longitudinal deformation of the ferroelectric layer. It can also be said that the stress-applying layer with a smaller thermal expansion coefficient can generate a larger tensile stress during the cooling process. The tensile stress can inhibit the formation of the dielectric M phase, increase the proportion of the ferroelectric O phase, and effectively inhibit the volume change of the ferroelectric layer due to phase change, thereby effectively improving the ferroelectric performance.

[0019] On this basis, because the stressor layer has a smaller coefficient of thermal expansion than the dielectric layer, and the stressor layer and the second electrode exert a greater overall tensile stress on the ferroelectric layer, a higher annealing temperature is not required to compensate for the stress deficiency. Therefore, during the preparation of the stressor layer, the high-temperature annealing temperature required for the stressor layer is lower, thereby reducing the thermal budget. Compared to related technologies, the high-temperature annealing process of the stressor layer in this application causes less damage to the ferroelectric layer.

[0020] In some possible implementations, the coefficient of thermal expansion of the stressor layer is smaller than the coefficient of thermal expansion of the second electrode, so that the stressor layer provides a greater tensile stress to the ferroelectric layer than the tensile stress provided by the second electrode. For example, the material of the stressor layer includes at least one of silicon dioxide, quartz, graphite, hexagonal boron nitride, silicon nitride, silicon, silicon germanium, and silicon carbide.

[0021] In a third aspect, the present application provides a method for preparing a chip, comprising: forming a stress applying layer composed of a dielectric material, and a first electrode, a ferroelectric layer, and a second electrode stacked on a substrate; the surface of the ferroelectric layer facing the second electrode is the first surface, the second electrode covers a portion of the first surface, and the portion of the first surface not covered by the second electrode is the first sub-surface; the chip also includes a stress applying layer composed of a dielectric material, the thermal expansion coefficient of the stress applying layer is smaller than the thermal expansion coefficient of the second electrode, and the stress applying layer extends from the first sub-surface to the side wall of the second electrode.

[0022] In some possible implementations, before forming the stress applying layer on the substrate, forming a stacked first electrode, a ferroelectric layer, and a second electrode includes sequentially forming the stacked first electrode, the ferroelectric layer, and a conductive film layer (hereinafter referred to as the second conductive film layer) on the substrate, and etching the second conductive film layer to obtain the second electrode.

[0023] In some possible implementations, before forming the first electrode, the chip preparation method also includes: forming a plurality of dielectric layers and a plurality of stress applying layers spaced apart on the substrate, the stress applying layer covering the surface and sidewall of the dielectric layer facing away from the substrate; the thermal expansion coefficient of the stress applying layer is smaller than the thermal expansion coefficient of the first electrode; forming the first electrode includes: filling the first electrode between adjacent stress applying layers.

[0024] The third aspect and any implementation of the third aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here.

[0025] In a fourth aspect, the present application provides a method for preparing a chip, comprising: forming stacked and alternating multiple dielectric layers and multiple sacrificial layers on a substrate; forming a hollow portion in the multiple dielectric layers and the multiple sacrificial layers, the hollow portion penetrating the multiple dielectric layers and the multiple sacrificial layers along the direction of the substrate pointing to the second electrode; filling the hollow portion with a ferroelectric layer and a first electrode in sequence, the ferroelectric layer being located between the first electrode and the multiple dielectric layers and the multiple sacrificial layers; removing the multiple sacrificial layers to form a spacer, and forming a stress application layer and a multiple second electrode in sequence in the spacer; the thermal expansion coefficient of the stress application layer is smaller than the thermal expansion coefficient of the dielectric layer, and the stress application layer extends from between the adjacent second electrode and the dielectric layer to between the second electrode and the ferroelectric layer.

[0026] In some possible implementations, forming the stress applying layer in the spacer region includes: forming the stress applying layer by using a plasma enhanced chemical vapor deposition process or an atomic layer deposition process.

[0027] The fourth aspect and any implementation of the fourth aspect correspond to the second aspect and any implementation of the second aspect, respectively. The technical effects corresponding to the fourth aspect and any implementation of the fourth aspect can be referred to the technical effects corresponding to the above-mentioned second aspect and any implementation of the second aspect, and will not be repeated here.

[0028] In a fifth aspect, the present application provides an electronic device, which includes a circuit board and the chip described in the first aspect or the second aspect, and the chip is arranged on the circuit board.

[0029] The fifth aspect and any implementation of the fifth aspect correspond to the first aspect, the second aspect, and any implementation of the first and second aspects, respectively. The technical effects corresponding to the fifth aspect and any implementation of the fifth aspect can be found in the technical effects corresponding to the first aspect, the second aspect, and any implementation of the first and second aspects, and are not further described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a block diagram illustrating a connection between a processor and a memory in an electronic device according to an embodiment of the present application;

[0031] FIG2 is a structural diagram of a ferroelectric capacitor provided in an embodiment of the present application;

[0032] FIG3 a is a diagram showing the working principle of a ferroelectric capacitor provided in an embodiment of the present application;

[0033] FIG3 b is a diagram showing the working principle of a ferroelectric capacitor provided in an embodiment of the present application;

[0034] FIG4 is a structural diagram of a ferroelectric capacitor provided in an embodiment of the present application;

[0035] FIG5 a is a structural diagram of a ferroelectric capacitor and a stress applying layer provided in an embodiment of the present application;

[0036] FIG5 b is a structural diagram of a ferroelectric capacitor and a stress applying layer provided in an embodiment of the present application;

[0037] FIG6 is a structural diagram of a ferroelectric capacitor and a stress applying layer provided in an embodiment of the present application;

[0038] FIG7 is a structural diagram of a ferroelectric capacitor and a stress applying layer provided in an embodiment of the present application;

[0039] FIG8 is a structural diagram of a ferroelectric capacitor and a stress applying layer provided in an embodiment of the present application;

[0040] FIG9 is a structural diagram of a ferroelectric capacitor and a stress applying layer provided in an embodiment of the present application;

[0041] FIG10 a is a diagram illustrating the preparation process of a two-dimensional ferroelectric capacitor according to an embodiment of the present application;

[0042] FIG10 b is a diagram illustrating the preparation process of a two-dimensional ferroelectric capacitor according to an embodiment of the present application;

[0043] FIG10c is a diagram showing the preparation process of a two-dimensional ferroelectric capacitor provided in an embodiment of the present application;

[0044] FIG11a is a diagram illustrating the preparation process of a two-dimensional ferroelectric capacitor according to an embodiment of the present application;

[0045] FIG11b is a diagram illustrating the preparation process of a two-dimensional ferroelectric capacitor according to an embodiment of the present application;

[0046] FIG11c is a diagram illustrating the preparation process of a two-dimensional ferroelectric capacitor according to an embodiment of the present application;

[0047] FIG12 is a structural diagram of a three-dimensional ferroelectric capacitor and a stress application layer provided in an embodiment of the present application;

[0048] FIG13 is a structural diagram of a three-dimensional ferroelectric capacitor and a stress application layer provided in an embodiment of the present application;

[0049] FIG14 is a structural diagram of a three-dimensional ferroelectric capacitor and a stress application layer provided in an embodiment of the present application;

[0050] FIG15 is a flow chart of the preparation of a three-dimensional ferroelectric capacitor and a stress application layer provided in an embodiment of the present application;

[0051] FIG16a is a diagram illustrating the preparation process of a three-dimensional ferroelectric capacitor and a stress application layer provided in an embodiment of the present application;

[0052] FIG16 b is a diagram illustrating the preparation process of a three-dimensional ferroelectric capacitor and a stress application layer provided in an embodiment of the present application;

[0053] FIG16c is a diagram illustrating the preparation process of a three-dimensional ferroelectric capacitor and a stress application layer provided in an embodiment of the present application;

[0054] FIG16 d is a diagram showing the preparation process of the three-dimensional ferroelectric capacitor and the stress application layer provided in an embodiment of the present application.

[0055] Reference numerals: 10 - substrate; 11 - first electrode; 111 - first conductive film layer; 12 - second electrode; 121 - first sub-electrode; 122 - second sub-electrode; 1211 - second conductive film layer; 13 - ferroelectric layer; 14 - stress applying layer; 15 - dielectric layer; 16 - sacrificial layer. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0057] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0058] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0059] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0060] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0061] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, or the like, containing a ferroelectric capacitor.

[0062] Consumer electronic products include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products include car navigation systems and car displays, etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronic products include servers, storage devices, radars, base stations, and other communication equipment that contain chips.

[0063] For ease of explanation, the following description uses a mobile phone as an example electronic device. As shown in Figure 1, the mobile phone may include a circuit board, which may integrate a processor, memory, and the like, with the memory including multiple memory chips. Of course, the mobile phone may also include other components, and the circuit board may also integrate other circuit structures, but this is not limited to these embodiments of the present application.

[0064] The processor reads and writes data to the memory. For example, the memory in a mobile phone can be used to store computer executable program code, which includes instructions. The processor executes the instructions stored in the memory to perform various functions and data processing in the mobile phone.

[0065] In recent years, technologies like big data and artificial intelligence have entered a golden age of rapid development. Advances in these emerging technologies are driving fundamental changes in how we live, work, and think. At the same time, the application and integration of these new technologies rely heavily on the collection, transmission, and computation of massive amounts of data. Consequently, the volume of information that needs to be processed is exploding, placing higher demands on memory performance.

[0066] When it comes to memory, its performance needs to be considered from multiple perspectives, including storage capacity, read / write speed, non-volatility, and integration capabilities. Existing dynamic random access memory (DRAM) and static random access memory (SRAM) have high read / write speeds, but DRAM requires constant refresh during use, resulting in high power consumption. Furthermore, these two types of memory have the disadvantages of high cost, limited capacity, and data volatility in applications, and their miniaturization processes are approaching physical limits. Non-volatile memory, represented by NAND Flash, has the advantage of large storage capacity, but has low read / write speeds and cannot meet the application requirements of high-speed storage. Therefore, there is an urgent need to find a memory that combines high read / write speeds, non-volatility, low power consumption, and miniaturization to improve chip computing capabilities, save chip area, and further reduce chip costs.

[0067] Ferroelectric random access memory (FeRAM) is becoming one of the most promising next-generation memory technologies due to its high-speed read / write speed, non-volatility, low power consumption, small device size, and excellent cycling performance. As shown in Figure 2, the core of a ferroelectric memory consists of a ferroelectric capacitor, which comprises a first electrode 11, a ferroelectric layer 13, and a second electrode 12 stacked in sequence. As shown in Figures 3a and 3b, the ferroelectric layer undergoes polarization reversal under electric fields of different directions, causing the capacitor to charge and discharge, thereby achieving a "0" or "1" storage state.

[0068] The performance of the ferroelectric layer is affected by many factors, such as the doping elements of the ferroelectric layer, the thickness of the ferroelectric layer, the oxygen vacancies in the ferroelectric layer, the materials of the first electrode 11 and the second electrode 12, etc. The thermal expansion coefficient of the materials of the first electrode 11 and the second electrode 12 has a great influence on the residual polarization strength Pr of the ferroelectric layer. If the thermal expansion coefficient of the first electrode 11 and the second electrode 12 is too large, it will be unfavorable for the formation of the ferroelectric O phase of the ferroelectric layer. At the same time, it is easy to cause the ferroelectric layer 13 to change phase (O phase to M phase). When the ferroelectric layer 13 undergoes a phase change, it is impossible to suppress the change in its own volume, and thus it is impossible to effectively improve the ferroelectric performance. Therefore, a higher annealing temperature is required to make up for the lack of stress, which is easy to cause damage to the ferroelectric layer 13 during the annealing process.

[0069] The larger the ferroelectric O phase of the ferroelectric layer 13 is, the better the ferroelectric property is; the larger the dielectric M phase (ferroelectric monoclinic phase) of the ferroelectric layer 13 is, the worse the ferroelectric property is.

[0070] In this regard, related technologies propose to use metals with low thermal expansion coefficients as the materials of the first electrode 11 and the second electrode 12 . However, the thermal expansion coefficients of existing metal materials are not small enough, and the above-mentioned problems still exist.

[0071] Based on this, an embodiment of the present application provides a chip comprising a substrate and a ferroelectric capacitor disposed on the substrate. As shown in FIG4 , the ferroelectric capacitor comprises a first electrode 11, a ferroelectric layer 13, and a second electrode 12, which are sequentially stacked on the substrate. The surface of the ferroelectric layer 13 facing the second electrode 12 is a first surface, the second electrode 12 covers a portion of the first surface, and the portion of the first surface not covered by the second electrode 12 is a first sub-surface.

[0072] On this basis, as shown in Figures 5a, 5b and 6, the chip also includes a stress applying layer 14 made of dielectric material, the thermal expansion coefficient of the stress applying layer 14 is smaller than the thermal expansion coefficient of the second electrode 12, and the stress applying layer 14 extends from the first sub-surface to the side wall of the second electrode 12.

[0073] In the present application, by reducing the size of the second electrode 12 to cover the first sub-surface with a stressor layer 14, the stressor layer 14 has a smaller thermal expansion coefficient than the second electrode 12. Therefore, in a high-temperature environment, the stressor layer 14 deforms less than the second electrode 12, and a stronger chemical bond can be formed. For example, when preparing the stressor layer 14 and the second electrode 12, the stressor layer 14 and the second electrode 12 are annealed separately, and the stressor layer 14 deforms less than the second electrode 12. In this way, although the ferroelectric layer 13 is susceptible to deformation in a high-temperature environment, because the stressor layer 14 contacts the first sub-surface, the stressor layer 14 with a smaller deformation can be used to provide in-plane tensile stress to the easily deformed ferroelectric layer 13, thereby reducing the lateral deformation of the ferroelectric layer 13. Furthermore, the stressor layer 14 extends to the sidewalls of the second electrode 12, so it can also be used to provide longitudinal tensile stress to the ferroelectric layer 13, thereby reducing the longitudinal deformation of the ferroelectric layer. It can also be said that the stress application layer 14 with a smaller thermal expansion coefficient can generate a larger tensile stress during the cooling process. The tensile stress can inhibit the formation of the dielectric M phase, increase the proportion of the ferroelectric O phase, and effectively inhibit the volume change of the ferroelectric layer 13 due to phase change, thereby effectively improving the ferroelectric performance.

[0074] On this basis, because the stressor layer 14 has a smaller coefficient of thermal expansion than the second electrode 12, and the stressor layer 14 and the second electrode 12 exert a greater overall tensile stress on the ferroelectric layer 13, a higher annealing temperature is not required to compensate for the stress deficiency. Therefore, during the preparation of the stressor layer 14, the temperature required for high-temperature annealing of the stressor layer 14 is relatively low, thereby reducing the thermal budget. Compared to related art, the present application causes less damage to the ferroelectric layer 13 when performing a high-temperature annealing process on the stressor layer 14.

[0075] The “longitudinal direction” in the longitudinal tensile stress refers to the direction from the first electrode 11 to the second electrode 12 , and the “transverse direction” in the transverse tensile stress refers to the direction perpendicular to the longitudinal direction.

[0076] In some possible implementations, as shown in FIG5a , the stress applying layer 14 may completely cover the first sub-surface to provide the ferroelectric layer 13 with in-plane tensile stress to the greatest extent and reduce the lateral deformation of the portion of the ferroelectric layer 13 in contact with the stress applying layer 14 .

[0077] In some possible implementations, based on different processes, as shown in FIG5 a , the stress applying layer 14 may completely cover the sidewalls of the second electrode 12 ; or, as shown in FIG5 b , the stress applying layer 14 may also partially cover the sidewalls of the second electrode 12 .

[0078] In some possible implementations, as shown in Figures 5a and 5b, the first electrode 11, the ferroelectric layer 13, and the second electrode 12 can be stacked in sequence on the substrate 10 along the direction of the substrate 10 pointing to the ferroelectric capacitor. In this case, the first electrode 11 is the bottom electrode and the second electrode 12 is the top electrode.

[0079] Alternatively, as shown in FIG6 , the first electrode 11 , the ferroelectric layer 13 , and the second electrode 12 may be stacked sequentially on the substrate 10 along the direction in which the ferroelectric capacitor points toward the substrate 10 . In this case, the first electrode 11 is the top electrode and the second electrode 12 is the bottom electrode.

[0080] In some possible implementations, the stressor layer 14 surrounds the second electrode 12, or in other words, the first sub-surface surrounds the second electrode 12 ( FIG. 4 ), so that the stressor layer 14 provides greater stress around the edge of the ferroelectric layer 13. Alternatively, the stressor layer 14 does not surround the second electrode 12, as long as the first surface of the ferroelectric layer 13 is not completely covered by the second electrode 12.

[0081] In some possible implementations, the embodiment of the present application does not limit the material of the ferroelectric layer 13 , and the material of the ferroelectric layer 13 may include a ferroelectric material or an antiferroelectric material.

[0082] For example, the material of the ferroelectric layer 13 may include a perovskite ferroelectric material. For example, the material of the ferroelectric layer 13 includes lead titanate (PbTiO 3 ).

[0083] For example, the material of the ferroelectric layer 13 may also include a hafnium oxide-based ferroelectric material. For example, the material of the ferroelectric layer 13 includes hafnium oxide, hafnium zirconium oxide, and the like.

[0084] Since the band gap of perovskite ferroelectric materials is small, the leakage current is large and the size of the ferroelectric layer 13 cannot be miniaturized. Moreover, due to the high temperature required for preparation, some film layers in the transistors on the chip are easily affected by high temperature, resulting in the ferroelectric capacitor being incompatible with the transistor. However, hafnium oxide-based ferroelectric materials have a wider band gap, low leakage current, low power consumption, good cycle performance, the size of the ferroelectric layer 13 can be miniaturized (for example, the thickness is reduced to less than 10nm and still has ferroelectricity), and the preparation process is compatible with transistors. These characteristics give ferroelectric capacitors unique advantages in building high-density storage chips. Therefore, optionally, the material of the ferroelectric layer 13 includes hafnium oxide-based ferroelectric materials.

[0085] In some possible implementations, the embodiments of the present application do not limit the materials of the first electrode 11 and the second electrode 12 , as long as the first electrode 11 and the second electrode 12 are conductive.

[0086] Table 1 shows the thermal expansion coefficients of several conductive materials. As can be seen from Table 1, the thermal expansion coefficients of tungsten (W), molybdenum (Mo), platinum (Pt), titanium nitride (TiN), nickel (Ni), and copper (Cu) gradually increase. Optionally, a conductive material with a smaller thermal expansion coefficient can be selected as the material of the first electrode 11 and the second electrode 12. For example, the material of the first electrode 11 and the second electrode 12 can include W. In this way, the first electrode 11 and the second electrode 12 can also provide a certain degree of in-plane tensile stress to the ferroelectric layer 13, thereby improving the lateral deformation of the portion of the ferroelectric layer 13 that is in contact with the first electrode 11 and the second electrode 12. At the same time, the thermal budget for forming the first electrode 11 and the second electrode 12 can also be reduced, thereby avoiding damage to the ferroelectric layer 13 due to high-temperature annealing during the preparation of the first electrode 11 and the second electrode 12.

[0087] Table 1

[0088] Considering that in some cases, the top electrode containing W cannot be grown directly on the ferroelectric layer 13, for example, the top electrode is the second electrode 12. In this case, as shown in FIG7 , the second electrode 12 may include a first sub-electrode 121 and a second sub-electrode 122, wherein the first sub-electrode 121 is disposed between the ferroelectric layer 13 and the second sub-electrode 122. The material of the first sub-electrode 121 includes a material that can be grown directly on the ferroelectric layer 13 (for example, TiN), and the material of the second sub-electrode 122 includes W.

[0089] In some possible implementations, the embodiment of the present application does not limit the material of the stress applying layer 14 , as long as the thermal expansion coefficient of the material of the stress applying layer 14 is smaller than the thermal expansion coefficient of the material of the second electrode 12 .

[0090] Table 2 shows the thermal expansion coefficients of some materials. As can be seen from Table 2, the thermal expansion coefficients of silicon dioxide (SiO2), quartz, graphite, hexagonal boron nitride (h-BN), silicon nitride (SiN), silicon (Si), silicon germanium (SiGe), and silicon carbide (SiC) gradually increase. Optionally, a dielectric material with a relatively low thermal expansion coefficient can be selected as the material for the stressor layer 14. For example, the thermal expansion coefficient of the material of the stressor layer 14 can be less than the thermal expansion coefficient of W. The material of the stressor layer 14 can include at least one of SiO2, Quartz, graphite, h-BN, SiN, Si, SiGe, and SiC, so that the tensile stress provided by the stressor layer 14 to the ferroelectric layer 13 exceeds 1 GPa. For example, if the material of the stressor layer 14 includes SiN, the tensile stress provided by the stressor layer 14 to the ferroelectric layer 13 can exceed 1.7 GPa.

[0091] Table 2

[0092] In some possible implementation methods, after depositing the SiO2, Quartz, Graphite, h-BN, Si, SiGe, or SiC film layer, a high-temperature annealing process can be used to treat the SiO2, Quartz, Graphite, h-BN, SiN, Si, SiGe, or SiC film layer.

[0093] For the SiN film layer, a high temperature annealing process may be used to treat the SiN film layer, or an ultraviolet curing process may be used to treat the SiN film layer.

[0094] In some embodiments, as shown in FIG8 , the surface of the ferroelectric layer 13 facing the first electrode 11 is a second surface, the first electrode 11 covers a portion of the second surface, and the portion of the second surface not covered by the first electrode 11 is a second sub-surface. The stressor layer 14 has a thermal expansion coefficient that is less than that of the first electrode 11, and the stressor layer 14 extends from the second sub-surface to the sidewalls of the first electrode 11. In addition, a dielectric layer 15 may be disposed between the stressor layer 14 and the substrate 10.

[0095] By reducing the size of the first electrode 11 to cover the second surface with a stressor layer 14, the stressor layer 14 has a smaller thermal expansion coefficient than the first electrode 11. Therefore, in a high-temperature environment, the stressor layer 14 deforms less than the first electrode 11, and a stronger chemical bond can be formed. For example, when preparing the stressor layer 14 and the first electrode 11, the stressor layer 14 and the first electrode 11 are annealed separately, and the stressor layer 14 deforms less than the first electrode 11. In this way, although the ferroelectric layer 13 is susceptible to deformation in a high-temperature environment, because the stressor layer 14 contacts the second surface, the stressor layer 14 with a smaller deformation can be used to provide in-plane tensile stress to the easily deformed ferroelectric layer 13, thereby reducing the lateral deformation of the ferroelectric layer 13. Furthermore, the stressor layer 14 extends to the sidewalls of the first electrode 11, so it can also be used to provide longitudinal tensile stress to the ferroelectric layer 13, thereby reducing the longitudinal deformation of the ferroelectric layer. It can also be said that the stress application layer 14 with a smaller thermal expansion coefficient can generate a larger tensile stress during the cooling process. The tensile stress can inhibit the formation of the dielectric M phase, increase the proportion of the ferroelectric O phase, and effectively inhibit the volume change of the ferroelectric layer due to phase change, thereby effectively improving the ferroelectric performance.

[0096] On this basis, because the stressor layer 14 has a smaller coefficient of thermal expansion than the first electrode 11, and the stressor layer 14 and the second electrode 12 exert a greater overall tensile stress on the ferroelectric layer 13, a higher annealing temperature is not required to compensate for the stress deficiency. Therefore, during the preparation of the stressor layer 14, the high-temperature annealing temperature required for the stressor layer 14 is relatively low, thereby reducing the thermal budget. Compared to related art, the high-temperature annealing process of the stressor layer 14 in this application causes less damage to the ferroelectric layer 13.

[0097] In addition, in some embodiments, as shown in Figure 9, when the ferroelectric layer 13 includes a second sub-surface not covered by the first electrode 11, the stress applying layer 14 can also be completely filled between the substrate 10 and the ferroelectric layer 13 and arranged adjacent to the first electrode 11, utilizing the lateral tensile stress provided by the stress applying layer 14.

[0098] In another embodiment, the present application also provides a chip preparation method, which can be divided into the following cases:

[0099] In the first case, it is assumed that the first electrode 11 is a bottom electrode, the second electrode 12 is a top electrode, and the stress applying layer 14 is formed on the side of the ferroelectric layer 13 facing the second electrode 12 .

[0100] Specifically, the chip fabrication process includes the following steps: As shown in FIG10a, a first conductive film layer 111 (i.e., a first electrode), a ferroelectric layer 13, and a second conductive film layer 1211 are sequentially formed on a substrate 10. As shown in FIG10b, the second conductive film layer 1211 is etched to form a second electrode 12. The surface of the ferroelectric layer 13 facing the second electrode 12 is the first surface, the second electrode 12 covers a portion of the first surface, and the portion of the first surface not covered by the second electrode 12 is the first sub-surface.

[0101] Next, as shown in FIG10c , a stressor film 141 is formed on the second electrode 12. The portion of the stressor film 141 facing away from the substrate 10 is removed to expose the surface of the second electrode 12 facing away from the substrate 10, facilitating electrical connection between the second electrode and the conductive traces for signal transmission. The stressor film 14 has a lower thermal expansion coefficient than that of the second electrode 12. The stressor film 14 extends from the first sub-surface to the sidewalls of the second electrode 12. For example, chemical mechanical polishing (CMP) can be used to remove the portion of the stressor film 141 facing away from the substrate 10.

[0102] In the second case, it is assumed that the first electrode 11 is a top electrode, the second electrode 12 is a bottom electrode, and a stress applying layer 14 is formed on the side of the ferroelectric layer 13 facing the second electrode 12 .

[0103] Specifically, the chip fabrication process includes the following steps: As shown in FIG11a, dielectric layers 15 and stressor layers 14 are sequentially formed on a substrate 10. Multiple dielectric layers 15 are spaced apart, and the stressor layers 14 cover the sidewalls and the surface facing away from the substrate 10 of the dielectric layers 15. Next, as shown in FIG11b, second electrodes 12 are filled between adjacent stressor layers 14. In this way, the stressor layers 14 can cover the sidewalls of the second electrodes 12, wherein the thermal expansion coefficient of the stressor layers 14 is smaller than that of the second electrodes 12.

[0104] Next, as shown in FIG11c , a ferroelectric layer 13 and a first electrode 11 are sequentially formed on the stress applying layer 14 and the second electrode 11. The surface of the ferroelectric layer 13 facing the second electrode 12 is the first surface, the second electrode 12 covers a portion of the first surface, and the portion of the first surface not covered by the second electrode 12 is the first sub-surface, thereby ensuring that the stress applying layer 14 covers the first sub-surface.

[0105] In some other possible implementations, the second electrode 12 may be formed first, and then the dielectric layer 15 and the stress applying layer 14 are formed. This embodiment of the present application does not limit this.

[0106] In a third case, if the first electrode 11 is a bottom electrode, the second electrode 12 is a top electrode, and the stress applying layer 14 is formed on both sides of the ferroelectric layer 13 facing the second electrode 12 and the first electrode 11 .

[0107] Specifically, the chip fabrication process includes the following steps: As shown in FIG11a, dielectric layers 15 and stressor layers 14 are sequentially formed on a substrate 10. Multiple dielectric layers 15 are spaced apart, and the stressor layers 14 cover the sidewalls and the surface facing away from the substrate 10 of the dielectric layers 15. Next, as shown in FIG11b, first electrodes 11 are filled between adjacent stressor layers 14. In this way, the stressor layers 14 can cover the sidewalls of the first electrodes 11, wherein the thermal expansion coefficient of the stressor layers 14 is smaller than that of the first electrodes 11.

[0108] Next, referring to FIG11c , a ferroelectric layer 13 and a second conductive film layer 1211 are sequentially formed on the stress applying layer 14 and the first electrode 11. The surface of the ferroelectric layer 13 facing the first electrode 11 is the second surface, the first electrode 11 covers a portion of the second surface, and the portion of the second surface not covered by the first electrode 11 is the second sub-surface, thereby ensuring that the stress applying layer 14 covers the second sub-surface.

[0109] 10b, the second conductive film layer 1211 is etched to obtain the second electrode 12. The surface of the ferroelectric layer 13 facing the second electrode 12 is the first surface, the second electrode 12 covers part of the first surface, and the portion of the first surface not covered by the second electrode 12 is the first sub-surface.

[0110] Next, as shown in FIG8 , a stress-applying film layer 141 is formed on the second electrode 12. The portion of the stress-applying film layer 141 facing away from the substrate 10 is removed to form the stress-applying layer 14. This exposes the surface of the second electrode 12 facing away from the substrate 10, facilitating electrical connection between the second electrode and the conductive lead for signal transmission. The stress-applying layer 14 has a lower thermal expansion coefficient than that of the second electrode 12. The stress-applying layer 14 extends from the first sub-surface to the sidewalls of the second electrode 12. For example, CMP can be used to remove the portion of the stress-applying film layer 141 facing away from the substrate 10.

[0111] In some possible implementations, for the above three situations, after depositing the stress applying film layer 141 or the stress applying layer 14, an annealing process may be used to increase the tensile stress of the stress applying film layer 141 or the stress applying layer 14 (the tensile stress may reach a maximum of 1.7 GPa). In some possible implementations, for the above three situations, the embodiments of the present application do not limit the processes for depositing the first conductive film layer (or first electrode) 111, the ferroelectric layer 13, the second conductive film layer (or second electrode) 1211, and the stress applying film layer 141.

[0112] Optionally, a physical vapor deposition (PVD) process may be used to deposit the bottom electrode, and the bottom electrode may be the first conductive film layer (or first electrode) 111 or the second conductive film layer (or second electrode) 1211 .

[0113] The ferroelectric layer 13 may be deposited by plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0114] The top electrode may be deposited by a chemical vapor deposition (CVD) process. The top electrode may be the second conductive film layer (or the second electrode) 1211 or the first conductive film layer (or the first electrode) 111 .

[0115] The stress applying film layer 141 may be deposited by plasma enhanced chemical vapor deposition (PECVD) or ALD process.

[0116] In addition, other explanations and beneficial effects of the embodiments of the present application are the same as those of the previous embodiment and will not be repeated here.

[0117] The above two embodiments respectively introduce the structure of a two-dimensional ferroelectric capacitor and its preparation method. In other embodiments, the ferroelectric capacitor may also be a three-dimensional ferroelectric capacitor.

[0118] Specifically, as shown in Figures 12 and 13, the chip includes a three-dimensional ferroelectric capacitor disposed on a substrate 10. The three-dimensional ferroelectric capacitor includes a first electrode 11, a ferroelectric layer 13, a multilayer second electrode 12, and a multilayer dielectric layer 15. Along the substrate 10 toward the three-dimensional capacitor, the multilayer second electrodes 12 and the multilayer dielectric layers 15 are alternately disposed. The ferroelectric layer 13 and the first electrode 11 penetrate the multilayer second electrodes 12 and the multilayer dielectric layers 15. The ferroelectric layer 13 is disposed between the multilayer second electrodes 12 and the first electrode 11.

[0119] On this basis, the chip further includes a stressor layer 14 made of a dielectric material. The thermal expansion coefficient of the stressor layer 14 is smaller than that of the dielectric layer 15. The stressor layer 14 extends from between the adjacent second electrode 12 and the dielectric layer 15 to between the second electrode 12 and the ferroelectric layer 13. Figures 12 and 13 exemplarily illustrate a portion of a three-dimensional capacitor.

[0120] In the present application, since the thermal expansion coefficient of the stress-applying layer 14 is smaller than that of the dielectric layer 15, in a high-temperature environment, the deformation of the stress-applying layer 14 is smaller than that of the dielectric layer 15, and a stronger chemical bond can be formed. For example, when preparing the first electrode 11, the first electrode 11 is subjected to an annealing process to form a stress-applying layer 14 with a smaller deformation. In this way, although the ferroelectric layer 13 is prone to deformation in a high-temperature environment, because the stress-applying layer 14 is in contact with the ferroelectric layer 13, the stress-applying layer 14 with a smaller deformation can be used to provide in-plane tensile stress to the ferroelectric layer 13 that is prone to deformation, thereby reducing the lateral deformation of the ferroelectric layer 13. Furthermore, the stress-applying layer 14 also extends between the adjacent second electrode 12 and the dielectric layer 15. Therefore, on the basis of the second electrode 12 providing tensile stress to the ferroelectric layer, the stress-applying layer 14 can also be used to provide longitudinal tensile stress to the ferroelectric layer 13, thereby reducing the longitudinal deformation of the ferroelectric layer. It can also be said that the stress application layer 14 with a smaller thermal expansion coefficient can generate a larger tensile stress during the cooling process. The tensile stress can inhibit the formation of the dielectric M phase, increase the proportion of the ferroelectric O phase, and effectively inhibit the volume change of the ferroelectric layer 13 due to phase change, thereby effectively improving the ferroelectric performance.

[0121] On this basis, because the stressor layer 14 has a smaller coefficient of thermal expansion than the dielectric layer 15, and the stressor layer 14 and the second electrode 12 exert a greater overall tensile stress on the ferroelectric layer 13, a higher annealing temperature is not required to compensate for the stress deficiency. Therefore, during the preparation of the stressor layer 14, the high-temperature annealing temperature required for the stressor layer 14 is relatively low, thereby reducing the thermal budget. Compared to related art, the high-temperature annealing process of the stressor layer 14 in this application causes less damage to the ferroelectric layer 13.

[0122] The “longitudinal direction” in the longitudinal tensile stress refers to the direction from the first electrode 11 to the second electrode 12 , and the “transverse direction” in the transverse tensile stress refers to the direction perpendicular to the longitudinal direction.

[0123] In some possible implementations, based on different processes, as shown in Figures 12 and 13, the stress applying layer 14 can completely cover the surface of the second electrode 12 facing toward and away from the substrate 10; or, the stress applying layer 14 can also partially cover the surface of the second electrode 12 facing toward and away from the substrate 10.

[0124] In some possible implementations, the embodiment of the present application does not limit the material of the ferroelectric layer 13 , and the material of the ferroelectric layer 13 may include a ferroelectric material or an antiferroelectric material.

[0125] For example, the material of the ferroelectric layer 13 may include a perovskite ferroelectric material. For example, the material of the ferroelectric layer 13 includes PbTiO 3 .

[0126] For example, the material of the ferroelectric layer 13 may also include a hafnium oxide-based ferroelectric material. For example, the material of the ferroelectric layer 13 includes hafnium oxide, hafnium zirconium oxide, and the like.

[0127] Since the band gap of perovskite ferroelectric materials is small, the leakage current is large and the size of the ferroelectric layer 13 cannot be miniaturized. Moreover, due to the high temperature required for preparation, some film layers in the transistors on the chip are easily affected by high temperature, resulting in the ferroelectric capacitor being incompatible with the transistor. However, hafnium oxide-based ferroelectric materials have a wider band gap, low leakage current, low power consumption, good cycle performance, the size of the ferroelectric layer 13 can be miniaturized (for example, the thickness is reduced to less than 10nm and still has ferroelectricity), and the preparation process is compatible with transistors. These characteristics give ferroelectric capacitors unique advantages in building high-density storage chips. Therefore, optionally, the material of the ferroelectric layer 13 includes hafnium oxide-based ferroelectric materials.

[0128] In some possible implementations, the embodiments of the present application do not limit the materials of the first electrode 11 and the second electrode 12 , as long as the first electrode 11 and the second electrode 12 are conductive.

[0129] Table 1 shows the thermal expansion coefficients of several conductive materials. As can be seen from Table 1, the thermal expansion coefficients of W, Mo, Pt, TiN, Ni, and Cu gradually increase. Optionally, a conductive material with a smaller thermal expansion coefficient can be selected as the material of the first electrode 11 and the second electrode 12. For example, the material of the first electrode 11 and the second electrode 12 can include W. In this way, the first electrode 11 and the second electrode 12 can also provide a certain degree of in-plane tensile stress to the ferroelectric layer 13, thereby improving the lateral deformation of the portion of the ferroelectric layer 13 that contacts the first electrode 11 and the second electrode 12. At the same time, the thermal budget for forming the first electrode 11 and the second electrode 12 can also be reduced, thereby avoiding damage to the ferroelectric layer 13 due to high temperature during the preparation of the first electrode 11 and the second electrode 12.

[0130] Considering that in some cases, the first electrode 11 containing W cannot be grown directly on the ferroelectric layer 13. In this case, as shown in Figure 12, the first electrode 11 may include a third sub-electrode and a fourth sub-electrode, and the third sub-electrode is arranged between the ferroelectric layer 13 and the fourth sub-electrode. The material of the third sub-electrode includes a material that can be grown directly on the ferroelectric layer 13 (for example, TiN), and the material of the fourth sub-electrode includes W.

[0131] In some possible implementations, the embodiment of the present application does not limit the material of the stress applying layer 14 , as long as the thermal expansion coefficient of the material of the stress applying layer 14 is smaller than the thermal expansion coefficient of the material of the dielectric layer 15 .

[0132] Table 2 shows the thermal expansion coefficients of some materials. As can be seen from Table 2, the thermal expansion coefficients of SiO2, Quartz, Graphite, h-BN, SiN, Si, SiGe, and SiC gradually increase. Optionally, a dielectric material with a smaller thermal expansion coefficient can be selected as the material for the stressor layer 14. For example, the thermal expansion coefficient of the material of the stressor layer 14 can be smaller than the thermal expansion coefficient of the second electrode 12. In this way, the stressor layer 14 can provide a greater tensile stress to the ferroelectric layer 13 while the second electrode 12 provides tensile stress to the ferroelectric layer 13.

[0133] For example, the thermal expansion coefficient of the material of the stressor layer 14 is smaller than the thermal expansion coefficient of W. The material of the stressor layer 14 may include at least one of SiO2, Quartz, Graphite, h-BN, and SiN, so that the tensile stress provided by the stressor layer 14 to the ferroelectric layer 13 exceeds 1 GPa. For example, if the material of the stressor layer 14 includes SiN, the tensile stress provided by the stressor layer 14 to the ferroelectric layer 13 may exceed 1.7 GPa.

[0134] In addition, in other embodiments, as shown in Figure 14, the material of the dielectric layer 15 can also be the same as the material of the stress applying layer 14. In this way, the thermal expansion coefficient of the dielectric layer 15 is the same as the thermal expansion coefficient of the stress applying layer 14. As long as the material of the dielectric layer 15 is a dielectric material with a smaller thermal expansion coefficient, the dielectric layer 15 can be used to provide tensile stress to the ferroelectric layer 13 without the need to set up an additional stress applying layer 14.

[0135] In another embodiment, the present application provides a method for preparing a chip, as shown in FIG15 , which can be implemented by the following steps:

[0136] S110 , as shown in FIG. 16 a , a plurality of dielectric layers 15 and a plurality of sacrificial layers 16 are stacked and alternately formed on the substrate 10 .

[0137] In some possible implementations, the embodiments of the present application do not limit the multi-layer dielectric layer 15 and the multi-layer sacrificial layer 16 , as long as the multi-layer dielectric layer 15 is composed of dielectric material.

[0138] For example, the material of the multi-layer dielectric layer 15 includes SiO 2 , and the material of the multi-layer sacrificial layer 16 includes silicon (Si).

[0139] S120 , as shown in FIG16 b , a hollow portion is formed in the multi-layer dielectric layer 15 and the multi-layer sacrificial layer 16 , and the hollow portion penetrates the multi-layer dielectric layer 15 and the multi-layer sacrificial layer 16 along the direction of the substrate 10 pointing to the second electrode 12 .

[0140] In some possible implementations, the multi-layer dielectric layer 15 and the multi-layer sacrificial layer 16 may be etched by an etching process to form a hollow portion. For example, dry etching may be used to etch the multi-layer dielectric layer 15 and the multi-layer sacrificial layer 16.

[0141] S130 , as shown in FIG16 c , the hollow portion is sequentially filled with a ferroelectric layer 13 and a first electrode 11 , wherein the ferroelectric layer 13 is located between the first electrode 11 and the multi-layer dielectric layer 15 and the multi-layer sacrificial layer 16 .

[0142] In some possible implementations, the present embodiment does not limit the process for forming the ferroelectric layer 13 and the first electrode 11. Optionally, the ferroelectric layer 13 may be formed using a PECVD process or an ALD process, and the first electrode 11 may be formed using a CVD process.

[0143] S140, as shown in FIG16d, removes the multiple layers of sacrificial layer 16 to form a spacer. Next, as shown in FIG13, a stressor layer 14 and multiple layers of second electrodes 12 are sequentially formed in the spacer. The stressor layer 14 has a thermal expansion coefficient that is smaller than that of the dielectric layer 15. The stressor layer 14 extends from between the adjacent second electrode 12 and dielectric layer 15 to between the second electrode 12 and the ferroelectric layer 13.

[0144] In some possible implementations, an etching process may be used to selectively etch the multi-layer sacrificial layer 16 to remove the multi-layer sacrificial layer 16. It should be noted that the material of the multi-layer sacrificial layer 16 is different from the material of the multi-layer dielectric layer 15 and the ferroelectric layer 13. Therefore, the etching material used to etch the multi-layer sacrificial layer 16 will not etch the multi-layer dielectric layer 15 and the ferroelectric layer 13.

[0145] In some possible implementations, after forming the stress applying layer 14 and before forming the multi-layer second electrode 12 , the stress applying layer 14 may be annealed to increase the tensile stress of the stress applying layer 14 (the maximum tensile stress may reach 1.7 GPa).

[0146] In some other embodiments, in step S110 , a multi-layer sacrificial layer 16 and a multi-layer second electrode 12 may be formed first, and in step S140 , a stress applying layer 14 and a multi-layer dielectric layer 15 may be filled in the spacer region.

[0147] The second electrode 12 is formed in step S140 to avoid the influence of the high temperature process before the second electrode 12 on the second electrode 12 .

[0148] In addition, other explanations and beneficial effects of the embodiments of the present application are the same as those of the previous embodiment and will not be repeated here.

[0149] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A chip, characterized in that: It includes a substrate, a first electrode, a ferroelectric layer and a second electrode which are sequentially stacked on the substrate; The surface of the ferroelectric layer facing the second electrode is a first surface, the second electrode covers a portion of the first surface, and a portion of the first surface not covered by the second electrode is a first sub-surface; The chip further comprises a stress applying layer made of a dielectric material, wherein a thermal expansion coefficient of the stress applying layer is smaller than a thermal expansion coefficient of the second electrode, and the stress applying layer extends from the first sub-surface to a side wall of the second electrode.

2. The chip according to claim 1, characterized in that: The stress applying layer surrounds the second electrode.

3. The chip according to claim 1 or 2, characterized in that: Along the second direction, the first electrode, the ferroelectric layer, and the second electrode are sequentially arranged on the substrate.

4. The chip according to claim 3, characterized in that: The surface of the ferroelectric layer facing the first electrode is a second surface, the first electrode covers a portion of the second surface, and a portion of the second surface not covered by the first electrode is a second sub-surface; The stress applying layer has a thermal expansion coefficient that is smaller than a thermal expansion coefficient of the first electrode, and the stress applying layer further extends from the second sub-surface to a sidewall of the first electrode.

5. The chip according to claim 4, characterized in that: The stress applying layer completely covers the side walls of the first electrode and the second electrode; and / or, The stress applying layer completely covers the first sub-surface and the second sub-surface.

6. The chip according to any one of claims 1 to 5, characterized in that: The stressor layer has a thermal expansion coefficient that is less than a thermal expansion coefficient of tungsten.

7. The chip according to claim 6, characterized in that: The material of the stress applying layer includes at least one of silicon dioxide, quartz, graphite, hexagonal boron nitride, silicon nitride, silicon, silicon germanium, and silicon carbide.

8. A chip, characterized in that: It comprises a substrate and a three-dimensional ferroelectric capacitor arranged on the substrate, wherein the three-dimensional ferroelectric capacitor comprises a first electrode, a ferroelectric layer, a multi-layer second electrode, and a multi-layer dielectric layer; Along the direction of the substrate pointing to the three-dimensional capacitor, the multi-layer second electrodes and the multi-layer dielectric layers are alternately arranged, the ferroelectric layer and the first electrode penetrate the multi-layer second electrodes and the multi-layer dielectric layers; the ferroelectric layer is arranged between the multi-layer second electrodes and the first electrode; The chip further comprises a stress applying layer made of dielectric material, wherein the thermal expansion coefficient of the stress applying layer is smaller than the thermal expansion coefficient of the dielectric layer; the stress applying layer extends from between the adjacent second electrode and the dielectric layer to between the second electrode and the ferroelectric layer.

9. The chip according to claim 8, characterized in that: A thermal expansion coefficient of the stress applying layer is smaller than a thermal expansion coefficient of the second electrode.

10. The chip according to claim 8 or 9, characterized in that: The material of the stress applying layer includes at least one of silicon dioxide, quartz, graphite, hexagonal boron nitride, silicon nitride, silicon, silicon germanium, and silicon carbide.

11. A method for preparing a chip, characterized in that: include: Forming a stress applying layer composed of a dielectric material, and a first electrode, a ferroelectric layer, and a second electrode stacked on a substrate; The surface of the ferroelectric layer facing the second electrode is a first surface, the second electrode covers a portion of the first surface, and the portion of the first surface not covered by the second electrode is a first sub-surface; the chip also includes a stress applying layer composed of a dielectric material, the thermal expansion coefficient of the stress applying layer is smaller than the thermal expansion coefficient of the second electrode, and the stress applying layer extends from the first sub-surface to the side wall of the second electrode.

12. The method for preparing a chip according to claim 11, characterized in that: Before forming the stress applying layer on the substrate, forming a stacked first electrode, a ferroelectric layer, and a second electrode includes: sequentially forming a first electrode, a ferroelectric layer, and a conductive film layer stacked on the substrate; The conductive film layer is etched to obtain the second electrode.

13. The method for preparing a chip according to claim 11 or 12, characterized in that: Before forming the first electrode, the chip preparation method further includes: forming a plurality of dielectric layers and a plurality of stress applying layers disposed at intervals on the substrate, wherein the stress applying layers cover the surface and sidewall of the dielectric layer away from the substrate; the thermal expansion coefficient of the stress applying layers is smaller than the thermal expansion coefficient of the first electrode; The forming of the first electrode comprises: The first electrode is filled between adjacent stress applying layers.

14. A method for preparing a chip, characterized in that: include: forming stacked and alternating multiple dielectric layers and multiple sacrificial layers on a substrate; forming a hollow portion in the multi-layer dielectric layer and the multi-layer sacrificial layer, along the direction of the substrate pointing to the second electrode, the hollow portion penetrating the multi-layer dielectric layer and the multi-layer sacrificial layer; Filling the hollow portion with a ferroelectric layer and a first electrode in sequence, wherein the ferroelectric layer is located between the first electrode and the multi-layer dielectric layer and the multi-layer sacrificial layer; The multi-layer sacrificial layers are removed to form a spacer area, and a stress applying layer and a multi-layer second electrode are sequentially formed in the spacer area; the thermal expansion coefficient of the stress applying layer is smaller than the thermal expansion coefficient of the dielectric layer, and the stress applying layer extends from between the adjacent second electrode and the dielectric layer to between the second electrode and the ferroelectric layer.

15. The method for preparing a chip according to claim 14, characterized in that: The forming of a stress applying layer in the spacer region comprises: The stress applying layer is formed by a plasma enhanced chemical vapor deposition process or an atomic layer deposition process.

16. An electronic device, characterized in that: It comprises a circuit board and the chip according to any one of claims 1 to 7 or any one of claims 8 to 10, wherein the chip is arranged on the circuit board.

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