Integrated circuit unit, gate drive circuit, and display panel

Abstract

An integrated circuit unit, a gate drive circuit, and a display panel. In the integrated circuit unit, an input control sub-circuit (100) is connected to a gating signal end (DA), a third clock signal end (CLKD3) and a first node (N); an input sub-circuit (200) is connected to a second clock signal end (CLKD2), the first node (N), a first level signal end (GVDD1) and a second node (P); an output control sub-circuit (300) is connected to a fourth clock signal end (CLKD4), the second node (P), the first level signal end (GVDD1) and a plurality of third nodes (Q(n)); an output circuit (400) comprises a plurality of output sub-circuits, and is connected to the plurality of third nodes (Q(n)), a plurality of fifth clock signal ends (CLKE(n)), a plurality of output ends (SCOUT(n)) and a fifth level signal end (VGL1); a first pull-down control sub-circuit (500) is connected to the third nodes (Q(n)), a second level signal end (GVDD2), a third level signal end (VGL2) and a fourth node (QB); a second pull-down control sub-circuit (600) is connected to the second node (P), the fourth clock signal end (CLKD4), the fourth node (QB) and a fourth level signal end (LVGL); and a pull-down sub-circuit (700) is connected to the fourth node (QB), the third node (Q(n)), the fourth level signal end (LVGL) and the third clock signal end (CLKD3).

Description

Integrated circuit unit, gate drive circuit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to an integrated circuit unit, a gate driving circuit, and a display panel. Background Art

[0002] Active-matrix organic light-emitting diodes (AMOLEDs) are poised to replace LCDs as the mainstream choice for next-generation displays due to their high contrast, wide viewing angles, and fast response times. OLED products rely on EL devices (electroluminescent devices) to generate light, and the required current is provided by driver transistors. Due to variations in driver transistors, achieving uniform light emission requires increased consistency in device characteristics, which requires external compensation and shutdown compensation.

[0003] Common external compensation methods have problems such as being unable to output random frame displacement signals or having overly complex circuits.

[0004] Summary of the Invention

[0005] The purpose of the present application is to provide a display device, a gate driving circuit, an integrated circuit unit and a driving method thereof, which can realize compensation of random gating.

[0006] According to one aspect of the present application, there is provided an integrated circuit unit, comprising:

[0007] An input control subcircuit is electrically connected to the strobe signal terminal, the third clock signal terminal, and the first node, and controls the first node according to the strobe signal terminal and the third clock signal terminal;

[0008] An input subcircuit electrically connected to the second clock signal terminal, the first node, the first level signal terminal, and the second node, and controlling the second node according to the second clock signal terminal and the first node;

[0009] an output control subcircuit electrically connected to the fourth clock signal terminal, the second node, the first level signal terminal, and the plurality of third nodes, and controlling the plurality of third nodes according to the fourth clock signal terminal and the second node;

[0010] an output circuit, comprising a plurality of output sub-circuits, wherein the plurality of output sub-circuits are electrically connected to a plurality of third nodes, a plurality of fifth clock signal terminals, a plurality of output terminals, and a fifth level signal terminal, and output a driving signal under the control of the third nodes and the fifth clock signal terminal;

[0011] a first pull-down control subcircuit electrically connected to the third node, the second level signal terminal, the third level signal terminal, and the fourth node, and controlling the fourth node according to the third node;

[0012] A second pull-down control subcircuit is electrically connected to the second node, the fourth clock signal terminal, the fourth node, and the fourth level signal terminal, and controls the fourth node according to the second node and the fourth clock signal terminal;

[0013] The pull-down sub-circuit is electrically connected to the fourth node, the third node, the fourth level signal terminal, and the third clock signal terminal, and controls the third node according to the fourth node and the third clock signal terminal.

[0014] In some embodiments, the pull-down sub-circuit includes a first sub-pull-down sub-circuit and a second sub-pull-down sub-circuit;

[0015] The first sub-pull-down sub-circuit is electrically connected to the fourth node, the third node, the fourth level signal terminal, and the fifth node, and controls the third node according to the fourth node;

[0016] The second sub-pull-down sub-circuit is electrically connected to the third node, the fifth node, and the third clock signal terminal, and controls the third node according to the third clock signal terminal.

[0017] In some embodiments, the first sub-pull-down sub-circuit includes a plurality of transistors, wherein the control electrodes of the transistors are electrically connected to the fourth node, the first terminals of the transistors are electrically connected to the third node, and the second terminals of the transistors are electrically connected to the fourth level signal terminal.

[0018] In some embodiments, the second sub-pull-down sub-circuit includes a plurality of transistors, wherein the control electrodes of the transistors are electrically connected to the third clock signal terminal, the first terminals of the transistors are electrically connected to the third node, and the second terminals of the transistors are electrically connected to the fifth node.

[0019] In some embodiments, the input subcircuit includes a first capacitor and a tenth transistor and an eleventh transistor, the first end and the second end of the first capacitor are respectively connected to the first level signal end and the second node, the control electrode, the first electrode, and the second electrode of the eleventh transistor are respectively electrically connected to the second clock signal end, the first level signal end, and the second node, and the control electrode, the first electrode, and the second electrode of the tenth transistor are respectively electrically connected to the first node, the second clock signal end, and the second node.

[0020] In some embodiments, the output control subcircuit includes a plurality of control transistors, and the control electrode, the first electrode, and the second electrode of the control transistor are electrically connected to the fourth clock signal terminal, the second node, and the third node respectively.

[0021] In some embodiments, the output subcircuit includes a capacitor, an output transistor, and a pull-down transistor, the first electrode of the capacitor and the control electrode of the output transistor being electrically connected to the third node as the control electrode of the output subcircuit, the first electrode of the output transistor being electrically connected to the fifth clock signal terminal, and the second electrode of the capacitor and the second electrode of the output transistor being jointly used as the output terminal;

[0022] The first control terminal and the first terminal of the pull-down transistor are electrically connected to the fourth node and the second electrode of the output transistor respectively. The second terminal of the pull-down transistor is electrically connected to the fifth level signal terminal as the third terminal of the output sub-circuit.

[0023] In some embodiments, the first pull-down control subcircuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor, the control electrode and the first electrode of the fourteenth transistor are respectively electrically connected to the second level signal terminal, the second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor, the control electrode of the fifteenth transistor is electrically connected to the second level signal terminal, the second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the seventeenth transistor, the second electrode of the sixteenth transistor is electrically connected to the third level signal terminal, the control electrode of the sixteenth transistor is electrically connected to the third node as the first control terminal of the pull-down control subcircuit, the first electrode of the seventeenth transistor is connected to the second level signal terminal, and the second electrode of the seventeenth transistor is electrically connected to the fourth node.

[0024] In some embodiments, the first pull-down control sub-circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor, the control electrode and the first electrode of the fourteenth transistor are respectively electrically connected to the second level signal terminal, the second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor and the control electrode of the fifteenth transistor, the second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the seventeenth transistor, the second electrode of the sixteenth transistor is electrically connected to the third level signal terminal, the control electrode of the sixteenth transistor is electrically connected to the third node as the first control terminal of the pull-down control sub-circuit, the first electrode of the seventeenth transistor is connected to the second level signal terminal, and the second electrode of the seventeenth transistor is electrically connected to the fourth node.

[0025] In some embodiments, the first pull-down control sub-circuit further includes an eighteenth transistor, and the control electrode, the first electrode, and the second electrode of the eighteenth transistor are electrically connected to the third node, the fourth node, and the fourth level signal terminal, respectively.

[0026] In some embodiments, the number of the first pull-down control sub-circuit, the second pull-down control sub-circuit, and the pull-down sub-circuit is plural.

[0027] In some embodiments, the second pull-down control subcircuit includes a thirty-seventh transistor and a thirty-eighth transistor, the control electrode and the first electrode of the thirty-seventh transistor are respectively connected to the second node and the fourth node, the second electrode of the thirty-seventh transistor is electrically connected to the second electrode of the thirty-eighth transistor, and the control electrode and the second electrode of the thirty-eighth transistor are respectively electrically connected to the fourth clock signal terminal and the fourth level signal terminal.

[0028] In some embodiments, the integrated circuit unit further includes a reset subcircuit, and the reset subcircuit is electrically connected to the reset signal terminal, the first level signal terminal, the second node, the fourth node, and the fourth level signal terminal respectively.

[0029] In some embodiments, the reset subcircuit includes a nineteenth transistor, a twentieth transistor, and a twenty-second transistor, the control electrodes of the nineteenth transistor, the twentieth transistor, and the twenty-second transistor are electrically connected to the reset signal terminal, respectively, the first electrode of the nineteenth transistor is electrically connected to the first level signal terminal, the second electrode of the nineteenth transistor is electrically connected to the fourth node, the first electrode of the twenty-second transistor is electrically connected to the second node, the second electrode of the twenty-second transistor is electrically connected to the first electrode of the twentieth transistor, and the second electrode of the twentieth transistor is electrically connected to the fourth level signal terminal.

[0030] In some embodiments, the integrated circuit unit further includes an anti-leakage electronic circuit, wherein the first control electrode, the first terminal, and the second terminal of the anti-leakage electronic circuit are electrically connected to the third node, the first level signal terminal, and the pull-down sub-circuit respectively.

[0031] In some embodiments, the integrated circuit unit further includes a third pull-down subcircuit, which is electrically connected to the second clock signal terminal, the third clock signal terminal, and the first node respectively, and controls the first node according to the second clock signal terminal and the third clock signal terminal.

[0032] In some embodiments, the input control subcircuit includes a plurality of gating transistors connected in parallel, the number of the gating transistors is less than or equal to the number of the gating signal terminals, and the control electrode of each of the gating transistors is connected to one of the gating signal terminals.

[0033] In some embodiments, the first electrodes of the plurality of parallel-connected gating transistors are electrically connected to the third clock signal terminal, the second electrodes of the gating transistors are electrically connected to the first node, and the control electrodes of the gating transistors are electrically connected to the gating signal to control the first node.

[0034] In some embodiments, among the selection signal terminals connected to the plurality of selection transistors, the pulse width of the selection signal of the nth selection signal terminal is twice the pulse width of the selection signal of the n-1th selection signal terminal, where n is an integer greater than 1.

[0035] In some embodiments, the high level width and the low level width of the strobe signal in one cycle of each of the strobe signal terminals are equal.

[0036] A second aspect of the present application provides a gate drive circuit, comprising a plurality of integrated circuit unit groups, wherein the integrated circuit unit groups include the integrated circuit units described in the above embodiments, the number of the selection signal terminals is twice the number of the selection transistors, and the selection signal terminals include a plurality of positive selection signal terminals and a plurality of negative selection signal terminals whose signals are opposite to those of the positive selection signal terminals.

[0037] In some embodiments, the integrated circuit unit group includes four integrated circuit units, the integrated circuit units in the same group are connected to the selected communication terminal in the same manner, and the connection order of the integrated circuit units in the same group and each clock signal terminal is different.

[0038] In some embodiments, different groups of the integrated circuit units have different connections to the selection signal terminal.

[0039] A third aspect of the present application provides a display panel, comprising the gate driving circuit described in the above embodiment.

[0040] The present application realizes random compensation of external compensation through the cooperation of the input control subcircuit, the input subcircuit, the output control subcircuit, the output circuit, the first pull-down control subcircuit, the second pull-down control subcircuit, and the pull-down subcircuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG1 is a schematic diagram of driving signals for the first three rows of pixels in the related art.

[0042] FIG2 is a schematic diagram of a circuit principle of an integrated circuit unit in the related art.

[0043] FIG3 is a schematic diagram showing the principle of an integrated circuit unit according to an embodiment of the present application.

[0044] FIG4 is a timing diagram of an integrated circuit unit according to an embodiment of the present application.

[0045] FIG5 is a circuit diagram of an integrated circuit unit according to an embodiment of the present application.

[0046] FIG6 is a circuit diagram of another embodiment of the integrated circuit unit of the present application.

[0047] FIG7 is a circuit diagram of another embodiment of the integrated circuit unit of the present application.

[0048] FIG8 is a circuit diagram of another embodiment of the integrated circuit unit of the present application.

[0049] FIG9 is a circuit diagram of another embodiment of the integrated circuit unit of the present application.

[0050] FIG10 is a circuit diagram of another embodiment of the integrated circuit unit of the present application.

[0051] FIG. 11 is a connection diagram of an embodiment of a gate driving circuit of the present application.

[0052] FIG12 is a timing diagram of the strobe signal terminal of the integrated circuit unit of the present application. DETAILED DESCRIPTION

[0053] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, identical numbers in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of devices consistent with certain aspects of the present application, as detailed in the appended claims.

[0054] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. Unless otherwise defined, technical or scientific terms used in this application should have the same ordinary meaning as those understood by persons of ordinary skill in the art to which this application belongs. The terms "first," "second," and similar words used in this specification and claims do not denote any order, quantity, or importance, but are simply used to distinguish different components. Similarly, the terms "a" or "an" and similar words do not denote a limitation of quantity, but rather denote the presence of at least one. The terms "plurality" or "several" mean two or more. The terms "include" or "comprising" and similar words mean that the elements or articles preceding the term "include" or "comprising" include the elements or articles listed after the term and their equivalents, and do not exclude other elements or articles. The terms "connected" or "connected" and similar words are not limited to physical or mechanical connections and can also include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0055] The transistors used in this application can be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of this application, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0056] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0057] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0058] Pixel circuits typically use a combination of transistors and capacitors to drive the organic light-emitting elements (OLEDs), such as a 3T1C circuit. However, this circuit suffers from poor uniformity, necessitating a compensation circuit to achieve uniform OLED light emission. A common compensation method involves external compensation using a GOA (Gate on Array) circuit to improve device uniformity.

[0059] As shown in Figure 1, the external compensation signal is typically composed of a combination of "row shift" and "frame shift" signals. The signal during the blanking period (Blanking Time) of a frame is the frame shift signal. Frame shift is further divided into sequential frame shift and random frame shift. In the sequential frame shift compensation method, the gate drive circuit can output drive signals to the pixels row by row to compensate the pixel drive circuit; in the random frame shift compensation method, the gate drive circuit can output compensation drive signals to any row of pixels in any frame to compensate the pixel drive transistors. However, the sequential frame shift compensation method is prone to generating compensation stripes, resulting in poor display.

[0060] As shown in FIG2 , a GOA unit for realizing random frame shifting is provided. However, the GOA units in the figure are all independent and are connected to different signals completely through the gating circuit in the dotted box in the figure, thereby achieving the purpose of gating the row. However, there are too many transistors in the dotted box, making the layout very difficult; and shielding the S point is not conducive to suppressing noise.

[0061] As shown in FIG3 , the present application discloses an integrated circuit unit, comprising: an input control subcircuit 100 , an input subcircuit 200 , an output control subcircuit 300 , an output circuit 400 , a first pull-down control subcircuit 500 , a second pull-down control subcircuit 600 , and a pull-down subcircuit 700 . The input control subcircuit 100 is electrically connected to the selection signal terminal DA, the third clock signal terminal CLKD3, and the first node N, and controls the first node N according to the selection signal terminal DA and the third clock signal terminal CLKD3; the input subcircuit 200 is electrically connected to the second clock signal terminal CLKD2, the first node N, the first level signal terminal GVDD1, and the second node P, and controls the second node P according to the second clock signal terminal CLKD2 and the first node N; the output control subcircuit 300 is electrically connected to the fourth clock signal terminal CLKD4, the second node P, the first level signal terminal GVDD1, and multiple third nodes Q(n), and controls the multiple third nodes Q(n) according to the fourth clock signal terminal CLKD4 and the second node P; the output circuit 400 includes multiple output subcircuits, and the multiple output subcircuits are respectively connected to the multiple third nodes Q(n), the multiple fifth clock signal terminals CLKE(n), and the multiple output terminals SCOUT(n) is electrically connected to the fifth level signal terminal VGL1, and outputs a driving signal under the control of the third node Q(n) and the fifth clock signal terminal CLKE(n); the first pull-down control sub-circuit 500 is electrically connected to the third node Q(n), the second level signal terminal GVDD2, the third level signal terminal VGL2, and the fourth node QB, respectively, and controls the fourth node QB according to the third node Q(n); the second pull-down control sub-circuit 600 is electrically connected to the second node P, the fourth clock signal terminal CLKD4, the fourth node QB, and the fourth level signal terminal LVGL, respectively, and controls the fourth node QB according to the second node P and the fourth clock signal terminal CLKD4; the pull-down sub-circuit 700 is electrically connected to the fourth node QB, the third node Q(n), the fourth level signal terminal LVGL, and the third clock signal terminal CLKD3, respectively, and controls the third node Q(n) according to the fourth node QB and the third clock signal terminal CLKD3.

[0062] As shown in FIG4 , in a first phase S1, a rising edge of the second clock signal terminal CLKD2 arrives, while the first node N is in a closed state and the second node P is set to a high potential. In a second phase S2, the second node P remains at a high potential. In a third phase S3, a rising edge of the fourth clock signal terminal CLKD4 arrives, setting the third node Q(n) to a high potential. In a fourth phase S4, the fourth clock signal terminal CLKD4 is closed, and multiple fifth clock signal terminals CLKE(n) sequentially arrive at rising edges, and the integrated circuit unit outputs. After the integrated circuit unit outputs, a rising edge of the third clock signal terminal CLKD3 arrives, pulling the third node Q(n) low. CLKE(n) refers to CLKE1, CLKE2, CLKE16, and so on.

[0063] The integrated circuit unit proposed in this application uses a gate signal terminal DA to achieve the purpose of gating the row, avoiding the use of excessive transistors, thus occupying less space and facilitating the realization of a narrow frame. In addition, the present application provides multiple output sub-circuits, so that multiple compensation signals can be output within a single GOA unit.

[0064] In one embodiment, the input control subcircuit 100 includes a plurality of gating transistors connected in parallel. The number of the gating transistors is less than or equal to the number of the gating signal terminals, and the control electrode of each gating transistor is connected to one of the gating signal terminals. It can be seen that as long as at least one gating transistor is connected, the control subcircuit 100 can control the first node N under the control of the third clock signal terminal CLKD3.

[0065] Further, referring to Figure 5 , the first electrodes of the plurality of parallel-connected gate transistors are electrically connected to the third clock signal terminal, the second electrodes of the gate transistors are electrically connected to the first node N, and the control electrodes of the gate transistors are electrically connected to the gate signal DA to control the first node N. Based on the above structural arrangement, the gate signal DA can control the potential of the first node N. The number of parallel-connected gate transistors can be varied as needed, and can be 1, 3, 6, 8, or 11, etc. The number of gate signal terminals is greater than or equal to the number of gate transistors, and the control electrode of each gate transistor is connected to a gate signal terminal. This embodiment uses eight gate transistors and eight gate signal terminals as an example. The eight gate transistors are the second transistor T1 to the ninth transistor T8, and the eight gate signal terminals are the first gate signal terminal D0 to the eighth gate signal terminal D7. The eight gate transistors are connected to the eight gate signal terminals accordingly. One cycle of the eighth gate signal terminal D7 can cover 28 cycles of the first gate signal terminal D0. One high level segment of the eighth selection signal terminal D7 can cover 27 cycles of the first selection signal terminal D0.

[0066] Furthermore, referring to Figures 11 and 12, among the select signal terminals connected to the plurality of select transistors, the pulse width of the select signal at the nth select signal terminal is twice the pulse width of the select signal at the n-1th select signal terminal, where n is an integer greater than 1. With this arrangement, the connectivity of the select signal terminals can be set simply by connecting them in sequence. Furthermore, the high-level width and the low-level width of the select signal in one cycle of each select signal terminal can be made equal. The equal high-level width and the low-level width can also ensure that the output after connection is performed in the order of Figure 11, thereby allowing the entire GOA unit to operate normally.

[0067] Optionally, the number of selection signal terminals can be greater than 8, and a selection signal terminal with a phase opposite to any one of the first selection signal terminal D0 to the eighth selection signal terminal D7 can be added. For example, a ninth selection signal terminal D0' with a phase opposite to the first selection signal terminal D0 can be added. Or 8 signal terminals, from the ninth selection signal terminal D0' to the sixteenth selection signal terminal D7', with phases opposite to the first selection signal terminal D0 to the eighth selection signal terminal D7, can be added. One of a pair of selection signal terminals with opposite phases is selected to be connected to the control electrode of the selection transistor. Taking 8 pairs of selection signal terminals with opposite phases as an example, there can be 28 combinations, which can achieve 28 effective outputs with different timings. Therefore, the present application can achieve local high refresh of at least 28 rows.

[0068] In one embodiment, as shown in Figure 4, the present application also includes a third pull-down sub-circuit, which is electrically connected to the second clock signal terminal CLKD2, the third clock signal terminal CLKD3, and the first node N, respectively, and controls the first node N according to the second clock signal terminal CLKD2 and the third clock signal terminal CLKD3.

[0069] The third pull-down sub-circuit includes a ninth transistor T9, wherein the control electrode, the first electrode, and the second electrode of the ninth transistor T9 are electrically connected to the second clock signal terminal CLKD2, the third clock signal terminal CLKD3, and the first node N, respectively. When the rising edge of the second clock signal terminal CLKD2 arrives, the ninth transistor T9 is turned on, and the potential of the first node N is pulled low.

[0070] In one embodiment, as shown in reference figure 5, the output sub-circuit includes a capacitor, an output transistor and a pull-down transistor, the first electrode of the capacitor and the control electrode of the output transistor are electrically connected to the third node Q(n) as the control electrode of the output sub-circuit, the first electrode of the output transistor is electrically connected to the fifth clock signal terminal CLKE(n), the second electrode of the capacitor and the second electrode of the output transistor are jointly used as the output terminal; the first control terminal and the first terminal of the pull-down transistor are electrically connected to the fourth node QB and the second electrode of the output transistor, respectively, and the second terminal of the pull-down transistor is electrically connected to the fifth level signal terminal VGL1 as the third terminal of the output sub-circuit.

[0071] In an exemplary embodiment, as shown in FIG5 , the output circuit 400 includes four output sub-circuits. The first output sub-circuit includes a capacitor C2, a 40th transistor T40, and a 41st transistor T41. The first electrode of the capacitor C2 and the control electrode of the 40th transistor T40 serve as the control electrode of the output sub-circuit and are electrically connected to the third node Q1. The first electrode of the 40th transistor T40 is electrically connected to the fifth clock signal terminal CLKE1. The second electrode of the capacitor C2 and the second electrode of the 40th transistor T40 serve as the output terminal. The first control terminal and the first terminal of the 41st transistor T41 are electrically connected to the fourth node QB and the second electrode of the 40th transistor T40, respectively. The second terminal of the 41st transistor T41 serves as the third terminal of the output sub-circuit and is electrically connected to the fifth level signal terminal VGL1. The second output sub-circuit includes a capacitor C3, a 42nd transistor T42, and a 43rd transistor T43. The third output sub-circuit includes a capacitor C4, a 44th transistor T44, and a 45th transistor T45. The fourth output sub-circuit includes a capacitor C5, a 46th transistor T46, and a 47th transistor T47. The connection methods of each output sub-circuit are the same and will not be described here one by one.

[0072] Based on the above description, when the voltage of the fourth node QB is positive, each output sub-circuit is pulled low to prevent erroneous output.

[0073] In one embodiment, as shown in Figure 5, the pull-down sub-circuit 700 includes a first sub-pull-down sub-circuit 710 and a second sub-pull-down sub-circuit 720; the first sub-pull-down sub-circuit 710 is electrically connected to the fourth node QB, the third node Q(n), the fourth level signal terminal LVGL, and the fifth node X, respectively, and controls the third node Q(n) according to the fourth node QB; the second sub-pull-down sub-circuit 720 is electrically connected to the third node Q(n), the fifth node X, and the third clock signal terminal CLKD3, respectively, and controls the third node Q(n) according to the third clock signal terminal CLKD3.

[0074] Specifically, the first sub-pull-down sub-circuit 710 includes multiple transistors, the control electrodes of the transistors are electrically connected to the fourth node QB, the first ends of the transistors are electrically connected to the third node Q(n), and the second ends of the transistors are electrically connected to the fourth level signal terminal LVGL.

[0075] 5 , when the output circuit 400 includes four output sub-circuits, the first pull-down sub-circuit 710 includes a 36th transistor T36, a 27th transistor T27, a 28th transistor T28, a 29th transistor T29, and a 30th transistor T30. The control electrodes of the 27th transistor T27, the 28th transistor T28, the 29th transistor T29, and the 30th transistor T30 are electrically connected to the fourth node QB, respectively. The first electrodes of the 27th transistor T27, the 28th transistor T28, the 29th transistor T29, and the 30th transistor T30 are electrically connected to the third nodes Q1-Q4, respectively. The second electrodes of the 27th transistor T27, the 28th transistor T28, the 29th transistor T29, and the 30th transistor T30 are electrically connected to the first electrode of the 36th transistor T36, respectively. The control electrode of the 36th transistor T36 is electrically connected to the fourth node QB, and the second electrode of the 36th transistor T36 is electrically connected to the fourth level signal terminal LVGL.

[0076] Based on the above description, when the fourth node QB is energized, the 36th transistor T36 is turned on and electrically connected to the fourth-level signal terminal LVGL. Simultaneously, the 27th transistor T27, the 28th transistor T28, the 29th transistor T29, and the 30th transistor T30 are also turned on and electrically connected to the 36th transistor T36. Therefore, the third nodes Q1-Q4 connected to the 27th transistor T27, the 28th transistor T28, the 29th transistor T29, and the 30th transistor T30 are all directly connected to the fourth-level signal terminal LVGL, thereby maintaining a low potential.

[0077] Specifically, the second sub-pull-down sub-circuit 720 includes a plurality of transistors, the control electrodes of the transistors are electrically connected to the third clock signal terminal CLKD3, the first terminals of the transistors are electrically connected to the third node Q(n), and the second terminals of the transistors are electrically connected to the fifth node X.

[0078] 5 , when the output circuit 400 includes four output sub-circuits, the second pull-down sub-circuit 720 includes a thirty-first transistor T31, a thirty-second transistor T32, a thirty-third transistor T33, a thirty-fourth transistor T34, and a thirty-fifth transistor T35. Control electrodes of the thirty-first transistor T31, the thirty-second transistor T32, the thirty-third transistor T33, the thirty-fourth transistor T34, and the thirty-fifth transistor T35 are electrically connected to the third clock signal terminal CLKD3, respectively. First electrodes of the thirty-first transistor T31, the thirty-second transistor T32, the thirty-third transistor T33, and the thirty-fourth transistor T34 are electrically connected to the third nodes Q1-Q4, respectively. Second electrodes of the thirty-first transistor T31, the thirty-second transistor T32, the thirty-third transistor T33, and the thirty-fourth transistor T34, and a first electrode of the thirty-fifth transistor T35 are electrically connected to the fifth node X, respectively. A second electrode of the thirty-fifth transistor T35 is connected to the fourth level signal terminal LVGL.

[0079] Based on the above description, when the rising edge of the third clock signal terminal CLKD3 arrives, the 35th transistor T35 is turned on and electrically connected to the fourth-level signal terminal LVGL. Simultaneously, the 31st transistor T31, the 32nd transistor T32, the 33rd transistor T33, and the 34th transistor T34 are also turned on and electrically connected to the 35th transistor T35. Therefore, the third nodes Q1-Q4 connected to the 31st transistor T31, the 32nd transistor T32, the 33rd transistor T33, and the 34th transistor T34 are all directly connected to the fourth-level signal terminal LVGL, thereby maintaining a low potential.

[0080] In one embodiment, as shown in FIG5 , the input sub-circuit 200 includes a first capacitor C1 and a tenth transistor T10 and an eleventh transistor T11. The first end and the second end of the first capacitor C1 are respectively connected to the first level signal terminal GVDD1 and the second node P. The control electrode, the first electrode, and the second electrode of the eleventh transistor T11 are respectively electrically connected to the second clock signal terminal CLKD2, the first level signal terminal GVDD1, and the second node P. The control electrode, the first electrode, and the second electrode of the tenth transistor T10 are respectively electrically connected to the first node N, the second clock signal terminal CLKD2, and the second node P.

[0081] The circuit can also connect a twelfth transistor T12 and a thirteenth transistor T13 in series and in parallel to prevent leakage. When the rising edge of the second clock signal terminal CLKD2 arrives, the eleventh transistor T11 is turned on, the first capacitor C1 is charged, and thus the second node P is set to a high potential.

[0082] In one embodiment, as shown in FIG5 , the output control subcircuit 300 includes a plurality of control transistors, wherein the control electrode, the first electrode, and the second electrode of the control transistor are electrically connected to the fourth clock signal terminal CLKD4 , the second node P, and the third node Q(n), respectively.

[0083] As shown in FIG5 , the output control subcircuit 300 includes a twenty-first transistor T21, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-fifth transistor T25, and a twenty-sixth transistor T26. The control electrode and the first electrode of the twenty-first transistor T21 are connected to the second node P and the first level signal terminal GVDD1, respectively. The second electrode of the twenty-first transistor T21 is connected to the first electrodes of the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-fifth transistor T25, and the twenty-sixth transistor T26. The control electrodes of the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-fifth transistor T25, and the twenty-sixth transistor T26 are electrically connected to the fourth clock signal terminal CLKD4. The second electrodes of the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-fifth transistor T25, and the twenty-sixth transistor T26 are connected to the third nodes Q1-Q4, respectively. When the second node P is at a high potential and the rising edge of the fourth clock signal terminal CLKD4 arrives, the third nodes Q1-Q4 are also at a high potential.

[0084] In other embodiments, as shown in Figures 9 and 10, the output control sub-circuit 300 further includes a new transistor T21'. The first electrode and control electrode of the new transistor T21' are both connected to the fourth clock signal terminal CLKD4, and the second electrode of the new transistor T21' is connected to the twenty-first transistor T21 instead of the original first-level signal terminal GVDD1. The provision of the new transistor T21' can prevent leakage of the fourth clock signal terminal CLKD4, thereby preventing the third nodes Q1-Q4 from being placed at a high potential, thereby maximizing the protection of the third nodes Q1-Q4.

[0085] In one embodiment, as shown in Figures 5 and 6, the first pull-down control sub-circuit 500 includes a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17. The control electrode and the first electrode of the fourteenth transistor T14 are respectively electrically connected to the second level signal terminal GVDD2, the second electrode of the fourteenth transistor T14 is electrically connected to the first electrode of the fifteenth transistor T15, the control electrode of the fifteenth transistor T15 is electrically connected to the second level signal terminal GVDD2, the second electrode of the fifteenth transistor T15 is electrically connected to the first electrode of the sixteenth transistor T16 and the control electrode of the seventeenth transistor T17, the second electrode of the sixteenth transistor T16 is electrically connected to the third level signal terminal VGL2, the control electrode of the sixteenth transistor T16 serving as the first control terminal of the pull-down control sub-circuit is electrically connected to the third node Q(n), the first electrode of the seventeenth transistor T17 is connected to the second level signal terminal GVDD2, and the second electrode of the seventeenth transistor T17 is electrically connected to the fourth node QB.

[0086] As shown in Figure 5, when the output circuit 400 includes four output sub-circuits, the third node Q(n) includes Q1-Q4, and Q2 is selected here as an example. When Q2 is at a low level, the fourth node QB is set to a high potential; when Q2 is at a low level, the fourth node QB is set to a low potential.

[0087] In other embodiments, as shown in FIG7 , the first pull-down control sub-circuit 500 includes a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17. The control electrode and the first electrode of the fourteenth transistor T14 are respectively electrically connected to the second level signal terminal GVDD2. The second electrode of the fourteenth transistor T14 is electrically connected to the first electrode of the fifteenth transistor T15 and the control electrode of the fifteenth transistor T15. The second electrode of the fifteenth transistor T15 is electrically connected to the first electrode of the sixteenth transistor T16 and the control electrode of the seventeenth transistor T17. The second electrode of the sixteenth transistor T16 is electrically connected to the third level signal terminal VGL2. The control electrode of the sixteenth transistor T16 is electrically connected to the third node Q(n) as the first control terminal of the pull-down control sub-circuit. The first electrode of the seventeenth transistor T17 is connected to the second level signal terminal GVDD2. The second electrode of the seventeenth transistor T17 is electrically connected to the fourth node QB.

[0088] This embodiment can achieve the same effect, but the control electrode charge of the fifteenth transistor T15 here comes from the second electrode of the fourteenth transistor T14, so the pressure on the fifteenth transistor T15 is reduced, thereby ensuring the reliability of the fifteenth transistor T15.

[0089] Furthermore, in this embodiment, the first pull-down control subcircuit 500 may further include an eighteenth transistor T18, the control electrode, the first electrode, and the second electrode of the eighteenth transistor T18 are electrically connected to the third node Q(n), the fourth node QB, and the fourth level signal terminal LVGL, respectively.

[0090] At this time, the control electrodes of the sixteenth transistor T16 and the eighteenth transistor T18 are connected to Q2 and Q3 respectively. As long as one of Q2 or Q3 has current, the fourth node QB can be pulled low, thereby achieving double-layer protection.

[0091] In one embodiment, referring to FIG. 8 , FIG. 9 , and FIG. 10 , there are multiple first pull-down control sub-circuit 500 , multiple second pull-down control sub-circuit 600 , and multiple pull-down sub-circuit 700 .

[0092] As shown in the figure, there are preferably two first pull-down control sub-circuits 500, the output circuit 400 includes four output sub-circuits, and the third node Q(n) includes Q1-Q4. The first pull-down control sub-circuit 500 includes a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a fourteenth additional transistor T14', a fifteenth additional transistor T15', a sixteenth additional transistor T16', a seventeenth additional transistor T17', and an eighteenth additional transistor T18'. The control electrodes of the sixteenth transistor T16, the eighteenth transistor T18, the sixteenth additional transistor T16', and the eighteenth additional transistor T18' are connected to the third nodes Q1-Q4, respectively. As long as there is current at any point on the third node Q(n), the fourth node QB can be pulled down, thereby achieving maximum protection.

[0093] In one embodiment, the second pull-down control sub-circuit 600 includes a 37th transistor T37 and a 38th transistor T38. The control electrode and the first electrode of the 37th transistor T37 are connected to the second node P and the fourth node QB, respectively. The second electrode of the 37th transistor T37 is electrically connected to the second electrode of the 38th transistor T38. The control electrode and the second electrode of the 38th transistor T38 are electrically connected to the fourth clock signal terminal CLKD4 and the fourth level signal terminal LVGL, respectively. When the second node P and the fourth clock signal terminal CLKD4 are both present, the voltage of the fourth node QB is pulled down.

[0094] In one embodiment, the second pull-down control sub-circuit 600 may be provided in multiple numbers. As shown in FIG. 9 , two second pull-down control sub-circuits 600 are selected to implement multi-layer protection.

[0095] In one embodiment, as shown in FIG5 , the integrated circuit unit further includes a reset sub-circuit 1000 , which is electrically connected to the reset signal terminal TRS, the first level signal terminal GVDD1 , the second node P, the fourth node QB, and the fourth level signal terminal LVGL, respectively.

[0096] As shown in FIG5 , the reset sub-circuit 1000 includes a nineteenth transistor T19, a twentieth transistor T20, and a twenty-second transistor T22. The control electrodes of the nineteenth transistor T19, the twentieth transistor T20, and the twenty-second transistor T22 are respectively electrically connected to the reset signal terminal TRS. The first electrode of the nineteenth transistor T19 is electrically connected to the first level signal terminal GVDD1, the second electrode of the nineteenth transistor T19 is electrically connected to the fourth node QB, the first electrode of the twenty-second transistor T22 is electrically connected to the second node P, the second electrode of the twenty-second transistor T22 is electrically connected to the first electrode of the twentieth transistor T20, and the second electrode of the twentieth transistor T20 is electrically connected to the fourth level signal terminal LVGL. When the rising edge of the reset signal TRS arrives, the second node P is pulled low, and the fourth node QB is set to a high potential.

[0097] In one embodiment, as shown in Figures 5 and 6, the integrated circuit unit further includes an anti-leakage electronic circuit, and the first control electrode, the first end, and the second end of the anti-leakage electronic circuit 800 are electrically connected to the third node Q(n), the first level signal end GVDD1, and the pull-down sub-circuit 700, respectively.

[0098] The leakage prevention electronic circuit 800 includes a 39th transistor T39 and a 48th transistor T48. The first electrodes of the 39th transistor T39 and the 48th transistor T48 are respectively electrically connected to the first level signal terminal GVDD1. The second electrodes of the 39th transistor T39 and the 48th transistor T48 are electrically connected to the fifth node X. The control electrodes of the 39th transistor T39 and the 48th transistor T48 are electrically connected to the third node Q(n). The 39th transistor T39 and the 48th transistor T48 are connected in parallel.

[0099] Of course, in other embodiments, as shown in FIG. 5 and FIG. 6 , the thirty-ninth transistor T39 and the forty-eighth transistor T48 may also be connected in series.

[0100] As shown in Figure 4, which is a timing diagram of an alternative embodiment, the reset signal terminal TRS is first reset, pulling the fourth node QB to a high potential, thereby ensuring that the third node Q(n) remains low. At the same time, the second node P is also pulled low to ensure that the entire timing sequence proceeds normally.

[0101] In the first phase S1, the rising edge of the second clock signal terminal CLKD2 arrives, and the second node P is set to a high potential. Although the selection signal DA is high at this time, the third clock signal terminal CLKD3 has not arrived, so the first node N remains low.

[0102] In the second phase S2, the rising edge of the third clock signal terminal CLKD3 arrives, and the second node P remains at a high level. Although the third clock signal terminal CLKD3 arrives, the selection signal DA is low, so the first node N still remains at a low level.

[0103] In the third phase S3, the rising edge of the fourth clock signal terminal CLKD4 arrives, the third node Q(n) is set to a high potential, and the fourth node QB is pulled down to a low potential;

[0104] In the fourth stage S4, the fourth clock signal terminal CLKD4 is turned off, and multiple fifth clock signal terminals CLKE(n) arrive at rising edges in sequence, and the integrated circuit unit outputs; after the integrated circuit unit outputs, the third clock signal terminal CLKD3 arrives at a rising edge, and the third node Q(n) is pulled low.

[0105] As shown in Figures 10 and 11, the present application also discloses a gate drive circuit, which includes multiple integrated circuit unit groups. An integrated circuit unit group includes at least one of the above-mentioned integrated circuit units. Each integrated circuit unit includes n gate transistors. The gate drive circuit includes 2n gate signal terminals, wherein the 2n gate signal terminals include D0, D0', D1, D1', D2, D2', D3, D3', D4, D4', D5, D5', ... Dn, D'n, a total of 16 signal terminals, wherein D0', D1', D2', D3', D4', D5', ... Dn' are respectively the inverted signals of D0, D1, D2, D3, D4, D5, ... Dn. The pulse width of Da is twice the pulse width of Da-1, where a is 2, 3 to n. The connections between the integrated circuit units of different groups and the gate signal terminals are different. The number of gate transistors in the present application can be set according to requirements.

[0106] In an optional embodiment, the control electrode of the ath gate transistor among the n gate transistors is selectively connected to one of Da or Da', where a is greater than 0 and less than n. The integrated circuit units in the same integrated circuit unit group are connected to the gate signal terminal in the same manner. By analogy, 2n+1 integrated circuit unit groups can be operated independently. Optionally, an integrated circuit unit group includes four integrated circuit units, and these four integrated circuit units realize shift output through a connection sequence different from each clock signal terminal. And an integrated circuit unit of the present application can have four output ports. Therefore, the gate drive circuit of this embodiment can realize 2n+5 rows working independently. In the row shift stage, the gate drive circuit can adjust the signal output sequence of the gate signal terminal and the constant signal terminal to shift rows. In the blanking stage, the gate drive circuit can adjust the signal output random frame shift of the gate signal terminal and the constant signal terminal to realize random external compensation.

[0107] The present application also discloses a display panel, comprising the above-mentioned gate driving circuit.

[0108] The display device, gate driving circuit, integrated circuit unit and driving method thereof provided in the embodiments of the present application belong to the same inventive concept. The descriptions of relevant details and beneficial effects can be referred to each other and will not be repeated here.

[0109] The above description is merely a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as a preferred embodiment as above, it is not intended to limit the present application. Any technician familiar with this profession can make some changes or modifications to the equivalent embodiment of the above-disclosed technical content without departing from the scope of the technical solution of the present application. However, any simple modification, equivalent change and modification of the above embodiment based on the technical essence of the present application that does not depart from the content of the technical solution of the present application still falls within the scope of the technical solution of the present application.

Claims

1. An integrated circuit unit, characterized in that: include: An input control subcircuit is electrically connected to the strobe signal terminal, the third clock signal terminal, and the first node, and controls the first node according to the strobe signal terminal and the third clock signal terminal; An input subcircuit electrically connected to the second clock signal terminal, the first node, the first level signal terminal, and the second node, and controlling the second node according to the second clock signal terminal and the first node; an output control subcircuit electrically connected to the fourth clock signal terminal, the second node, the first level signal terminal, and the plurality of third nodes, and controlling the plurality of third nodes according to the fourth clock signal terminal and the second node; an output circuit comprising a plurality of output sub-circuits, wherein the plurality of output sub-circuits are electrically connected to a plurality of third nodes, a plurality of fifth clock signal terminals, a plurality of output terminals, and a fifth level signal terminal, and output drive signals under the control of the third nodes and the fifth clock signal terminal; a first pull-down control subcircuit electrically connected to the third node, the second level signal terminal, the third level signal terminal, and the fourth node, and controlling the fourth node according to the third node; A second pull-down control subcircuit is electrically connected to the second node, the fourth clock signal terminal, the fourth node, and the fourth level signal terminal, and controls the fourth node according to the second node and the fourth clock signal terminal; The pull-down sub-circuit is electrically connected to the fourth node, the third node, the fourth level signal terminal, and the third clock signal terminal, and controls the third node according to the fourth node and the third clock signal terminal.

2. The integrated circuit unit according to claim 1, wherein: The pull-down sub-circuit includes a first sub-pull-down sub-circuit and a second sub-pull-down sub-circuit; The first sub-pull-down sub-circuit is electrically connected to the fourth node, the third node, the fourth level signal terminal, and the fifth node, and controls the third node according to the fourth node; The second sub-pull-down sub-circuit is electrically connected to the third node, the fifth node, and the third clock signal terminal, and controls the third node according to the third clock signal terminal.

3. The integrated circuit unit according to claim 2, wherein: The first sub-pull-down sub-circuit includes a plurality of transistors, wherein the control electrodes of the transistors are electrically connected to the fourth node, the first terminals of the transistors are electrically connected to the third node, and the second terminals of the transistors are electrically connected to the fourth level signal terminal.

4. The integrated circuit unit according to claim 2, wherein: The second sub-pull-down sub-circuit includes a plurality of transistors, wherein the control electrodes of the transistors are electrically connected to the third clock signal terminal, the first terminals of the transistors are electrically connected to the third node, and the second terminals of the transistors are electrically connected to the fifth node.

5. The integrated circuit unit according to claim 1, wherein: The input sub-circuit includes a first capacitor and a tenth transistor and an eleventh transistor. The first end and the second end of the first capacitor are respectively connected to the first level signal end and the second node. The control electrode, the first electrode, and the second electrode of the eleventh transistor are respectively electrically connected to the second clock signal end, the first level signal end, and the second node. The control electrode, the first electrode, and the second electrode of the tenth transistor are respectively electrically connected to the first node, the second clock signal end, and the second node.

6. The integrated circuit unit according to claim 1, wherein: The output control subcircuit includes a plurality of control transistors, wherein the control electrodes, first electrodes, and second electrodes of the control transistors are electrically connected to the fourth clock signal terminal, the second node, and the third node respectively.

7. The integrated circuit unit according to claim 1, wherein: The output subcircuit includes a capacitor, an output transistor, and a pull-down transistor, wherein the first electrode of the capacitor and the control electrode of the output transistor are electrically connected to the third node as the control electrode of the output subcircuit, the first electrode of the output transistor is electrically connected to the fifth clock signal terminal, and the second electrode of the capacitor and the second electrode of the output transistor serve as the output terminal; The first control terminal and the first terminal of the pull-down transistor are electrically connected to the fourth node and the second electrode of the output transistor respectively. The second terminal of the pull-down transistor is electrically connected to the fifth level signal terminal as the third terminal of the output sub-circuit.

8. The integrated circuit unit according to claim 1, wherein: The first pull-down control sub-circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor. The control electrode and the first electrode of the fourteenth transistor are respectively electrically connected to the second level signal terminal, the second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor, the control electrode of the fifteenth transistor is electrically connected to the second level signal terminal, the second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the seventeenth transistor, the second electrode of the sixteenth transistor is electrically connected to the third level signal terminal, the control electrode of the sixteenth transistor is electrically connected to the third node as the first control terminal of the pull-down control sub-circuit, the first electrode of the seventeenth transistor is connected to the second level signal terminal, and the second electrode of the seventeenth transistor is electrically connected to the fourth node.

9. The integrated circuit unit according to claim 1, wherein: The first pull-down control subcircuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor. The control electrode and the first electrode of the fourteenth transistor are respectively electrically connected to the second level signal terminal, the second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor and the control electrode of the fifteenth transistor, the second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the seventeenth transistor, the second electrode of the sixteenth transistor is electrically connected to the third level signal terminal, the control electrode of the sixteenth transistor is electrically connected to the third node as the first control terminal of the pull-down control subcircuit, the first electrode of the seventeenth transistor is connected to the second level signal terminal, and the second electrode of the seventeenth transistor is electrically connected to the fourth node.

10. The integrated circuit unit according to claim 8 or 9, characterized in that: The first pull-down control sub-circuit further includes an eighteenth transistor, and the control electrode, the first electrode, and the second electrode of the eighteenth transistor are electrically connected to the third node, the fourth node, and the fourth level signal terminal respectively.

11. The integrated circuit unit according to claim 1, wherein: There are multiple first pull-down control sub-circuit, multiple second pull-down control sub-circuit, and multiple pull-down sub-circuit.

12. The integrated circuit unit according to claim 1, wherein: The second pull-down control subcircuit includes a thirty-seventh transistor and a thirty-eighth transistor, the control electrode and the first electrode of the thirty-seventh transistor are respectively connected to the second node and the fourth node, the second electrode of the thirty-seventh transistor is electrically connected to the second electrode of the thirty-eighth transistor, and the control electrode and the second electrode of the thirty-eighth transistor are respectively electrically connected to the fourth clock signal terminal and the fourth level signal terminal.

13. The integrated circuit unit according to claim 1, wherein: The integrated circuit unit further includes a reset subcircuit, which is electrically connected to the reset signal terminal, the first level signal terminal, the second node, the fourth node, and the fourth level signal terminal respectively.

14. The integrated circuit unit according to claim 13, wherein: The reset subcircuit includes a nineteenth transistor, a twentieth transistor, and a twenty-second transistor. The control electrodes of the nineteenth transistor, the twentieth transistor, and the twenty-second transistor are electrically connected to the reset signal terminal, respectively. The first electrode of the nineteenth transistor is electrically connected to the first level signal terminal, the second electrode of the nineteenth transistor is electrically connected to the fourth node, the first electrode of the twenty-second transistor is electrically connected to the second node, the second electrode of the twenty-second transistor is electrically connected to the first electrode of the twentieth transistor, and the second electrode of the twentieth transistor is electrically connected to the fourth level signal terminal.

15. The integrated circuit unit according to claim 1, wherein: The integrated circuit unit further includes an anti-leakage electronic circuit, wherein a first control electrode, a first terminal, and a second terminal of the anti-leakage electronic circuit are electrically connected to the third node, the first level signal terminal, and the pull-down sub-circuit respectively.

16. The integrated circuit unit according to claim 1, wherein: The integrated circuit unit further includes a third pull-down subcircuit, which is electrically connected to the second clock signal terminal, the third clock signal terminal, and the first node respectively, and controls the first node according to the second clock signal terminal and the third clock signal terminal.

17. The integrated circuit unit according to claim 1, wherein: The input control subcircuit includes a plurality of gating transistors connected in parallel, the number of the gating transistors is less than or equal to the number of the gating signal terminals, and the control electrode of each of the gating transistors is connected to one of the gating signal terminals.

18. The integrated circuit unit according to claim 17, wherein: The first electrodes of the plurality of parallel-connected selection transistors are electrically connected to the third clock signal terminal, the second electrodes of the selection transistors are electrically connected to the first node, and the control electrodes of the selection transistors are electrically connected to the selection signal to control the first node.

19. The integrated circuit unit according to claim 18, characterized in that Among the selection signal terminals connected to the selection transistors, the pulse width of the selection signal of the nth selection signal terminal is twice the pulse width of the selection signal of the n-1th selection signal terminal, where n is an integer greater than 1.

20. The integrated circuit unit according to claim 19, wherein: The high level width and the low level width of the selection signal in one cycle of each selection signal terminal are equal.

21. A gate drive circuit, characterized in that: It comprises a plurality of integrated circuit unit groups, wherein the integrated circuit unit group comprises at least one integrated circuit unit as described in any one of claims 1 to 20, the number of the selection signal terminals is twice the number of the selection transistors, and the selection signal terminals comprise a plurality of positive selection signal terminals and a plurality of negative selection signal terminals whose signals are opposite to those of the positive selection signal terminals.

22. The gate driving circuit according to claim 21, wherein: The integrated circuit unit group includes four integrated circuit units. The integrated circuit units in the same group are connected to the selected communication terminal in the same manner, and the integrated circuit units in the same group are connected to the clock signal terminals in different orders.

23. The gate driving circuit according to claim 22, wherein: Different groups of the integrated circuit units have different connections with the selection signal terminal.

24. A display panel, characterized in that: Comprising the gate drive circuit as described in any one of claims 21-23.

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