Display panel and display device

Abstract

A display panel and a display device. The display panel has a main display area and a secondary display area located on at least one side of the main display area. The display panel comprises a substrate, a plurality of pixel units, and a plurality of openings. The plurality of pixel units are located on one side of the substrate. The plurality of pixel units comprise a plurality of first pixel units and a plurality of second pixel units. The plurality of first pixel units are located in the main display area. The plurality of second pixel units are located in the secondary display area. The light transmittance of the main display area is less than the light transmittance of the secondary display area. The plurality of openings at least run through the substrate. The plurality of openings are located in the secondary display area. A plurality of second pixel units are arranged surrounding at least one of the plurality of openings. Orthographic projection of the plurality of openings on the substrate do not overlap orthographic projections of the plurality of second pixel units on the substrate.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202311119302.6, filed on August 31, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] With the development of display technology, full-screen displays with cameras (FDCs) have been gradually adopted in display products due to their large screen-to-body ratio. Full-screen displays typically place optical components such as cameras under the display panel, significantly increasing the screen-to-body ratio.

[0004] Summary of the Invention

[0005] On the one hand, a display panel is provided, comprising a main display area and a secondary display area located on at least one side of the main display area. The display panel comprises: a substrate, a plurality of pixel units and a plurality of openings. The plurality of pixel units are located on one side of the substrate. The plurality of pixel units comprise: a plurality of first pixel units and a plurality of second pixel units. The plurality of first pixel units are located in the main display area, and the plurality of second pixel units are located in the secondary display area. The transmittance of the main display area is less than the transmittance of the secondary display area. The plurality of openings at least penetrate the substrate. The plurality of openings are located in the secondary display area, and a plurality of the second pixel units are arranged around at least one of the plurality of openings, and the orthographic projections of the plurality of openings on the substrate do not overlap with the orthographic projections of the plurality of second pixel units on the substrate.

[0006] In some embodiments, the substrate includes: a first sub-substrate located in the main display area, and a second sub-substrate located in the auxiliary display area. The first sub-substrate and the second sub-substrate are connected. The plurality of first pixel units are located on the first sub-substrate. The second sub-substrate includes: a plurality of island portions and a plurality of bridging portions. The plurality of island portions are arranged in a plurality of rows and columns. At least one second pixel unit is provided on each island portion. A plurality of bridging portions are located between the plurality of island portions in the same row and between the plurality of island portions in the same column, and two adjacent island portions are connected by the bridging portions; and a plurality of the island portions and a plurality of the bridging portions are arranged around the at least one opening.

[0007] In some embodiments, the pixel units include pixel circuits, the first pixel unit includes a first pixel circuit, and the second pixel unit includes a second pixel circuit; the multiple pixel circuits of the multiple pixel units are arranged in multiple rows, the multiple rows of pixel circuits include multiple first-type pixel circuit rows; the first-type pixel circuit rows include multiple first pixel circuits and multiple second pixel circuits. The display panel also includes: first-type signal lines electrically connected to each pixel circuit in the first-type pixel circuit rows. Along the row direction, the first-type signal lines run from the main display area, through multiple island portions where the multiple second pixel circuits in the first-type pixel circuit rows are located, and multiple bridge portions arranged along the same line as the multiple island portions, and then through the secondary display area.

[0008] In some embodiments, the multiple rows of pixel circuits further include multiple rows of second-type pixel circuits; the second-type pixel circuit rows include multiple first-type pixel circuits, and along the row direction, the multiple first-type pixel circuits in the second-type pixel circuit rows are located on opposite sides of the secondary display area; along the column direction, at least one second-type pixel circuit row is provided between two adjacent rows of the first-type pixel circuits. The display panel further includes: second-type signal lines electrically connected to each pixel circuit in the second-type pixel circuit rows. Along the row direction, the portion of the second-type signal line proximate to the secondary display area winds along the boundary of the secondary display area to an adjacent island portion or bridge portion, passes through multiple island portions and multiple bridge portions arranged in the same row as the adjacent island portion or bridge portion, and penetrates the secondary display area.

[0009] In some embodiments, a portion of the second-type signal line located on the island portion is arranged along a boundary of the island portion.

[0010] In some embodiments, a portion of the second-type signal line located on the island portion does not overlap with a second pixel circuit located on the island portion.

[0011] In some embodiments, the signal transmitted by the first type of signal line is the same as the signal transmitted by the second type of signal line.

[0012] In some embodiments, the first type of signal line includes at least one of a scan signal line, an enable signal line, and an initial signal line.

[0013] In some embodiments, the number of second pixel units disposed on the island portion is plural, and among the plurality of island portions located in the same row, the second pixel circuits of the plurality of second pixel units on each of the island portions are arranged in the same row.

[0014] In some embodiments, the pixel unit includes a pixel circuit, the first pixel unit includes a first pixel circuit, and the second pixel unit includes a second pixel circuit. The multiple pixel circuits of the multiple pixel units are arranged in multiple columns, and the multiple columns of pixel circuits include multiple first-type pixel circuit columns. The first-type pixel circuit column includes multiple first pixel circuits and multiple second pixel circuits. Along the column direction, the multiple first pixel circuits of the first-type pixel circuit column are located on opposite sides of the secondary display area. The display panel also includes: a third-type signal line electrically connected to each pixel circuit in the first-type pixel circuit column. Along the column direction, the third-type signal line passes through the secondary display area from the main display area, through the multiple island portions where the multiple second pixel circuits of the first-type pixel circuit column are located, and the multiple bridge portions arranged in the same column as the multiple island portions.

[0015] In some embodiments, the multiple columns of pixel circuits further include multiple columns of second-type pixel circuits; the second-type pixel circuit columns include multiple first-type pixel circuits, and along the column direction, the multiple first-type pixel circuits of the second-type pixel circuit columns are located on opposite sides of the secondary display area. Along the row direction, at least one second-type pixel circuit column is disposed between two adjacent columns of the first-type pixel circuits. The display panel further includes: a fourth-type signal line electrically connected to each pixel circuit in the second-type pixel circuit columns. Along the column direction, a portion of the fourth-type signal line proximate to the secondary display area winds along the boundary of the secondary display area to an adjacent island portion or bridge portion, passes through multiple island portions and multiple bridge portions disposed in the same column as the adjacent island portion or bridge portion, and penetrates the secondary display area.

[0016] In some embodiments, a portion of the fourth-category signal line located on the island portion is arranged along a boundary of the island portion.

[0017] In some embodiments, a portion of the fourth-type signal line located on the island portion does not overlap with the second pixel circuit located on the island portion.

[0018] In some embodiments, the multiple columns of pixel circuits further include multiple columns of second-category pixel circuits; the second-category pixel circuit columns include multiple first-category pixel circuits, and along the column direction, the multiple first-category pixel circuits of the second-category pixel circuit columns are located on opposite sides of the secondary display area. Along the row direction, at least one second-category pixel circuit column is provided between two adjacent columns of the first-category pixel circuits. The display panel further includes: a fourth-category signal line electrically connected to each pixel circuit in the second-category pixel circuit columns. The fourth-category signal line is located in the main display area. Along the column direction, a portion of the fourth-category signal line close to the secondary display area winds from the first side of the secondary display area along the boundary of the secondary display area to the second side of the secondary display area. The first side of the secondary display area and the second side of the secondary display area are opposite sides of the secondary display area along the row direction.

[0019] In some embodiments, the number of second pixel units disposed on the island portion is plural, and the second pixel circuits of the plurality of second pixel units on each of the plurality of island portions located in the same column are arranged in the same column.

[0020] In some embodiments, the signal transmitted by the third type signal line is the same as the signal transmitted by the fourth type signal line.

[0021] In some embodiments, the third type signal line includes at least one of a data signal line and a first voltage signal line.

[0022] In some embodiments, the pixel unit includes a pixel circuit. The first pixel unit includes a first pixel circuit and a first electrode pattern located on a side of the first pixel circuit away from the first sub-substrate. Multiple first electrode patterns are connected and form an integrated structure. The second pixel unit includes a second pixel circuit and a second electrode pattern located on a side of the second pixel circuit away from the island portion. The second electrode patterns on different island portions are arranged independently of each other. Alternatively, the display panel includes a connecting pattern located on the bridging portion. The second electrode patterns on two adjacent island portions are connected via the connecting pattern. The second electrode pattern is also connected to the first electrode pattern.

[0023] In some embodiments, when the second electrode pattern is connected to the connection pattern and the first electrode pattern, the display panel further includes: a plurality of first barrier dam groups located in the secondary display area, wherein each first barrier dam group surrounds each opening, and each first barrier dam group is further located between the second pixel circuit and an adjacent opening.

[0024] In some embodiments, the first barrier dam group includes: at least one barrier dam. In the case where the first barrier dam group includes a plurality of barrier dams, the plurality of barrier dams are concentrically arranged and spaced apart.

[0025] In some embodiments, when the second electrode patterns on different island portions are independently arranged, the display panel further includes: a fifth type of signal line, the fifth type of signal line being used to transmit a common voltage signal. The fifth type of signal line includes: at least one first sub-signal line extending in the column direction, and multiple second sub-signal lines extending in the row direction. The first sub-signal line is located in the main display area. The second sub-signal line extends from the auxiliary display area through multiple island portions and multiple bridge portions located in the same row to the main display area, where it is connected to the first sub-signal line. The second sub-signal line is also connected to the second electrode pattern on each of the island portions it passes through.

[0026] In some embodiments, the first sub-signal line, the second sub-signal line, and the second electrode pattern are located in different layers.

[0027] In some embodiments, the display panel further comprises: a second barrier dam group and a plurality of third barrier dam groups located in the auxiliary display area. The second barrier dam group is disposed along a boundary of the auxiliary display area and surrounds the auxiliary display area. One third barrier dam group is located on each island portion, the third barrier dam group being disposed along a boundary of the corresponding island portion and surrounding the second pixel unit on the corresponding island portion.

[0028] In some embodiments, the second barrier dam group includes at least one barrier dam. If the second barrier dam group includes multiple barrier dams, the multiple barrier dams are concentrically arranged and spaced apart. The third barrier dam group includes at least one barrier dam. If the second barrier dam group includes multiple barrier dams, the multiple barrier dams are concentrically arranged and spaced apart.

[0029] In another aspect, a display device is provided, comprising: a display panel as described in any of the above embodiments, and an optical element, wherein the optical element is located on the non-light-emitting side of the display panel and in the secondary display area of ​​the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below should be considered schematic diagrams and are not intended to limit the actual dimensions, etc., of the products involved in the embodiments of the present disclosure.

[0031] FIG1 is a schematic diagram of a display device according to some embodiments of the present disclosure;

[0032] FIG2 is a schematic diagram of another display device according to some embodiments of the present disclosure;

[0033] FIG3 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0034] FIG4 is a structural diagram of another display panel according to some embodiments of the present disclosure;

[0035] FIG5 is a structural diagram of another display panel according to some embodiments of the present disclosure;

[0036] FIG6 is a structural diagram of another display panel according to some embodiments of the present disclosure;

[0037] FIG7 is a structural diagram of a substrate according to some embodiments of the present disclosure;

[0038] FIG8 is a structural diagram of the display panel cut along the FF direction in FIG5 ;

[0039] FIG9 is an equivalent circuit diagram of a pixel circuit and a light-emitting device according to some embodiments of the present disclosure;

[0040] FIG10 is an equivalent circuit diagram of another pixel circuit and a light-emitting device according to some embodiments of the present disclosure;

[0041] FIG11 is a structural diagram of another display panel according to some embodiments of the present disclosure;

[0042] FIG12 is a structural diagram of another display panel according to some embodiments of the present disclosure;

[0043] FIG13 is a structural diagram of another display panel according to some embodiments of the present disclosure;

[0044] 14 to 24 are top views of the structures of some film layers in a display panel according to some embodiments of the present disclosure;

[0045] FIG25 is a top view of a first electrode layer according to some embodiments of the present disclosure;

[0046] FIG26 is a top view of another first electrode layer according to some embodiments of the present disclosure;

[0047] FIG27 is a partial structural diagram of a secondary display area of ​​a display panel according to some embodiments of the present disclosure;

[0048] FIG28 is a structural diagram of the display panel taken along line GG in FIG27 ;

[0049] 29 to 33 are top views of some film layers in another display panel according to some embodiments of the present disclosure;

[0050] FIG34 is a partial structural diagram of a secondary display area of ​​another display panel according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0052] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0053] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0054] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0055] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0056] As used herein, "perpendicular" and "equal" include the conditions described and conditions similar to the conditions described, where the range of the similar conditions is within an acceptable deviation range, where the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, that the difference between the two equalities is less than or equal to 5% of either.

[0057] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0058] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0059] As shown in FIG1 , some embodiments of the present disclosure provide a display device 1000. The display device 1000 can be any display device that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, camera view displays (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0060] The display device 1000 includes a frame, a display driver IC (Integrated Circuit), and other electronic components.

[0061] In some examples, as shown in Figure 2, the display device 1000 further includes a display panel 100 and an optical element 200. The display panel 100 is embedded in the frame and electrically connected to the display IC to receive display signals provided by the display IC.

[0062] Exemplarily, as shown in FIG. 2 to FIG. 4 , the display panel 100 has a display area A, which is a region of the display panel 100 used for displaying images.

[0063] The display area A may be in the shape of a rectangle or a rounded rectangle, etc. A rounded rectangle means that all four corners of the rectangle are rounded.

[0064] The display area A includes a main display area A1 and a subsidiary display area A2 . The subsidiary display area A2 is located on at least one side of the main display area A1 .

[0065] For example, the shape of the auxiliary display area A2 can be circular, elliptical, rectangular, etc.

[0066] For example, the auxiliary display area A2 is located on one side or multiple sides of the main display area A1.

[0067] For example, when the display area A is in the shape of a rectangle, the sub-display area A2 can be located at any position in the middle of the rectangle, or the sub-display area A2 can be located near any corner of the rectangle, or the sub-display area A2 can be located near any side of the rectangle.

[0068] For example, in the display panel 100 , both the portion located in the main display area A1 and the portion located in the auxiliary display area A2 can be used for image display.

[0069] Exemplarily, the light transmittance of the auxiliary display area A2 is greater than the light transmittance of the main display area A1.

[0070] Exemplarily, the optical element 200 is located on the non-light-exiting side of the display panel 100 , and is located in the auxiliary display area A2 of the display panel 100 .

[0071] The light-emitting side of the display panel 100 refers to the side of the display panel 100 that can display images. The non-light-emitting side of the display panel 100 refers to the side opposite the light-emitting side of the display panel 100. Because the light transmittance of the secondary display area A2 is greater than that of the primary display area A1, external light is less lost after passing through the secondary display area A2, allowing the optical element 200 to receive sufficient light without affecting its functionality.

[0072] For example, as shown in FIG2 , the optical element 200 may be a camera, a fingerprint recognition sensor, an infrared sensor, and the like.

[0073] When the optical element 200 is working, it is necessary for external light to pass through the auxiliary display area A2 and illuminate the optical element 200 to activate its corresponding function. This disclosure takes the optical element 200 as an example of a camera.

[0074] For example, when the camera is working, external light can pass through the portion of the display panel 100 located in the secondary display area A2. In this way, the camera can collect the light and realize the function of taking pictures or videos. For example, when the camera is working (for example, the user takes a selfie), the secondary display area A2 can present a black screen, and the main display area A1 presents the user's selfie picture, which clearly shows the location of the camera. Alternatively, the secondary display area A2 and the main display area A1 as a whole present the user's selfie picture, without showing the location of the camera.

[0075] For example, when the camera is not working, the portions of the display panel 100 located in the auxiliary display area A2 and the main display area A1 can both display, so that the display panel 100 and the display device 1000 as a whole can display images.

[0076] In one implementation, in the display panel of the display device, the transmittance of the secondary display area is low, so that less light enters the camera through the secondary display area, and the light collected by the camera is limited, affecting the camera's picture clarity.

[0077] Based on this, in some examples of the present disclosure, as shown in FIG5 , the display panel 100 includes: a substrate 10 and a pixel unit layer.

[0078] The substrate 10 may be a rigid substrate made of glass, or a flexible substrate made of a highly elastic material such as dimethylsiloxane, PI (Polyimide), or PET (Polyethylene terephthalate).

[0079] The pixel unit layer includes a plurality of pixel units 30. The plurality of pixel units 30 are located on one side of the substrate 10, for example, on one surface of the substrate 10. The plurality of pixel units 30 interact with each other and can be used to display images.

[0080] As shown in FIG5 , the plurality of pixel units 30 include a plurality of first pixel units 301 and a plurality of second pixel units 302. The plurality of first pixel units 301 are located in the primary display area A1, and the plurality of second pixel units 302 are located in the secondary display area A2. Thus, both the primary display area A1 and the secondary display area A2 of the display panel 100 can display images.

[0081] The structures of the first pixel unit 301 and the second pixel unit 302 can be the same or similar. When the structures of the first pixel unit 301 and the second pixel unit 302 are the same, the size of the first pixel unit 301 can be the same as the size of the second pixel unit 302, or the size of the first pixel unit 301 can be larger than the size of the second pixel unit 302. The size here can be the area of ​​the orthographic projection of the pixel unit 30 on the plane where the substrate 10 is located.

[0082] 5 , the distribution density of the plurality of first pixel units 301 is greater than the distribution density of the plurality of second pixel units 302. The greater the distribution density of the pixel units 30, the greater the pixel density of the display panel 100. Thus, the pixel density of the main display area A1 in the display panel 100 is greater than the pixel density of the auxiliary display area A2.

[0083] In addition, the second pixel unit 302 will block the light incident on the optical element 200 through the secondary display area A2 of the display panel 100, making it almost impossible for the light to pass through. The distribution density of the multiple first pixel units 301 is set to be greater than the distribution density of the multiple second pixel units 302, so that the area occupied by the multiple second pixel units 302 is smaller, so that the light blocked by the second pixel units 302 can be relatively less, and the part of the substrate 10 located between two adjacent second pixel units 302 (it can be understood that the transmittance of this part to external light is greater than the transmittance of the second pixel unit 302 to light) has a larger area, and more light is incident on the optical element 200 after passing through this part in the secondary display area A2, ensuring that the optical element 200 can work normally.

[0084] Exemplarily, the distribution density of the first pixel unit 301 may also be less than or equal to the distribution density of the second pixel unit 302 , thereby making the pixel density of the secondary display area A2 higher, which is beneficial to improving the display quality of the secondary display area A2 of the display panel 100 .

[0085] 5 , the display panel 100 further includes a plurality of openings 20. The plurality of openings 20 at least penetrate the substrate 10. The plurality of openings 20 are located in the auxiliary display area A2.

[0086] For example, a plurality of openings 20 penetrate the substrate 10 from the pixel unit layer, and the openings 20 extend through the entire display panel 100, forming a hollow area of ​​the display panel 100. External light can be incident on the optical element 200 through the plurality of openings 20, that is, directly incident on the optical element 200 through the space within the openings 20. Therefore, compared with the path of external light passing through the substrate between two adjacent second pixel units 302 and then incident on the optical element 200, the light transmittance of the secondary display area A2 can be further improved by entering the optical element 200 through the openings 20, so that the optical element 200 can collect enough light, ensuring that the optical element 200 uses the light to work normally and improving the performance of the optical element 200, for example, making the camera take clearer and having better photographic effects.

[0087] At least one of the plurality of openings 20 is surrounded by a plurality of second pixel units 302. The orthographic projections of the plurality of openings 20 on the substrate 10 do not overlap with the orthographic projections of the plurality of second pixel units 302 on the substrate 10. For example, among the plurality of openings 20, the opening 20 near the boundary line of the auxiliary display area A2 is also surrounded by a plurality of first pixel units 301. However, among the plurality of openings 20, the opening 20 located roughly in the middle of the auxiliary display area A2 is only surrounded by a plurality of second pixel units 302. The orthographic projections of the plurality of openings 20 on the substrate 10 do not overlap with the orthographic projections of the plurality of second pixel units 302 on the substrate 10.

[0088] For example, the opening 20 may be surrounded by at least one sidewall, wherein the sidewall of the opening 20 is perpendicular or substantially perpendicular to the plane of the substrate 10. The sidewall of the opening 20 has a certain height. The height here refers to the dimension of the sidewall of the opening 20 along the thickness direction of the substrate 10.

[0089] The shapes of the plurality of openings 20 are various and can be selected and set according to actual needs.

[0090] For example, as shown in FIG5 , the orthographic projection of the opening 20 on the plane of the substrate 10 can be substantially in the shape of a cross, and the opening 20 has a plurality of connected sidewalls, wherein the angle between two connected sidewalls is a right angle or a substantially right angle. This facilitates the preparation of the opening 20 and helps simplify the preparation process of the display panel 100 and the display device 1000.

[0091] As another example, as shown in Figure 6, the boundary line of the orthographic projection of the opening 20 onto the plane of the substrate 10 is jagged. This arrangement reduces the probability of external light interfering with or diffracting the sidewalls of the opening 20 as it passes through the opening 20 to the optical element 200, thereby preventing interference or diffracted light from entering the camera and affecting image quality.

[0092] The shapes of the orthographic projections of the plurality of openings 20 on the plane of the substrate 10 may be the same or different. For example, the shapes of the plurality of openings 20 away from the boundary line of the auxiliary display area A2 may be different from the shapes of the plurality of openings 20 close to the boundary line of the auxiliary display area A2.

[0093] Some embodiments of the present disclosure provide a display panel 100, wherein the display panel 100 is provided with a main display area A1 and a sub-display area A2 located on at least one side of the main display area A1. The display panel 100 includes a substrate 10 and a plurality of pixel units 30 located on the substrate 10. A first pixel unit 301 is provided in the main display area A1, a second pixel unit 302 is provided in the sub-display area A2, and the transmittance of the main display area A1 is less than the transmittance of the sub-display area A2. The present disclosure also provides a display panel 100 including multiple openings 20 passing through the substrate 10, and the multiple openings 20 are located in the secondary display area A2. A plurality of second pixel units 302 are arranged around the openings 20, so that the light from the outside world incident from the secondary display area A2 directly passes through the multiple openings 20 and enters the optical element 200, rather than passing through multiple solid film layers (such as the substrate 10 and other film layers), effectively reducing the loss of light in the process of passing through the solid film layer, so that the transmittance of the secondary display area A2 is further increased. Therefore, when the display panel 100 is applied to the display device 1000, the light intensity of the light reaching the optical element 200 is greater, and more light reaches the optical element 200, thereby ensuring the normal operation of the optical element 200.

[0094] In some examples, as shown in FIG7 , the substrate 10 includes a first sub-substrate 11 and a second sub-substrate 12. The first sub-substrate 11 and the second sub-substrate 12 are connected. The first sub-substrate 11 is located in the main display area A1, and the second sub-substrate 12 is located in the auxiliary display area A2.

[0095] A plurality of first pixel units 301 are located on the first sub-substrate 11 .

[0096] The second sub-substrate 12 includes a plurality of island portions 13 and a plurality of bridge portions 14. For example, the area of ​​the island portion 13 is larger than the area of ​​the bridge portion 14. The areas of the island portions 13 and the areas of the bridge portions 14 may be substantially equal.

[0097] Multiple islands 13 are arranged in multiple rows and columns. Each island 13 is provided with at least one second pixel unit 302. Multiple bridges 14 are located between multiple islands 13 in the same row and between multiple islands 13 in the same column. Two adjacent islands 13 are connected by the bridges 14.

[0098] Of course, the bridge portion 14 near the boundary of the auxiliary display area A2 is also connected to the first sub-substrate 11 , and the island portion 13 near the boundary of the auxiliary display area A2 may also be directly connected to the first sub-substrate 11 .

[0099] As shown in Figures 5 and 7 , at least one opening 20 is surrounded by multiple islands 13 and multiple bridges 14. For example, the islands 13 and bridges 14 connected in sequence form a portion of the sidewall of the opening 20. For the opening 20 near the auxiliary display area A2, the first sub-substrate 11 is also arranged around the opening 20, forming a portion of the sidewall of the opening 20.

[0100] The plurality of second pixel units 302 are arranged around the opening 20 , and external light can pass through the auxiliary display area A2 through the opening 20 . The plurality of second pixel units 302 can also realize the display function of the auxiliary display area A2 .

[0101] The pixel units 30 described above constitute subpixels of the display panel 100. Multiple pixel units 30 constitute multiple subpixels of the display panel 100, and the multiple subpixels include multiple red subpixels, multiple green subpixels, and multiple blue subpixels. A red subpixel refers to a subpixel that emits red light, a green subpixel refers to a subpixel that emits green light, and a blue subpixel refers to a subpixel that emits blue light. For example, three pixel units 30 can be provided on one island portion 13, and the three pixel units 30 can be one red subpixel, one green subpixel, and one blue subpixel. Alternatively, four pixel units 30 can be provided on one island portion 13, and the four pixel units 30 can be two green subpixels, one red subpixel, and one blue subpixel.

[0102] Adjacent red sub-pixels, blue sub-pixels, and green sub-pixels constitute pixels of the display panel 100 , and the light emitted by the multiple pixels cooperates with each other to form a display image of the display panel 100 .

[0103] As shown in FIG8 , the pixel unit 30 includes a pixel circuit 31 and a light emitting device 32 . The pixel circuit 31 and the light emitting device 32 are electrically connected, and the light emitting device 32 emits light under a signal provided by the pixel circuit 31 .

[0104] The pixel circuit 31 has various structures, which can be selected based on actual needs. For example, the pixel circuit 31 may have a structure such as "6T1C," "7T1C," "6T2C," or "7T2C." Here, "T" represents a transistor, and the number preceding "T" represents the number of transistors. "C" represents a storage capacitor, and the number preceding "C" represents the number of storage capacitors.

[0105] For example, the present disclosure uses the "7T1C" structure of the pixel circuit 31 as an example for description. FIG9 shows an equivalent circuit diagram of a sub-pixel.

[0106] Exemplarily, as shown in FIG9 , the pixel circuit 31 includes: a first reset transistor T1 , a compensation transistor T2 , a driving transistor T3 , a switch transistor T4 , a first emission control transistor T5 , a second emission control transistor T6 , a second reset transistor T7 and a storage capacitor Cst.

[0107] For example, as shown in FIG9 , the control electrode of the second reset transistor T7 is electrically connected to the reset signal terminal Reset, the first electrode of the second reset transistor T7 is electrically connected to the first initial signal terminal Vinit1, and the second electrode of the second reset transistor T7 is electrically connected to the first node N1 (i.e., electrically connected to the second electrode of the compensation transistor T2). The second reset transistor T7 is configured to be turned on under the control of the reset signal provided by the reset signal terminal Reset, and transmit the first initial signal received from the first initial signal terminal Vinit1 to the first node N1, thereby resetting the first node N1.

[0108] For example, as shown in FIG9 , the control electrode of the first reset transistor T1 is electrically connected to the first scan signal terminal Scan1, the first electrode of the first reset transistor T1 is electrically connected to the second initial signal terminal Vinit2, and the second electrode of the first reset transistor T1 is electrically connected to the fourth node N4. The first reset transistor T1 is configured to be turned on under the control of the scan signal provided by the first scan signal terminal Scan1, transmit the second initial signal received from the second initial signal terminal Vinit2 to the fourth node N4, and reset the fourth node N4.

[0109] For example, as shown in FIG9 , the control electrode of the switching transistor T4 is electrically connected to the first scan signal terminal Scan1, the first electrode of the switching transistor T4 is electrically connected to the data line Data, and the second electrode of the switching transistor T4 is electrically connected to the second node N2. The switching transistor T4 is configured to be turned on under the control of the scan signal provided by the first scan signal terminal Scan1, and transmit the data signal transmitted by the data line Data to the second node N2.

[0110] 9 , the control electrode of the driving transistor T3 is electrically connected to the first node N1, the first electrode of the driving transistor T3 is electrically connected to the second node N2, and the second electrode of the driving transistor T3 is electrically connected to the third node N3. The driving transistor T3 is configured to be turned on under the control of the voltage of the first node N1 and transmit a signal (e.g., a data signal) from the second node N2 to the third node N3.

[0111] For example, as shown in FIG9 , the control electrode of the compensation transistor T2 is electrically connected to the first scan signal terminal Scan1, the first electrode of the compensation transistor T2 is electrically connected to the third node N3, and the second electrode of the compensation transistor T2 is electrically connected to the first node N1. The compensation transistor T2 is configured to be turned on under the control of the scan signal provided by the first scan signal terminal Scan1, and transmit a signal (e.g., a data signal) from the third node N3 to the first node N1.

[0112] For example, as shown in FIG9 , a control electrode of the first emission control transistor T5 is electrically connected to the enable signal terminal EM, a first electrode of the first emission control transistor T5 is electrically connected to the first voltage signal terminal VDD, and a second electrode of the first emission control transistor T5 is electrically connected to the second node N2. The first emission control transistor T5 is configured to be turned on under the control of an enable signal provided by the enable signal terminal EM, and to transmit a voltage signal received from the first voltage signal terminal VDD to the second node N2.

[0113] For example, as shown in FIG9 , a control electrode of the second light-emitting control transistor T6 is electrically connected to the enable signal terminal EM, a first electrode of the second light-emitting control transistor T6 is electrically connected to the third node N3, and a second electrode of the second light-emitting control transistor T6 is electrically connected to the fourth node N4. The second light-emitting control transistor T6 is configured to be turned on under the control of an enable signal provided by the enable signal terminal EM, and transmit the voltage signal from the third node N3 to the fourth node N4.

[0114] Exemplarily, as shown in FIG9 , a first electrode of the storage capacitor Cst is electrically connected to the first node N1 , and a second electrode of the storage capacitor Cst is electrically connected to the first voltage signal terminal VDD.

[0115] One end of the light emitting device 32 (eg, the second electrode of the light emitting device 32 mentioned below) is electrically connected to the fourth node N4, and the other end (eg, the first electrode of the light emitting device 32 mentioned below) is electrically connected to the common voltage terminal VSS.

[0116] The above description is based on an example in which all transistors in the pixel circuit 31 are LTPS (Low Temperature Poly-Silicon) transistors.

[0117] Of course, the compensation transistor T2 and the second reset transistor T7 in the pixel circuit 31 can be LTPO (Low Temperature Polycrystalline Oxide) transistors, and the remaining transistors can be LTPS transistors. In this case, the equivalent circuit of the pixel circuit 31 is shown in FIG10 , which differs from the equivalent circuit of FIG9 in that the control electrode of the compensation transistor T2 is electrically connected to the second scan signal terminal Scan2 , and the scan signal provided by the second scan signal terminal Scan2 is different from the scan signal provided by the first scan signal terminal Scan1 .

[0118] In some embodiments, as shown in FIG8 , the first pixel unit 301 includes a first pixel circuit 311, and the second pixel unit 302 includes a second pixel circuit 321. The pixel circuit 31 includes the first pixel circuit 311 and the second pixel circuit 321. The structure of the first pixel circuit 311 and the structure of the second pixel circuit 321 can be the same, for example, both have the aforementioned "7T1C" structure, thereby simplifying the manufacturing process of the pixel circuit 31.

[0119] 5 , the island 13 may have multiple second pixel units 302. In the multiple islands 13 in the same row, the second pixel circuits 321 of the multiple second pixel units 302 on each island 13 are arranged in the same row.

[0120] In the plurality of islands 13 located in the same column, the second pixel circuits 321 of the plurality of second pixel units 302 on each island 13 are arranged in the same column.

[0121] For example, in FIG. 5 , the first direction X is the row direction, the second direction Y is the column direction, and the third direction Z is the direction of the thickness of the substrate 10 .

[0122] Thus, the plurality of second pixel circuits 321 located in the auxiliary display area A2 are arranged in multiple rows and columns, so that the plurality of second pixel circuits 321 are arranged more regularly, which is beneficial to simplify the layout design of the second pixel circuits 321 and the display panel 100 .

[0123] For example, as shown in FIG11 , the plurality of pixel circuits 31 of the plurality of pixel units 30 are arranged in a plurality of rows. The plurality of rows of pixel circuits 31 include a plurality of first-type pixel circuit rows 33. The first-type pixel circuit rows 33 include a plurality of first pixel circuits 311 and a plurality of second pixel circuits 321. Furthermore, along the row direction, the plurality of first pixel circuits 311 of the first-type pixel circuit rows 33 are located on opposite sides of the secondary display area A2. The first-type pixel circuit rows 33 extend from the primary display area A1 through the secondary display area A2.

[0124] As shown in FIG11 , the display panel 100 further includes first-type signal lines 40 electrically connected to each pixel circuit 31 in the first-type pixel circuit row 33. The first-type signal lines 40 may extend along a first direction X, which may be the row direction of the plurality of rows of pixel circuits 31. The first-type signal lines 40 are used to transmit signals to each pixel circuit 31 in the first-type pixel circuit row 33.

[0125] Along the row direction, the first signal line 40 runs from the main display area A1, passes through the islands 13 where the second pixel circuits 321 of the first pixel circuit row 33 are located, and the bridges 14 arranged along the islands 13, and penetrates the auxiliary display area A2.

[0126] For example, the portion of the first-type signal line 40 that passes through the plurality of islands 13 where the plurality of second pixel circuits 321 in the first-type pixel circuit row 33 are located overlaps with the second pixel circuits 321 on the plurality of islands 13. This facilitates electrical connection between the first-type signal line 40 and the second pixel circuits 321 in the first-type pixel circuit row 33.

[0127] By adopting the above-mentioned setting method, each pixel circuit 31 in the first-type pixel circuit row 33 can also be connected to the same first-type signal line 40, so that the difference in the signals transmitted by the first-type signal line 40 received by multiple pixel circuits 31 in the same row is small, which is beneficial to reducing the difference in the display images of the main display area A1 and the auxiliary display area A2 of the display panel 100, and improving the display effect of the display panel 100.

[0128] Moreover, a portion of the first-type signal line 40 passes through the multiple island portions 13 where the multiple second pixel circuits 321 of the first-type pixel circuit row 33 are located, and the multiple bridge portions 14 arranged in the same row as the multiple island portions 13, so that the size of the first-type signal line 40 can be shortened, which is beneficial to saving the preparation cost of the first-type signal line 40.

[0129] In addition, the first type signal line 40 passes through the secondary display area A2 through multiple island portions 13 and bridge portions 14, which can avoid the first type signal line 40 covering or blocking the opening 20, ensuring that the secondary display area A2 has a higher light transmittance, thereby ensuring that the optical element 200 can collect more light and ensure that the optical element 200 works normally.

[0130] In some examples, as shown in FIG11 , the plurality of rows of pixel circuits 31 further include a plurality of second-type pixel circuit rows 34. The second-type pixel circuit rows 34 include a plurality of first pixel circuits 311. Along the row direction, the plurality of first pixel circuits 311 of the second-type pixel circuit rows 34 are located on opposite sides of the auxiliary display area A2.

[0131] The second-type pixel circuit row 34 does not include the second pixel circuit 321 .

[0132] In the column direction, at least one second-type pixel circuit row 34 is arranged between two adjacent first-type pixel circuit rows 33 .

[0133] For example, as shown in FIG11 , when the distribution density of the plurality of first pixel units 301 is relatively close to that of the plurality of second pixel units 302, a second-type pixel circuit row 34 is provided between two adjacent first-type pixel circuit rows 33 along the column direction. In this case, the orthographic projection area of ​​the opening 20 on the plane of the substrate 10 is relatively small. This allows for a relatively better display quality in the secondary display area A2 and improved display uniformity across the display area of ​​the display panel 100.

[0134] For another example, when the distribution density of the plurality of first pixel units 301 differs significantly from the distribution density of the plurality of second pixel units 302, a plurality of second-type pixel circuit rows 34 are provided between two adjacent first-type pixel circuit rows 33 along the column direction. In this case, the orthographic projection area of ​​the opening 20 on the plane of the substrate 10 is relatively large. This allows the secondary display area A2 of the display panel 100 to have a higher light transmittance, allowing the optical element 200 to collect more light, resulting in better photography.

[0135] 11 , the display panel 100 further includes a second type signal line 50 electrically connected to each pixel circuit 31 in the second type pixel circuit row 34. The second type signal line 50 extends substantially along the first direction X.

[0136] Along the row direction, the portion of the second-type signal line 50 near the auxiliary display area A2 winds along the boundary of the auxiliary display area A2 to the adjacent island portion 13 or bridge portion 14, passes through multiple island portions 13 and multiple bridge portions 14 arranged in the same row as the adjacent island portion 13 or bridge portion 14, and penetrates the auxiliary display area A2. The second-type signal line 50 passes through the island portion 13 where the second pixel circuit 321 is located in the row of the first pixel circuit 311, but is not connected to the second pixel circuit 321 on the island portion 13.

[0137] The second-type signal lines 50 run through the auxiliary display area A2, which can reduce the size of the second-type signal lines 50 and prevent the majority of the second-type signal lines 50 from extending along the boundary of the auxiliary display area A2, thereby increasing the length of the second-type signal lines 50. Furthermore, the second-type signal lines 50 run through the auxiliary display area A2 via the multiple island portions 13 and bridge portions 14, preventing the second-type signal lines 50 from covering or blocking the openings 20. This ensures that the auxiliary display area A2 has a high light transmittance, thereby ensuring that the optical element 200 can collect more light and ensures the normal operation of the optical element 200.

[0138] Exemplarily, as shown in FIG. 11 , the portion of the second-type signal line 50 located on the island portion 13 does not overlap with the second pixel circuit 321 located on the island portion 13 .

[0139] Since the second pixel circuit 321 on the island portion 13 is connected to the corresponding first-type signal line 40, and the first-type signal line 40 and the second pixel circuit 321 electrically connected thereto have an overlapping portion, the above-mentioned arrangement can make the distance between the portion of the first-type signal line 40 located on the island portion 13 and the portion of the second-type signal line 50 located on the island portion 13 relatively large, thereby ensuring the accuracy of the electrical signals transmitted by the first-type signal line 40 and the second-type signal line 50. Accordingly, the signals received by the first-type pixel circuit row 33 and the second-type pixel circuit row 34 are relatively accurate, so that the light-emitting devices 32 electrically connected thereto can be displayed normally, thereby making the display panel 100 have a better display effect, avoiding interference between the signals transmitted by the first-type signal line 40 and the signals transmitted by the second-type signal line 50 due to the small distance between the first-type signal line 40 and the second-type signal line 50, and avoiding the second-type signal line 50 from being mistakenly connected to the second pixel circuit 321 on the island portion 13.

[0140] For example, as shown in FIG11 , the portion of the second-type signal line 50 located on the island 13 is arranged along the boundary of the island 13, and a certain distance is maintained between the second-type signal line 50 and the boundary of the island 13. This allows for a more regular arrangement of the plurality of second-type signal lines 50, and a smaller area of ​​the island 13 occupied by the regularly arranged plurality of second-type signal lines 50, thereby facilitating the layout design of other structures on the island 13 (e.g., the first-type signal line 40, the second pixel circuit 321, etc.). Furthermore, in terms of the fabrication of the display panel 100 and the display device 1000, the above arrangement allows for a relatively smaller area of ​​the island 13 and a larger area of ​​the opening 20, thereby facilitating improved light transmittance in the secondary display area A2 of the display panel 100, allowing more light to enter the optical element 200 through the opening 20, thereby improving the image quality of the optical element 200, such as a camera.

[0141] For example, the signal transmitted by the first-type signal line 40 is the same as the signal transmitted by the second-type signal line 50. In addition, because both the first-type signal line 40 and the second-type signal line 50 run from the main display area A1 through the auxiliary display area A2, the signals transmitted by the first-type signal line 40 and the second-type signal line 50 can have substantially the same transmission path from the main display area A1 to the auxiliary display area A2. The loss of the signal transmitted by the first-type signal line 40 is substantially the same as the loss of the signal transmitted by the second-type signal line 50. This helps reduce the difference in signals received by the pixel circuits 31 in the first-type pixel circuit row 33 and the pixel circuits 31 in the second-type pixel circuit row 34, thereby improving the display effect of the display panel 100.

[0142] The first type signal line 40 includes at least one of a scan signal line, an enable signal line, and an initial signal line.

[0143] For example, the first type signal line 40 includes a scan signal line, an enable signal line, or an initial signal line.

[0144] For another example, the first type of signal lines 40 include scan signal lines and enable signal lines, or scan signal lines and initial signal lines.

[0145] For another example, the first type of signal lines 40 include scan signal lines, enable signal lines, and initial signal lines.

[0146] When the first type signal line 40 is a scan signal line, the first type signal line 40 can be electrically connected to the first scan signal terminal Scan1 or the second scan signal terminal Scan2 of the pixel circuit 31 to transmit a scan signal to the first scan signal terminal Scan1 or the second scan signal terminal Scan2.

[0147] In the case that the first-type signal line 40 is an enable signal line, the first-type signal line 40 may be electrically connected to the enable signal terminal EM of the pixel circuit 31 to transmit the enable signal to the enable signal terminal EM.

[0148] When the first type signal line 40 is the first initial signal line VinL (see FIG. 16 ), the first type signal line 40 may be electrically connected to the first initial signal terminal Vinit1 of the pixel circuit 31 and transmit the first initial signal to the first initial signal terminal Vinit1 .

[0149] In the case that the first-type signal line 40 is the second initial signal line, the first-type signal line 40 may be electrically connected to the second initial signal terminal Vinit2 of the pixel circuit 31 and transmit the second initial signal to the second initial signal terminal Vinit2.

[0150] Since the reset signal for the pixel circuits in one row is generally provided by the scanning signal line of the pixel circuits in the next row, the first type of signal line 40 here may also include a reset signal line. In the case where the first type of signal line 40 is a reset signal line, the first type of signal line 40 can be electrically connected to the reset signal terminal Reset of the pixel circuit 31 and transmit the reset signal to the reset signal terminal Reset.

[0151] 11 , the multiple rows of pixel circuits 31 further include multiple rows of third-type pixel circuits 35, each of which includes multiple first pixel circuits 311. The multiple first pixel circuits 311 in the third-type pixel circuit rows 35 are all located on the same side of the secondary display area A2 along the first direction X.

[0152] The display panel 100 further includes a sixth type signal line 51 electrically connected to the plurality of pixel circuits 31 in the third type pixel circuit row 35. The sixth type signal line 51 extends along the first direction X and is located in the main display area A1.

[0153] The signal transmitted by the sixth type signal line 51 is the same as the signal transmitted by the first type signal line 40 .

[0154] In some examples, as shown in FIG12 , the plurality of pixel circuits 31 of the plurality of pixel units 30 are arranged in a plurality of columns, and the plurality of pixel circuit columns 31 include a plurality of first-type pixel circuit columns 36. The first-type pixel circuit columns 36 include a plurality of first pixel circuits 311 and a plurality of second pixel circuits 321. Along the column direction, the plurality of first pixel circuits 311 of the first-type pixel circuit columns 36 are located on opposite sides of the auxiliary display area A2. The first-type pixel circuit columns 36 extend from the main display area A1 through the auxiliary display area A2.

[0155] As shown in FIG. 12 and FIG. 13 , the display panel 100 further includes a third-type signal line 60 electrically connected to each pixel circuit 31 in the first-type pixel circuit column 36 .

[0156] Along the column direction, the third signal line 60 runs from the main display area A1, passes through the islands 13 where the second pixel circuits 321 of the first pixel circuit column 36 are located, and the bridges 14 arranged in the same column as the islands 13, and penetrates the auxiliary display area A2.

[0157] For example, the portion of the third-type signal line 60 that passes through the plurality of islands 13 where the plurality of second pixel circuits 321 of the first-type pixel circuit column 36 are located overlaps with the second pixel circuits 321 on the plurality of islands 13. This facilitates electrical connection between the third-type signal line 60 and the second pixel circuits 321 in the first-type pixel circuit column 36.

[0158] By adopting the above-mentioned setting method, each pixel circuit 31 in the first-type pixel circuit column 36 can also be connected to the same third-type signal line 60, so that the difference in the signals transmitted by the third-type signal line 60 received by multiple pixel circuits 31 located in the same column is smaller, which is beneficial to reducing the difference in the display images of the main display area A1 and the auxiliary display area A2 of the display panel 100, and improving the display effect of the display panel 100.

[0159] Moreover, a portion of the third-type signal line 60 passes through the multiple island portions 13 where the multiple second pixel circuits 321 of the first-type pixel circuit column 36 are located, and the multiple bridge portions 14 arranged in the same column as the multiple island portions 13, which can make the size of the third-type signal line 60 shorter, which is beneficial to saving the preparation cost of the third-type signal line 60.

[0160] In addition, the third-type signal line 60 passes through the secondary display area A2 through multiple island portions 13 and bridge portions 14, which can avoid the third-type signal line 60 covering or blocking the opening 20, ensuring that the secondary display area A2 has a higher light transmittance, thereby ensuring that the optical element 200 can collect more light and ensure that the optical element 200 works normally.

[0161] 12 , the plurality of pixel circuit columns 31 further include a plurality of second-type pixel circuit columns 37. The second-type pixel circuit columns 37 include a plurality of first pixel circuits 311. Along the column direction, the plurality of first pixel circuits 311 of the second-type pixel circuit columns 37 are located on opposite sides of the auxiliary display area A2.

[0162] The second type pixel circuit column 37 does not include the second pixel circuit 321 .

[0163] Along the row direction, at least one second-type pixel circuit column 37 is disposed between two adjacent first-type pixel circuit columns 36 .

[0164] For example, when the distribution density of the plurality of first pixel units 301 is slightly different from the distribution density of the plurality of second pixel units 302, a second-type pixel circuit column 37 is disposed between two adjacent first-type pixel circuit columns 36 along the row direction. In this case, the orthographic projection area of ​​the opening 20 on the plane of the substrate 10 is relatively small, thereby achieving a relatively good display effect in the secondary display area A2 and improving display uniformity in the display area of ​​the display panel 100.

[0165] For another example, when the distribution density of the plurality of first pixel units 301 differs significantly from the distribution density of the plurality of second pixel units 302, a plurality of second-type pixel circuit columns 37 are disposed between two adjacent first-type pixel circuit columns 36 along the row direction. In this case, the orthographic projection area of ​​the opening 20 on the plane of the substrate 10 is relatively large. This allows the secondary display area A2 of the display panel 100 to have a higher light transmittance, allowing the optical element 200 to collect more light, resulting in better photography.

[0166] It is understandable that there are many ways to arrange the signal lines electrically connected to the second-type pixel circuit column 37 , and a selection can be made based on actual needs.

[0167] In some examples, as shown in FIG12 , the display panel 100 further includes a fourth type of signal line 70 electrically connected to each pixel circuit 31 in the second type of pixel circuit column 37 . The fourth type of signal line 70 extends substantially along the second direction Y. The second direction Y is the column direction of the plurality of columns of pixel circuits 31 . The first direction X and the second direction Y form an angle, which may be 90°.

[0168] Along the column direction, the portion of the fourth-type signal line 70 near the auxiliary display area A2 winds along the boundary of the auxiliary display area A2 to the adjacent island portion 13 or bridge portion 14. It then passes through multiple island portions 13 and multiple bridge portions 14 arranged in the same column as the adjacent island portion 13 or bridge portion 14, ultimately penetrating the auxiliary display area A2. The fourth-type signal line 70 passes through the island portion 13 where the second pixel circuit 321 is located in the column of the first pixel circuit 311, but is not connected to the second pixel circuit 321.

[0169] The fourth-type signal line 70 runs through the auxiliary display area A2, which can reduce the size of the fourth-type signal line 70. In addition, the fourth-type signal line 70 runs through the auxiliary display area A2 via the multiple island portions 13 and the bridge portion 14, which can prevent the fourth-type signal line 70 from covering or blocking the opening 20, ensuring that the auxiliary display area A2 has a high light transmittance, thereby ensuring that the optical element 200 can collect more light and ensure the normal operation of the optical element 200.

[0170] Illustratively, the portion of the fourth-type signal line 70 located on the island portion 13 does not overlap with the second pixel circuit 321 located on the island portion 13 .

[0171] Since the second pixel circuit 321 on the island portion 13 is connected to the corresponding third-type signal line 60, and the third-type signal line 60 and the second pixel circuit 321 electrically connected thereto have an overlapping portion, the above-mentioned arrangement can make the distance between the portion of the third-type signal line 60 located on the island portion 13 and the portion of the fourth-type signal line 70 located on the island portion 13 relatively large, thereby ensuring the accuracy of the signals transmitted by the third-type signal line 60 and the fourth-type signal line 70. Accordingly, the signals received by the first-type pixel circuit column 36 and the second-type pixel circuit column 37 are relatively accurate, so that the light-emitting device 32 electrically connected thereto can be displayed normally, thereby making the display panel 100 have a better display effect, avoiding interference between the signal transmitted by the third-type signal line 60 and the signal transmitted by the fourth-type signal line 70 due to the small distance between the third-type signal line 60 and the fourth-type signal line 70, and avoiding the fourth-type signal line 70 from being mistakenly connected to the second pixel circuit 321 on the island portion 13.

[0172] For example, as shown in FIG12 , the portion of the fourth-category signal line 70 located on the island 13 is arranged along the boundary of the island 13, and a certain distance is maintained between the fourth-category signal line 70 and the boundary of the island 13. This allows the arrangement of the plurality of fourth-category signal lines 70 to be more regular, and the area of ​​the island 13 occupied by the plurality of fourth-category signal lines 70 after regular arrangement is smaller, thereby facilitating the arrangement design of other structures on the island 13 (e.g., the third-category signal line 60, the second pixel circuit 321, etc.). Furthermore, in terms of the fabrication of the display panel 100 and the display device 1000, the above arrangement allows the area of ​​the island 13 to be designed to be relatively small, while the area of ​​the opening 20 to be designed to be larger, thereby facilitating improved light transmittance of the secondary display area A2 of the display panel 100, allowing more light to enter the optical element 200 through the opening 20, thereby improving the image quality of the optical element 200, such as a camera.

[0173] In other examples, as shown in FIG13 , the display panel 100 further includes a fourth type of signal line 70 electrically connected to each pixel circuit 31 in the second type of pixel circuit column 37. The fourth type of signal line 70 is located in the main display area A1.

[0174] Along the column direction, the portion of the fourth-category signal line 70 near the auxiliary display area A2 winds along the boundary of the auxiliary display area A2. The portion of the fourth-category signal line 70 near the auxiliary display area A2 winds from a first side of the auxiliary display area A2 along the boundary of the auxiliary display area A2 to a second side of the auxiliary display area A2. The first side and the second side of the auxiliary display area A2 are opposite sides of the auxiliary display area A2 along the row direction.

[0175] For example, the fourth-category signal line 70 includes a first sub-section 701, a second sub-section 702, and a third sub-section 703 connected in sequence, wherein the first sub-section 701 and the third sub-section 703 are approximately located in a straight line and are located on opposite sides of the auxiliary display area A2 along the first direction X. One end of the second sub-section 702 is connected to the first sub-section 701, and the other end of the second sub-section 702 runs along the boundary of the auxiliary display area A2, from one side of the auxiliary display area A2 along the first direction X, to the other side of the auxiliary display area A2 along the first direction X, and is connected to the third sub-section 703.

[0176] In the above-mentioned arrangement, the fourth type of signal line 70 is only located in the main display area A1, so that the number of signal lines arranged on the island portion 13 and the bridge portion 14 of the sub-display area A2 can be reduced. During the preparation of the display panel 100, the area of ​​the island portion 13 and the bridge portion 14 can be set to be relatively small, while the area of ​​the opening 20 can be set to be relatively large, so that more light enters the optical element 200 from the opening 20, which is beneficial to improving the image quality of the optical element 200 such as a camera.

[0177] For example, the signal transmitted by the third-type signal line 60 is identical to the signal transmitted by the fourth-type signal line 70. Furthermore, because both the third-type signal line 60 and the fourth-type signal line 70 run from the main display area A1 through the auxiliary display area A2, the signals transmitted by the third-type signal line 60 and the fourth-type signal line 70 have substantially the same transmission path from the main display area A1 to the auxiliary display area A2. The signal loss transmitted by the third-type signal line 60 is substantially the same as the signal loss transmitted by the fourth-type signal line 70. This helps reduce the difference in signals received by the pixel circuits 31 in the first-type pixel circuit column 36 and the pixel circuits 31 in the second-type pixel circuit column 37, thereby improving the display quality of the display panel 100.

[0178] The third type signal line 60 includes at least one of a data signal line DataL and a first voltage signal line VDDL. For example, the third type signal line 60 includes a data signal line or a first voltage signal line. For another example, the third type signal line 60 includes a data signal line and a first voltage signal line.

[0179] When the third-type signal line 60 is a data signal line DataL (see FIG. 18 ), the third-type signal line 60 is electrically connected to the data signal terminal Data of the pixel circuit 31 to transmit a data signal to the data signal terminal Data.

[0180] In the case where the third-type signal line 60 is a first voltage signal line, the third-type signal line 60 is electrically connected to the first voltage signal terminal VDD of the pixel circuit 31 , and transmits the first voltage signal to the first voltage signal terminal.

[0181] Of course, the fourth type signal line 70 may also include at least one of a data signal line DataL (refer to FIG. 19 and FIG. 20 ) and a first voltage signal line VDDL.

[0182] 12 , the plurality of pixel circuit columns 31 further include a plurality of third-type pixel circuit columns 38, each of which includes a plurality of first pixel circuits 311. The plurality of first pixel circuits 311 in the third-type pixel circuit columns 38 are all located on the same side of the auxiliary display area A2.

[0183] The display panel 100 further includes a seventh signal line 71 electrically connected to the plurality of pixel circuits 31 in the third pixel circuit row 35. The seventh signal line 71 extends along the second direction Y and is located in the main display area A1 (see FIG17 for details).

[0184] The signal transmitted by the seventh type signal line 71 is the same as the signal transmitted by the third type signal line 60 .

[0185] In some embodiments, as shown in FIG. 14 to FIG. 20 , the display panel 100 includes an active layer PL, a first conductive layer Gate1 , a second conductive layer Gate2 , a third conductive layer SD1 , and a fourth conductive layer SD2 sequentially disposed on one side of a substrate 10 .

[0186] FIG14 shows a top-down structure of the active layer PL. FIG15 shows a top-down structure of a stacked arrangement of the active layer PL and the first conductive layer Gate1. FIG16 shows a top-down structure of a stacked arrangement of the active layer PL, the first conductive layer Gate1, and the second conductive layer Gate2. FIG17 shows a top-down structure of the third conductive layer SD1. FIG18 shows a top-down structure of a stacked arrangement of the active layer PL, the first conductive layer Gate1, the second conductive layer Gate2, and the third conductive layer SD1. FIG19 shows a top-down structure of the fourth conductive layer SD2. FIG20 shows a top-down structure of a stacked arrangement of the active layer PL, the first conductive layer Gate1, the second conductive layer Gate2, the third conductive layer SD1, and the fourth conductive layer SD2.

[0187] It is understandable that, among the above-mentioned multiple film layers, an insulating layer (not shown in the figure) may be provided between any two adjacent film layers.

[0188] For example, the material of the active layer PL may include semiconductor materials such as amorphous silicon, single crystal silicon, and polycrystalline silicon.

[0189] For example, the materials of the first conductive layer Gate1, the second conductive layer Gate2, the third conductive layer SD1, and the fourth conductive layer SD2 are all conductive materials. The materials of the first conductive layer Gate1 and the second conductive layer Gate2 can be the same, and the materials of the third conductive layer SD1 and the fourth conductive layer SD2 can be the same.

[0190] For example, the conductive material may be a metal material, such as Al (aluminum), Ag (silver), Cu (copper), Cr (chromium), etc.

[0191] It should be noted that the orthographic projection of the active layer PL on the substrate 10 overlaps with the orthographic projection of the first conductive layer Gate1 on the substrate 10. After forming the first conductive layer Gate1 on the side of the active layer PL away from the substrate 10, the active layer PL can be doped using the first conductive layer Gate1 as a mask. This allows the portion of the active layer PL covered by the first conductive layer Gate1 to constitute the active pattern of some transistors, while the portion of the active layer PL not covered by the first conductive layer Gate1 constitutes a conductor, which can constitute the first or second electrode of some transistors. The portion where the first conductive layer Gate1 overlaps with the active layer PL constitutes the gate pattern of some transistors.

[0192] Of course, the above description of the display panel 100 is based on the case where all transistors in the pixel circuit 31 are LTPS transistors. In the case where the transistors in the pixel circuit 31 include LTPO transistors, the display panel 100 further includes: a second active layer PO and a fifth conductive layer Gate3, wherein the second active layer PO is located between the second conductive layer Gate2 and the third conductive layer SD1, and the fifth conductive layer Gate3 is located between the second active layer PO and the third conductive layer SD1.

[0193] For example, the material of the second active layer PO may include a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO for short).

[0194] For the convenience of description, the display panel 100 is introduced below on the assumption that all transistors in the pixel circuit 31 are LTPS transistors.

[0195] The first type signal lines 40 and the second type signal lines 50 may be located in the first conductive layer Gate1 or in the second conductive layer Gate2.

[0196] As shown in Figures 17 to 20, the portion of the fourth-type signal line 70 located in the main display area A1 is provided in the third conductive layer SD1, and the portion of the fourth-type signal line 70 located in the auxiliary display area A2 is provided in both the third conductive layer SD1 and the fourth conductive layer SD2. The third-type signal line 60 is located in the third conductive layer SD1.

[0197] As shown in FIG. 21 to FIG. 24 , the display panel 100 further includes a second electrode layer AND and a first electrode layer NL sequentially stacked on the fourth conductive layer SD2 .

[0198] A light emitting layer is further provided between the second electrode layer AND and the first electrode layer NL, and a pixel defining layer PDL is further provided between the second electrode layer AND and the light emitting layer.

[0199] Figure 21 shows a top-down structure of the second electrode layer AND. Figure 22 shows a top-down structure of the pixel definition layer PDL, wherein the box in Figure 22 indicates the location of the opening of the pixel definition layer PDL. Figure 23 shows a top-down structure of the active layer PL, the first conductive layer Gate1, the second conductive layer Gate2, the third conductive layer SD1, the fourth conductive layer SD2, the second electrode layer AND, and the pixel definition layer PDL. Figure 23 shows a top-down structure of the active layer PL, the first conductive layer Gate1, the second conductive layer Gate2, the third conductive layer SD1, the fourth conductive layer SD2, the second electrode layer AND, the pixel definition layer PDL, and the encapsulation layer ENL.

[0200] In some embodiments, the light emitting device 32 in the pixel unit 30 includes a first electrode, a light emitting layer, and a second electrode. The light emitting layer emits light under voltage provided by the first electrode and the second electrode. The first electrode is located in the first electrode layer NL, and the second electrode is located in the second electrode layer AND.

[0201] As shown in Figures 25 and 26 , the first pixel unit 301 further includes a first electrode pattern 322 located on a side of the first pixel circuit 311 away from the first sub-substrate 11. The first electrode pattern 322 constitutes a first electrode, such as a cathode, of the light-emitting device 32 in the first pixel unit 301. The first electrode pattern 322 is used to transmit a common voltage.

[0202] The plurality of first electrode patterns 322 are connected to form an integral structure. For example, there is no hollow portion between the plurality of first electrode patterns 322 in the integral structure.

[0203] The second pixel unit 302 further includes a second electrode pattern 323 located on a side of the second pixel circuit 321 away from the island 13. The second electrode pattern 323 constitutes a first electrode, such as a cathode, of the light emitting device 32 in the second pixel unit 302. The second electrode pattern 323 is also used to transmit a common voltage.

[0204] There are many ways to configure the second electrode pattern 323 in the second pixel unit 302 , and the configuration can be based on actual needs, which is not limited in the present disclosure.

[0205] In some examples, as shown in FIG. 25 , the display panel 100 further includes a connection pattern 324 on the bridge portion 14 .

[0206] When multiple second pixel units are disposed on the same island 13 , the multiple second electrode patterns 323 of the multiple pixel units on the same island 13 are interconnected to form an integrated structure. The second electrode patterns 323 on two adjacent islands 13 are connected via a connection pattern 324 .

[0207] In this way, the differences between the common voltages transmitted by the multiple second electrode patterns 323 can be reduced, so that the common voltages received by the light-emitting device 32 of each second pixel unit 302 are roughly the same, so that each second pixel unit 302 can emit light according to the preset brightness, thereby improving the display effect of the secondary display area A2 of the display panel 100.

[0208] The second electrode pattern 323 is also connected to the first electrode pattern 322. The second electrode pattern 323 can be directly connected to the first electrode pattern 322 near the boundary of the auxiliary display area A2, or can be connected to the first electrode pattern 322 via a connection pattern 324. Thus, signals can be uniformly provided to the second electrode pattern 323 and the first electrode pattern 322, so that the difference between the common voltages transmitted by the second electrode pattern 323 and the first electrode pattern 322 is small. This ensures that the common voltages received by the light-emitting device 32 of the second pixel unit 302 and the light-emitting device 32 of the first pixel unit 301 are substantially the same. As a result, both the first pixel unit 301 and the second pixel unit 302 can emit light at a preset brightness, thereby improving the display consistency between the main display area A1 and the auxiliary display area A2 of the display panel 100 and enhancing the display quality of the display panel 100 and the display device 1000.

[0209] Exemplarily, as shown in FIG. 24 and FIG. 27 , when the second electrode pattern 323 is connected to the connection pattern 322 and the first electrode pattern 322 , the display panel 100 further includes: a plurality of first barrier dam groups 81 located in the auxiliary display area A2 .

[0210] In FIG. 24 and FIG. 27 , for clarity, only the boundary lines 323L of the second electrode pattern 323 around the opening 20 are illustrated, and the connection pattern 322 and the second electrode pattern 323 are located between two adjacent boundary lines 323L.

[0211] One first barrier dam group 81 surrounds one opening 20 and is further located between the second pixel circuit 321 and the adjacent opening 20 .

[0212] A portion of the first barrier dam group 81 is located in the auxiliary display area A2 . This portion of the first barrier dam 80 is located on the island 13 and the bridge 14 and has a certain distance from the boundary lines of the island 13 and the bridge 14 .

[0213] The presence of the first barrier dam group 81 can prevent external water and oxygen from entering the island portion 13 or the bridge portion 14 from the side wall of the opening 20, thereby preventing the second pixel circuit 321 in the second pixel unit 302 on the island portion 13 from being corroded by water and oxygen and affecting its signal transmission, and preventing the light-emitting device corresponding to the second pixel circuit 321 from being corroded by water and oxygen and affecting its light-emitting life.

[0214] In the process of preparing the light-emitting layer and the second electrode pattern 323 after forming the first blocking dam group 81, it is generally necessary to first prepare a light-emitting film, which covers the second pixel circuit and the first blocking dam group 81, and then prepare a first electrode film on the light-emitting film. The light-emitting film and the first electrode film are both disconnected on the side of the first blocking dam group 81 away from the second pixel circuit to form the light-emitting layer and the second electrode pattern.

[0215] Furthermore, two first barrier dam groups 81 are disposed on one bridge portion 14 , and the connection pattern 322 is located on the bridge portion 14 and between the two first barrier dam groups 81 .

[0216] As shown in FIG. 24 , FIG. 27 and FIG. 28 , the first barrier dam group 81 includes at least one barrier dam 80 .

[0217] Exemplarily, as shown in FIG28 , the first barrier dam group 81 includes a barrier dam 80 , the dimension L1 of which in a direction perpendicular to its extending direction and in a direction from the adjacent opening 20 to the island portion may be 5 μm, 6 μm or 7 μm.

[0218] Exemplarily, the first barrier dam group 81 includes a plurality of barrier dams 80. The plurality of barrier dams 80 are concentrically arranged and spaced apart. Concentricity here means that the centers of the orthographic projections of the plurality of barrier dams 80 on the plane where the substrate 10 is located are the same.

[0219] As shown in FIG. 28 , there is a certain distance L2 between two adjacent barrier dams 80 , and the distance may be, for example, 2.5 μm, 3 μm, 3.5 μm, 4 μm or 5 μm.

[0220] For example, when the first barrier dam 80 includes two barrier dams 80, the spacing L2 between the two barrier dams 80 can be 5 μm, and the dimension L1 of each barrier dam 80 in a direction perpendicular to its extension direction and along the direction of the adjacent opening 20 pointing to the island structure can also be 5 μm.

[0221] For another example, when the first barrier dam 80 includes three barrier dams 80, the spacing L2 between any two adjacent barrier dams 80 among the three barrier dams 80 can be 3 μm, and the dimension L1 of each barrier dam 80 along a direction perpendicular to its extension direction and along the direction of the adjacent opening 20 pointing to the island structure can also be 3 μm.

[0222] It can be understood that a flat layer PLN is provided between the third conductive layer SD1 and the fourth conductive layer SD2 of the display panel, and a first passivation layer PVX1 is provided between the fourth conductive layer SD2 and the second electrode layer AND. The flat layer PLN and the first passivation layer PVX1 are located between the second pixel circuit and the opening (here refers to the area where the opening is to be formed, and the opening is prepared after the blocking dam is formed) and the portion thereof are etched to form a groove. The bottom of the groove is located inside the flat layer PLN, and the flat layer PLN and the first passivation layer PVX1 are located between two adjacent grooves to form a blocking dam 80 (refer to Figure 28, wherein the second passivation layer PVX2 is located on the side of the second electrode layer away from the substrate, and the interlayer dielectric layer ILD is located between the second conductive layer and the third conductive layer).

[0223] Therefore, the blocking dam 80 has a certain step difference relative to the groove. In the process of preparing the light-emitting device located on the island 13, the material of the first electrode layer will partially fall into the groove, and partially be located on the blocking dam 80. As a result, the materials of the first electrode layer in the groove and on the blocking dam 80 are disconnected, so that the formed second electrode pattern 323 is disconnected at the blocking dam 80.

[0224] In other examples, as shown in Figures 26, 33, and 34, when multiple second pixel units are provided on the same island 13, the multiple second electrode patterns 323 of the multiple pixel units on the same island 13 are interconnected to form an integrated structure. The second electrode patterns 323 on different islands 13 are provided independently of each other.

[0225] For example, the second electrode patterns 323 on two adjacent islands are disconnected from each other.

[0226] Exemplarily, when the second electrode patterns 323 on different islands 13 are independently arranged, as shown in FIG. 29 to FIG. 31 , the display panel 100 further includes a fifth type of signal line 90 .

[0227] The fifth type of signal line 90 includes at least one first sub-signal line 91 extending along the column direction, and a plurality of second sub-signal lines 92 extending along the row direction.

[0228] The first sub-signal line 91 may be located in the main display area A1. For example, when the fifth type signal line 90 includes two first sub-signal lines 91, the two first sub-signal lines 91 may be located on opposite sides of the auxiliary display area A2 along the first direction X.

[0229] The second sub-signal line 92 is located in the auxiliary display area A2 and extends through multiple islands 13 and multiple bridges 14 located in the same row to the main display area A1, where it connects to the first sub-signal line 91. The second sub-signal line 92 is also connected to the second electrode pattern 323 on each island 13 through which it passes. The fifth type of signal line 90 is used to transmit a common voltage signal to the second electrode pattern 323 on each island 13.

[0230] Illustratively, the first sub-signal line 91 , the second sub-signal line 92 and the second electrode pattern 323 are located in different layers.

[0231] For example, the first sub-signal line 91 is located in the third conductive layer SD1 , the second sub-signal line 92 is located in the first conductive layer Gate1 , and the second electrode pattern 323 is located in the first electrode layer NL.

[0232] For example, as shown in Figures 30-32, the fifth type of signal line 90 further includes a transfer pattern 93 located on the second electrode layer AND. The second sub-signal line 92 is electrically connected to the transfer pattern 93 via a via extending through the second conductive layer Gate2, the third conductive layer SD1, and the fourth conductive layer SD2. The transfer pattern 93 is electrically connected to the second electrode pattern 323 through the via. The second sub-signal line 92 is also electrically connected to the first sub-signal line 91 via a via extending through the second conductive layer Gate2.

[0233] Figure 29 shows another top-down structure of the first conductive layer Gate1. Figure 30 shows another top-down structure of the third conductive layer SD1. Figure 31 shows another top-down structure of the active layer PL, the first conductive layer Gate1, the second conductive layer Gate2, the third conductive layer SD1, and the fourth conductive layer SD2. Figure 32 shows another top-down structure of the second electrode layer AND. Figure 33 shows another top-down structure of the active layer PL, the first conductive layer Gate1, the second conductive layer Gate2, the third conductive layer SD1, the fourth conductive layer SD2, and the second electrode layer AND.

[0234] Exemplarily, as shown in FIG. 33 and FIG. 34 , the display panel 100 further includes a second barrier dam group 82 and a plurality of third barrier dam groups 83 located in the auxiliary display area A2 .

[0235] In FIG. 33 and FIG. 34 , for clarity, only the boundary line 323L of the second electrode pattern 323 around the opening 20 is illustrated, and the area enclosed by the boundary line 323L is the second electrode pattern 323 .

[0236] The second barrier dam set 82 is disposed along the boundary of the subsidiary display area A2 and surrounds the subsidiary display area A2.

[0237] One third barrier dam group 83 is located on one island 13 . The third barrier dam group 83 is disposed along the boundary of the corresponding island 13 and surrounds the second pixel unit 302 on the corresponding island 13 .

[0238] Exemplarily, the second barrier dam group 82 includes: at least one barrier dam 80 ; when the second barrier dam group 82 includes a plurality of barrier dams 80 , the plurality of barrier dams 80 are concentrically arranged and spaced apart.

[0239] The third barrier dam group 83 includes: at least one barrier dam 80; when the second barrier dam group 82 includes a plurality of barrier dams 80, the plurality of barrier dams 80 are concentrically arranged and spaced apart.

[0240] The boundary line 323L of the second electrode pattern may be located between two adjacent barrier dams 80 , or may substantially coincide with the outer boundary of the third barrier dam 83 .

[0241] It is understood that the manufacturing process of at least one barrier dam 80 in the second barrier dam group 82 and at least one barrier dam 80 in the third barrier dam group 83 can refer to the manufacturing process of at least one barrier dam 80 in the first barrier dam group 81. The dimensions of each barrier dam 80 in the second barrier dam group 82 and each barrier dam 80 in the third barrier dam group 83 can refer to the dimensions of the barrier dam 80 in the first barrier dam group 81, and will not be further described here.

[0242] As shown in FIG. 24 , FIG. 27 , FIG. 28 , FIG. 33 and FIG. 34 , the display panel 100 further includes an encapsulation layer ENL located on a side of the first electrode layer NL away from the substrate.

[0243] 24, 27, 33 and the top view of FIG34, only the boundary of the encapsulation layer ENL is shown for clarity. It is understood that, except for the opening 20, all other areas are covered by the encapsulation layer ENL.

[0244] For example, the encapsulation layer ENL can be a thin film encapsulation layer, which can encapsulate the above-mentioned pixel unit so that the pixel circuit 31 and the light-emitting device 32 are isolated from external water vapor, etc., thereby improving the luminous performance and luminous life of the light-emitting device 32, and avoiding the oxidation of the pixel circuit 31 and the light-emitting device 32 by water vapor when water vapor invades.

[0245] Compared with the barrier dam 80 and the boundary line 323L of the second electrode pattern located on the same side of the opening 20 , the distance between the boundary line of the encapsulation layer ENL and the opening 20 is the shortest.

[0246] The encapsulation layer ENL includes an inorganic encapsulation layer and an organic encapsulation layer. The inorganic encapsulation layer may include a first inorganic encapsulation layer ENL1 and a second inorganic encapsulation layer ENL3. The organic encapsulation layer ENL2 may be located between the first inorganic encapsulation layer ENL1 and the second inorganic encapsulation layer ENL3.

[0247] For example, the inorganic encapsulation layer can be made of an inorganic material and can be formed using a vapor deposition process. The organic encapsulation layer can be made of an organic material and can be formed using an inkjet printing process. The inorganic encapsulation layer can be made of an OC (Optical Clear) adhesive, which facilitates encapsulation of the pixel units on the island 13.

[0248] It can be understood that the organic encapsulation layer ENL2 is primarily used for planarization and stress relief, while the first and second inorganic encapsulation layers ENL1 and ENL3 of the inorganic encapsulation layer are primarily used to block water and oxygen, and to encapsulate the organic encapsulation layer ENL2 located between the first and second inorganic encapsulation layers ENL1 and ENL3. Taking the first barrier dam group 81 as an example, due to its certain height, the first barrier dam group 81 can be used to block the material of the organic encapsulation layer ENL2, so that the organic encapsulation layer ENL2 is within the area enclosed by the first barrier dam group 81, while the organic encapsulation layer ENL2 is not present outside the area enclosed by the first barrier dam group 81. The inorganic encapsulation layer covers the first barrier dam group 81.

[0249] The following briefly describes the formation of the opening 20 on the display panel 100. When the display panel 100 includes the connection pattern 324, after forming the first barrier dam group 81, a second electrode layer AND, a light-emitting layer, a first electrode layer NL, and an encapsulation layer ENL are sequentially formed on the side of the first barrier dam group 81 and the pixel circuit 31 away from the substrate 10. The encapsulation layer ENL, the first electrode layer NL, and the substrate 10 are then etched in the area where the opening is to be formed, forming the opening 20 that penetrates the display panel 100.

[0250] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel comprising a main display area and a secondary display area located at at least one side of the main display area; The display panel comprises: substrate; A plurality of pixel units located on one side of the substrate; the plurality of pixel units include: a plurality of first pixel units and a plurality of second pixel units; the plurality of first pixel units are located in the main display area, and the plurality of second pixel units are located in the auxiliary display area; the transmittance of the main display area is less than the transmittance of the auxiliary display area; At least a plurality of openings pass through the substrate; the plurality of openings are located in the secondary display area, and a plurality of the second pixel units are arranged around at least one of the plurality of openings, and the orthographic projections of the plurality of openings on the substrate do not overlap with the orthographic projections of the plurality of second pixel units on the substrate.

2. The display panel according to claim 1, wherein: The substrate comprises: a first sub-substrate located in the main display area, and a second sub-substrate located in the auxiliary display area; the first sub-substrate and the second sub-substrate are connected; the plurality of first pixel units are located on the first sub-substrate; The second sub-substrate comprises: A plurality of islands are arranged in a plurality of rows and columns; at least one second pixel unit is disposed on each island; A plurality of bridging portions are located between a plurality of island portions in the same row and between a plurality of island portions in the same column; two adjacent island portions are connected by the bridging portion; and a plurality of the island portions and the bridging portions are arranged around the at least one opening.

3. The display panel according to claim 2, wherein: The pixel unit includes a pixel circuit, the first pixel unit includes a first pixel circuit, and the second pixel unit includes a second pixel circuit; The plurality of pixel circuits of the plurality of pixel units are arranged into a plurality of rows, the plurality of rows of pixel circuits comprising a plurality of first-type pixel circuit rows; the first-type pixel circuit rows comprising a plurality of the first pixel circuits and a plurality of the second pixel circuits; Along the row direction, a plurality of the first pixel circuits of the first type pixel circuit row are located at two opposite sides of the auxiliary display area; The display panel further comprises: a first type of signal line electrically connected to each pixel circuit in the first type of pixel circuit row; Along the row direction, the first type of signal line passes through the main display area, through multiple islands where multiple second pixel circuits of the first type of pixel circuit row are located, and multiple bridges arranged in the same row as the multiple islands, and penetrates the sub-display area.

4. The display panel according to claim 3, wherein: The plurality of rows of pixel circuits further include a plurality of rows of second-type pixel circuits; the rows of the second-type pixel circuits include a plurality of the first-type pixel circuits, and along the row direction, the plurality of the first-type pixel circuits of the rows of the second-type pixel circuits are located at opposite sides of the secondary display area; along the column direction, at least one row of the second-type pixel circuits is arranged between two adjacent rows of the first-type pixel circuits; The display panel further comprises: a second type of signal line electrically connected to each pixel circuit in the second type of pixel circuit row; Along the row direction, the portion of the second type of signal line close to the auxiliary display area is wound along the boundary of the auxiliary display area to an adjacent island portion or a bridge portion, and passes through multiple island portions and multiple bridge portions arranged in the same row as the adjacent island portion or bridge portion, and penetrates the auxiliary display area.

5. The display panel according to claim 4, wherein: The portion of the second-type signal line located on the island portion is arranged in a winding manner along the boundary of the island portion.

6. The display panel according to claim 4 or 5, wherein: A portion of the second-type signal line located on the island portion does not overlap with a second pixel circuit located on the island portion.

7. The display panel according to any one of claims 4 to 6, wherein: The signal transmitted by the first type of signal line is the same as the signal transmitted by the second type of signal line.

8. The display panel according to any one of claims 3 to 7, wherein: The first type of signal lines include at least one of scan signal lines, enable signal lines and initial signal lines.

9. The display panel according to any one of claims 2 to 8, wherein: There are multiple second pixel units arranged on the island portion; among the multiple island portions located in the same row, the second pixel circuits of the multiple second pixel units on each of the island portions are arranged in the same row.

10. The display panel according to any one of claims 2 to 9, wherein: The pixel unit includes a pixel circuit, the first pixel unit includes a first pixel circuit, and the second pixel unit includes a second pixel circuit; The plurality of pixel circuits of the plurality of pixel units are arranged into a plurality of columns, the plurality of columns of pixel circuits comprising a plurality of first-type pixel circuit columns; the first-type pixel circuit columns comprising a plurality of the first pixel circuits and a plurality of the second pixel circuits; Along the column direction, a plurality of the first pixel circuits of the first type pixel circuit column are located at two opposite sides of the auxiliary display area; The display panel further comprises: a third type of signal line electrically connected to each pixel circuit in the first type of pixel circuit column; Along the column direction, the third type signal line passes through the auxiliary display area from the main display area, through multiple islands where multiple second pixel circuits of the first type pixel circuit column are located, and multiple bridges arranged in the same column as the multiple islands.

11. The display panel according to claim 10, wherein: The plurality of columns of pixel circuits further include a plurality of second-type pixel circuit columns; the second-type pixel circuit columns include a plurality of the first pixel circuits, and along the column direction, the plurality of the first pixel circuits of the second-type pixel circuit columns are located at opposite sides of the auxiliary display area; along the row direction, at least one second-type pixel circuit column is arranged between two adjacent first-type pixel circuit columns; The display panel further comprises: a fourth type of signal line electrically connected to each pixel circuit in the second type of pixel circuit column; Along the column direction, the portion of the fourth type signal line close to the auxiliary display area is wound along the boundary of the auxiliary display area to an adjacent island portion or a bridge portion, and passes through a plurality of island portions and a plurality of bridge portions arranged in the same column as the adjacent island portion or bridge portion, and penetrates the auxiliary display area.

12. The display panel according to claim 11, wherein: The portion of the fourth type signal line located on the island portion is arranged in a winding manner along the boundary of the island portion.

13. The display panel according to claim 11 or 12, wherein: A portion of the fourth-type signal line located on the island portion does not overlap with the second pixel circuit located on the island portion.

14. The display panel according to claim 10, wherein: The plurality of columns of pixel circuits further include a plurality of second-type pixel circuit columns; the second-type pixel circuit columns include a plurality of first pixel circuits, and along the column direction, the plurality of first pixel circuits of the second-type pixel circuit columns are located at opposite sides of the auxiliary display area; along the row direction, at least one second-type pixel circuit column is arranged between two adjacent first-type pixel circuit columns; The display panel further comprises: a fourth type of signal line electrically connected to each pixel circuit in the second type of pixel circuit column; the fourth type of signal line is located in the main display area; Along the column direction, a portion of the fourth type of signal line close to the auxiliary display area is wound from the first side of the auxiliary display area along the boundary of the auxiliary display area to the second side of the auxiliary display area; the first side of the auxiliary display area and the second side of the auxiliary display area are the opposite sides of the auxiliary display area along the row direction.

15. The display panel according to any one of claims 10 to 14, wherein: There are a plurality of second pixel units disposed on the island portion; and among the plurality of island portions located in the same column, the second pixel circuits of the plurality of second pixel units on each of the island portions are arranged in the same column.

16. The display panel according to any one of claims 10 to 14, wherein: The signal transmitted by the third type signal line is the same as the signal transmitted by the fourth type signal line.

17. The display panel according to any one of claims 10 to 16, wherein: The third type signal line includes at least one of a data signal line and a first voltage signal line.

18. The display panel according to any one of claims 2 to 17, wherein: The pixel unit includes a pixel circuit; The first pixel unit includes a first pixel circuit and a first electrode pattern located on a side of the first pixel circuit away from the first sub-substrate; a plurality of the first electrode patterns are connected and form an integrated structure; the second pixel unit includes a second pixel circuit and a second electrode pattern located on a side of the second pixel circuit away from the island; Among them, the second electrode patterns on different island portions are arranged independently of each other; or, the display panel includes a connecting pattern located on the bridging portion; the second electrode patterns on two adjacent island portions are connected through the connecting pattern; and the second electrode pattern is also connected to the first electrode pattern.

19. The display panel according to claim 18, wherein: In the case where the second electrode pattern is connected to the connection pattern and the first electrode pattern, the display panel further comprises: a plurality of first barrier dam groups located in the auxiliary display area; A first barrier dam group surrounds one of the openings; the first barrier dam group is also located between the second pixel circuit and the adjacent opening.

20. The display panel according to claim 19, wherein: The first barrier dam group includes: at least one barrier dam; when the first barrier dam group includes a plurality of barrier dams, the plurality of barrier dams are concentrically arranged and spaced apart.

21. The display panel according to claim 18, wherein: When the second electrode patterns on different islands are independently arranged, The display panel further includes: a fifth type of signal line, the fifth type of signal line being used to transmit a common voltage signal; The fifth type of signal lines includes: at least one first sub-signal line extending along the column direction, and a plurality of second sub-signal lines extending along the row direction; The first sub-signal line is located in the main display area; the second sub-signal line is located in the auxiliary display area and extends to the main display area through multiple island portions and multiple bridge portions located in the same row, and is connected to the first sub-signal line; the second sub-signal line is also connected to the second electrode pattern on each of the island portions it passes through.

22. The display panel according to claim 21, wherein: The first sub-signal line, the second sub-signal line and the second electrode pattern are located in different layers.

23. The display panel according to claim 21 or 22, wherein: The display panel further comprises: a second barrier dam group and a plurality of third barrier dam groups located in the auxiliary display area; The second barrier dam group is arranged along the boundary of the auxiliary display area and surrounds the auxiliary display area; A third barrier dam group is located on one of the islands. The third barrier dam group is arranged along the boundary of the corresponding island and surrounds the second pixel unit on the corresponding island.

24. The display panel according to claim 23, wherein: The second barrier dam group includes: at least one barrier dam; when the second barrier dam group includes a plurality of barrier dams, the plurality of barrier dams are arranged concentrically and at intervals; The third barrier dam group includes: at least one barrier dam; in the case where the second barrier dam group includes a plurality of barrier dams, the plurality of barrier dams are concentrically arranged and spaced apart.

25. A display device, wherein: The display device comprises: a display panel as claimed in any one of claims 1 to 24, and an optical element; The optical element is located on the non-light emitting side of the display panel and in the auxiliary display area of ​​the display panel.

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