Syndrome based decoding of a misaligned codeword

Abstract

A method for decoding includes, in a decoder 20 of an error correction code (ECC), receiving in a buffer 24 a codeword 50 of the ECC that contains multiple symbols, the codeword having a misalignment with one or both boundaries of the buffer. In the buffer, one or more bits that do not belong to the codeword are zeroed. One or more syndromes are calculated for the codeword across both the codeword and the zeroed bits. Based on the calculated syndromes, locations of one or more erroneous symbols are identified in the codeword, and the erroneous symbols are corrected in the identified locations to recover an error-free version of the codeword. The method further includes compensating for the misalignment between the codeword and the buffer, as part of calculating the syndromes or as part of identifying the locations of the erroneous symbols.

Description

[0001] SYNDROME BASED DECODING OF A MISALIGNED CODEWORD CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application 63 / 579,301, filed August 29, 2023, whose disclosure is incorporated herein by reference. TECHNICAL FIELD Embodiments described herein relate generally to error correction codes, and particularly to methods and systems for syndrome-based decoding of a misaligned codeword. BACKGROUND Various error correction codes, e.g., cyclic codes such as Bose–Chaudhuri– Hocquenghem (BCH) codes and Reed Solomon (RS) codes may be decoded using a syndrome decoding approach. BCH and RS codes have many applications, including high speed optical based networking. For example, an extended BCH(256,239) code serving as a component code in a product-like code referred to as Open FEC (OFEC) is specified in Annex E of the ITU-T G.709.3 / Y.1331.3 standard of June 22, 2018, which defines the flexible optical transport network (OTN), also known as FlexO. The same code as OFEC using the same component BCH(256,239) component codes is also specified, for example, by the Optical Internetworking Forum (OIF). SUMMARY An embodiment that is described herein provides a method for decoding, the method includes, in a decoder of an error correction code (ECC), receiving in a buffer a codeword of the ECC that contains multiple symbols, the codeword having a misalignment with one or both boundaries of the buffer. In the buffer, one or more bits that do not belong to the codeword are zeroed. One or more syndromes are calculated for the codeword across both the codeword and the zeroed bits. Based on the calculated syndromes, locations of one or more erroneous symbols are identified in the codeword, and the erroneous symbols are corrected in the identified locations to recover an error-free version of the codeword. The method further includes compensating for the misalignment between the codeword and the buffer, as part of calculating the syndromes or as part of identifying the locations of the erroneous symbols. In some embodiments, zeroing the bits includes zeroing a first number of symbols matching the trailing bits that follow the codeword in the buffer, thereby causing the syndromes to be cyclically shifted by the first number, and identifying the locations includes (i) compensating for the misalignment by cyclically shifting the syndromes back by the first number and then (ii) identifying the locations based on the cyclically-shifted syndromes. In other embodiments, zeroing the bits includes zeroing a first number of symbols matching the trailing bits that follow the codeword in the buffer, thereby causing the syndromes to be cyclically shifted by the first number, and identifying the locations by calculating the locations based on the cyclically-shifted syndromes, and then compensating for the misalignment by cyclically shifting the locations back by the first number. In yet other embodiments, zeroing the bits includes zeroing a second number of leading bits that precede the codeword in the buffer.

[0002] In an embodiment, receiving the codeword includes receiving the codeword in one or more chunks having a common length, and calculating the syndromes includes calculating the syndromes iteratively over the chunks. In another embodiment, calculating the syndromes iteratively includes calculating a given syndrome over multiple iterations using a common combinational circuit over the multiple chunks. In yet another embodiment, the ECC includes a cyclic code selected from a list including a Bose-Chaudhuri-Hocquenghem (BCH) code and a Reed Solomon code.

[0003] In some embodiments, the method includes: receiving (i) low-reliability bits (LRBs) indicative of bits in the codeword having low reliability levels, and (ii) a shift value corresponding to the misalignment, calculating from the codeword a test pattern using the LRBs, calculating shifted LRBs by cyclically shifting the LRBs depending on the shift value, deriving from the syndromes respective test pattern syndromes by modifying the syndromes based on the shifted LRBs, and hard decoding the test pattern using the test patern syndromes for recovering the error-free version of the codeword.

[0004] There is additionally provided, in accordance with an embodiment that is described herein, a decoder that includes a buffer and circuitry. The buffer is configured to receive a codeword of an error correction code (EC.C) that contains multiple symbols, the codeword having a misalignment with one or both boundaries of the buffer. The circuitry is configured to: zero, in the buffer, one or more bits that do not belong to the codeword, calculate one or more syndromes for the codeword across both the codeword and the zeroed bits, based on the calculated syndromes, identify locations of one or more erroneous symbols in the codeword, and correct the erroneous symbols in the identified locations to recover an error-free version of the codeword. The circuitry is further configured to compensate for the misalignment between the codeword and the buffer, as part of calculating the syndromes or as part of identifying the locations of the erroneous symbols. These and other embodiments will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

[0005] BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Fig. 1 is a block diagram that schematically illustrates a syndrome based error correction code (ECC) decoder that compensates for buffered codeword misalignment, in accordance with an embodiment that is described herein;

[0007] Figs. 2A and 2B are flow charts that schematically illustrate methods for compensating for codeword misalignment as part of calculating the syndromes and as part of identifying the locations of the erroneous symbols, in accordance with embodiments that are described herein;

[0008] Fig. 3 is a block diagram that schematically illustrates an ECC decoder that iteratively calculates syndromes over multiple chunks of a codeword and that compensates for codeword misalignment, in accordance with an embodiment that is described herein;

[0009] Fig. 4 is a block diagram that schematically illustrates an ECC decoder 150 for decoding an extended BCH code, in accordance with an embodiment that is described herein; and

[0010] Fig. 5 is a flow chart that schematically illustrates a method for soft decoding of a codeword that is misaligned to the buffer boundaries, in accordance with an embodiment that is described herein.

[0011] DETAILED DESCRIPTION OF EMBODIMENTS

[0012] OVERVIEW

[0013] Embodiments that are described herein provide improved methods and circuits for decoding BCH and other cyclic error correction codes, by efficiently calculating syndromes for a codeword that is misaligned to buffer boundaries. To this end, buffered bits not belonging to the codeword are masked to zero, and the codeword misalignment is compensated for as part of calculating the syndromes or as part of calculating locations of erroneous symbols.

[0014] The description that follows refers mainly to cyclic codes that are defined over a finite field. In the present context, the term “symbol” refers to an element of the finite field over which the underlying code is defined. Depending on the code, a symbol may have a single bit or multiple bits. An error correction code (ECC) defines a mapping between data messages and respective codewords of the ECC. Each codeword comprises a sequence of symbols (e.g., bits) and carries a data message plus redundant information.

[0015] A codeword of the ECC that is received over a noisy channel may contain erroneous symbols. The goal of the decoder is to recover the original message, by identifying a codeword of the ECC based on the received codeword. For example, the identified codeword may be a codeword of the ECC that is closest to the received codeword in accordance with a suitable distance measure (e.g., a hamming distance or a Euclidian distance).

[0016] In the present context and in the claims, the term “codeword" refers to either (i) a codeword of the ECC or (ii) a codeword that contains one or more erroneous symbols.

[0017] In some embodiments decoding a received codeword involves deriving from the codeword one or more syndromes. When all the syndromes equal zero, the received codeword is a codeword of the ECC. Otherwise, based on the syndromes, the decoder calculates locations of the erroneous symbols in the received codeword and the respective error values, and corrects the received codeword, accordingly.

[0018] Syndromes may be calculated in various ways. In one approach, a syndrome vector is calculated by multiplying the parity-check matrix of the underlying ECC by the received codeword. This method, however, is typically inefficient because it requires saving the complete parity-check matrix or calculating it on the fly. In another approach, the syndromes are calculated by considering the symbols of the received codeword as coefficients of a polynomial, and evaluating this polynomial over selected powers of a primitive element of a suitable finite field.

[0019] The received codeword is typically stored temporarily in a buffer of the decoder. The buffer may contain the full codeword, or a portion of the codeword (e.g., when the codeword is received in multiple chunks). In some implementations, the codeword (or part thereof) is misaligned to one or both boundaries of the buffer. This may occur, for example, when the length of the codeword is not a multiple of the buffer length, when the codeword length is smaller than the buffer length, when the input includes fields not belonging to the codeword, or due to the way the decoder synchronizes the reception of the codeword.

[0020] In principle, codeword misalignment could be handled using extra buffering and / or applying extra computations, which typically would result in large silicon area and in high power consumption. For example, when calculating the syndromes over multiple chunks of the codeword, different hardware circuits may be respectively tailored for the first chunk, middle chunks, and last chunk, and for different levels of codeword misalignment. In the disclosed embodiments, codeword misalignment to the buffer boundaries is compensated for as part of calculating the syndromes or as part of identifying the locations of the erroneous symbols. In a multi-chunk hardware implementation, due to the compensation for the misalignment, a common combinational logic circuit can be used across all chunks, which reduces silicon area and power consumption compared to using different circuits for different chunks.

[0021] Consider a method for decoding, the method includes: in a decoder of an error correction code (ECC), receiving in a buffer a codeword of the ECC that contains multiple symbols, the codeword having a misalignment with one or both boundaries of the buffer. One or more bits in the buffer that do not belong to the codeword are zeroed. Multiple syndromes are calculated for the codeword across both the codeword and the zeroed bits. Based on the calculated syndromes, locations of one or more erroneous symbols in the codeword are identified, and the erroneous symbols in the identified locations are corrected to recover an error-free version of the codeword. The method further includes compensating for the misalignment between the codeword and the buffer, as part of calculating the syndromes or as part of identifying the locations of the erroneous symbols.

[0022] In some embodiments, zeroing the bits comprises zeroing a first number of symbols matching the trailing bits that follow the codeword in the buffer, thereby causing the syndromes to be cyclically shifted by the first number. In one embodiment the locations are identified by (i) compensating for the misalignment by cyclically shifting the syndromes back by the first number and then (ii) identifying the locations based on the cyclically-shifted syndromes. In another embodiment, the locations are identified by calculating the locations based on the cyclically-shifted syndromes, and then compensating for the misalignment by cyclically shifting the locations back by the first number. In yet another embodiment, zeroing the bits comprises zeroing a second number of leading bits that precede the codeword in the buffer. In this embodiment the syndromes are not cyclically shifted.

[0023] In an embodiment, the codeword is received in one or more chunks having a common length, and the syndromes are calculated iteratively over the chunks. Moreover, a given syndrome is calculated over multiple iterations using a common combinational circuit over the multiple chunks. By sharing the same circuit across all the chunks, which incurs low- complexity hardware and low power consumptions.

[0024] The disclosed methods are applicable for decoding a cyclic code such as, for example, a Bose-Chaudhuri-Hocquenghem (BCH) code or a Reed Solomon code. The disclosed embodiments are also applicable to decoding codes that are related to cyclic codes such as, for example, extended cyclic codes.

[0025] In an embodiment the decoder decodes the received codeword using soft decoding methods. In this embodiment, the method includes: receiving, in addition to the codeword, (i) low-reliability bits (LRBs) indicative of bits in the codeword having low reliability levels, and (ii) a shift value corresponding to the misalignment, calculating shifted LRBs by cyclically shifting the LRBs depending on the shift value, deriving from the syndromes respective test pattern syndromes by modifying the syndromes based on the shifted LRBs, and decoding the test pattern using the test pattern syndromes for recovering the error-free version of the codeword.

[0026] In the disclosed techniques a codeword received and stored misallied to the decoder buffer. Bits in the buffer that do not belong to the codeword are zeroed, thereby causing the syndromes to be cyclically shifted by a shift value that equals the number of zeroed trailing bits (or the number of symbols that matches the trailing bits). The syndromes or the error locations are cyclically shifted back to compensate for the codeword misalignment. In implementations in which the codeword is received in multiple chunks, a common combinational logic circuit is used for calculating the syndrome cumulatively across all the chunks, thereby incurring small silicon area and low power consumption.

[0027] SYSTEM DESCRIPTION Fig. 1 is a block diagram that schematically illustrates a syndrome based ECC decoder

[0028] 20 that compensates for buffered codeword misalignment, in accordance with an embodiment that is described herein.

[0029] Decoder 20 may comprise, for example, a decoder for decoding cyclic codes such as a BCH code or a RS code. BCH codes may be used in various applications such as satellite and other communication systems, compact disc players, DVDs, disk drives, USB flash drives, solid-state drives, and two-dimensional bar codes. RS codes may be used in many applications, including consumer technologies such as MiniDiscs, CDs, DVDs, Blu-ray discs, QR codes, Data Matrix, data transmission technologies such as DSL and WiMAX, broadcast systems such as satellite communications, DVB and ATSC, and storage systems such as RAID 6.

[0030] Consider an ECC defined over a Galois Field GF(q), ‘q’ being a prime number, and a prime power qmwith ‘m’ being a positive integer. For a primitive BCH code, the codeword length ‘ n’ is given by n = qm— 1. In some embodiments, the decoder may calculate the syndromes by considering the received codeword as a polynomial R having coefficients (Z / , I = 0 ... n — 1 in GF(q), and evaluating R on certain powers of a primitive element α of GF(qm). In case of a binary code such as a BCH code, the coefficients alof R are bits having binary values ‘0’ and ‘1’. The number of syndromes required for the decoding a primitive BCH code is given by d-1, wherein ‘d’ denotes the minimal distance of the underlying code. The jthsyndrome, denoted Sj, is given by:

[0031] Equation 1:

[0032] In some embodiments the overall sum in Equation 1 can be divided into multiple partial sums, wherein each of the partial sums is calculated within one computational cycle (e.g., within a single clock cycle) using combinational logic.

[0033] In some embodiments the codeword represented by R is received in multiple chunks, each of which comprises ‘r' coefficients, 1 < r < n In addition, it is assumed that the chunks are received in a descending order of the powers of α. Consequently, the first chunk contains r coefficients corresponding to the highest powers of α, and the last chunk contains r coefficients corresponding to the lowest powers of α. In some embodiments the jthsyndrome can be calculated iteratively over the chunks, wherein in the first iteration the syndrome is given by:

[0034] Equation 2: and in subsequent iterations, the syndrome is updated as given by:

[0035] Equation 3: Alternatively, the syndrome may be initialized to zero, and calculated iteratively using Equation 3, starting with the first chunk (corresponding to the highest powers of α). In Equations 2 and 3, the +,values in the sums depend on the iteration number. A codeword (or part thereof) received for decoding is typically stored in a buffer before being processed. The description that follows refers mainly to situations in which the buffered codeword (or part thereof) is misaligned to the buffer boundaries. This means that the buffer contains one or more leading bits that precede the codeword, one or more trailing bits that follow the codeword, or both. It is noted that for an RS code, for low complexity implementation, the number of trailing bits may be chosen to be a multiple of the number of bits per symbol, in an embodiment. In some embodiments, to handle codeword misalignment, the decoder masks (forces to zero) buffered bits that do not belong to the codeword. Such masking, however, may result in cyclically shifted syndromes, and consequently also in cyclically shifted locations of the erroneous symbols, by the same amount. As will be described in detail below, in the disclosed embodiments, the decoder compensates for codeword misalignment that results in cyclically shifted syndromes. Decoder 20 comprises a buffer 24 and circuitry 28 that comprises a masking module 30, a syndrome calculator 34, an error calculator 38, an error corrector 42 and a timing module 46. Timing module 46 controls the input and output of data to and from buffer 24. In the example of Fig. 1, after an input cycle completes, buffer 24 contains a codeword 50 of the underlying ECC, leading bits 52 (denoted “LDb”) and trailing bits 54 (denoted TRb). The leading and trailing bits are not part of codeword 50. In alternative embodiments, the buffer may contain codeword 50 and only one of leading bits 52 and trailing bits 54. Although in the example of Fig. 1 buffer 24 contains a full codeword, in alternative embodiments, the length of the buffer may be shorter than the length of the codeword. In such embodiments, the input is divided into multiple chunks having the same length as buffer 24. A configuration of this sort will be described in detail with reference to Fig. 3 below. In some embodiments the decoder processes the buffer content for decoding codeword 50. For ignoring the leading and trailing bits in the buffer, masking module 30 applies a mask value 58 to the buffer content. The masking operation retains the codeword value and zeroes the leading and trailing bits that do not belong to the codeword. In the present context, the phrase “zero bits in the buffer” means that either the relevant bits in the buffer are zeroed, or the relevant bits are zeroed after being read from the buffer (without modifying the buffer content). In an embodiment, mask value 58 is generated by timing module 46. In some embodiments, the mask value corresponding to the leading and trailing bits is constant over time and can be hard-wired. Syndrome calculator 34 calculates the syndromes associated with codeword 50 by processing the entire buffer content. The syndrome calculation may be based, for example, on Equation 1 or on Equations 2 and 3 above. The effect of codeword misalignment will be described further below. Error calculator 38 receives the syndromes calculated by the syndrome calculator, and based on the syndromes determines the number of erroneous symbols in the codeword, the locations of the erroneous symbols in the codeword and the error values, using any suitable method. For example, the error calculator may produce a location polynomial corresponding to the erroneous symbols using the Berlekamp–Massey algorithm, wherein the roots of this polynomial correspond to the error locations. Error corrector 42 receives the error locations (e.g., in the form of indices in the codeword) and values from the error calculator, and corrects codeword 50 accordingly. Typically, the error corrector outputs an error-free version of codeword 50 (or a suitable indication when the decoding fails). A mis-correction event may occur, for example, when the underlying code is capable of correcting a small number of errors and the level of noise causing errors in the codeword is high. The misalignment of codeword 50 in buffer 24 due to one or more zeroed leading bits 52 in the buffer does not modify the correct syndrome value. The misalignment of codeword 50, due to zeroing a number D>0 of trailing bits 54 (In RS codes, an integer number D>0 of symbols matches the trailing bits, and zeroing means zeroing the integer number D>0 of the symbols matching the trailing bits), however, has the effect of shifting the correct syndrome value cyclically by D. In some embodiments, as will be described below with reference to Figs. 2A and 2B, the decoder compensates for codeword misalignment due to the trailing bits as part of calculating the syndromes or as part of identifying the locations of the erroneous symbols. To this end, timing module 46 provides a shift value D (that equals the number of trailing bits 54 or the number of trailing symbols) to the syndrome calculator or to the error calculator. In some embodiments decoder 20 supports decoding codeword 50 using soft decoding methods. In these embodiments, in addition to codeword 50, the decoder receives soft information 64, e.g., reliability levels that are respectively assigned to the symbols of codeword 50. In some embodiments, the decoder additionally receives or calculates one or more low-reliability bits (LRBs) that are indicative of the codeword symbols having the lowest reliability levels. Moreover, circuitry 28 comprises soft decoding logic 66 that handles the generation and decoding of test patterns 68 derived from codeword 50. Embodiments for ECC decoding using soft decoding will be described in detail with reference to Fig. 5 below. METHODS FOR COMPENSATING FOR CODEWORD MISALIGNMENT Figs. 2A and 2B are flow charts that schematically illustrate methods for compensating for codeword misalignment as part of calculating the syndromes and as part of identifying the locations of the erroneous symbols, in accordance with embodiments that are described herein. In describing the methods of Figs. 2A and 2B, the underlying codeword is assumed to be misaligned with the buffer boundaries due to one or more trailing bits following the codeword in the buffer. As a result of zeroing the trailing bits (or integer number of symbols matching the trailing bits), the syndromes are cyclically shifted by a shift value D that equals the number of trailing bits (or the integer number of symbols matching the trailing bits), and the error locations derived from the cyclically-shifted syndromes are also cyclically shifted by the same shift value D. The method of Fig. 2A begins with syndrome calculator 34 calculating syndromes over zeroed leading bits 52 (if any), codeword 50 and zeroed trailing bits 54, at a syndrome calculation step 80. As noted above, the resulting syndromes are cyclically shifted by a nonzero shift value D that equals the number of trailing bits (or integer number of symbols matching the trailing bits). At a compensation step 82, the syndrome calculator corrects the syndromes by cyclically shifting the syndromes back by the shift value D. At an error location calculation step 84, the error calculator identifies the correct locations of the erroneous symbols in the codeword based on the corrected syndromes of step 82. Following step 84 the method terminates. The method of Fig. 2B begins with syndrome calculator 34 calculating syndromes over zeroed leading bits 52 (if any), codeword 50 and zeroed trailing bits 54, at a syndrome calculation step 90. As noted above, the resulting syndromes are cyclically shifted by a nonzero shift value D that equals the number of trailing bits (or number of trailing symbols). Step 90 is essentially the same as step 80 of the method of fig. 2A. At an error location calculation step 92, the error calculator identifies locations of the erroneous symbols in the codeword based on the cyclically-shifted syndromes. At a locations correction step 94, the error locator corrects the error locations by cyclically shifting the error locations back by the shift value D. Following step 94 the method terminates. ITERATIVE SYNDROME CALCULATION

[0036] Fig. 3 is a block diagram that schematically illustrates an ECC decoder 100 that iteratively calculates syndromes over multiple chunks of a codeword and that compensates for codeword misalignment, in accordance with an embodiment that is described herein.

[0037] It is noted that the method of Fig. 3 focuses on iterative syndrome calculation, and functions carried out by decoder elements such as error calculator 38, error corrector 48, timing 46 and soft decoding logic 66 of Fig. 1 are omitted from Fig. 3 for the sake of clarity.

[0038] Decoder 100 receives input data in a sequence of chunks 104. For clarity, Fig. 3 depicts only three chunks, including a first chunk 104 A, a middle chunk 104B and a last chunk 104C. In the present example, codeword 50 spans all the chunks, wherein the last chunk contains a number D of trailing bits 54, and the first chunk optionally contains one or more leading bits 52.

[0039] Decoder 100 comprises a buffer 120, and circuitry 122 that comprises a masking module 124 and multiple iterative syndrome calculators 130. For the sake of clarity, Fig. 3 depicts only two iterative syndrome calculators - 130A for powders of αjand 130B for powders of αi, wherein for a primitive BCH code j and i are in the range 1 . . . d-1, and ‘d’ denotes the minimal distance of the code. In practical implementations, the decoder may comprise up to d- 1 different iterative syndrome calculators. The calculation of the error locations (calculated by error locator 38) is based on (d-1) syndromes. Typically, for a narrow sense primitive BCH code only syndromes of odd powers of α are calculated directly, whereas syndromes of even powers of a can be derived, with low complexity, from the odd-power syndromes. For RS codes and general BCH codes, the number of syndromes required is d-1=2t, wherein 't’ denotes the number of correctable errors.

[0040] In the example of Fig. 3, buffer 120 and chunks 104 share a common length (r of Equations 2 and 3) of 16 bits. Alternatively, other suitable buffer and chunk length can also be used.

[0041] The chunks are received and buffered over multiple iterations. For each iteration, masking module 124 masks the content of buffer 120 using a respective mask value. In the present example, mask value for the first chunk contains ‘0’ bits in locations of the leading bits and ‘ 1 ’ bits for the codeword part, the mask value for the middle chunk contains only ‘ 1 ’ bits, and the mask value for the last chunk contains ‘0’ bits in locations of the trailing bits and ‘ 1’ bits for the codeword part. Masking over the entire chunks has the effect of retaining the codeword and zeroing the leading bits and the trailing bits.

[0042] Each of the iterative syndrome calculators (e.g., 130A and 130B) calculates a syndrome value iteratively over the received chunks, for a dedicated power of the primitive element (X. The different iterative syndrome calculators have the same structure but differ by the internal circuits depending on the power of α. As an example of syndrome calculators 130, iterative syndrome calculator 130A is now described in detail.

[0043] Syndrome calculator I30A receives a masked result from masking module 124 per iteration (i.e., per chunk) and updates an incremental calculation of the syndrome.

[0044] Iterative syndrome calculator 130A comprises feed forward circuit 140, a bitwise logical XOR gate 142, a feedback circuit 146 and a syndrome buffer 148. The iterative syndrome calculator calculates the syndrome iteratively as given in Equation 3 above.

[0045] Specifically, the syndrome buffer holds the updated syndrome value Sj up to the current iteration, feed forward circuit 140 calculates the sum of the current iteration, the feedback circuit calculates the multiplication αrj· Sj, and the bitwise XOR gate calculates the A’ operation in Equation 3. In some embodiments, the iterative syndrome calculator calculates an updated syndrome per iteration (based on Equation 3) using combinational logic. For example, in an embodiment, since the powers of the primitive element are known and do not vary in time, the sum operation calculated by the feed forward circuit and the multiplication operation implemented by the feedback circuit can be implemented using combinational logic comprising logical XOR gates.

[0046] AN EXAMPLE ECC DECODER FOR AN EXTENDED BCH CODE

[0047] Fig. 4 is a block diagram that schematically illustrates an ECC decoder 150 for decoding an extended BCH code, in accordance with an embodiment that is described herein.

[0048] It is noted that functions carried out by decoder elements such as error calculator 38, error corrector 48, timing 46 and soft decoding logic 66 of Fig. 1 are omitted from Fig. 4 for the sake of clarity . The example code of Fig. 4 comprises the extended BCH(256,239) code cited above, which can correct up to t=2 bits, and serves as a component code in a higher level product-like code (e.g., the OFEC code mentioned above). For low latency decoding, multiple decoders can be executed in parallel. For example, the OFEC code uses a parallelism factor of 16, and the overall decoder may typically run hundreds of BCH decoders in parallel. It is therefore important to implement a low complexity and low power consumption decoder, which is achievable by applying a common iterative syndrome calculator circuit across all codeword chunks, as described above.

[0049] Decoder 150 receives an extended BCH codeword 152 comprising a 255-bit BCH codeword 154 and a single trailing parity-check bit 158. The parity-check bit is calculated over the entire BCH codeword 154. The decoder receives the extended BCH codeword in 16-bit chunks 162, including a first chunk 162 A, a middle chunk 162B and a last chunk 162C. Each of the first 15 chunks includes 16 bits of the BCH codeword, whereas the last chunk includes 15 bits of the BCH codeword and the trailing parity-check bit 158. ECC decoder 150 comprises a 16-bit buffer 166 and circuitry 168. Buffer 166 receives and temporarily stores one 16-bit chunk at a time. A masking module 170 receives a mask value per chunk (e.g., from a timing module, not shown) and masks the buffer content with the mask value. In the present example, the first 15 chunks are masked with an all ‘ 1’s mask value, whereas the last chunk is masked with a 15-bit all ‘ 1’s and a single zero bit (corresponding to the parity-check bit).

[0050] To decode the extended BCH codeword, decoder 150 is required to calculate syndromes over the 255-bit BCH codeword, and to calculate a parity result over the entire 256 bits of the extended BCH codeword.

[0051] In principle, since in the present example the number of correctable errors is t=2 and the underling code is a primitive BCH code, the syndromes need to be calculated over four powers of the primitive element α1...α4. Moreover, since the syndromes of the even powers can be derived with low complexity from respective syndromes of the odd powers, decoder 150 of Fig. 4 comprises only two iterative syndrome calculators 174A and 174B for calculating iteratively S(α1) and S(α3), e.g., using Equation 3 above. Due to the zeroing of parity-check bit 158 in the last chunk, the calculated syndromes are cyclically shifted by one element. In some embodiments, compensation for zeroing the parity bit misalignment can be carried out as part of calculating the syndromes or as part of calculating the error locations, as described above. To check the parity bit over the entire extended BCH codeword, decoder 150 comprises an all-XOR gate 180 and a parity-bit register 184 that is initialized to zero. For each received chunk, the all-XOR gate applies a 16-bit XOR operation among the 16 bits of the chunk and over the current parity value in the parity-bit register, and updates the parity-bit register with the 1-bit XOR result. Following the last chunk, the decoder verifies that the value of the parity-bit register equals ‘0’. MODIFICATIONS FOR SOFT DECODING In some embodiments the received codeword is accompanied with soft information that can be exploited for improving the decoding capabilities. For example, in a soft decoding approach referred to as the “chase decoding method” the decoder attempts decoding several different test patterns that are derived from the received codeword. In some embodiments, the soft information received with the original codeword comprises reliability levels assigned respectively to the bits (or symbols) of the codeword. The soft information may also comprise low-reliability bits (LRBs) that are indicative of bit locations (or symbol locations) in the received codeword having the lowest reliability levels. (In an alternative embodiment, the LRBs are calculated by the decoder). The decoder generates the test pattern by flipping selected bits in the original codeword indicated by the LRBs. Since the syndromes of the received codeword are known, the decoder can efficiently calculate a syndrome for the test pattern by modifying the original syndrome calculated for the received codeword based on the locations of the flipped bits. For example, if a ‘0’ bit in the received codeword is flipped, the power of the primitive element corresponding to the flipped bit (or to a symbol containing the flipped bit) is added to the syndrome of the received codeword. Similarly, if a ‘1’ bit in the codeword is flipped, the power of the primitive element corresponding to the flipped bit (or to a symbol containing the flipped bit is removed from the syndrome of the received codeword. It is noted that for binary codes or GF(2m) codes, adding and removing (of a power of the primitive element) is mathematically the same operation. In chase decoding of an RS code, flipping a single bit will modify the coefficient of a corresponding power of the primitive element that is used to modify the syndromes. In case the syndrome of the received codeword is cyclically shifted by some shift value due to zeroing a shift value number of trailing bits (or a number of symbols matching the trailing bits), the decoder generates the syndromes of the test pattern from the original syndromes of the received codeword based on a cyclically shifted version of the LRBs depending on the shift value. The decoder applies hard decoding to the test pattern using the syndromes calculated for the test pattern to find the error locations in the test pattern. In the present context, the phrase “shifting the LRBs cyclically depending on the shift value” means that the indices in the codeword indicated by the LRBs are shifted cyclically depending on the shift value. For example, for a binary code, the LRBs are cyclically shifted by the same shift value as the number of trailing bits. In an embodiment, for an RS code, the shift value equals the number of symbols matching the trailing bits, and the LRBs are shifted by the shift value multiplied by the number of bits per symbol. Fig. 5 is a flow chart that schematically illustrates a method for soft decoding of a codeword that is misaligned to the buffer boundaries, in accordance with an embodiment that is described herein. The method can be executed, for example, by decoder 20, 100 or 150. The method will be described for a binary BCH code. The method is however similarly applicable to other cyclic code such as the RS code. The method begins with the decoder receiving a codeword, reliability levels assigned to the codeword bits and corresponding LRBs indicative of one or more codeword bits having the lowest reliability levels, at a reception step 200. The codeword is misaligned by a number of trailing bits (shift value) in the buffer that stores the codeword. At an original syndrome generation step 204, the decoder generates for the received codeword original syndromes that are cyclically shifted by the shift value due to zeroing trailing bits of the codeword misalignment. At a pattern-generation step 208 the decoder derives from the received codeword a test pattern based on the received LRBs, by flipping one or more bits of the codeword that are indicated by the LRBs. In order to generate a syndrome for the test pattern based on a corresponding cyclically-shifted syndrome of the received codeword, the locations of the powers of the primitive elements should be properly aligned. To this end, the decoder shifts the LRBs cyclically, by the shift value, at a LRBs shifting step 212. At a test pattern syndrome calculation step 216, the decoder calculates syndromes for the test pattern by modifying the original syndromes of the received codeword based on the cyclically-shifted LRBs. The syndromes of the test pattern are shifted by the same shift value as the syndromes of the received codeword. At a decoding step 220, the decoder decodes the test pattern by finding cyclically- shifted error locations based on the cyclically-shifted syndromes of the test pattern. At a correction step 224, the decoder shifts the error locations back by the shift value, and corrects the test pattern using the cyclically-shifted error locations. Following step 224 the method terminates. The method of Fig. 5 is given by way of example, and other suitable methods can also be used. For example, instead of calculating shifted error locations as described in the method of Fig. 2B, the decoder can shift back the cyclically-shifted syndromes as described in the method of Fig. 2A. The configurations of decoder 20 of Fig. 1, decoder 100 of Fig. 3, and decoder 150 of Fig. 4 are example configurations that are depicted solely for the sake of clarity. In alternative embodiments, any other suitable decoder configurations can also be used. The different elements of decoders 20, 100 and 150 and their components may be implemented using dedicated hardware or firmware, such as using hard-wired or programmable logic, e.g., in an Application-Specific Integrated Circuit (ASIC) or Field- Programmable Gate Array (FPGA). Additionally or alternatively, some functions of decoders 20, 100 and 150, e.g., functions of syndrome calculator 34, error calculator 38, error corrector 42, soft decoder logic 66, iterative syndrome calculators 130 and 174 (e.g., 130A, 130B, 174A and 174B), may be implemented in software and / or using a combination of hardware and software elements. Elements that are not mandatory for understanding of the disclosed techniques have been omitted from the figure for the sake of clarity. In some embodiments, some functions of decoders 20, 100 and 150, e.g., functions of syndrome calculator 34, error calculator 38, error corrector 42, soft decoding logic 66, iterative syndrome calculators 130 and 174 (e.g., 130A, 130B, 174A and 174B), may be implemented in one or more programmable processors, which are programmed in software to carry out the functions described herein. The software may be downloaded to any of the processors in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and / or stored on non-transitory tangible media, such as magnetic, optical, or electronic memory. The embodiments described above are given by way of example, and other suitable embodiments can also be used. For example, although the embodiments described above refer mainly to BCH codes, the disclosed embodiments are similarly applicable to other cyclic codes such as, for example, the RS code. A low complexity approach in RS codes is to use misalignment that is a multiple of the symbol size. Moreover, in RS chase decoding, when a bit is flipped to derive a test pattern, the syndrome is modified in terms of location and value of the bit in a corresponding RS symbol. The disclosed embodiments are also applicable to shortened cyclic codes, in which some of the symbols have been removed. In such embodiments, cyclic shifts to the syndromes and error locations are based on indices of the non-shortened code, because the shortened code is not a cyclic code. It will be appreciated that the embodiments described above are cited by way of example, and that the following claims are not limited to what has been particularly shown and described hereinabove. Rather, the scope includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated by reference in the present patent application are to be considered an integral part of the application except that to the extent any terms are defined in these incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered.

Claims

CLAIMS1. A method for decoding, comprising: in a decoder of an error correction code (ECC), receiving in a buffer a codeword of the ECC that contains multiple symbols, the codeword having a misalignment with one or both boundaries of the buffer; zeroing, in the buffer, one or more bits that do not belong to the codeword; calculating one or more syndromes for the codeword across both the codeword and the zeroed bits; based on the calculated syndromes, identifying locations of one or more erroneous symbols in the codeword; and correcting the erroneous symbols in the identified locations to recover an error-free version of the codeword, further comprising compensating for the misalignment between the codeword and the buffer, as part of calculating the syndromes or as part of identifying the locations of the erroneous symbols.

2. The method according to claim 1, wherein zeroing the bits comprises zeroing a first number of symbols matching trailing bits that follow the codeword in the buffer, thereby causing the syndromes to be cyclically shifted by the first number, and wherein identifying the locations comprises (i) compensating for the misalignment by cyclically shifting the syndromes back by the first number and then (ii) identifying the locations based on the cyclically-shifted syndromes.

3. The method according to claim 1, wherein zeroing the bits comprises zeroing a first number of symbols matching trailing bits that follow the codeword in the buffer, thereby causing the syndromes to be cyclically shifted by the first number, and wherein identifying the locations comprises calculating the locations based on the cyclically-shifted syndromes, and then compensating for the misalignment by cyclically shifting the locations back by the first number.

4. The method according to any of claims 1 to 3, wherein zeroing the bits comprises zeroing a second number of leading bits that precede the codeword in the buffer.

5. The method according to any of claims 1 to 3, wherein receiving the codeword comprises receiving the codeword in one or more chunks having a common length, andwherein calculating the syndromes comprises calculating the syndromes iteratively over the chunks.

6. The method according to claim 5, wherein calculating the syndromes iteratively comprises calculating a given syndrome over multiple iterations using a common combinational circuit over the multiple chunks.

7. The method according to any of claims 1 to 3, wherein the ECC comprises a cyclic code selected from a list comprising a Bose-Chaudhuri-Hocquenghem (BCH) code and a Reed Solomon code.

8. The method according to any of claims claim 1 to 3, and comprising: receiving (i) low-reliability bits (LRBs) indicative of bits in the codeword having low reliability levels, and (ii) a shift value corresponding to the misalignment; calculating from the codeword a test pattern using the LRBs; calculating shifted LRBs by cyclically shifting the LRBs depending on the shift value; deriving from the syndromes respective test pattern syndromes by modifying the syndromes based on the shifted LRBs; and hard decoding the test pattern using the test pattern syndromes for recovering the error- free version of the codeword.

9. A decoder, comprising: a buffer, configured to receive a codeword of an error correction code (ECC) that contains multiple symbols, the codeword having a misalignment with one or both boundaries of the buffer; and circuitry, configured to: zero, in the buffer, one or more bits that do not belong to the codeword; calculate one or more syndromes for the codeword across both the codeword and the zeroed bits; based on the calculated syndromes, identify locations of one or more erroneous symbols in the codeword; and correct the erroneous symbols in the identified locations to recover an error-free version of the codeword, the circuitry is further configured to compensate for the misalignment between the codeword and the buffer, as part of calculating the syndromes or as part of identifying the locations of the erroneous symbols.

10. The decoder according to claim 9, wherein the circuitry is configured to zero the bits by zeroing a first number of symbols matching trailing bits that follow the codeword in the buffer, thereby causing the syndromes to be cyclically shifted by the first number, and to identify the locations by (i) compensating for the misalignment by cyclically shifting the syndromes back by the first number and then (ii) identifying the locations based on the cyclically-shifted syndromes.

11. The decoder according to claim 9, wherein the circuitry is configured to zero the bits by zeroing a first number of symbols matching the trailing bits that follow the codeword in the buffer, thereby causing the syndromes to be cyclically shifted by the first number, and to identify the locations by calculating the locations based on the cyclically-shifted syndromes, and then compensating for the misalignment by cyclically shifting the locations back by the first number.

12. The decoder according to any of claims 9 to 11, wherein the circuitry is configured to zero the bits by zeroing a second number of leading bits that precede the codeword in the buffer.

13. The decoder according to any of claims 9 to 11 , wherein the circuitry is configured to receive the codeword in one or more chunks having a common length, and to calculate the syndromes iteratively over the chunks.

14. The decoder according to claim 13, wherein the circuitry is configured to calculate the syndromes iteratively by calculating a given syndrome over multiple iterations using a common combinational circuit over the multiple chunks.

15. The decoder according to any of claims 9 to 11, wherein the ECC comprises a cyclic code selected from a list comprising a Bose-Chaudhuri-Hocquenghem (BCH) code and a Reed Solomon code.

16. The decoder according to any of claims 9 to 11, wherein the circuitry is configured to: receive(i) low-reliability bits (LRBs) indicative of bits in the codeword having low reliability levels, and (ii) a shift value corresponding to the misalignment; calculate from the codeword a test pattern using the LRBs; calculate shifted LRBs by cyclically shifting the LRBs depending on the shift value; derive from the syndromes respective test pattern syndromes by modifying the syndromes based on the shifted LRBs; andhard decode the test pattern using the test pattern syndromes for recovering the error- free version of the codeword.

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