Chip packaging structure

Abstract

Disclosed in the present invention is a chip packaging structure, comprising: a first chip and a second chip; a packaging frame, wherein the packaging frame comprises a base island and a plurality of pins, the second chip is provided on the base island, and the plurality of pins are respectively connected to the corresponding first chip and the corresponding second chip; a first electrical connection member, wherein the first electrical connection member is connected to the first chip, the second chip, and one of the plurality of pins; and a plastic packaging part, wherein the plastic packaging part covers the first chip, the second chip, the packaging frame, and the first electrical connection member, and part of the base island and part of the first electrical connection member are exposed from the plastic packaging part. Therefore, by exposing part of the base island and part of the first electrical connection member from the plastic packaging part, the heat dissipation capability of the chip packaging structure can be improved, the heat dissipation efficiency of the chip packaging structure can be improved, and the chip packaging structure can meet the heat dissipation requirement of a high-power-density device, thereby improving the working reliability of the first chip and the second chip.

Description

Chip packaging structure Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a chip packaging structure. Background Art

[0002] In the related technology, the existing chip packaging structure adopts a bottom heat dissipation packaging solution, and the heat generated by the chip is only dissipated through a single side. In addition, the heat transfer path of the chip packaging structure is long and the heat dissipation efficiency is low. The existing chip packaging structure cannot meet the requirements of fast and efficient heat dissipation under high heat flux density, and thus cannot meet the heat dissipation requirements of high power density devices, resulting in reduced chip working reliability.

[0003] Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a chip packaging structure with strong heat dissipation capabilities, which can improve the heat dissipation efficiency of the chip packaging structure, enable the chip packaging structure to meet the heat dissipation requirements of high-power density devices, and improve the operating reliability of the first chip and the second chip.

[0005] The chip packaging structure according to the present invention includes:

[0006] A first chip and a second chip, the first chip and the second chip are connected;

[0007] A packaging frame having a base island and a plurality of pins, wherein the second chip is arranged on the base island, and the plurality of pins are respectively connected to the corresponding first chip and the second chip;

[0008] a first electrical connector connected to the first chip, the second chip, and one of the plurality of pins;

[0009] The plastic sealing part covers the first chip, the second chip, the packaging frame and the first electrical connector, and a portion of the base island and a portion of the first electrical connector are exposed outside the plastic sealing part.

[0010] According to the chip packaging structure of the present invention, part of the base island and part of the first electrical connector are exposed to the plastic packaging part, and the heat generated by the first chip and the second chip can be dissipated through the base island and the first electrical connector, which can improve the heat dissipation capacity of the chip packaging structure, improve the heat dissipation efficiency of the chip packaging structure, enable the chip packaging structure to meet the heat dissipation requirements of high power density devices, and improve the working reliability of the first chip and the second chip.

[0011] In some examples of the present invention, the first chip and the second chip are located on the same side of the base island, and the first electrical connector is located on the side of the first chip away from the base island. A first heat dissipation surface is formed on the side of the first electrical connector away from the first chip, and the first heat dissipation surface is exposed to the plastic packaging part.

[0012] In some examples of the present invention, a second heat dissipation surface is formed on a side of the base island away from the first chip, and the second heat dissipation surface is exposed to the plastic packaging portion.

[0013] In some examples of the present invention, the chip packaging structure further includes: a second electrical connector connected between the first chip and the second chip, and the plastic packaging portion covers the outside of the second electrical connector.

[0014] In some examples of the present invention, the first chip and the second chip are located on the same side of the base island, and the second electrical connection is located on a side of the first chip away from the base island.

[0015] In some examples of the present invention, the chip packaging structure further includes: a third electrical connector and a fourth electrical connector, and the plurality of pins are connected to the corresponding first chip and the second chip through the first electrical connector, the third electrical connector, and the fourth electrical connector, respectively.

[0016] In some examples of the present invention, the multiple pins include: a source pin, a drain pin and a gate pin, the source pin is connected to the first electrical connector, the drain pin is connected to the drain of the second chip through the third electrical connector, and the gate pin is connected to the gate of the first chip through the fourth electrical connector.

[0017] In some examples of the present invention, a source pin among the plurality of pins is spaced apart from the base island.

[0018] In some examples of the present invention, the chip packaging structure further includes: a substrate, wherein the source pins among the plurality of pins are integrally formed with the base island, the substrate is arranged between the first chip and the base island, and the substrate is respectively connected to the first chip and the base island.

[0019] In some examples of the present invention, the substrate includes: an insulating body, a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer are respectively arranged on two opposite surfaces of the insulating body, and the first conductive layer and the second conductive layer are respectively connected to the first chip and the base island.

[0020] In some examples of the present invention, both the first conductive layer and the second conductive layer are metal layers.

[0021] In some examples of the present invention, a first assembly groove recessed toward the base island is formed on a surface of the base island opposite to the first chip, and at least a portion of the substrate is assembled in the first assembly groove.

[0022] In some examples of the present invention, at least one of the first electrical connector, the second electrical connector, the third electrical connector, and the fourth electrical connector is configured as a sheet-like structure.

[0023] In some examples of the present invention, the substrate of the second chip is configured as a sapphire substrate.

[0024] In some examples of the present invention, a second assembly groove recessed toward the inside of the base island is formed on a surface of the base island opposite to the second chip, and at least a portion of the second chip is assembled in the second assembly groove.

[0025] In some examples of the present invention, a source pin among the plurality of pins is formed with a third heat dissipation surface, and the third heat dissipation surface is exposed outside the plastic packaging portion.

[0026] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments with reference to the following drawings, in which:

[0028] FIG1 is a side view of a chip packaging structure according to a first embodiment of the present invention;

[0029] FIG2 is a top view of a chip packaging structure according to a first embodiment of the present invention;

[0030] 3 is a schematic diagram showing the connection principle between a first chip and a second chip according to an embodiment of the present invention;

[0031] FIG4 is a side view of a chip packaging structure according to a second embodiment of the present invention;

[0032] FIG5 is a top view of a chip packaging structure according to a second embodiment of the present invention.

[0033] Figure numerals: Chip packaging structure 100; first chip 10; second chip 20; packaging frame 30; base island 31; second heat dissipation surface 32; drain pin 33; gate pin 34; first assembly groove 35; source pin 36; third heat dissipation surface 361; second assembly groove 37; substrate 40; insulating body 41; first conductive layer 42; second conductive layer 43; first electrical connector 50; first heat dissipation surface 51; plastic sealing part 60; second electrical connector 70; third electrical connector 80; conductive silver paste layer 90; fourth electrical connector 91; source S1 of second chip 20; gate G1 of second chip 20; drain D1 of second chip 20; source S2 of first chip 10; gate G2 of first chip 10; drain D2 of first chip 10. DETAILED DESCRIPTION

[0034] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0035] The chip package structure 100 according to an embodiment of the present invention will be described below with reference to FIG. 1 to FIG. 5 .

[0036] As shown in Figures 1 to 5, the chip packaging structure 100 according to an embodiment of the present invention includes: a first chip 10, a second chip 20, a packaging frame 30, a first electrical connector 50, and a plastic packaging portion 60. The first chip 10 and the second chip 20 are connected. The packaging frame 30 has a base island 31 and a plurality of pins. The second chip 20 is provided on the base island 31, and the plurality of pins are respectively connected to the corresponding first chip 10 and second chip 20. The first electrical connector 50 is connected to the first chip 10, the second chip 20, and one of the plurality of pins. The plastic packaging portion 60 covers the first chip 10, the second chip 20, the packaging frame 30, and the first electrical connector 50, and a portion of the base island 31 and a portion of the first electrical connector 50 are exposed from the plastic packaging portion 60.

[0037] Among them, chips are mainly divided into enhancement-mode devices and depletion-mode devices based on their operating characteristics. This application uses the example of a first chip 10 being a low-voltage enhancement-mode device and a second chip 20 being a high-voltage depletion-mode device. For example, the first chip 10 can be a silicon-based MOSFET chip, and the second chip 20 can be a GaN-based HEMT chip. The first chip 10 and the second chip 20 can be packaged together in a common gate and common source manner to form a normally closed cascode GaN HEMT. The driving power supply is compatible with the driving power supply of the first chip 10, which can simplify the driving circuit design, greatly save costs and reduce design difficulty, and meet the requirements of higher voltage and high power applications. As shown in Figure 3, the chip packaging structure 100 of the present application has a forward turn-on voltage enhancement operating mode through cascading. The first chip 10 controls the conduction and shutdown of the entire device, and the second chip 20 can withstand the high voltage when the device is shut down.

[0038] The package frame 30 has a base island 31 and a plurality of pins. The base island 31 is used to mount the first chip 10 and the second chip 20. The second chip 20 is disposed on the base island 31 and can be electrically connected to the base island 31. The plurality of pins are used to connect to external circuits and are respectively connected to the corresponding first chip 10 and second chip 20. At least one of the plurality of pins is connected to the first chip 10, at least one of the plurality of pins is connected to the second chip 20, and one of the plurality of pins is connected to the first electrical connector 50. The first electrical connector 50 is connected to both the first chip 10 and the second chip 20. In other words, the first electrical connector 50 is simultaneously connected to the first chip 10, the second chip 20, and one of the plurality of pins. For example, if there are three pins, the three pins are respectively connected to the first chip 10, the second chip 20, and the first electrical connector 50. The package frame 30 can be made of a metal material, for example, the package frame 30 can be made of copper.

[0039] The first electrical connector 50 is electrically conductive and is connected to the first chip 10, the second chip 20, and one pin. For example, the first electrical connector 50 is electrically connected to the first chip 10, the second chip 20, and one pin. The plastic encapsulation portion 60 can be made of an inorganic material, such as resin, silicon dioxide, plastic, or the like.

[0040] The plastic encapsulation portion 60 covers the first chip 10, the second chip 20, the packaging frame 30 and the first electrical connector 50, and a portion of the base island 31 and a portion of the first electrical connector 50 are exposed from the plastic encapsulation portion 60. Since a portion of the base island 31 and a portion of the first electrical connector 50 are exposed from the plastic encapsulation portion 60, the heat generated by the first chip 10 and the second chip 20 can be dissipated through the base island 31 and the first electrical connector 50. Compared with the prior art, the chip packaging structure 100 of the present application has an increased heat dissipation area, which can improve the heat dissipation capacity of the chip packaging structure 100, enhance the heat dissipation capacity of the first chip 10 and the second chip 20, improve the heat dissipation efficiency of the chip packaging structure 100, enable the chip packaging structure 100 to meet the heat dissipation requirements of high-power density devices, and improve the working reliability of the first chip 10 and the second chip 20. Moreover, since the second chip 20 is arranged on the base island 31 and no substrate 40 is arranged between the second chip 20 and the base island 31, the path for the heat generated by the second chip 20 to be transferred to the base island 31 can be shortened, thereby further improving the heat dissipation capacity of the chip packaging structure 100, further enhancing the heat dissipation capacity of the first chip 10 and the second chip 20, and further improving the heat dissipation efficiency of the chip packaging structure 100.

[0041] Therefore, with part of the base island 31 and part of the first electrical connector 50 exposed to the plastic packaging part 60, the heat generated by the first chip 10 and the second chip 20 can be dissipated through the base island 31 and the first electrical connector 50, which can improve the heat dissipation capacity of the chip packaging structure 100, improve the heat dissipation efficiency of the chip packaging structure 100, enable the chip packaging structure 100 to meet the heat dissipation requirements of high power density devices, and improve the working reliability of the first chip 10 and the second chip 20.

[0042] In some embodiments of the present invention, the substrate of the second chip 20 can be constructed as a sapphire substrate. By constructing the substrate of the second chip 20 as a sapphire substrate, good bottom insulation of the second chip 20 can be achieved, and the provision of the base plate 40 between the second chip 20 and the base island 31 can be eliminated. This ensures that the path for heat generated by the second chip 20 to be transferred to the base island 31 is shortened, thereby further improving the heat dissipation capability of the chip package structure 100, further enhancing the heat dissipation capability of the first chip 10 and the second chip 20, and further improving the heat dissipation efficiency of the chip package structure 100.

[0043] In some embodiments of the present invention, as shown in FIG. 2 , the chip packaging structure 100 may further include a second electrical connector 70 connected between the first chip 10 and the second chip 20 , and the plastic package 60 covers the second electrical connector 70 .

[0044] Among them, the second electrical connector 70 has a conductive function, and the second electrical connector 70 can be made of copper material. The second electrical connector 70 is connected between the drain D2 of the first chip 10 and the source S1 of the second chip 20. The plastic packaging part 60 is covered on the outside of the second electrical connector 70. Such a setting can realize the electrical connection between the first chip 10 and the second chip 20, further improve the working reliability of the first chip 10 and the second chip 20, and the second electrical connector 70 can be firmly installed in the chip packaging structure 100, which can improve the connection stability between the second electrical connector 70 and the first chip 10 and the second chip 20.

[0045] In some embodiments of the present invention, as shown in FIG. 1 and FIG. 2 , the first chip 10 and the second chip 20 are located on the same side of the base island 31 , and the second electrical connection 70 is located on a side of the first chip 10 away from the base island 31 .

[0046] As shown in Figures 1 and 4, when the chip packaging structure 100 is placed in the direction shown in Figure 1, along the thickness direction of the base island 31, the first chip 10 and the second chip 20 are both located on the upper side of the base island 31, the second electrical connector 70 is located on the upper side of the first chip 10, and the first chip 10 and the second chip 20 are located between the base island 31 and the second electrical connector 70. After the chip packaging structure 100 is packaged, the second electrical connector 70 is located in the plastic sealing part 60, and the second electrical connector 70 can be firmly installed in the chip packaging structure 100, which can further improve the connection stability between the second electrical connector 70 and the first chip 10 and the second chip 20.

[0047] In some embodiments of the present invention, as shown in Figure 1, the first chip 10 and the second chip 20 are located on the same side of the base island 31, and the first electrical connector 50 is located on the side of the first chip 10 away from the base island 31. A first heat dissipation surface 51 is formed on the side of the first electrical connector 50 away from the first chip 10, and the first heat dissipation surface 51 is exposed to the plastic packaging part 60.

[0048] As shown in Figures 1 and 4 , when the chip package structure 100 is placed in the orientation shown in Figures 1 and 4 , along the thickness direction of the base island 31, the first chip 10 and the second chip 20 are both located on the upper side of the base island 31, the first electrical connector 50 is located on the upper side of the first chip 10, and the first chip 10 and the second chip 20 are located between the base island 31 and the first electrical connector 50. A first heat dissipation surface 51 is formed on the upper surface of the first electrical connector 50. After the chip package structure 100 is packaged, the first heat dissipation surface 51 is exposed to the plastic packaging portion 60, and the heat generated by the first chip 10 and the second chip 20 can be dissipated through the first heat dissipation surface 51. Therefore, by exposing the first heat dissipation surface 51 to the plastic packaging portion 60, the first electrical connector 50 can be firmly mounted on the chip package structure 100 while ensuring that the first electrical connector 50 has a heat dissipation effect, which can improve the stability of the connection between the first electrical connector 50 and the first chip 10, the second chip 20, and the base island 31.

[0049] In some embodiments of the present invention, the first heat dissipation surface 51 may be a plane. After the chip packaging structure 100 is packaged, the first heat dissipation surface 51 is exposed to the plastic packaging part 60 . This arrangement can further improve the surface flatness of the chip packaging structure 100 .

[0050] In some embodiments of the present invention, as shown in FIG. 1 , a second heat dissipation surface 32 is formed on a side of the base island 31 away from the first chip 10 , and the second heat dissipation surface 32 is exposed to the plastic packaging portion 60 .

[0051] As shown in Figures 1 and 4 , when the chip package structure 100 is placed in the orientation shown in Figures 1 and 4 , a second heat dissipation surface 32 is formed on the lower surface of the base island 31 along the thickness direction of the base island 31. After the chip package structure 100 is packaged, the second heat dissipation surface 32 is exposed to the plastic packaging portion 60. Heat generated by the first chip 10 and the second chip 20 can be dissipated through the second heat dissipation surface 32, thereby further improving the heat dissipation capacity of the chip package structure 100, further enhancing the heat dissipation capacity of the first chip 10 and the second chip 20, and further improving the heat dissipation efficiency of the chip package structure 100. Therefore, by exposing the second heat dissipation surface 32 to the plastic packaging portion 60, while ensuring that the base island 31 has a heat dissipation effect, the base island 31 can be firmly mounted on the chip package structure 100, which can improve the stability of the connection between the base island 31 and the first chip 10, the second chip 20, and the first electrical connector 50.

[0052] In some embodiments of the present invention, the second heat dissipation surface 32 may be a plane. After the chip packaging structure 100 is packaged, the second heat dissipation surface 32 is exposed to the plastic packaging portion 60 . This configuration can further improve the surface flatness of the chip packaging structure 100 .

[0053] In some embodiments of the present invention, as shown in Figures 1 and 2, the chip package structure 100 may further include: a third electrical connector 80 and a fourth electrical connector 91. A plurality of pins are connected to the corresponding first chip 10 and second chip 20 through the first electrical connector 50, the third electrical connector 80, and the fourth electrical connector 91, respectively. As shown in Figure 2, the first electrical connector 50 has a conductive function, and there may be three pins. The first pin may be connected to the first chip 10 through the third electrical connector 80, the second pin may be connected to the second chip 20 through the fourth electrical connector 91, and the third pin may be connected to the first electrical connector 50, thereby achieving the effect of leading out the pins of the chip package structure 100.

[0054] In some embodiments of the present invention, as shown in Figure 2, the multiple pins may include: a source pin 36, a drain pin 33 and a gate pin 34, the source pin 36 is connected to the first electrical connector 50, the drain pin 33 is connected to the drain D1 of the second chip 20 through the third electrical connector 80, and the gate pin 34 is connected to the gate G2 of the first chip 10 through the fourth electrical connector 91.

[0055] As shown in FIG2 , there may be three pins, one of which is a drain pin 33, another is a gate pin 34, and the last is a source pin 36. A third electrical connector 80 is connected between the drain pin 33 and the drain D1 of the second chip 20 to connect the drain pin 33. The gate pin 34 is connected to the gate G2 of the first chip 10 via a fourth electrical connector 91 to connect the gate pin 34. The source pin 36 is connected to the first electrical connector 50 to connect the source pin 36.

[0056] In some embodiments of the present invention, the first electrical connector 50 is connected to the source S2 of the first chip 10, the gate G1 of the second chip 20, and the source pin 36. By connecting the first electrical connector 50 to the source pin 36, the source pin 36 can be led out.

[0057] In some embodiments of the present invention, as shown in FIG2 , at least one of the first electrical connector 50 , the second electrical connector 70 , the third electrical connector 80 , and the fourth electrical connector 91 is configured as a sheet-like structure. This application uses the example of the first electrical connector 50 , the second electrical connector 70 , the third electrical connector 80 , and the fourth electrical connector 91 all being configured as sheet-like structures. At least one of the first electrical connector 50 , the second electrical connector 70 , the third electrical connector 80 , and the fourth electrical connector 91 has a rectangular cross-sectional shape, or at least one of the first electrical connector 50 , the second electrical connector 70 , the third electrical connector 80 , and the fourth electrical connector 91 has a similar rectangular cross-sectional shape. The first electrical connector 50, the second electrical connector 70, the third electrical connector 80, and the fourth electrical connector 91 can all be configured as copper sheets. By configuring at least one of the first electrical connector 50, the second electrical connector 70, the third electrical connector 80, and the fourth electrical connector 91 as a sheet-like structure, the package resistance of the chip package structure 100 can be reduced, and the power dissipation of the chip package structure 100 can be reduced, which is conducive to achieving lower power dissipation of the chip package structure 100 and also conducive to achieving low thermal resistance of the chip package structure 100. Furthermore, by configuring at least one of the first electrical connector 50, the second electrical connector 70, the third electrical connector 80, and the fourth electrical connector 91 as a sheet-like structure, the heat dissipation area of ​​the chip package structure 100 can be further increased, the heat dissipation capability of the chip package structure 100 can be further improved, the heat dissipation capability of the first chip 10 and the second chip 20 can be further enhanced, and the heat dissipation efficiency of the chip package structure 100 can be further improved.

[0058] In the prior art, the first chip and the second chip, as well as the chip and the pins, are connected via wires (i.e., wiring harnesses). These wires generate parasitic inductance and resistance, increase line delay, limit heat conduction, and affect the heat dissipation of the chip packaging structure. In the present application, at least one of the first electrical connector 50, the second electrical connector 70, the third electrical connector 80, and the fourth electrical connector 91 is configured as a sheet-like structure. This improves the current transmission capability of the electrical connectors, improves the overall efficiency of the chip packaging structure 100, reduces the power consumption of the chip packaging structure 100, improves the heat dissipation performance of the chip packaging structure 100, and reduces the packaging parasitic parameters of the chip packaging structure 100. Furthermore, the process is simple and the overall cost is relatively low.

[0059] In some embodiments of the present invention, the cross-sectional shape of the first electrical connector 50, the cross-sectional shape of the second electrical connector 70, the cross-sectional shape of the third electrical connector 80 and the cross-sectional shape of the fourth electrical connector 91 are the same. Such an arrangement can make the structural shapes of the first electrical connector 50, the second electrical connector 70, the third electrical connector 80 and the fourth electrical connector 91 similar, which facilitates the production of the chip packaging structure 100 and can improve the production efficiency of the first electrical connector 50, the second electrical connector 70, the third electrical connector 80 and the fourth electrical connector 91, thereby improving the production efficiency of the chip packaging structure 100.

[0060] In some embodiments of the present invention, the cross-sectional area of ​​the first electrical connector 50, the cross-sectional area of ​​the second electrical connector 70, the cross-sectional area of ​​the third electrical connector 80 and the cross-sectional area of ​​the fourth electrical connector 91 are the same. Such a configuration is more convenient for the production of the chip packaging structure 100, and can further improve the production efficiency of the first electrical connector 50, the second electrical connector 70, the third electrical connector 80 and the fourth electrical connector 91, thereby further improving the production efficiency of the chip packaging structure 100.

[0061] In some embodiments of the present invention, as shown in Figures 4 and 5, a source pin 36 among the plurality of pins is spaced apart from the base island 31. The source pin 36 is disposed adjacent to the base island 31 and spaced apart from the base island 31. By spaced apart from the base island 31, the substrate 40 between the first chip 10 and the base island 31 can be omitted. It can also be understood that by spaced apart from the base island 31, the substrate 40 can be omitted between the first chip 10 and the base island 31, which can shorten the path for heat generated by the first chip 10 to be transferred to the base island 31. This can further enhance the heat dissipation capability of the chip package structure 100, further strengthen the heat dissipation capability of the first chip 10, and further enhance the heat dissipation efficiency of the chip package structure 100.

[0062] In some embodiments of the present invention, as shown in Figures 1 and 2, the chip packaging structure 100 may further include: a substrate 40, a source pin 36 among the multiple pins and the base island 31 are integrally formed, the substrate 40 is arranged between the first chip 10 and the base island 31, and the substrate 40 is respectively connected to the first chip 10 and the base island 31.

[0063] Among them, the source pin 36 and the base island 31 among the multiple pins are constructed as an integrally formed part. It can also be understood that the source pin 36 and the base island 31 are constructed as an integral part, the substrate 40 is arranged between the first chip 10 and the base island 31, the first chip 10, the substrate 40 and the base island 31 are stacked in sequence, and the substrate 40 is respectively connected to the first chip 10 and the base island 31, and the substrate 40 is electrically connected to the first chip 10 and the base island 31. The source pin 36 and the base island 31 can both be made of metal materials. For example, the source pin 36 and the base island 31 can both be made of copper materials. By making the source pin 36 and the base island 31 of the same material, it is convenient to set the source pin 36 and the base island 31 as an integrally formed part, and to facilitate the production and manufacturing of the source pin 36 and the base island 31.

[0064] In some embodiments of the present invention, as shown in FIG. 1 , a first assembly groove 35 recessed toward the inside of the base island 31 is formed on the surface of the base island 31 opposite to the first chip 10 , and at least a portion of the substrate 40 is assembled in the first assembly groove 35 .

[0065] As shown in FIG1 , when the chip package structure 100 is placed in the orientation shown in FIG1 , a first assembly groove 35 is formed on the upper surface of the base island 31 along the thickness direction of the base island 31, which is recessed into the base island 31. At least a portion of the substrate 40 is assembled within the first assembly groove 35. In other words, a portion of the substrate 40 is assembled within the first assembly groove 35, or the entire structure of the substrate 40 is assembled within the first assembly groove 35. This arrangement can reduce the thickness of the chip package structure 100, allowing the chip package structure 100 to adapt to thinner package thickness requirements, shortening the heat dissipation path, and further improving the heat dissipation capacity of the chip package structure 100. Furthermore, by providing the first assembly groove 35, the mass of the chip package structure 100 can be reduced, which is conducive to the lightweight design of the chip package structure 100 and can achieve a chip package structure 100 with lower thermal resistance.

[0066] In some embodiments of the present invention, as shown in Figure 1, the substrate 40 may include: an insulating body 41, a first conductive layer 42 and a second conductive layer 43, the first conductive layer 42 and the second conductive layer 43 are respectively arranged on two opposite surfaces of the insulating body 41, and the first conductive layer 42 and the second conductive layer 43 are respectively connected to the first chip 10 and the base island 31.

[0067] As shown in Figure 1, the insulating body 41 has an insulating function. For example, the insulating body 41 can be made of ceramic material. When the chip packaging structure 100 is placed in the direction shown in Figure 1, the first conductive layer 42 is arranged on the upper surface of the insulating body 41, so that the first conductive layer 42 is opposite to the first chip 10, and the second conductive layer 43 is arranged on the lower surface of the insulating body 41, so that the second conductive layer 43 is opposite to the base island 31, thereby facilitating the electrical connection between the first conductive layer 42 and the first chip 10, and facilitating the electrical connection between the second conductive layer 43 and the base island 31.

[0068] In some embodiments of the present invention, as shown in FIG1 , the first conductive layer 42 and the second conductive layer 43 are both configured as metal layers. For example, the first conductive layer 42 and the second conductive layer 43 are both configured as copper layers. However, the present invention is not limited thereto. The first conductive layer 42 and the second conductive layer 43 may also be configured as aluminum layers or other structures. By configuring the first conductive layer 42 and the second conductive layer 43 as metal layers, electrical connections can be achieved between the substrate 40, the first chip 10, and the base island 31.

[0069] It should be noted that the second chip 20 can be a lateral, high-voltage, depletion-mode GaN-based power chip on a sapphire substrate, and the first chip 10 can be a vertical, low-voltage, enhancement-mode silicon-based power MOS chip. The first chip 10 can be electrically connected to the substrate 40 via a conductive silver paste layer 90. The second chip 20 can also be electrically connected to the base island 31 via the conductive silver paste layer 90. The substrate 40 can also be electrically connected to the base island 31 via the conductive silver paste layer 90.

[0070] The first electrical connector 50 can be connected to the source S2 of the first chip 10 through the conductive silver paste layer 90. The first electrical connector 50 can also be connected to the gate G1 of the second chip 20 through the conductive silver paste layer 90. The first electrical connector 50 can also be connected to the base island 31 through the conductive silver paste layer 90. The second electrical connector 70 can be connected to the drain D2 of the first chip 10 through the conductive silver paste layer 90. The second electrical connector 70 can also be connected to the source S1 of the second chip 20 through the conductive silver paste layer 90. One third electrical connector 80 can be connected to the drain D1 of the second chip 20 through the conductive silver paste layer 90, and another third electrical connector 80 can be connected to the gate G2 of the first chip 10 through the conductive silver paste layer 90. By providing the conductive silver paste layer 90, electrical connection between the various components can be achieved.

[0071] In some embodiments of the present invention, as shown in FIG. 4 , a second assembly groove 37 recessed toward the inside of the base island 31 is formed on the surface of the base island 31 opposite to the second chip 20 , and at least a portion of the second chip 20 is assembled in the second assembly groove 37 .

[0072] As shown in FIG4 , when the chip package structure 100 is placed in the orientation shown in FIG4 , a second assembly groove 37 is formed on the upper surface of the base island 31 along the thickness direction of the base island 31, and is recessed into the base island 31. At least a portion of the second chip 20 is assembled within the second assembly groove 37. In other words, a portion of the second chip 20 is assembled within the second assembly groove 37, or the entire structure of the second chip 20 is assembled within the second assembly groove 37. This arrangement can further reduce the thickness of the chip package structure 100, allowing the chip package structure 100 to adapt to thinner package thickness requirements, shortening the heat dissipation path, and further improving the heat dissipation capability of the chip package structure 100. Furthermore, by providing the second assembly groove 37, the mass of the chip package structure 100 can be reduced, which is beneficial to the lightweight design of the chip package structure 100 and can achieve a chip package structure 100 with lower thermal resistance.

[0073] In some embodiments of the present invention, the first assembly groove 35 and the second assembly groove 37 are connected, and the first assembly groove 35 and the second assembly groove 37 form a groove structure. Such a setting can connect the first assembly groove 35 and the second assembly groove 37 into the same groove structure. Processing a groove on the base island 31 can meet the use requirements of the first assembly groove 35 and the second assembly groove 37, which is convenient for the production and manufacturing of the base island 31, thereby improving the production efficiency of the chip packaging structure 100.

[0074] In some embodiments of the present invention, as shown in FIG4 , a source pin 36 among the plurality of pins is formed with a third heat dissipation surface 361, which is exposed to the plastic package portion 60. Heat generated by the first chip 10 and the second chip 20 can be transferred to the source pin 36 via the first electrical connector 50, and the heat is dissipated through the third heat dissipation surface 361 of the source pin 36. Compared with the prior art, this can further increase the heat dissipation area of ​​the chip package structure 100, further improve the heat dissipation capability of the chip package structure 100, further enhance the heat dissipation capability of the first chip 10 and the second chip 20, further improve the heat dissipation efficiency of the chip package structure 100, enable the chip package structure 100 to meet the heat dissipation requirements of high-power density devices, and further improve the operating reliability of the first chip 10 and the second chip 20.

[0075] In some embodiments of the present invention, as shown in FIG4 , the third heat dissipation surface 361 and the second heat dissipation surface 32 are coplanarly arranged. It can also be understood that the third heat dissipation surface 361 and the second heat dissipation surface 32 are located in the same plane. After the chip packaging structure 100 is packaged, the second heat dissipation surface 32 is exposed to the plastic sealing portion 60, the third heat dissipation surface 361 is exposed to the plastic sealing portion 60, and the third heat dissipation surface 361 and the second heat dissipation surface 32 are located in the same plane, which can further improve the surface flatness of the chip packaging structure 100.

[0076] As shown in FIG. 1 and FIG. 2 , a chip package structure 100 according to a first embodiment of the present invention is described in detail.

[0077] The chip package structure 100 includes a first chip 10, a second chip 20, a package frame 30, a substrate 40, a first electrical connector 50, a plastic encapsulation portion 60, a second electrical connector 70, a third electrical connector 80, a fourth electrical connector 91, a drain pin 33, a gate pin 34, a source pin 36, and multiple conductive silver paste layers 90. This application uses the placement orientation of the chip package structure 100 in FIG. 1 as an example for illustration.

[0078] The first chip 10 can be a silicon-based MOSFET chip, and the second chip 20 can be a GaN-based HEMT chip. The first chip 10 and the second chip 20 can be packaged together in a common gate and common source manner to form a normally closed cascode GaN HEMT. The driving power supply is compatible with the driving of the first chip 10, which can simplify the driving circuit design, greatly save costs and reduce design difficulty, and meet the application requirements of higher voltage and high power. As shown in Figure 3, the chip packaging structure 100 of the present application has a forward turn-on voltage enhancement mode of operation through cascading. The first chip 10 controls the conduction and shutdown of the entire device, and the second chip 20 can play a role in withstanding high voltage when the device is turned off.

[0079] The package frame 30 includes a base island 31, a drain pin 33, a gate pin 34, and a source pin 36. The second chip 20 is disposed on the upper side of the base island 31, and the second chip 20 is disposed on the base island 31 through a conductive silver paste layer 90, thereby achieving electrical connection between the second chip 20 and the base island 31. The third electrical connector 80 is connected between the drain pin 33 and the drain electrode D1 of the second chip 20. The third electrical connector 80 can be located on the upper side of the second chip 20 and the upper side of the drain pin 33. The third electrical connector 80 can be connected to the drain pin 33 through the conductive silver paste layer 90. The third electrical connector 80 can also be connected to the drain electrode D1 of the second chip 20 through the conductive silver paste layer 90, thereby achieving the lead-out effect of the drain pin 33.

[0080] The substrate 40 is disposed between the first chip 10 and the base island 31, and the substrate 40 is connected to the first chip 10 and the base island 31, respectively. The first chip 10, the substrate 40, and the base island 31 are stacked in sequence, and the substrate 40 is electrically connected to the first chip 10 and the base island 31. The substrate 40 can be connected to the first chip 10 through a conductive silver paste layer 90, and the substrate 40 can also be connected to the base island 31 through a conductive silver paste layer 90, thereby achieving the effect of electrically connecting the substrate 40 to the first chip 10 and the base island 31. The substrate 40 may include: an insulating body 41, a first conductive layer 42, and a second conductive layer 43. The first conductive layer 42 and the second conductive layer 43 are respectively disposed on two opposing surfaces of the insulating body 41, and the first conductive layer 42 and the second conductive layer 43 are respectively connected to the first chip 10 and the base island 31.

[0081] The first electrical connector 50 can be electrically connected to the gate G1 of the second chip 20 through a conductive silver paste layer 90. The first electrical connector 50 can also be electrically connected to the source S2 of the first chip 10 through the conductive silver paste layer 90. The first electrical connector 50 can also be electrically connected to the source pin 36 through the conductive silver paste layer 90. The second electrical connector 70 can be electrically connected to the drain D2 of the first chip 10 through the conductive silver paste layer 90. The second electrical connector 70 can also be electrically connected to the source S1 of the second chip 20 through the conductive silver paste layer 90. The fourth electrical connector 91 can be electrically connected to the gate G2 of the first chip 10 through the conductive silver paste layer 90. The fourth electrical connector 91 can also be electrically connected to the gate pin 34 through the conductive silver paste layer 90. The base island 31 of the package frame 30 is provided with a first mounting groove 35. The substrate 40 is disposed on the bottom wall of the first mounting groove 35, and at least a portion of the substrate 40 is located within the first mounting groove 35. The source pin 36 and the base island 31 are constructed as an integrally formed part.

[0082] The plastic encapsulation portion 60 covers the outside of the first chip 10, the outside of the second chip 20, the outside of the package frame 30, the outside of the substrate 40, the outside of the first electrical connector 50, the outside of the second electrical connector 70, the outside of the third electrical connector 80, the outside of the fourth electrical connector 91, the outside of the drain pin 33, the outside of the gate pin 34, the outside of the source pin 36, and the outside of the multiple conductive silver paste layers 90. Furthermore, portions of the structure of the base island 31 and the first electrical connector 50 are exposed to the plastic encapsulation portion 60. Specifically, the first heat dissipation surface 51 of the first electrical connector 50 and the second heat dissipation surface 32 of the base island 31 are exposed to the plastic encapsulation portion 60.

[0083] According to the chip packaging structure 100 of the first embodiment of the present invention, part of the base island 31 and part of the first electrical connector 50 are exposed to the plastic packaging part 60, and the heat generated by the first chip 10 and the second chip 20 can be dissipated through the base island 31 and the first electrical connector 50, which can improve the heat dissipation capacity of the chip packaging structure 100, improve the heat dissipation efficiency of the chip packaging structure 100, enable the chip packaging structure 100 to meet the heat dissipation requirements of high power density devices, and improve the working reliability of the first chip 10 and the second chip 20.

[0084] As shown in FIG. 4 and FIG. 5 , a chip packaging structure 100 according to a second embodiment of the present invention is described in detail.

[0085] The chip package structure 100 includes a first chip 10, a second chip 20, a package frame 30, a first electrical connector 50, a plastic encapsulation portion 60, a second electrical connector 70, a third electrical connector 80, a fourth electrical connector 91, a drain pin 33, a gate pin 34, a source pin 36, and multiple conductive silver paste layers 90. This application uses the placement orientation of the chip package structure 100 shown in FIG. 4 as an example for illustration.

[0086] The first chip 10 can be a silicon-based MOSFET chip, and the second chip 20 can be a GaN-based HEMT chip. The first chip 10 and the second chip 20 can be packaged together in a common gate and common source manner to form a normally closed cascode GaN HEMT. The driving power supply is compatible with the driving of the first chip 10, which can simplify the driving circuit design, greatly save costs and reduce design difficulty, and meet the application requirements of higher voltage and high power. As shown in Figure 3, the chip packaging structure 100 of the present application has a forward turn-on voltage enhancement mode of operation through cascading. The first chip 10 controls the conduction and shutdown of the entire device, and the second chip 20 can play a role in withstanding high voltage when the device is turned off.

[0087] The package frame 30 includes a base island 31, a drain pin 33, a gate pin 34, and a source pin 36. The second chip 20 is disposed on the upper side of the base island 31 and is disposed on the base island 31 via a conductive silver paste layer 90, achieving electrical connection between the second chip 20 and the base island 31. A third electrical connector 80 is connected between the drain pin 33 and the drain electrode D1 of the second chip 20. The third electrical connector 80 can be located on the upper side of the second chip 20 and the upper side of the drain pin 33. The third electrical connector 80 can be connected to the drain pin 33 via the conductive silver paste layer 90. The third electrical connector 80 can also be connected to the drain electrode D1 of the second chip 20 via the conductive silver paste layer 90, achieving the lead-out effect of the drain pin 33. The base island 31 of the package frame 30 is provided with a second assembly groove 37. The second chip 20 is disposed on the bottom wall of the second assembly groove 37, and at least part of the structure of the second chip 20 is located within the second assembly groove 37. The source lead 36 and the base island 31 are constructed as separate parts, and the source lead 36 and the base island 31 are spaced apart from each other.

[0088] The first electrical connector 50 can be electrically connected to the gate G1 of the second chip 20 through the conductive silver paste layer 90. The first electrical connector 50 can also be electrically connected to the source S2 of the first chip 10 through the conductive silver paste layer 90. The first electrical connector 50 can also be electrically connected to the source pin 36 through the conductive silver paste layer 90. The second electrical connector 70 can be electrically connected to the drain D2 of the first chip 10 through the conductive silver paste layer 90. The second electrical connector 70 can also be electrically connected to the source S1 of the second chip 20 through the conductive silver paste layer 90. The fourth electrical connector 91 can be electrically connected to the gate G2 of the first chip 10 through the conductive silver paste layer 90. The fourth electrical connector 91 can also be electrically connected to the gate pin 34 through the conductive silver paste layer 90.

[0089] The plastic encapsulation portion 60 covers the outside of the first chip 10, the outside of the second chip 20, the outside of the package frame 30, the outside of the first electrical connector 50, the outside of the second electrical connector 70, the outside of the third electrical connector 80, the outside of the fourth electrical connector 91, the outside of the drain pin 33, the outside of the gate pin 34, the outside of the source pin 36, and the outside of the multiple conductive silver paste layers 90. Furthermore, portions of the structure of the base island 31, the first electrical connector 50, and the source pin 36 are exposed from the plastic encapsulation portion 60. Specifically, the first heat dissipation surface 51 of the first electrical connector 50, the second heat dissipation surface 32 of the base island 31, and the third heat dissipation surface 361 of the source pin 36 are exposed from the plastic encapsulation portion 60.

[0090] According to the chip packaging structure 100 of the second embodiment of the present invention, part of the structure of the base island 31, part of the structure of the first electrical connector 50 and part of the structure of the source pin 36 are exposed to the plastic packaging part 60. The heat generated by the first chip 10 and the second chip 20 can be dissipated through the base island 31 and the first electrical connector 50, which can improve the heat dissipation capacity of the chip packaging structure 100, improve the heat dissipation efficiency of the chip packaging structure 100, enable the chip packaging structure 100 to meet the heat dissipation requirements of high power density devices, and improve the working reliability of the first chip 10 and the second chip 20.

[0091] To sum up, when the chip packaging structure 100 of the first embodiment of the present invention and the chip packaging structure 100 of the second embodiment of the present invention are working, the heat generated by the first chip 10 and the second chip 20 can be dissipated through the base island 31 and the first electrical connector 50, which can improve the heat dissipation capacity of the chip packaging structure 100, improve the heat dissipation efficiency of the chip packaging structure 100, enable the chip packaging structure 100 to meet the heat dissipation requirements of high power density devices, and improve the working reliability of the first chip 10 and the second chip 20.

[0092] The difference between the chip packaging structure 100 according to the first embodiment of the present invention and the chip packaging structure 100 according to the second embodiment of the present invention is that the chip packaging structure 100 according to the first embodiment of the present invention is provided with a substrate 40, which is disposed between the base island 31 and the first chip 10. The source pins 36 of the packaging frame 30 and the base island 31 are integrally formed parts. The base island 31 is provided with a first assembly groove 35, and the first chip 10 is mounted in the first assembly groove 35. The chip packaging structure 100 according to the second embodiment of the present invention is not provided with a substrate 40. The first chip 10 is mounted on the base island 31 via a conductive silver paste layer 90. The source pins 36 of the packaging frame 30 and the base island 31 are separate parts, and the source pins 36 and the base island 31 are spaced apart. The base island 31 is provided with a second assembly groove 37, and the second chip 20 is mounted in the second assembly groove 37.

[0093] It should be noted that GaN-based HEMT chips, as representatives of third-generation semiconductor materials, feature a wide bandgap, high breakdown field strength, and high two-dimensional electron gas concentration. Consequently, they exhibit high current, high breakdown voltage, high power, high efficiency, and excellent microwave characteristics. However, as the power of GaN-based HEMT chips increases, self-heating has become a major issue affecting their performance. This temperature decreases their current, gain, and output power, leading to increased leakage current and reduced reliability. During the packaging process, GaN-based HEMT chips are often packaged using flip-chip technology. However, the low thermal conductivity of the solder used in flip-chip soldering limits heat conduction, thus limiting the heat dissipation capacity of the GaN-based HEMT chips. Therefore, according to the chip packaging structure 100 of the embodiment of the present invention, partial structure of the base island 31, partial structure of the first electrical connector 50, and partial structure of the source pin 36 are exposed to the plastic packaging portion 60. The heat generated by the first chip 10 and the second chip 20 can be dissipated simultaneously through the base island 31 and the first electrical connector 50, thereby improving the heat dissipation efficiency of the GaN-based HEMT chip, improving the heat dissipation capacity of the chip packaging structure 100, improving the heat dissipation efficiency of the chip packaging structure 100, enabling the chip packaging structure 100 to meet the heat dissipation requirements of high-power density devices, and improving the operating reliability of the first chip 10 and the second chip 20.

[0094] In some embodiments of the present invention, the chip package structure 100 may be provided with a heat sink (not shown). The heat sink may be mounted on an outer surface of the chip package structure 100, for example, the heat sink may be mounted directly on the outer surface of the chip package structure 100. Furthermore, the heat sink may be disposed corresponding to the first heat dissipation surface 51, the second heat dissipation surface 32, or both the first heat dissipation surface 51 and the second heat dissipation surface 32. When the heat sink is in operation, it dissipates heat from the chip package structure 100, achieving a cooling effect and significantly reducing the thermal resistance between the chip package structure 100 and the environment. Compared to not using a heat sink, using a heat sink to dissipate heat from the chip package structure 100 allows the chip package structure 100 to consume more power while maintaining the same temperature rise, without compromising the operational reliability of the chip package structure 100. When using a heat sink to dissipate heat from the chip package structure 100, the on-resistance of the silicon-based MOSFET chip changes less than when not using a heat sink to dissipate heat from the chip package structure 100. The type of radiator can be reasonably selected according to actual usage requirements and is not specifically limited.

[0095] It should be noted that, unless there is any conflict, the embodiments and features in the embodiments of this application can be combined with each other.

[0096] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0097] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that: include: A first chip and a second chip, wherein the first chip and the second chip are connected; A packaging frame, wherein the packaging frame has a base island and a plurality of pins, the second chip is arranged on the base island, and the plurality of pins are respectively connected to the corresponding first chip and the second chip; A first electrical connection member, the first electrical connection member is connected to the first chip, the second chip, and one of the plurality of pins; A plastic sealing part, wherein the plastic sealing part covers the first chip, the second chip, the packaging frame and the first electrical connector, and a portion of the base island and a portion of the first electrical connector are exposed from the plastic sealing part.

2. The chip packaging structure according to claim 1, characterized in that: The first chip and the second chip are located on the same side of the base island, and the first electrical connector is located on a side of the first chip away from the base island. A first heat dissipation surface is formed on the side of the first electrical connector away from the first chip, and the first heat dissipation surface is exposed to the plastic packaging part.

3. The chip packaging structure according to claim 1, characterized in that: A second heat dissipation surface is formed on a side of the base island away from the first chip, and the second heat dissipation surface is exposed to the plastic sealing part.

4. The chip packaging structure according to claim 1, characterized in that: Also includes: A second electrical connector is connected between the first chip and the second chip, and the plastic sealing part covers the outside of the second electrical connector.

5. The chip packaging structure according to claim 4, characterized in that: The first chip and the second chip are located on the same side of the base island, and the second electrical connection member is located on a side of the first chip away from the base island.

6. The chip packaging structure according to claim 4, characterized in that: Also includes: A third electrical connector and a fourth electrical connector, wherein the plurality of pins are connected to the corresponding first chip and the second chip through the first electrical connector, the third electrical connector and the fourth electrical connector respectively.

7. The chip packaging structure according to claim 6, characterized in that: The plurality of pins include: a source pin, a drain pin and a gate pin, the source pin is connected to the first electrical connector, the drain pin is connected to the drain of the second chip through the third electrical connector, and the gate pin is connected to the gate of the first chip through the fourth electrical connector.

8. The chip packaging structure according to claim 7, characterized in that: A source lead among the plurality of leads is spaced apart from the base island.

9. The chip packaging structure according to claim 7, characterized in that: Also includes: A substrate, wherein source pins among the plurality of pins are integrally formed with the base island, the substrate is disposed between the first chip and the base island, and the substrate is respectively connected to the first chip and the base island.

10. The chip packaging structure according to claim 9, characterized in that: The substrate comprises: an insulating body, a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer are respectively arranged on two opposite surfaces of the insulating body, and the first conductive layer and the second conductive layer are respectively connected to the first chip and the base island.

11. The chip packaging structure according to claim 10, characterized in that: The first conductive layer and the second conductive layer are both metal layers.

12. The chip packaging structure according to claim 9, characterized in that: A first assembly groove recessed toward the inside of the base island is formed on a surface of the base island opposite to the first chip, and at least a portion of the substrate is assembled in the first assembly groove.

13. The chip packaging structure according to claim 6, characterized in that: At least one of the first electrical connector, the second electrical connector, the third electrical connector, and the fourth electrical connector is configured as a sheet-like structure.

14. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The substrate of the second chip is configured as a sapphire substrate.

15. The chip packaging structure according to any one of claims 1 to 7, characterized in that: A second mounting groove recessed toward the inside of the base island is formed on a surface of the base island opposite to the second chip, and at least a portion of the second chip is mounted in the second mounting groove.

16. The chip packaging structure according to claim 7, characterized in that: The source pins among the plurality of pins are formed with a third heat dissipation surface, and the third heat dissipation surface is exposed outside the plastic packaging part.

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