Semiconductor device, manufacturing method therefor and electronic apparatus

Abstract

A semiconductor device, a manufacturing method therefor and an electronic apparatus. The semiconductor device comprises a plurality of storage units which are distributed in different layers, are stacked in the direction perpendicular to a substrate and are periodically distributed, each layer comprising a plurality of columns of storage units; and a relaxation buffer layer which is located between the substrate and the storage units.

Description

Semiconductor device and manufacturing method thereof, and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 7, 2023, with application number 202311153052.8 and invention name “Semiconductor device, manufacturing method thereof, and electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present application relate to, but are not limited to, the field of design and manufacturing of semiconductor devices, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0003] Dynamic Random Access Memory (DRAM) is a common type of system memory widely used in personal computers, laptops, and consumer electronics. Traditional DRAM consists of multiple, repeated "memory cells," each containing a capacitor and a transistor. A capacitor can store one bit of data. After charging and discharging, the amount of charge stored in the capacitor corresponds to the binary data "1" and "0," respectively. The transistor acts as a switch that controls the charging and discharging of the capacitor.

[0004] To minimize product costs, people want to create as many memory cells as possible on a limited substrate. This led to the development of 3D DRAM architecture and concepts. One approach to implementing 3D DRAM devices is to use a silicon / silicon germanium (Si / SiGe) stack as both the channel layer and the sacrificial layer.

[0005] Since the lattice mismatch between Si and Ge reaches 4%, the SiGe layer grown epitaxially on the Si substrate will produce strain due to the lattice mismatch. The strain will be released after the Si / SiGe multilayer stacking, resulting in an increase in defects in the channel formed by the Si layer, causing device degradation and seriously affecting the performance of DRAM.

[0006] Summary of the Invention

[0007] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0008] An embodiment of the present application provides a semiconductor device, comprising:

[0009] A plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to the substrate and periodically distributed; each layer includes a plurality of columns of memory cells;

[0010] A relaxed buffer layer is located between the substrate and the memory cell.

[0011] In an exemplary embodiment of the present application, a lattice constant of the relaxed buffer layer in a relaxed state is different from a lattice constant of the substrate.

[0012] In an exemplary embodiment of the present application, the relaxed buffer layer may include a first relaxed buffer layer and a second relaxed buffer layer, the first relaxed buffer layer is located between the substrate and the second relaxed buffer layer, and the second relaxed buffer layer is located between the first relaxed buffer layer and the memory cell;

[0013] Along a direction away from the substrate, the lattice constant of the first relaxed buffer layer changes, and the lattice constant of the second relaxed buffer layer remains unchanged;

[0014] Dislocations are present in both the first relaxed buffer layer and the second relaxed buffer layer, and a dislocation density in the first relaxed buffer layer is greater than a dislocation density in the second relaxed buffer layer.

[0015] In an exemplary embodiment of the present application, at least a region of the first relaxed buffer layer away from the substrate is a film layer in which strain is completely relaxed.

[0016] In an exemplary embodiment of the present application, the material of the substrate may be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide, and indium phosphide.

[0017] In an exemplary embodiment of the present application, the material of the relaxed buffer layer may be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium arsenide, and indium phosphide.

[0018] In an exemplary embodiment of the present application, the memory cell includes a transistor, and the transistor includes a semiconductor column; the main material of the semiconductor column can be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide.

[0019] In an exemplary embodiment of the present application, the material of the substrate and the main material of the semiconductor pillar may both be silicon, and the material of the relaxed buffer layer may be silicon germanium.

[0020] In an exemplary embodiment of the present application, the material of the substrate may be silicon, the material of the relaxed buffer layer may be selected from any one or more of gallium arsenide, aluminum gallium arsenide and indium gallium arsenide, and the main material of the semiconductor column may be gallium arsenide or indium gallium arsenide.

[0021] In an exemplary embodiment of the present application, the semiconductor device may further include an isolation layer, located between the relaxed buffer layer and the memory cell, and configured to isolate the relaxed buffer layer from the memory cell.

[0022] In an exemplary embodiment of the present application, the transistor may further include a gate electrode surrounding at least a portion of a sidewall of the semiconductor pillar.

[0023] In an exemplary embodiment of the present application, the semiconductor pillar may extend along a first direction parallel to the substrate.

[0024] In an exemplary embodiment of the present application, the memory cell may further include a capacitor connected to the transistor in the same memory cell.

[0025] In an exemplary embodiment of the present application, the semiconductor device may further include: a plurality of bit lines extending in a direction perpendicular to the substrate.

[0026] In an exemplary embodiment of the present application, the transistors of two columns of memory cells that are located in different layers and adjacent to each other along the first direction may be connected to the same bit line.

[0027] In an exemplary embodiment of the present application, the semiconductor device may further include: a plurality of word lines extending along a second direction parallel to the substrate.

[0028] In an exemplary embodiment of the present application, the transistors of a column of memory cells located in the same layer and arranged along the second direction may be connected to the same word line.

[0029] An embodiment of the present application further provides a method for manufacturing a semiconductor device, wherein the semiconductor device comprises a plurality of memory cells and a relaxed buffer layer; the plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to a substrate, and periodically distributed, and the memory cells comprise transistors;

[0030] The method for manufacturing the semiconductor device comprises:

[0031] forming the relaxed buffer layer on the substrate, and making the relaxed buffer layer a relaxed film layer;

[0032] The plurality of memory cells are formed on a side of the relaxed buffer layer away from the substrate.

[0033] In an exemplary embodiment of the present application, forming the relaxed buffer layer on the substrate and making the relaxed buffer layer a relaxed film layer may include:

[0034] A first relaxed buffer layer is grown on one side of the substrate using an epitaxial process; wherein the lattice constant of the first relaxed buffer layer varies along a direction away from the substrate, the first relaxed buffer layer has dislocations, and a region of the first relaxed buffer layer away from the substrate is a film layer in which strain is completely relaxed;

[0035] A second relaxed buffer layer is grown on a side of the first relaxed buffer layer away from the substrate using an epitaxial process, and the lattice structure of the second relaxed buffer layer is consistent with the lattice structure of the first relaxed buffer layer away from the substrate; the first relaxed buffer layer and the second relaxed buffer layer constitute the relaxed buffer layer.

[0036] In an exemplary embodiment of the present application, forming the plurality of memory cells on a side of the relaxed buffer layer away from the substrate may include:

[0037] forming an isolation layer on a side of the relaxed buffer layer away from the substrate by using an epitaxial process;

[0038] Semiconductor layers and sacrificial layers are alternately grown on a side of the isolation layer away from the substrate using an epitaxial process to obtain a stacked structure consisting of alternating semiconductor layers and sacrificial layers.

[0039] In an exemplary embodiment of the present application, the lattice constant of the relaxed buffer layer in a relaxed state is different from the lattice constant of the substrate, and the lattice constant of the relaxed buffer layer in a relaxed state is between the lattice constants of the sacrificial layer and the semiconductor layer.

[0040] In an exemplary embodiment of the present application, forming the plurality of memory cells may further include: after obtaining the stacking structure,

[0041] A patterning process is performed on the semiconductor layer in the stacked structure so that the semiconductor layer forms a semiconductor column of the transistor, and a gate electrode is formed on at least a portion of a sidewall of the semiconductor column. The semiconductor column and the gate electrode constitute the transistor.

[0042] In an exemplary embodiment of the present application, the method for manufacturing the semiconductor device may further include: forming a capacitor connected to the transistor, wherein the transistor and the capacitor connected thereto constitute the memory cell.

[0043] An embodiment of the present application further provides an electronic device, which includes the semiconductor device provided in the above embodiment of the present application.

[0044] Other features and advantages of the present application will be described in the following description, and in part will become more apparent from the description, or understood by practicing the present application. The purposes and advantages of the present application can be realized and obtained through the structures particularly pointed out in the description and drawings.

[0045] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0046] Summary of the Figures

[0047] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0048] FIG1A is a schematic longitudinal cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application;

[0049] FIG1B is a top view of the semiconductor device shown in FIG1A ;

[0050] FIG2 is a process flow chart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application;

[0051] 3A is a schematic longitudinal cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application after forming a first relaxed buffer layer;

[0052] FIG3B is a top view of the semiconductor device shown in FIG3A ;

[0053] FIG4 is a schematic longitudinal cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application after CMP is performed on the surface of the first relaxed buffer layer;

[0054] 5A is a schematic longitudinal cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application after a second relaxed buffer layer is formed;

[0055] FIG5B is a top view of the semiconductor device shown in FIG5A ;

[0056] 6A is a schematic longitudinal cross-sectional view of a semiconductor device after forming a stacked structure provided by an exemplary embodiment of the present application;

[0057] FIG6B is a top view of the semiconductor device shown in FIG6A ;

[0058] 7A is a schematic longitudinal cross-sectional view of a semiconductor device after semiconductor pillars are formed, provided by an exemplary embodiment of the present application;

[0059] FIG7B is a top view of the semiconductor device shown in FIG7A ;

[0060] 8A is a schematic longitudinal cross-sectional view of a semiconductor device after bit lines are formed, provided by an exemplary embodiment of the present application;

[0061] FIG8B is a top view of the semiconductor device shown in FIG8A ;

[0062] 9A is a schematic longitudinal cross-sectional view of a semiconductor device according to an exemplary embodiment of the present application after a sacrificial layer is removed;

[0063] FIG9B is a top view of the semiconductor device shown in FIG9A ;

[0064] 10A is a schematic longitudinal cross-sectional view of a semiconductor device after word lines are formed, provided by an exemplary embodiment of the present application;

[0065] FIG10B is a top view of the semiconductor device shown in FIG10A ;

[0066] The meanings of the various symbols in the accompanying drawings are:

[0067] 10-substrate; 21-first relaxed buffer layer; 22-second relaxed buffer layer; 30-isolation layer; 31-first insulating layer; 32-second insulating layer; 40-semiconductor layer; 41-semiconductor column; 42-first electrode region; 43-channel region; 44-second electrode region; 45-third electrode region; 50-sacrificial layer; 61-first trench; 62-second trench; 70-bit line; 80-word line; 81-gate insulating layer; 82-gate electrode; 90-transistor; 100-capacitor; 101-dielectric layer; 102-fourth electrode layer; 110-memory unit.

[0068] Details

[0069] To make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other in any way.

[0070] The embodiments of the present application are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present application are not limited to the shapes or values ​​shown in the drawings.

[0071] The ordinal numbers such as “first” and “second” in this application are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0072] In this application, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on this application. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in the disclosure are not limited and may be appropriately replaced according to the circumstances.

[0073] In this application, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0074] In this application, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0075] In the present application, the first electrode region may be a drain electrode and the second electrode region may be a source electrode, or the first electrode region may be a source electrode and the second electrode region may be a drain electrode. In cases where transistors with opposite polarities are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchangeable. Therefore, in the present application, unless otherwise specified, the "source electrode" and the "drain electrode" may be interchangeable.

[0076] In the present disclosure, “electrical connection” or “connection” includes situations where constituent elements are connected together through an element having some electrical function, such as electrical signal connection (coupling connection, such as coupled to), or physical direct connection. There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected constituent elements. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0077] In this application, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0078] In some embodiments of the present application, the terms "film" and "layer" may be interchanged. For example, "semiconductor layer" may be replaced with "semiconductor film." Similarly, "insulating film" may be replaced with "insulating layer."

[0079] The phrase "A and B are disposed in the same layer" in this application means that A and B are distributed on the same horizontal plane, or, although not on the same horizontal plane, are located in different areas of the same support surface. In one embodiment, A and B are formed simultaneously through the same patterning process on the same film layer.

[0080] In the embodiments of this application, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, if A and B are formed from the same material into a single film layer and are simultaneously connected through the same patterning process, or if B is directly grown on A via epitaxial growth, the two materials may not be identical.

[0081] Epitaxially grown Si on Si substrate 1-x Ge x The layer will produce strain due to lattice mismatch. When the strain exceeds the critical value, dislocation will be generated, causing strain relaxation. And with the increase of Ge concentration, the critical thickness decreases exponentially. According to theoretical calculations, Si is grown directly on Si substrate. 0.8 Ge 0.2 The critical thickness of the layer relaxation is about 15nm, the critical thickness of the metastable state is about 250nm, and the growth of Si 0.7 Ge 0.3 The critical thickness for layer relaxation is only about 8 nm, and the critical thickness for metastable state is about 100 nm.

[0082] In the process of realizing 3D DRAM devices with Si / SiGe stacking, due to the requirements of the selective etching process of SiGe and Si, the Ge concentration cannot be reduced indefinitely. Therefore, in order to obtain more stacking layers and achieve higher integration, it is necessary to seek new methods to achieve more layers of Si / Si while ensuring the quality of the stacking crystal. 1-x Ge x Laminated structure.

[0083] An embodiment of the present application provides a semiconductor device.

[0084] FIG1A is a schematic longitudinal cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application; FIG1B is a top view of the semiconductor device shown in FIG1A .

[0085] As shown in FIG. 1A and FIG. 1B , the semiconductor device includes:

[0086] Multiple memory cells 110 are distributed in different layers, stacked in a direction perpendicular to the substrate 10 and periodically distributed. Each layer includes multiple columns of memory cells 110 , each memory cell 110 includes a transistor 90 , and each transistor 90 includes a semiconductor pillar 41 .

[0087] The relaxed buffer layer 20 is a relaxed film layer and is located between the substrate 10 and the memory cell 110 .

[0088] The semiconductor device of the embodiment of the present application introduces a relaxed buffer layer between the substrate and the storage unit, which can reduce the lattice mismatch between the substrate and the epitaxial stack structure (such as the Si / SiGe stack structure) during the manufacturing process of the semiconductor device, thereby reducing the strain accumulation in the epitaxial stack structure. Under the same conditions, the number of layers that can be stacked in the epitaxial stack structure can be increased.

[0089] In addition, the introduction of the relaxed buffer layer can increase the tensile strain in the channel region of the transistor, thereby improving the electron mobility in the channel region and further increasing the operating speed of the transistor (eg, switching speed).

[0090] Moreover, the introduction of the relaxed buffer layer can reduce the strain accumulation of the epitaxial sacrificial layer (for example, the SiGe epitaxial sacrificial layer) in the epitaxial stack structure during the manufacturing process of semiconductor devices, so that under the same conditions, the critical thickness of the epitaxial sacrificial layer is increased, thereby obtaining a thicker epitaxial sacrificial layer, which can reduce the process difficulty of 3D semiconductor device processing.

[0091] In an exemplary embodiment of the present application, the semiconductor pillars 41 of the transistors of the plurality of memory cells 110 located in the same layer may be formed from the same semiconductor layer 40 ;

[0092] The semiconductor layer 40 and the relaxed buffer layer 20 are both epitaxial layers grown on the substrate.

[0093] In an exemplary embodiment of the present application, the lattice constant of the relaxed buffer layer in the relaxed state is different from the lattice constant of the substrate. For example, if the substrate is made of silicon and the relaxed buffer layer is made of silicon germanium, the lattice constant of the relaxed buffer layer in the relaxed state is greater than the lattice constant of the substrate; if the substrate is made of germanium and the relaxed buffer layer is made of silicon, the lattice constant of the relaxed buffer layer in the relaxed state is less than the lattice constant of the substrate.

[0094] In an exemplary embodiment of the present application, as shown in FIG1A , the relaxed buffer layer 20 may include a first relaxed buffer layer 21 and a second relaxed buffer layer 22 , wherein the first relaxed buffer layer 21 is located between the substrate and the second relaxed buffer layer 22 , and the second relaxed buffer layer 22 is located between the first relaxed buffer layer 21 and the memory cell 110 ;

[0095] Along the direction from the substrate 10 to the second relaxed buffer layer 22 , the lattice constant of the first relaxed buffer layer 21 changes, and the lattice constant of the second relaxed buffer layer 22 remains unchanged;

[0096] Dislocations are present in both the first relaxed buffer layer 21 and the second relaxed buffer layer 22 , and the dislocation density in the first relaxed buffer layer 21 is greater than the dislocation density in the second relaxed buffer layer 22 .

[0097] In an exemplary embodiment of the present application, at least a region of the first relaxed buffer layer away from the substrate is a film layer in which strain is completely relaxed.

[0098] In an exemplary embodiment of the present application, the material of the substrate may be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide, and indium phosphide.

[0099] In an exemplary embodiment of the present application, the material of the relaxed buffer layer may be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide.

[0100] In an exemplary embodiment of the present application, the material of the semiconductor pillar may include any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium arsenide, indium arsenide, and indium phosphide.

[0101] In an exemplary embodiment of the present application, the host material of the semiconductor pillar can be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium arsenide, indium arsenide, and indium phosphide. The "host material" here refers to the doped "guest material." To obtain different resistivities, a small amount of impurity elements is typically doped into a semiconductor material. The semiconductor material is the host material, and the impurity elements doped into the semiconductor material are the guest material.

[0102] In an exemplary embodiment of the present application, the material of the substrate and the main material of the semiconductor pillar may both be silicon, and the material of the relaxed buffer layer may be silicon germanium.

[0103] In an exemplary embodiment of the present application, the material of the substrate may be silicon, the material of the relaxed buffer layer may be selected from any one or two of gallium arsenide, aluminum gallium arsenide and indium gallium arsenide, and the main material of the semiconductor column may be gallium arsenide or indium gallium arsenide.

[0104] In an exemplary embodiment of the present application, the semiconductor device may further include an isolation layer 30, which is located between the relaxed buffer layer and the memory cell and is configured to isolate the relaxed buffer layer from the memory cell. In the semiconductor device shown in FIG1 , a first insulating layer 31 is used as the isolation layer 30.

[0105] In an exemplary embodiment of the present application, as shown in FIG. 1A , the transistor 90 may further include a gate electrode 82 , which surrounds at least a portion of a sidewall of the semiconductor pillar 41 .

[0106] In an exemplary embodiment of the present application, as shown in FIG. 1A , a transistor 90 sequentially includes a first electrode region 42 , a channel region 43 , and a second electrode region 44 , and a gate electrode 82 surrounds at least a portion of a sidewall of the channel region 43 .

[0107] Here, surrounding can be understood as partial surrounding or full surrounding. In some embodiments, the surrounding can be full surrounding, that is, the entire side wall of the channel region is surrounded by the gate electrode, and the cross-section of the gate electrode after surrounding is a closed ring. The cross-section is intercepted along a direction perpendicular to the substrate and parallel to the second direction. For example, in some embodiments, the surrounding can be partial surrounding, that is, part of the side wall of the channel region is surrounded by the gate electrode, and the cross-section after surrounding is not closed, but presents a ring shape. For example, a ring with an opening or two independent semiconductor layers. For example, the opposite side surfaces of the channel region are surrounded by the gate electrode, and the cross-section of the gate electrode is a ring with two openings.

[0108] In an exemplary embodiment of the present application, the semiconductor pillar 41 may extend along a first direction parallel to the substrate 10. The first direction may be an X direction as shown in FIG1A and FIG1B.

[0109] In an exemplary embodiment of the present application, as shown in FIG. 1A , the memory cell 110 may further include a capacitor 100 , and the capacitor 100 is connected to the transistor 90 in the same memory cell 110 .

[0110] 1A and 1B , the semiconductor device may further include: a plurality of bit lines 70 extending in a direction perpendicular to the substrate 10. The direction perpendicular to the substrate 10 may be the Z direction as shown in FIG1A .

[0111] In an exemplary embodiment of the present application, as shown in FIG. 1A , transistors 90 of two columns of memory cells 110 located in different layers and adjacent to each other along the first direction may be connected to the same bit line 70 .

[0112] 1A and 1B , the semiconductor device may further include: a plurality of word lines 80 extending along a second direction parallel to the substrate 10. The second direction may be the Y direction as shown in FIG1B .

[0113] In an exemplary embodiment of the present application, as shown in FIG. 1B , transistors 90 of a column of memory cells 110 located in the same layer and arranged along the second direction may be connected to the same word line 80 .

[0114] The semiconductor layer can be understood as semiconductor material, where the emphasis is not on its shape and structure but only on its function.

[0115] In this application, separation can be understood as being separate and independent. Separation can be achieved through physical structural disconnection or electrical disconnection. For example, the semiconductor layer between the active channels of two transistors can be modified to achieve insulation to achieve electrical separation between the two channels.

[0116] In an exemplary embodiment of the present application, the electrode material of the gate electrode may be any one or more of the following different types of materials:

[0117] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it may be a metal alloy containing the aforementioned metals;

[0118] Alternatively, the material may be a metal oxide, metal nitride, metal silicide, metal carbide, or the like, such as metal oxide materials with high conductivity, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); or metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0119] Of course, it can also be polysilicon material; it can also be conductive material doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0120] In an exemplary embodiment of the present application, the gate insulating layer may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The following will exemplarily illustrate the characteristics of the gate insulating layer of the present application.

[0121] Low-K materials, such as silicon oxide.

[0122] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, they may include oxides of one or more of hafnium, aluminum, lanthanum, and zirconium. For example, they may include, but are not limited to, at least one of the following high-K materials: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2).

[0123] The above-mentioned memory cell may be a memory cell including a transistor, wherein the transistor may be an access transistor. The memory cell may further include other components, such as a capacitor in a 1T1C memory cell, or a read transistor and a storage node in a 2T0C memory cell.

[0124] In an exemplary embodiment of the present application, the dielectric layer may be made of silicon oxide or a High-K dielectric material, i.e., a dielectric material having a dielectric constant K ≥ 3.9. The High-K dielectric material may include, but is not limited to, at least one of the following: aluminum oxide (Al2O3) or hafnium oxide.

[0125] In an exemplary embodiment of the present application, the semiconductor device may be a 3D memory, such as a 3D DRAM, etc. The 3D memory may have a 1T1C or 2T (including a read transistor and a write transistor) structure.

[0126] An embodiment of the present application also provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a plurality of memory cells and a relaxed buffer layer; the plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to a substrate, and periodically distributed, and the memory cells include transistors.

[0127] The semiconductor device provided in the embodiment of the present application can be obtained by the manufacturing method.

[0128] FIG2 is a process flow chart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application.

[0129] As shown in FIG2 , the method for manufacturing the semiconductor device includes:

[0130] forming the relaxed buffer layer on the substrate, and making the relaxed buffer layer a relaxed film layer;

[0131] The plurality of memory cells are formed on a side of the relaxed buffer layer away from the substrate.

[0132] The manufacturing method of the semiconductor device described in the embodiment of the present application introduces a relaxed buffer layer between the substrate and the storage unit, which can reduce the lattice mismatch between the substrate and the epitaxial stack structure (such as the Si / SiGe stack structure) during the manufacturing process of the semiconductor device, thereby reducing the strain accumulation in the epitaxial stack structure. Under the same conditions, the number of layers that can be stacked in the epitaxial stack structure can be increased.

[0133] In addition, the introduction of the relaxed buffer layer can increase the tensile strain in the channel region of the transistor, thereby improving the electron mobility in the channel region and further increasing the operating speed of the transistor (eg, switching speed).

[0134] Moreover, the introduction of the relaxed buffer layer can reduce the strain accumulation of the epitaxial sacrificial layer (for example, the SiGe epitaxial sacrificial layer) in the epitaxial stack structure during the manufacturing process of semiconductor devices, so that under the same conditions, the critical thickness of the epitaxial sacrificial layer is increased, thereby obtaining a thicker epitaxial sacrificial layer, which can reduce the process difficulty of 3D semiconductor device processing.

[0135] In an exemplary embodiment of the present application, forming the relaxed buffer layer on the substrate and making the relaxed buffer layer a relaxed film layer may include:

[0136] A first relaxed buffer layer is grown on one side of the substrate using an epitaxial process; wherein the lattice constant of the first relaxed buffer layer varies along a direction from the substrate to the second relaxed buffer layer, the first relaxed buffer layer has dislocations, and a region of the first relaxed buffer layer away from the substrate is a film layer in which strain is completely relaxed;

[0137] A second relaxed buffer layer is grown on a side of the first relaxed buffer layer away from the substrate using an epitaxial process, and the lattice structure of the second relaxed buffer layer is consistent with the lattice structure of the first relaxed buffer layer away from the substrate; the first relaxed buffer layer and the second relaxed buffer layer constitute the relaxed buffer layer.

[0138] In an exemplary embodiment of the present application, forming the plurality of memory cells on a side of the relaxed buffer layer away from the substrate may include:

[0139] forming an isolation layer on a side of the relaxed buffer layer away from the substrate by using an epitaxial process;

[0140] Semiconductor layers and sacrificial layers are alternately grown on a side of the isolation layer away from the substrate using an epitaxial process to obtain a stacked structure consisting of alternating semiconductor layers and sacrificial layers.

[0141] In an exemplary embodiment of the present application, the lattice constant of the relaxed buffer layer in a relaxed state is different from the lattice constant of the substrate, and the lattice constant of the relaxed buffer layer in a relaxed state is between the lattice constants of the sacrificial layer and the semiconductor layer.

[0142] In an exemplary embodiment of the present application, forming the plurality of memory cells may further include: after obtaining the stacking structure,

[0143] A patterning process is performed on the semiconductor layer in the stacked structure so that the semiconductor layer forms a semiconductor column of the transistor, and a gate electrode is formed on at least a portion of a sidewall of the semiconductor column. The semiconductor column and the gate electrode constitute the transistor.

[0144] In an exemplary embodiment of the present application, the method for manufacturing the semiconductor device may further include: forming a capacitor connected to the transistor, wherein the transistor and the capacitor connected thereto constitute the memory cell.

[0145] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "composition process" mentioned in this embodiment includes processes such as depositing a film layer, applying a photoresist, mask exposure, development, etching, and stripping the photoresist, and is a mature preparation process in the relevant technology. The "photolithography process" mentioned in this embodiment includes coating a film layer, mask exposure, and development, and is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, and chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, and no specific limitations are made here.

[0146] FIG3A is a schematic longitudinal cross-sectional view of a semiconductor device provided in an exemplary embodiment of the present application after forming a first relaxed buffer layer; FIG3B is a top view of the semiconductor device shown in FIG3A; FIG4 is a schematic longitudinal cross-sectional view of a semiconductor device provided in an exemplary embodiment of the present application after CMP is performed on the surface of the first relaxed buffer layer; FIG5A is a schematic longitudinal cross-sectional view of a semiconductor device provided in an exemplary embodiment of the present application after forming a second relaxed buffer layer; FIG5B is a top view of the semiconductor device shown in FIG5A; FIG6A is a schematic longitudinal cross-sectional view of a semiconductor device provided in an exemplary embodiment of the present application after forming a stacked structure; FIG6B is a top view of the semiconductor device shown in FIG6A; FIG7 A is a schematic longitudinal cross-sectional view of a semiconductor device provided in an exemplary embodiment of the present application after forming a semiconductor column; Figure 7B is a top view of the semiconductor device shown in Figure 7A; Figure 8A is a schematic longitudinal cross-sectional view of a semiconductor device provided in an exemplary embodiment of the present application after forming a bit line; Figure 8B is a top view of the semiconductor device shown in Figure 8A; Figure 9A is a schematic longitudinal cross-sectional view of a semiconductor device provided in an exemplary embodiment of the present application after removing the sacrificial layer; Figure 9B is a top view of the semiconductor device shown in Figure 9A; Figure 10A is a schematic longitudinal cross-sectional view of a semiconductor device provided in an exemplary embodiment of the present application after forming a word line; Figure 10B is a top view of the semiconductor device shown in Figure 10A.

[0147] As shown in FIG. 3A to FIG. 10B and FIG. 1A and FIG. 1B , in an exemplary embodiment of the present application, the method for manufacturing the semiconductor device may include the following process.

[0148] S10 : providing a substrate 10 , and epitaxially growing a first relaxed buffer layer 21 on the substrate 10 .

[0149] Exemplarily, step S10 may include:

[0150] S11: providing a substrate 10 and performing surface treatment on the substrate 10, including but not limited to: baking the water vapor on the surface of the substrate 10 at a low temperature, then heating it to a high temperature and removing impurity elements such as C and O on the surface of the substrate 10 in a H2 atmosphere, so that the surface of the substrate 10 presents a clean and fresh Si atomic layer;

[0151] S12: epitaxially growing a first relaxed buffer layer 21 on the surface of the surface-treated substrate 10, comprising: first, at a certain temperature T1 (for example, T1 < 600°C), using polycarbonate activated silicon dioxide (DCS) and germanium (GeH4) as precursors to grow a Si layer of a certain thickness t1 (for example, t1 > 10 nm); 1-y Ge y , then raise the temperature to T2 (for example, T1≤T2≤850℃) and grow Si with a certain thickness t2 (for example, t2>100nm) 1-y Ge y , then maintain the temperature of T2 for annealing, so that Si 1-y Ge y The Si on the surface away from the substrate and the surface nearby 1-y Ge y The lattice constant of the film is close to or reaches that of crystalline Si 1-y Ge y Lattice constant, i.e. Si 1-y Ge y Surface Si 1-y Ge y The film is a film layer in which the strain is completely relaxed, and a first relaxed buffer layer 21 is obtained, as shown in FIG3A and FIG3B ; wherein, along the direction away from the substrate 10, the lattice constant of the first relaxed buffer layer 21 changes until the surface away from the substrate side and the Si near the surface 1-y Ge y The lattice constant of the film is close to or reaches that of crystalline Si 1-y Ge y Lattice constant.

[0152] Since strain relaxation will cause the roughness of the film surface to increase, as shown in FIG3A , the surface of the first relaxed buffer layer 21 has many protrusions. In this embodiment, the protrusions can be as high as tens of nanometers or even higher. In addition, the cross-sectional TEM image of the Si / Si 1-y Ge y A large number of dislocations (not shown) can be observed at the interface, which are gradually suppressed during the film growth process. The threading dislocation density on the surface of the first relaxed buffer layer 21 is about 1×10 6 pieces / cm 2 to 5×10 7 pieces / cm 2 .

[0153] S20 : ​​performing a planarization process on the surface of the first relaxed buffer layer 21 .

[0154] Exemplarily, step S20 may include:

[0155] S21: polishing the surface of the first relaxed buffer layer 21 using a chemical mechanical polishing (CMP) process. After polishing, the height of the protrusions on the surface of the first relaxed buffer layer 21 can be reduced to within a few nanometers. For example, the surface roughness (RMS) of the surface of the first relaxed buffer layer 21 is less than 2 nm.

[0156] S22: using organic reagents and inorganic reagents to repeatedly clean the surface of the polished first relaxed buffer layer 21. The cleaned first relaxed buffer layer 21 is shown in FIG4.

[0157] S30 : epitaxially growing a second relaxed buffer layer 22 on a side of the first relaxed buffer layer 21 away from the substrate 10 .

[0158] For example, step S30 may include: epitaxially growing Si with a certain thickness t3 (for example, t3 ≥ 10 nm) at a certain temperature T3 (T3 ≤ T2). 1-y Ge y layer, and make the Si 1-y Ge y The first relaxed buffer layer 21 is completely relaxed on the surface of the Si 1-y Ge y Lattice growth (ie, unstrained Si 1-y Ge y layer), a second relaxed buffer layer 22 is obtained, as shown in FIG5A and FIG5B; wherein the dislocation density in the second relaxed buffer layer 22 is significantly smaller than the dislocation density in the first relaxed buffer layer 21.

[0159] S40: epitaxially grow a first insulating layer 31 on a side of the second relaxed buffer layer 22 away from the substrate 10, and epitaxially grow a semiconductor layer 40 and a sacrificial layer 50 in an alternating manner on a side of the first insulating layer 31 away from the substrate 10, to obtain a stacked structure consisting of alternating semiconductor layers 40 and sacrificial layers 50.

[0160] Exemplarily, step S40 may include:

[0161] S41: epitaxial growth of a first insulating layer 31, comprising: performing Si epitaxial growth on a side of the second relaxed buffer layer 22 away from the substrate 10 using DCS as a precursor at a temperature T3, to obtain a first insulating layer 31 formed of a Si epitaxial layer, wherein the thickness of the first insulating layer 31 is t4 (e.g., 5 nm ≤ t4 ≤ 100 nm); the first insulating layer 31 serves as an isolation layer between the second relaxed buffer layer 22 and the stacked structure for insulation;

[0162] S42: epitaxial growth of the stacked structure, including: continuing to maintain the temperature at T3, using DCS and GeH4 as precursors to staggered epitaxial growth of Si on the side of the first insulating layer 31 away from the substrate 10 1-x Ge x (y≤x) and Si superlattice structure, Si / Si 1-x Ge x Stacked structure; wherein the Si epitaxial layer is used as the semiconductor layer 40 for subsequently forming the source / drain electrodes and channel of the transistor; Si 1-x Ge x The epitaxial layer is a strained layer, serving as a sacrificial layer 50 , as shown in FIG. 6A and FIG. 6B .

[0163] Since the stacking structure is in the relaxed Si 1-y Ge y The coherent epitaxial formation is carried out on the layer, and the stacking structure is relatively relaxed Si 1-y Ge y The lattice mismatch of the layer is smaller than the mismatch of the stacked structure relative to the Si substrate, so the strain accumulation in the stacked structure will be greatly reduced, which means that the critical thickness of the stacked structure that can achieve co-lattice growth is increased. Therefore, the solution of the embodiment of the present application can further increase the number of stacking layers of the Si / SiGe stacked structure, thereby improving the storage density of 3D semiconductor devices.

[0164] S50 : performing patterned etching on the stack structure to form first trenches 61 and second trenches 62 penetrating through the semiconductor layers 40 in the stack structure to obtain a patterned stack structure; and filling the first trenches 61 and the second trenches 62 with a second insulating layer 32 .

[0165] Exemplarily, step S50 may include:

[0166] S51: using a photolithography method to define a pattern of first trenches 61 and second trenches 62 to be formed on the top surface of the stack structure away from the substrate 10, and etching the stack structure in a direction toward the substrate 10 to form a plurality of first trenches 61 and a plurality of second trenches 62 penetrating each semiconductor layer 40 in the stack structure; wherein each first trench 61 extends in a direction perpendicular to the substrate 10 and in a first direction parallel to the substrate 10, and the plurality of first trenches 61 are spaced apart along a second direction parallel to the substrate 10, and the plurality of first trenches 61 space the semiconductor layers 40 into a plurality of semiconductor pillars 41 extending in the first direction and spaced apart in the second direction; each second trench 62 extends in a direction perpendicular to the substrate 10 and in the second direction, and the plurality of second trenches 62 are spaced apart along the first direction;

[0167] The first direction may be the X direction as shown in FIG7A and FIG7B , the second direction may be the Y direction as shown in FIG7B , and the direction perpendicular to the substrate 10 may be the Z direction as shown in FIG7A ; the first trench 61 and the second trench 62 may expose the first insulating layer 31 , for example, the first trench 61 and the second trench 62 may extend to the surface or the interior of the first insulating layer 31 away from the substrate 10 ;

[0168] S52: Fill the first trench 61 and the second trench 62 with the second insulating layer 32, as shown in Figures 7A and 7B. The second insulating layer 32 is used to separate two adjacent columns of memory cells along the first direction and to separate memory cells located in different layers.

[0169] Exemplarily, the material of the second insulating layer 32 can be a low-K dielectric material, that is, a dielectric material with a dielectric constant K<3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing films, and also including air (that is, forming an air gap).

[0170] S60 : etching to form a bit line hole in the semiconductor pillar 41 , and forming a bit line 70 in the bit line hole.

[0171] Exemplarily, step S60 may include: etching the patterned stack structure along a direction toward the substrate 10, forming bit line holes in the patterned stack structure that penetrate the semiconductor pillars 41 of different layers, forming bit lines 70 in the bit line holes, and connecting the bit lines 70 to the semiconductor pillars 41, as shown in Figures 8A and 8B.

[0172] Exemplarily, there may be a bit line hole between two adjacent second trenches 62 in the first direction; the bit line hole may extend in a direction perpendicular to the substrate 10 and expose the first insulating layer 31. For example, the bit line hole may extend to the surface or interior of the first insulating layer 31 away from the substrate 10, and the formed bit line 70 also extends in a direction perpendicular to the substrate 10.

[0173] For example, the material of the bit line can be selected from any one or more metal materials having similar properties, such as tungsten, molybdenum, and cobalt. The bit line can have a single-layer or multi-layer structure, for example, a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0174] S70 : etching and removing the sacrificial layer 50 .

[0175] Exemplarily, step S70 may include: defining a photolithography pattern using a photolithography method, etching away the second insulating layer 32 in the first trench 61, and exposing the sidewall of the first trench 61 to the sacrificial layer 50 in the patterned stacked structure; removing the sacrificial layer 50 using a selective etching process; and filling the space vacated after etching away the sacrificial layer 50 and the first trench 61 with the second insulating layer 32, as shown in Figures 9A and 9B.

[0176] S80: forming word lines and gate electrodes of transistors.

[0177] A semiconductor pillar 41 between two adjacent second trenches 62 is subsequently used to form two transistors 90 connected to the same bit line 70. As shown in FIG10A , along a direction away from the bit line 70, the semiconductor pillar 41 includes, in sequence, a first electrode region 42, a channel region 43, a second electrode region 44, and a third electrode region 45. One of the first electrode region 42 and the second electrode region 412 serves as the source electrode of the transistor, the other serves as the drain electrode of the transistor, and the third electrode region 45 serves as the inner electrode of the capacitor connected to the transistor. The transistor is connected to the bit line 70 via the first electrode region 42, and the transistor is connected to the third electrode region of the capacitor via the second electrode region 44.

[0178] Exemplarily, step S80 may include:

[0179] S81: using photolithography to define a photolithographic pattern, and etching away the second insulating layer 32 in a portion of the first trench 61 to expose at least a portion of the sidewall of the channel region 43 of the semiconductor pillar 41;

[0180] S82: depositing a gate insulating layer 81 and a gate electrode 82 in sequence on the exposed sidewalls of the channel region 43 to form the gate insulating layer 81 and the gate electrode 82 surrounding at least a portion of the sidewalls of the channel region 43. The semiconductor pillar 41 and the gate electrode 82 constitute a transistor 90.

[0181] S83: Connect the gate electrodes 82 of multiple transistors located in the same layer and spaced apart along the second direction to form a word line 80 extending along the second direction, with the gate electrodes 82 of the transistors serving as part of the word line 80, as shown in Figures 10A and 10B; or, form a separate word line 80 extending along the second direction, and connect the gate electrodes 82 of a column of transistors located in the same layer and spaced apart along the second direction to the same word line 80.

[0182] Exemplarily, step S81 may further include: after exposing at least a portion of the sidewall of the channel region 43 of the semiconductor pillar 41 and before performing step S82,

[0183] A selective etching process is used to remove the second insulating layer 32 between the semiconductor pillars 41 of different layers, exposing the entire sidewalls of the channel regions 43 of the semiconductor pillars 41 ;

[0184] Step S82 may include: sequentially depositing a gate insulating layer 81 and a gate electrode 82 on the entire exposed sidewall surface of the channel region 43 of the semiconductor pillar 41 to form the gate insulating layer 81 and the gate electrode 82 that completely surround the channel region 43 .

[0185] Step S80 may further include: after step S83,

[0186] S84 : filling the gaps between adjacent semiconductor pillars 41 with a second insulating layer 32 .

[0187] S90: forming a capacitor.

[0188] Exemplarily, step S90 may include:

[0189] S91: using photolithography to define a photolithographic pattern, and etching away the second insulating layer 32 in a portion of the first trench 61 to expose at least a portion of the sidewall of the third electrode region 45 of the semiconductor pillar 41;

[0190] S92: A dielectric layer 101 and a fourth electrode layer 102 are sequentially deposited on the exposed side walls of the third electrode region 45 to form a dielectric layer 101 and a fourth electrode layer 102 surrounding at least part of the side walls of the third electrode region 45. The third electrode region 45, the dielectric layer 101 and the fourth electrode layer 102 constitute a capacitor 100. The fourth electrode layer 102 surrounding the third electrode region 45 serves as an external electrode of the capacitor 100. The transistor 90 and the capacitor 100 constitute a storage unit 110, thereby obtaining a semiconductor device as shown in Figures 1A and 1B.

[0191] Exemplarily, step S91 may further include: after exposing at least a portion of the sidewall of the third electrode region 45 of the semiconductor pillar 41 and before performing step S92,

[0192] A selective etching process is used to remove the second insulating layer 32 between the semiconductor pillars 41 of different layers, exposing the entire sidewall of the third electrode region 45 of the semiconductor pillar 41;

[0193] Step S92 may include: sequentially depositing a dielectric layer 101 and a fourth electrode layer 102 on the entire exposed sidewall surface of the third electrode region 45 of the semiconductor pillar 41 to form the dielectric layer 101 and the fourth electrode layer 102 completely surrounding the third electrode region 45 .

[0194] Exemplarily, step S90 may further include: after step S92,

[0195] S93 : using a second insulating layer 32 to fill gaps between adjacent semiconductor pillars 41 , so that two adjacent memory cells 110 located in different layers and two adjacent memory cells 110 located in the same layer and spaced apart along the second direction are insulated by the second insulating layer 32 .

[0196] For example, the material of the second insulating layer 32 is not limited to one type, that is, the material of the second insulating layer 32 used in each step may be the same or different.

[0197] An embodiment of the present application further provides an electronic device, which includes the semiconductor device provided in the above embodiment of the present application.

[0198] In an exemplary embodiment of the present application, the electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0199] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A semiconductor device, comprising: A plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to the substrate and distributed periodically; each layer includes a plurality of columns of memory cells; A relaxed buffer layer is located between the substrate and the memory cell.

2. The semiconductor device according to claim 1, wherein The lattice constant of the relaxed buffer layer in a relaxed state is different from the lattice constant of the substrate.

3. The semiconductor device according to claim 1, wherein The relaxed buffer layer includes a first relaxed buffer layer and a second relaxed buffer layer, the first relaxed buffer layer is located between the substrate and the second relaxed buffer layer, and the second relaxed buffer layer is located between the first relaxed buffer layer and the storage unit; Along a direction away from the substrate, the lattice constant of the first relaxed buffer layer changes, and the lattice constant of the second relaxed buffer layer remains unchanged; Dislocations are present in both the first relaxed buffer layer and the second relaxed buffer layer, and a dislocation density in the first relaxed buffer layer is greater than a dislocation density in the second relaxed buffer layer.

4. The semiconductor device according to claim 3, wherein: The first relaxed buffer layer is a film layer in which strain is completely relaxed at least in a region on a side away from the substrate.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The material of the substrate is selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide and indium phosphide; and / or, The material of the relaxed buffer layer is selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide; and / or, The memory cell includes a transistor, and the transistor includes a semiconductor column; a main material of the semiconductor column is selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide.

6. The semiconductor device according to claim 5, wherein: The material of the substrate and the main material of the semiconductor pillar are both silicon, and the material of the relaxed buffer layer is silicon germanium; or, The material of the substrate is silicon, the material of the relaxed buffer layer is selected from any one or more of gallium arsenide, aluminum gallium arsenide and indium gallium arsenide, and the main material of the semiconductor column is gallium arsenide or indium gallium arsenide.

7. The semiconductor device according to claim 5, wherein: The semiconductor device further includes an isolation layer, which is located between the relaxed buffer layer and the memory cell and is configured to isolate the relaxed buffer layer from the memory cell; and / or, The transistor further comprises a gate electrode, wherein the gate electrode surrounds at least a portion of a sidewall of the semiconductor pillar; and / or, The semiconductor pillar extends along a first direction parallel to the substrate; and / or, The memory cell further comprises a capacitor connected to the transistor in the same memory cell; and / or, The semiconductor device further comprises: a plurality of bit lines extending in a direction perpendicular to the substrate; and / or, The transistors of two columns of the memory cells located in different layers and adjacent to each other along the first direction are connected to the same bit line; The semiconductor device further comprises: a plurality of word lines extending along a second direction parallel to the substrate; and / or, The transistors of a column of the memory cells located in the same layer and arranged along the second direction are connected to the same word line.

8. A method for manufacturing a semiconductor device, the semiconductor device comprising a plurality of memory cells and a relaxed buffer layer; the plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to a substrate and distributed periodically, and the memory cells comprise transistors; The method for manufacturing the semiconductor device comprises: forming the relaxed buffer layer on the substrate, and making the relaxed buffer layer a relaxed film layer; The plurality of memory cells are formed on a side of the relaxed buffer layer away from the substrate.

9. The manufacturing method according to claim 8, wherein: Forming the relaxed buffer layer on the substrate and making the relaxed buffer layer a relaxed film layer comprises: A first relaxed buffer layer is grown on one side of the substrate by using an epitaxial process; wherein the lattice constant of the first relaxed buffer layer changes along a direction away from the substrate, dislocations are present in the first relaxed buffer layer, and a region of the first relaxed buffer layer on a side away from the substrate is a film layer in which strain is completely relaxed; A second relaxed buffer layer is grown on a side of the first relaxed buffer layer away from the substrate using an epitaxial process, and the lattice structure of the second relaxed buffer layer is consistent with the lattice structure of the first relaxed buffer layer away from the substrate; the first relaxed buffer layer and the second relaxed buffer layer constitute the relaxed buffer layer.

10. The manufacturing method according to claim 9, wherein: Forming the plurality of memory cells on a side of the relaxed buffer layer away from the substrate comprises: forming an isolation layer on a side of the relaxed buffer layer away from the substrate by using an epitaxial process; Semiconductor layers and sacrificial layers are alternately grown on a side of the isolation layer away from the substrate by using an epitaxial process, so as to obtain a stacked structure consisting of alternating semiconductor layers and sacrificial layers.

11. The manufacturing method according to claim 10, wherein: The lattice constant of the relaxed buffer layer in a relaxed state is different from the lattice constant of the substrate, and the lattice constant of the relaxed buffer layer in a relaxed state is between the lattice constants of the sacrificial layer and the semiconductor layer.

12. The manufacturing method according to claim 10, wherein: Forming the plurality of storage units further comprises: after obtaining the stacking structure, Performing a patterning process on the semiconductor layer in the stacked structure so that the semiconductor layer forms a semiconductor column of the transistor, and forming a gate electrode on at least a portion of the sidewall of the semiconductor column, wherein the semiconductor column and the gate electrode constitute the transistor; and / or The method for manufacturing the semiconductor device further includes: forming a capacitor connected to the transistor, wherein the transistor and the capacitor connected thereto constitute the memory cell.

13. An electronic device comprising the semiconductor device according to any one of claims 1 to 7.

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