Scan driving circuit, scan driving method, and display apparatus

Abstract

A scan driving circuit, a scan driving method, and a display apparatus. A pull-up unit (102) is provided with a first switch unit (T1) and a second switch unit (T2), a control end of the first switch unit (T1) is connected to a second output end (P) of a logic control unit (101), a first end thereof is connected to a voltage signal source, a second end thereof is connected to a first node (N1), and the first switch unit (T1) is turned on when the second output end (P) of the logic control unit (101) is at a high level; a control end of the second switch unit (T2) is connected to a third node (N3), a first end thereof is connected to a second node (N2), a second end thereof is connected to the second output end (P) of the logic control unit (101), and the second switch unit (T2) is turned on when a clock signal is at a high level. The voltage signal source provides a first end of the first switch unit (T1) with a preset level signal (VM) having a level less than a high level of the clock signal and higher than a low level of the clock signal, and the preset level signal (VM) is used to pull up the level of the first node (N1) in advance, so that the problem of insufficient effective charging time of a scan transistor (S-TFT) caused by a level switch delay can be improved and the potential coupling effect of parasitic capacitance (C') can be reduced.

Description

Scan driving circuit, scan driving method and display device

[0001] Related applications

[0002] This application claims priority to Chinese patent application number 2023111346695 filed on September 5, 2023, entitled “Scanning driving circuit, scanning driving method and display device”, and the entire contents of the Chinese patent application are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of display technology, and in particular to a scan driving circuit, a scan driving method and a display device. Background Art

[0004] The scan signal, as an input signal to the pixel cells, controls the on / off state of the corresponding scan transistors. When the scan transistors in a row are turned on, the data voltage is applied to the pixels in that row, thereby displaying a specific image. However, when the scan signal switches from a low-level VSS to a high-level VDD, there is a switching delay, which results in insufficient time for the scan transistors to effectively charge, affecting the display quality.

[0005] Summary of the Invention

[0006] The present application provides a scan driving circuit, a scan driving method and a display device.

[0007] According to one aspect of an embodiment of the present application, a scan driving circuit is disclosed, comprising a plurality of scan driving modules, each of which comprises a logic control unit, a pull-up unit, and a pull-down unit, wherein the pull-down unit is connected to a first output terminal of the logic control unit and a first node.

[0008] The pull-up unit includes a pull-up switch unit, a bootstrap capacitor, a first switch unit and a second switch unit, the control end of the pull-up switch unit is connected to the second node, the first end of the pull-up switch unit is connected to the third node, the third node is configured to receive a clock signal, and the second end of the pull-up switch unit is connected to the first node; one end of the bootstrap capacitor is connected to the first node, and the other end is connected to the second node; the control end of the first switch unit is connected to the second output end of the logic control unit, the first end of the first switch unit is connected to a voltage signal source, and the voltage signal source is used to provide a preset level signal, the preset level signal is less than the high level of the clock signal and greater than the low level of the clock signal, the second end of the first switch unit is connected to the first node; the control end of the second switch unit is connected to the third node, the first end of the second switch unit is connected to the second node, and the second end of the second switch unit is connected to the second output end of the logic control unit.

[0009] In which, the first switch unit is configured to be turned on when the second output terminal of the logic control unit is at a high level, so as to pull the potential of the first node to the preset level signal, and the second switch unit is configured to be turned on when the clock signal is at a high level, so as to pull the potential of the first node to the high level of the clock signal.

[0010] The scan drive circuit disclosed in the present application has a pull-up unit provided with a first switch unit and a second switch unit. The control end of the first switch unit is connected to the second output end of the logic control unit, the first end is connected to the voltage signal source, and the second end is connected to the first node. The first switch unit is turned on when the second output end of the logic control unit is at a high level; the control end of the second switch unit is connected to the third node, the first end is connected to the second node, and the second end is connected to the second output end of the logic control unit. The second switch unit is turned on when the clock signal is at a high level. A preset level signal, which is less than the high level of the clock signal and greater than the low level of the clock signal, is provided to the first end of the first switch unit through the voltage signal source. The preset level signal is used to pull up the level of the first node in advance, thereby reducing the voltage difference between the level of the first node and the high level of the clock signal. When the scan signal of the first node needs to be switched to the high level of the clock signal, the problem of insufficient effective charging time of the scan transistor caused by the level switching delay can be improved. At the same time, the influence of the parasitic capacitance on the potential coupling of other nodes is reduced, thereby improving the picture display effect.

[0011] According to one aspect of an embodiment of the present application, a scanning driving method is disclosed, which is used for the aforementioned scanning driving circuit. The scanning driving method includes: when the second output terminal of the logic control unit is at a high level and the clock signal is at a low level, causing the voltage signal source to output a preset level signal to the first terminal of the first switching unit.

[0012] The technical solutions provided by the embodiments of the present application include at least the following beneficial effects:

[0013] The scanning driving method disclosed in the present application enables the voltage signal source to output a preset level signal to the first end of the first switching unit when the second output terminal of the logic control unit is at a high level and the clock signal is at a low level. This can reduce the voltage difference between the level of the first node and the high level of the clock signal in advance before the high level of the clock signal arrives, thereby improving the problem of insufficient effective charging time of the scanning transistor caused by the level switching delay. At the same time, it reduces the influence of the parasitic capacitance on the potential coupling of other nodes, thereby improving the picture display effect.

[0014] It should be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0016] FIG. 1 schematically shows a composition diagram of an OLED display.

[0017] FIG. 2 shows a circuit diagram of a conventional scan driving circuit.

[0018] FIG3 shows a driving waveform diagram of a conventional scan driving circuit.

[0019] FIG4 schematically shows a circuit diagram of a pixel unit.

[0020] FIG5 schematically shows a circuit diagram of a scan driving circuit provided in an embodiment of the present application.

[0021] FIG6 schematically shows a driving waveform diagram of a scan driving circuit according to an embodiment of the present application.

[0022] FIG. 7 schematically shows a comparison of voltage fluctuations during level switching using the present application and the prior art.

[0023] FIG8 schematically shows a schematic diagram of the structural composition of a display device provided in an embodiment of the present application.

[0024] The following are the descriptions of the reference numerals:

[0025] 10. Scan drive module; 101. Logic control unit; Q, first output terminal; P, second output terminal; 102. Pull-up unit; M1, pull-up switch unit; C, bootstrap capacitor; T1, first switch unit; T2, second switch unit; N1, first node; N2, second node; N3, third node; 103. Pull-down unit; M2, pull-down switch unit; 100. Drive circuit; 20. Timing controller; 30. Data drive circuit; 40. Power supply circuit; 200. Display panel; S-TFT, scan transistor; D-TFT, drive transistor; Cst, first capacitor; OLED, sub-pixel; C', parasitic capacitor. DETAILED DESCRIPTION

[0026] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0027] In the description of the present application, unless otherwise specified, “plurality” means two or more.

[0028] Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or to implicitly specify the quantity of the technical features indicated. Thus, a feature designated "first," "second," or "third" may explicitly or implicitly include one or more features.

[0029] OLED (Organic Light-Emitting Diode) displays have fast response speed and wide viewing angle, and can produce brightness with high luminous efficiency. OLED includes an anode electrode, a cathode electrode, and an organic compound layer formed between the anode electrode and the cathode electrode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). Once a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light-emitting layer (EML), thereby forming excitons, and the light-emitting layer (EML) generates visible light.

[0030] The structure of an OLED display is shown in FIG1 , which generally includes a display panel and a driving circuit. The display panel is provided with pixel units (R, G, B) and necessary wiring. The driving circuit includes a timing controller 20 (i.e., TCON), a scan driving circuit, a data driving circuit 30, and a power supply circuit 40. The scan driving circuit is used to output a scan signal. The scan signal serves as an input signal of the pixel unit and is used to control the on-off state of the scan transistor corresponding to each pixel unit. When the scan transistor on a certain row is turned on, the data voltage can act on the pixel unit on the row, thereby realizing the picture display.

[0031] The structure of a conventional scan drive circuit is shown in Figure 2, which includes a logic control part and an output part. The logic control part is used to receive a trigger signal IN (i.e., a scan signal) and output a corresponding high-level signal or a low-level signal to the output part based on the received trigger signal. The output part includes a pull-up circuit and a pull-down circuit, wherein the pull-up circuit is composed of a pull-up transistor M1 and a bootstrap capacitor C. The output end of the pull-up transistor M1 serves as the scan signal output node, and its output state can be switched between the low level VSS of the clock signal CK and the high level VDD of the clock signal CK. The pull-down circuit is composed of a pull-down transistor M2.

[0032] However, when the scan signal switches from a low level VSS to a high level VDD, the switching delay causes insufficient effective charging time for the scan transistor S-TFT (as shown in FIG4 ). This results in insufficient opening of the scan transistor S-TFT, which may result in incomplete writing of the data voltage VData, affecting the display brightness. Furthermore, the parasitic capacitance C' may also have a coupling effect on the potentials of other nodes, such as the gate-drain potential of the scan transistor S-TFT and the drain-source potential of the drive transistor D-TFT. This adversely affects the display quality of the display.

[0033] To solve the above problems, one embodiment of the present application provides a scan driving circuit, which includes multiple scan driving modules 10, each of which is used to drive a row of pixel units. As shown in Figure 5, the scan driving module 10 includes a logic control unit 101 and an output unit.

[0034] The logic control unit 101 is configured to receive a scan signal and output a corresponding high-level signal or low-level signal based on the received scan signal. The logic control unit 101 has a first output terminal Q and a second output terminal P. The output levels of the first output terminal Q and the second output terminal P are opposite. When the first output terminal Q outputs a low level, the second output terminal P outputs a high level, causing the scan signal output node of the output unit to be high, thereby turning on the scan transistors on the corresponding row. When the first output terminal Q outputs a high level, the second output terminal P outputs a low level, causing the scan signal output node of the output unit to be low, thereby turning off the scan transistors on the corresponding row.

[0035] Multiple scan driving modules 10 are cascaded, and the logic control units 101 of at least some of the scan driving modules 10 are configured to output a corresponding low-level signal or a high-level signal to the second output terminal P based on the scan signal of the previous-level scan driving module 10, and to output a corresponding low-level signal or a high-level signal to the first output terminal Q based on the scan signal of the next-level scan driving module 10. Exemplarily, before the scan signal (here specifically a high-level scan signal) of the previous-level scan driving module 10 arrives, the second output terminal P of the logic control unit 101 outputs a low level and the first output terminal Q outputs a high level. At this time, the scan transistor on the row corresponding to the current scan driving module 10 is turned off; when the scan signal (here specifically a high-level scan signal) of the previous-level scan driving module 10 arrives, the potentials of the second output terminal P and the first output terminal Q of the logic control unit 101 are reversed, the second output terminal P of the logic control unit 101 outputs a high level and the first output terminal Q outputs a low level. At this time, the scan transistor on the row corresponding to the current scan driving module 10 is turned on; when the scan signal (here specifically a high-level scan signal) of the next-level scan driving module 10 arrives, the potentials of the second output terminal P and the first output terminal Q of the logic control unit 101 are reversed again, the second output terminal P of the logic control unit 101 outputs a low level and the first output terminal Q outputs a high level. At this time, the scan transistor on the row corresponding to the current scan driving module 10 is turned off.

[0036] It should be noted that the logic control unit 101 may have a first input terminal (not shown in the figure) and a second input terminal (not shown in the figure). The first input terminal may be connected to a scan signal output node of the next-stage scan driver module 10, and the second input terminal may be connected to a scan signal output node of the previous-stage scan driver module 10. When the second input terminal receives a high-level scan signal from the previous-stage scan driver module 10, the second output terminal P of the logic control unit 101 outputs a high level, and the first output terminal Q outputs a low level. When the first input terminal receives a high-level scan signal from the next-stage scan driver module 10, the first output terminal Q of the logic control unit 101 outputs a high level, and the second output terminal P outputs a low level.

[0037] For the scan driver module 10 at the first level, its second input terminal can be connected to a timing controller. The second input terminal receives a trigger signal output by the timing controller, thereby outputting a high-level scan signal to turn on the scan transistors on the corresponding row. For the scan driver module 10 at the last level, a redundant scan driver module can be connected to turn off the scan transistors on the last row.

[0038] The logic control unit 101 may adopt any existing logic control unit structure as long as it can implement the present application, and the specific composition structure of the logic control unit 101 will not be described in further detail here.

[0039] In the aforementioned embodiment, multiple scan driving modules 10 are cascaded, and the logic control unit 101 outputs corresponding low-level signals or high-level signals based on the scan signals of the upper-level scan driving module 10 and the lower-level scan driving module 10. This is only an exemplary embodiment of the present application and is not limited to this in actual implementation.

[0040] 5 , the output unit includes a pull-up unit 102 and a pull-down unit 103 .

[0041] The pull-up unit 102 includes a pull-up switch unit M1, a bootstrap capacitor C, a first switch unit T1, and a second switch unit T2, and includes a first node N1, a second node N2, and a third node N3. The first node N1 serves as a scan signal output node of the scan driver module 10, outputting a scan signal Scan. The third node N3 serves as a clock signal input node, configured to receive a clock signal CK.

[0042] The pull-up switch unit M1 has a control terminal, a first terminal, and a second terminal. The control terminal of the pull-up switch unit M1 is connected to the second node N2, the first terminal of the pull-up switch unit M1 is connected to the third node N3, and the second terminal of the pull-up switch unit M1 is connected to the first node N1. When the pull-up switch unit M1 is fully turned on, the potential of the first node N1 is equal to the potential of the third node N3, that is, the potential of the first node N1 is equal to the high potential of the clock signal. At this time, the scan driver module 10 outputs a high potential scan signal VDD.

[0043] In this embodiment, the pull-up switch unit M1 is a pull-up transistor, the control terminal corresponds to the gate of the pull-up transistor, and the first terminal and the second terminal correspond to the source and drain of the pull-up transistor, respectively. The pull-up transistor is preferably a MOS transistor, which has strong anti-interference capabilities, low power consumption, and simple control.

[0044] In one embodiment, the pull-up switch unit M1 is a thin film transistor, which has a fast response time and consumes less power, thereby helping to achieve a good picture display effect.

[0045] Optionally, the pull-up switch unit M1 may also be a switch unit of other forms.

[0046] The first switch unit T1 has a control terminal, a first terminal, and a second terminal. The control terminal of the first switch unit T1 is connected to the second output terminal P of the logic control unit 101, the first terminal of the first switch unit T1 is connected to a voltage signal source, and the second terminal of the first switch unit T1 is connected to a first node N1. The voltage signal source is used to provide a preset level signal VM. The preset level signal VM is less than the high level VDD of the clock signal CK and greater than the low level VSS of the clock signal CK. When the second output terminal P of the logic control unit 101 is at a high level, the first switch unit T1 is turned on, raising the potential of the first node N1 to the preset level signal VM. When the second output terminal P of the logic control unit 101 is at a low level, the first switch unit T1 is turned off, and the preset level signal VM cannot be output to the first node N1 through the first switch unit T1.

[0047] In this embodiment, the first switch unit T1 is a transistor, the control terminal corresponds to the gate of the transistor, and the first terminal and the second terminal correspond to the source and drain of the transistor, respectively. The transistor is preferably a MOS transistor, which has strong anti-interference ability, low power consumption, and simple control method.

[0048] In one embodiment, the first switch unit T1 is a thin film transistor, which has a fast response time and consumes less power, thereby helping to achieve a good picture display effect.

[0049] Optionally, the first switch unit T1 may also be a switch unit of other forms.

[0050] In this embodiment, the preset level signal VM is less than the turn-on voltage of the scanning transistor in the pixel unit, wherein the control terminal of the scanning transistor is connected to the first node N1. Setting the preset level signal VM to be less than the turn-on voltage of the scanning transistor in the pixel unit can prevent the preset level signal VM from prematurely turning on the scanning transistor in the pixel unit, which may cause abnormal image display.

[0051] In some embodiments, other mechanisms may be provided to prevent the scanning transistor in the pixel unit from being turned on prematurely. In this case, the preset level signal VM may be greater than or equal to the turn-on voltage of the scanning transistor in the pixel unit.

[0052] Optionally, the preset level signal VM may be a fixed level signal, and when the first switch unit T1 is turned on, the potential of the first node N1 is pulled up to the fixed level.

[0053] Optionally, the preset level signal VM may include multiple level signals with different amplitudes. For example, the preset level signal VM includes a first level signal and a second level signal greater than the first level signal. Accordingly, the period during which the second output terminal P of the logic control unit 101 is at a high level and the clock signal CK is at a low level includes a first period and a second period later than the first period. The voltage signal source is configured to provide the first level signal during the first period and the second level signal during the second period. For another example, the preset level signal VM includes a first level signal, a second level signal, and a third level signal. The amplitudes of the first level signal, the second level signal, and the third level signal increase in sequence. Accordingly, the period during which the second output terminal P of the logic control unit 101 is at a high level and the clock signal CK is at a low level includes a first period, a second period, and a third period. The time corresponding to the first period, the second period, and the third period is sequentially delayed. The voltage signal source is configured to provide the first level signal during the first period, the second level signal during the second period, and the third level signal during the third period. Through this configuration, the potential of the first node N1 can be raised in stages.

[0054] In one embodiment, the voltage signal source is a timing controller, which outputs the preset level signal VM through an idle output channel of the timing controller without adding any additional electronic components. Of course, the voltage signal source can also be an additional voltage source.

[0055] The second switch unit T2 has a control terminal, a first terminal, and a second terminal. The control terminal of the second switch unit T2 is connected to the third node N3, the first terminal of the second switch unit T2 is connected to the second node N2, and the second terminal of the second switch unit T2 is connected to the second output terminal P of the logic control unit 101. When the clock signal CK is at a high level, the second switch unit T2 is turned on to turn on the pull-up switch unit M1, thereby pulling the potential of the first node N1 up to the high level VDD of the clock signal CK. When the clock signal CK is at a low level, the second switch unit T2 is turned off, and the pull-up switch unit M1 is turned off, so that the high level VDD of the clock signal CK cannot be output to the first node N1 via the pull-up switch unit M1.

[0056] In this embodiment, the second switch unit T2 is a transistor, the control terminal corresponds to the gate of the transistor, and the first terminal and the second terminal correspond to the source and drain of the transistor, respectively. The transistor is preferably a MOS transistor, which has strong anti-interference ability, low power consumption, and simple control method.

[0057] In one embodiment, the second switch unit T2 is a thin film transistor, which has a fast response time and consumes less power, thereby helping to achieve a good picture display effect.

[0058] Optionally, the second switch unit T2 may also be a switch unit of other forms.

[0059] One end of the bootstrap capacitor C is connected to the first node N1 , and the other end is connected to the second node N2 .

[0060] 5 , the pull-down unit 103 is connected to the first output terminal Q of the logic control unit 101 and the first node N1 , and is configured to pull down the potential of the first node N1 .

[0061] In this embodiment, the pull-down unit 103 includes a pull-down switch unit M2, which has a control terminal, a first terminal, and a second terminal. The control terminal of the pull-down switch unit M2 is connected to the first output terminal Q of the logic control unit 101, the first terminal of the pull-down switch unit M2 is connected to the first node N1, and the second terminal of the pull-down switch unit M2 is connected to the common ground terminal, i.e., VSS. When the first output terminal Q of the logic control unit 101 is high, the pull-down switch unit M2 is turned on, pulling the voltage level of the first node N1 down to the voltage level of the common ground terminal, i.e., pulling the voltage level of the first node N1 down to the low level VSS of the clock signal.

[0062] In this embodiment, the pull-down switch unit M2 is a pull-down transistor, the control terminal corresponds to the gate of the pull-down transistor, and the first terminal and the second terminal correspond to the source and drain of the pull-down transistor, respectively. The pull-down transistor is preferably a MOS transistor, which has strong anti-interference capabilities, low power consumption, and simple control.

[0063] In one embodiment, the pull-down switch unit M2 is a thin film transistor, which has a fast response time and consumes less power, thereby helping to achieve a good picture display effect.

[0064] Optionally, the pull-down switch unit M2 may also be a switch unit of other forms.

[0065] The working principle of the pull-up unit 102 is described below with reference to FIG5 and FIG6 :

[0066] At time t0, the second output terminal P is at a low level VSS, the first switch unit T1 is turned off, and the preset level signal VM cannot be output to the first node N1 via the first switch unit T1. The first node N1 is at a low level, so the scan signal Scan is at a low level VSS. At time t1, the second output terminal P is at a high level V1, the clock signal CK is at a low level VSS, the first switch unit T1 is turned on, and the second switch unit T2 is turned off. The preset level signal VM is output to the first node N1 via the first switch unit T1, so the scan signal Scan is at the preset level signal VM. At time t2, the second output terminal P is still at a high level, the clock signal CK is also at a high level, the first switch unit T1, the second switch unit T2, and the pull-up switch unit M1 are all turned on, and under the action of the bootstrap capacitor C, the second output terminal P is further pulled up to a higher level V2. At this time, the pull-up switch unit M1 is fully turned on, and the first and second ends of the pull-up switch unit M1 can reach the same potential. Therefore, the first node N1 is at the high level VDD of the clock signal CK, and the scan signal Scan is at the high level VDD of the clock signal CK. At time t3, the second output terminal P is at a low level VSS, the clock signal CK is at a low level VSS, and the potential of the first node N1 is pulled down to a low level VSS by the pull-down unit 103.

[0067] It should be noted that, in actual implementation, when the potential of the first node N1 needs to be pulled up to the preset level signal VM, the clock signal CK is preferably configured to be at a low level VSS to ensure that the second switch unit T2 does not turn on prematurely. That is, when the clock signal CK is at a low level VSS and the second output terminal P is at a high level, the first switch unit T1 is turned on, and the preset level signal VM is output to the first node N1 via the first switch unit T1. When the clock signal CK is at a high level VSS and the second output terminal P is at a high level, the first switch unit T1 and the second switch unit T2 are configured to be turned on, thereby turning on the pull-up switch unit M1, causing the high level VDD of the clock signal CK to be output to the first node N1, thereby causing the scan signal Scan to be at the high level VDD of the clock signal CK.

[0068] In summary, the scan driving circuit disclosed in the present application is provided with a first switch unit T1 and a second switch unit T2 in the pull-up unit 102, the control end of the first switch unit T1 is connected to the second output end P of the logic control unit 101, the first end is connected to the voltage signal source, and the second end is connected to the first node N1, and the first switch unit T1 is turned on when the second output end P of the logic control unit 101 is at a high level; the control end of the second switch unit T2 is connected to the third node N3, the first end is connected to the second node N2, and the second end is connected to the second output end P of the logic control unit 101, and the second switch unit T2 is turned on when the clock signal CK is at a high level VDD. Before the rising edge of the clock signal CK arrives, a preset level signal VM, which is less than the high level VDD of the clock signal CK and greater than the low level VSS of the clock signal CK, is provided to the first terminal of the first switch unit T1 via a voltage signal source. The preset level signal VM is used to preemptively raise the level of the first node N1, thereby reducing the voltage difference between the level of the first node N1 and the high level VDD of the clock signal CK. As shown in FIG7 , the voltage difference ΔV between the level of the first node N1 and the high level VDD of the clock signal CK of the present application is less than the corresponding voltage difference ΔV' of the scan drive circuit shown in FIG2 . When the rising edge of the clock signal CK arrives, the level of the first node N1 only needs to be pulled up to the high level VDD of the clock signal CK by the preset level signal VM. Since the level change amplitude of the first node N1 is small, the influence of parasitic capacitance on the potential coupling of other nodes can be reduced. At the same time, the problem of insufficient effective charging time of the scan transistor caused by level switching delay can be improved, thereby improving the image display effect.

[0069] The present application also provides a scanning driving method, which can be applied to the scanning driving circuit in any of the aforementioned embodiments. The scanning driving method includes: when the second output terminal of the logic control unit is at a high level and the clock signal is at a low level, the voltage signal source outputs a preset level signal to the first end of the first switching unit.

[0070] In one embodiment, the preset level signal is a fixed level signal, and when the second output terminal of the logic control unit is at a high level and the clock signal is at a low level, the voltage signal source outputs a preset level signal to the first terminal of the first switch unit.

[0071] In one embodiment, the preset level signal includes two level signals of different amplitudes. Accordingly, the period during which the second output terminal of the logic control unit is at a high level and the clock signal is at a low level includes a first period and a second period later than the first period. When the second output terminal of the logic control unit is at a high level and the clock signal is at a low level, during the first period, the voltage signal source outputs a first level signal to the first terminal of the first switch unit, and during the second period, the voltage signal source outputs a second level signal to the first terminal of the first switch unit.

[0072] In one embodiment, the preset level signal includes three level signals of different amplitudes. Accordingly, the period during which the second output terminal of the logic control unit is at a high level and the clock signal is at a low level includes a first period, a second period later than the first period, and a third period later than the second period. When the second output terminal of the logic control unit is at a high level and the clock signal is at a low level, during the first period, the voltage signal source outputs a first level signal to the first terminal of the first switch unit, during the second period, the voltage signal source outputs a second level signal to the first terminal of the first switch unit, and during the third period, the voltage signal source outputs a third level signal to the first terminal of the first switch unit.

[0073] The preset level signal is used to pull up the level of the first node in advance, reducing the voltage difference between the level of the first node and the high level of the clock signal. When the rising edge of the clock signal arrives, the level of the first node only needs to be pulled up by the preset level signal to the high level of the clock signal. The level change amplitude of the first node is small, which can reduce the influence of the parasitic capacitance on the potential coupling of other nodes. At the same time, it improves the problem of insufficient effective charging time of the scanning transistor caused by the level switching delay, thereby improving the picture display effect.

[0074] 8 , the present application further provides a display device, which includes a driving circuit 100 and a display panel 200. The driving circuit 100 is connected to the display panel 200 to drive the display panel 200 to display an image.

[0075] The display panel 200 includes a plurality of pixel units arranged in an array to form a pixel unit array, wherein the pixel unit includes a scanning transistor S-TFT, a driving transistor D-TFT, a first capacitor Cst, and a sub-pixel OLED.

[0076] The control terminal of the scanning transistor S-TFT is connected to the row line, that is, connected to the aforementioned first node N1. The first terminal of the scanning transistor S-TFT is connected to the column line for receiving the data voltage VData. The second terminal of the scanning transistor S-TFT is connected to the control terminal of the driving transistor D-TFT. The first terminal of the driving transistor D-TFT is connected to the power supply ELVDD, and the second terminal of the driving transistor D-TFT is connected to the power supply ELVSS. When the scanning transistor S-TFT is turned on, the control terminal of the driving transistor D-TFT is at a high level, turning on the driving transistor D-TFT. One terminal of the first capacitor Cst is connected to the control terminal of the driving transistor D-TFT, that is, the second terminal of the scanning transistor S-TFT, and one terminal of the first capacitor Cst is connected to the second terminal of the driving transistor D-TFT.

[0077] It can be understood that the control terminal of the scanning transistor S-TFT corresponds to the gate of the scanning transistor S-TFT, and the first terminal and the second terminal correspond to the source and drain of the scanning transistor S-TFT, respectively. Similarly, the control terminal of the driving transistor D-TFT corresponds to the gate of the driving transistor D-TFT, and the first terminal and the second terminal correspond to the source and drain of the driving transistor D-TFT, respectively.

[0078] The sub-pixel is an OLED, the anode of the OLED is connected to the second terminal of the driving transistor D-TFT, and the cathode of the OLED is connected to the power supply ELVSS. When the driving transistor D-TFT is turned on, the OLED is turned on and emits light, thereby realizing the picture display.

[0079] The driving circuit 100 includes the scan driving circuit described in any of the above technical solutions. The scan driving circuit can be formed in the edge area of ​​the display panel 200 using a gate in panel (GIP or GOA) method. For example, the display panel 200 includes a display area and a non-display area located at the edge, and the scan driving circuit is formed in the non-display area of ​​the display panel 200.

[0080] The driver circuit 100 also includes a timing controller 20, a data driver circuit 30, and a power supply circuit 40. For details, see Figure 1. The data driver circuit 30 is connected to the timing controller 20 and is configured to output corresponding data voltages VData to each column data line based on control signals from the timing controller 20, thereby driving the pixel units on the currently conducting row to achieve image display. The power supply circuit 40 is configured to provide power supplies ELVDD and ELVSS.

[0081] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present application are indicated by the appended claims.

Claims

1. A scanning driving circuit, wherein: The invention comprises a plurality of scan driving modules, wherein the scan driving modules comprise a logic control unit, a pull-up unit and a pull-down unit, wherein the pull-down unit is connected to a first output terminal and a first node of the logic control unit; wherein the pull-up unit comprises: A pull-up switch unit, wherein a control end of the pull-up switch unit is connected to a second node, a first end of the pull-up switch unit is connected to a third node, the third node is configured to receive a clock signal, and a second end of the pull-up switch unit is connected to the first node; A bootstrap capacitor, one end of which is connected to the first node, and the other end of which is connected to the second node; a first switch unit, wherein a control end of the first switch unit is connected to the second output end of the logic control unit, a first end of the first switch unit is connected to a voltage signal source, the voltage signal source is used to provide a preset level signal, the preset level signal is less than a high level of the clock signal and greater than a low level of the clock signal, and a second end of the first switch unit is connected to the first node; a second switch unit, wherein a control end of the second switch unit is connected to the third node, a first end of the second switch unit is connected to the second node, and a second end of the second switch unit is connected to a second output end of the logic control unit; Among them, the first switch unit is configured to be turned on when the second output terminal of the logic control unit is at a high level, so as to pull the potential of the first node to the preset level signal, and the second switch unit is configured to be turned on when the clock signal is at a high level, so as to pull the potential of the first node to the high level of the clock signal.

2. The scan driving circuit according to claim 1, wherein: The preset level signal is smaller than a turn-on voltage of a scanning transistor in the pixel unit, and a control terminal of the scanning transistor is connected to the first node.

3. The scanning driving circuit according to claim 1 or 2, wherein: The preset level signal includes a first level signal and a second level signal greater than the first level signal, the period during which the second output terminal of the logic control unit is at a high level and the clock signal is at a low level includes a first period and a second period later than the first period, and the voltage signal source is configured to provide the first level signal in the first period and provide the second level signal in the second period.

4. The scan driving circuit according to claim 3, wherein: The voltage signal source is a timing controller.

5. The scan driving circuit according to claim 1, wherein: The first switch unit and the second switch unit are thin film transistors.

6. The scan driving circuit according to claim 1, wherein: The pull-down unit comprises a pull-down switch unit, a control end of the pull-down switch unit is connected to the first output end of the logic control unit, a first end of the pull-down switch unit is connected to the first node, and a second end of the pull-down switch unit is connected to a common ground end.

7. The scan driving circuit according to claim 1, wherein: The multiple scanning driving modules are cascaded, and the logic control units of at least some of the scanning driving modules are configured to output a corresponding low-level signal or a high-level signal to the second output terminal based on the scanning signal of the previous-level scanning driving module, and to output a corresponding low-level signal or a high-level signal to the first output terminal based on the scanning signal of the next-level scanning driving module.

8. The scan driving circuit according to claim 1, wherein: The pull-up switch unit is a pull-up transistor, the control end of the pull-up switch unit corresponds to the gate of the pull-up transistor, and the first end of the pull-up switch unit and the second end of the pull-up switch unit correspond to the source and drain of the pull-up transistor respectively.

9. The scan driving circuit according to claim 8, wherein: The pull-up transistor is a MOS transistor.

10. The scan driving circuit according to claim 8, wherein: The pull-up switch unit is a thin film transistor.

11. The scan driving circuit according to claim 1, wherein: The preset level signal is a fixed level signal. When the first switch unit is turned on, the potential of the first node is pulled up to the fixed level signal.

12. The scan driving circuit according to claim 1, wherein: The preset level signal includes a plurality of level signals with different amplitudes.

13. The scan driving circuit according to claim 12, wherein: The preset level signal includes a first level signal, a second level signal and a third level signal, and the amplitudes of the first level signal, the second level signal and the third level signal increase in sequence; The period during which the second output terminal of the logic control unit is at a high level and the clock signal is at a low level includes a first period, a second period and a third period, and the time corresponding to the first period, the second period and the third period is postponed in sequence. The voltage signal source is configured to provide the first level signal in the first period, provide the second level signal in the second period, and provide the third level signal in the third period.

14. The scan driving circuit according to claim 1, wherein: The pull-down switch unit is a pull-down transistor, the control end of the pull-down switch unit corresponds to the gate of the pull-down transistor, and the first end of the pull-down switch unit and the second end of the pull-down switch unit correspond to the source and drain of the pull-down transistor respectively.

15. The scan driving circuit according to claim 14, wherein: The pull-down transistor is a MOS transistor.

16. A scanning driving method, wherein: For use in the scan driving circuit according to any one of claims 1 to 15, the scan driving method comprises: When the second output terminal of the logic control unit is at a high level and the clock signal is at a low level, the voltage signal source is enabled to output a preset level signal to the first terminal of the first switch unit.

17. A display device, wherein: include: A display panel including a pixel unit array; A driving circuit, used to drive the pixel unit, comprises the scanning driving circuit according to any one of claims 1 to 15.

18. The display device according to claim 17, wherein: The pixel unit is a self-luminous pixel unit.

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