Semiconductor device

Abstract

Provided is a semiconductor device that can be miniaturized or highly integrated. A semiconductor device according to the present invention has a first insulator that is on a substrate, a second insulator that is on the first insulator, an oxide semiconductor that contacts an upper surface of the second insulator, a pair of first conductors that contact an upper surface of the oxide semiconductor and are separated from each other on the oxide semiconductor, and a pair of second conductors that are respectively positioned on the pair of first conductors. The first insulator includes silicon and oxygen. The second insulator provides a barrier against hydrogen. The distance between the pair of second conductors is greater than the distance between the pair of first conductors.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device each including an oxide semiconductor. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] In recent years, the development of semiconductor devices has progressed, and large scale integration (LSI), central processing units (CPU), memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed on chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] Furthermore, Patent Document 3 discloses a transistor with a microstructure in which a source electrode layer and a drain electrode layer are provided in contact with the upper surface of an oxide semiconductor.

[0009] JP 2012-257187 A JP 2011-151383 A International Publication No. 2016-125052

[0010] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0011] Another object of one embodiment of the present invention is to provide a storage device with a large storage capacity.Another object of one embodiment of the present invention is to provide a storage device with high operation speed.Another object of one embodiment of the present invention is to provide a storage device with low power consumption.Another object of one embodiment of the present invention is to provide a novel storage device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0013] A semiconductor device according to one embodiment of the present invention includes a first insulator, a second insulator over the first insulator, an oxide semiconductor in contact with a top surface of the second insulator, a pair of first conductors in contact with a top surface of the oxide semiconductor and spaced apart from each other over the oxide semiconductor, and a pair of second conductors located on the pair of first conductors, respectively. The first insulator contains silicon and oxygen. The second insulator has a barrier property against hydrogen. The distance between the pair of second conductors is greater than the distance between the pair of first conductors.

[0014] In the above, the semiconductor device preferably includes a fourth insulator located on the second insulator and having an opening between the pair of first conductors that reaches the oxide semiconductor, a fifth insulator in contact with a side surface of the fourth insulator and an upper surface of the first conductor in the opening, a sixth insulator in contact with the upper surface of the oxide semiconductor in the opening, and a third conductor overlapping with the upper surface of the oxide semiconductor in the opening with the sixth insulator interposed therebetween. In this case, the fifth insulator preferably has a barrier property against hydrogen. Furthermore, the sixth insulator preferably has a stacked structure in which a plurality of layers including insulators are stacked. In this case, a layer of the plurality of layers that is in contact with the oxide semiconductor preferably contains an oxide containing one or both of aluminum and hafnium.

[0015] In the above, a third insulator is preferably provided in contact with top surfaces of the pair of second conductors, part of side surfaces of the pair of first conductors, and part of side surfaces of the oxide semiconductor, and the third insulator preferably has a barrier property against hydrogen.

[0016] In the above, the second insulator preferably includes silicon nitride, aluminum oxide, hafnium oxide, or tantalum oxide.

[0017] In the above, the oxide semiconductor preferably includes a first layer in contact with the second insulator and a second layer located on the first layer in contact with the first conductor, wherein the first layer and the second layer preferably have different compositions and the first layer is thinner than the second layer.

[0018] In the above, it is preferable that the second conductor has higher conductivity than the first conductor and is thicker than the first conductor.

[0019] In the above, the first conductor preferably contains tantalum nitride.

[0020] In the above, it is preferable that the first conductor contains tantalum nitride and the second conductor contains tungsten.

[0021] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0022] According to one embodiment of the present invention, a storage device with a large storage capacity can be provided. Alternatively, according to one embodiment of the present invention, a storage device with a high operating speed can be provided. Alternatively, according to one embodiment of the present invention, a storage device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a novel storage device can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0024] FIG. 1A is a plan view illustrating an example of a semiconductor device. FIGS. 1B to 1D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 2A and 2B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 3A to 3C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 4A to 4C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 5A to 5D are cross-sectional views illustrating an example of a method for manufacturing an oxide semiconductor. FIGS. 6A to 6D are cross-sectional views illustrating an example of an oxide semiconductor. FIG. 7A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 7B to 7D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 8A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 8B to 8D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 9A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 9B to 9D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 10A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 10B to 10D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 11A is a plan view illustrating an example of a method for manufacturing a semiconductor device. 11B to 11D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIGS. 12A to 12D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 13A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 13B to 13D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 14A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 14B to 14D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIGS. 15A to 15D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 16A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 16B to 16D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 17A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 17B to 17D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 18A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 18B to 18D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 19 is a block diagram illustrating an example of a memory device. 20A and 20B are a schematic diagram and a circuit diagram showing an example of a memory device.21A and 21B are schematic diagrams showing an example of a memory device. FIG. 22 is a circuit diagram showing an example of a memory device. FIG. 23 is a cross-sectional view showing an example of a memory device. FIG. 24 is a cross-sectional view showing an example of a memory device. FIGS. 25A to 25C are circuit diagrams showing an example of a memory device. FIGS. 26A and 26B are diagrams showing an example of a semiconductor device. FIGS. 27A and 27B are diagrams showing an example of an electronic component. FIGS. 28A and 28B are diagrams showing an example of electronic equipment, and FIGS. 28C to 28E are diagrams showing an example of a mainframe computer. FIG. 29A is a diagram showing an example of space equipment. FIG. 29B is a diagram showing an example of a storage system applicable to a data center.

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0027] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0028] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0029] It should be noted that the terms "film" and "layer" may be interchangeable. For example, the term "conductive layer" may be interchangeable with the term "conductive film." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or the term "conductive film."

[0030] The openings include, for example, grooves, slits, etc. Furthermore, the area in which the openings are formed may be referred to as an opening portion.

[0031] Although the drawings used in this embodiment mode show the case where the sidewall of the insulator in the opening portion is substantially perpendicular to the substrate surface or the surface where the insulator is formed, the sidewall may have a tapered shape.

[0032] In this specification, a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle between the inclined side and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side of the structure and the substrate surface do not necessarily need to be completely flat, but may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0033] Embodiment 1 In this embodiment, a semiconductor device including an oxide semiconductor layer and a method for manufacturing the semiconductor device will be described with reference to drawings.

[0034] <Configuration Example of Semiconductor Device> A configuration example of a semiconductor device will be described with reference to FIGS. 1A to 4C. FIGS. 1A to 1D are plan views and cross-sectional views of a semiconductor device (transistor 200). FIG. 1A is a plan view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted from the plan view of FIG. 1A for clarity. FIG. 2A is an enlarged view of FIG. 1B, and FIG. 2B is an enlarged view of FIG. 1C. 3A to 4C are enlarged cross-sectional views of the transistor 200 in the channel length direction.

[0035] The transistor 200 includes an insulator 215 provided on a substrate (not shown), an insulator 216 on the insulator 215, a conductor 205 (conductors 205a and 205b) provided so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and the conductor 205, an insulator 224 on the insulator 222, an insulator 226 on the insulator 224, and an oxide 230 (oxide 2 The oxide 230 includes a conductor 242a (conductor 242a1 and conductor 242a2) and a conductor 242b (conductor 242b1 and conductor 242b2) on the oxide 230, an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 on the oxide 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250. In addition, an insulator 255 is provided between the insulator 242a1, the conductor 242b1, the conductor 242a2, the conductor 242b2, the insulator 271a, the insulator 271b, the insulator 275, and the insulator 280 and the insulator 250.

[0036] An insulator 275 is provided on the insulators 271a and 271b, and an insulator 280 is provided on the insulator 275. The insulators 255, 250, and conductor 260 are embedded inside openings provided in the insulators 280 and 275. An insulator 282 is provided on the insulator 280 and the conductor 260. An insulator 283 is provided on the insulator 282.

[0037] The oxide 230 has a region that functions as a channel formation region of the transistor 200. The conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region that functions as a first gate insulator of the transistor 200. The conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 200. The insulators 226, 224, and 222 each have a region that functions as a second gate insulator of the transistor 200.

[0038] The conductor 242a has a region which functions as one of the source electrode and the drain electrode of the transistor 200. The conductor 242b has a region which functions as the other of the source electrode and the drain electrode of the transistor 200.

[0039] The conductor 242a has a layered structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b has a layered structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. The conductors 242a1 and 242b1 in contact with the oxide 230b are preferably conductors that are resistant to oxidation, such as metal nitrides. This prevents the conductors 242a and 242b from being excessively oxidized by the oxygen contained in the oxide 230b. Furthermore, the conductors 242a2 and 242b2 are preferably conductors such as metal layers that have higher conductivity than the conductors 242a1 and 242b1. This allows the conductors 242a and 242b to function as highly conductive wiring or electrodes. Furthermore, in this case, it is preferable that the thicknesses of the conductors 242a2 and 242b2 are thicker than the thicknesses of the conductors 242a1 and 242b1. This can further increase the conductivity of the conductors 242a and 242b. In this way, a semiconductor device can be provided in which the conductors 242a and 242b, which function as wirings or electrodes, are provided in contact with the upper surface of the oxide 230, which functions as an active layer.

[0040] Here, the conductors 242a and 242b can also be expressed as a pair of conductors. Similarly, the conductors 242a1 and 242b1, and the conductors 242a2 and 242b2 can also be expressed as a pair of conductors.

[0041] As shown in FIG. 3A , in a cross-sectional view of the transistor 200 in the channel length direction, the distance L2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L1 between the conductor 242a2 and the conductor 242b2. This configuration allows the distance between the source and the drain to be shortened, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. By miniaturizing the semiconductor device in this way, it is possible to provide a semiconductor device with improved operating speed.

[0042] The portion of the oxide 230 that does not overlap with either the conductor 242a or the conductor 242b and overlaps with the conductor 260 via the insulator 250 functions as a channel formation region. The oxide 230 has a portion (first portion) that overlaps with the conductor 242a1 or the conductor 242b1, and a portion (second portion) that overlaps with both the conductor 242a1 and the conductor 242a2 or both the conductor 242b1 and the conductor 242b2. The oxide 230 receives stress (tensile stress or compressive stress) from the conductor in contact with the oxide 230. Since the stress applied to the oxide 230 increases with the thickness of the conductor in contact with the oxide 230, the second portion receives a greater stress than the first portion. When the oxide 230 becomes low-density due to the tensile stress from the conductor, oxygen vacancies are likely to occur, resulting in a low-resistance region. 2A and 3A, a first portion of the oxide 230b has a low resistance region N and a second portion has an even lower resistance region N ＋ The oxide 230 has a low resistance region (region N or region N ＋ ) allows the transistor 200 to pass a larger current when it is in a conductive state.

[0043] The openings in the insulators 280 and 275 overlap the region between the conductors 242a2 and 242b2. Furthermore, portions of the conductors 242a1 and 242b1 are formed to protrude into the openings. Therefore, the insulator 255 contacts the top surface of the conductor 242a1, the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2 within the openings. Furthermore, the insulator 250 contacts the top surface of the oxide 230 in the region between the conductors 242a1 and 242b1.

[0044] The insulator 255 is preferably an insulator that is resistant to oxidation, such as a nitride. The insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, and has the function of protecting the conductors 242a2 and 242b2. As will be described in detail later, after the conductors 242a1 and 242b1 are separated, it is preferable to perform heat treatment in an oxygen-containing atmosphere before forming the insulator 250. At this time, since the insulator 255 is formed in contact with the side surfaces of the conductors 242a2 and 242b2, excessive oxidation of the conductors 242a2 and 242b2 can be prevented.

[0045] The insulator 226 is provided between the oxide 230 and the insulator 224 and functions as a barrier insulator that prevents impurities such as hydrogen contained in the insulator 224 from diffusing into the oxide 230 .

[0046] In this specification and the like, a barrier insulator refers to an insulator having barrier properties. In this specification and the like, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0047] The insulator 226 preferably has a barrier property against at least hydrogen. Examples of barrier insulators against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 226 preferably has a single-layer structure or a stacked-layer structure of the above-mentioned barrier insulators against hydrogen. In particular, the insulator 226 more preferably contains silicon nitride.

[0048] In particular, when silicon oxide is used for the insulator 224, it is particularly preferable to provide the insulator 226 having a barrier property against hydrogen. Silicon oxide is characterized by low cost, high productivity, ease of processing, and a low dielectric constant, and is a film that is often used as an interlayer insulating film. On the other hand, silicon oxide has a characteristic of easily diffusing hydrogen. Therefore, by providing the insulator 226 having a barrier property against hydrogen between the oxide 230 and the insulator 224 containing silicon oxide, rather than providing the oxide 230 directly on the insulator 224, the hydrogen concentration in the oxide 230 can be kept low, and the reliability of the transistor 200 can be improved.

[0049] The insulator 226 is preferably as thin as possible, which can improve productivity of the transistor 200. The thickness of the insulator 226 can be, for example, 0.5 nm to 10 nm, preferably 0.5 nm to 8 nm, more preferably 1.0 nm to 5 nm, even more preferably 1.5 nm to 3 nm, and typically 2 nm.

[0050] The oxide 230 preferably includes an oxide 230a on the insulator 226 and an oxide 230b on the oxide 230a. By including the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b.

[0051] Here, the transistor 200 includes the insulator 226, which can prevent hydrogen from diffusing from the insulator 224 to the oxide 230. Therefore, the transistor 200 includes the insulator 226, which can reduce the thickness of the oxide 230a. Reducing the thickness of the oxide 230a improves ease of processing and therefore productivity. For example, when the thickness of the oxide 230b is 100%, the thickness of the oxide 230a can be 5% to 80%, preferably 10% to 60%, and more preferably 10% to 40%. The thickness of the oxide 230a can be, for example, 1 nm to less than 10 nm, preferably 2 nm to 8 nm, more preferably 3 nm to 7 nm, and typically 5 nm. The thickness of each layer constituting the oxide 230 is not limited to this example and can be changed as needed depending on the required electrical characteristics of the transistor 200.

[0052] Furthermore, the transistor 200 includes the insulator 226 between the insulator 224 and the oxide 230. Therefore, the oxide 230a may not necessarily have the function of suppressing impurity diffusion. Alternatively, the oxide 230a itself may not be provided.

[0053] In this embodiment, the oxide 230 has a two-layer structure of the oxide 230 a and the oxide 230 b, but is not limited thereto. The oxide 230 may have a single-layer structure of the oxide 230 b, or a stacked structure of three or more layers.

[0054] In the oxide 230b, a channel formation region and a source region and a drain region sandwiching the channel formation region are formed in the transistor 200. At least a part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.

[0055] The above-mentioned areas N and N ＋ The pair of regions N correspond to the source and drain regions, and the portion sandwiched between the pair of regions N corresponds to the channel forming region.

[0056] The channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0057] The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, the source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0058] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0059] Note that when the carrier concentration of the oxide 230b is reduced, the impurity concentration in the oxide 230b is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0060] In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the oxide 230b. Furthermore, in order to reduce the impurity concentration in the oxide 230b, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the oxide 230b refer to, for example, elements other than the main component constituting the oxide 230b. For example, an element with a concentration of less than 1 atomic % or less than 0.1 atomic % can be considered an impurity.

[0061] Note that the channel formation region, the source region, and the drain region may each be formed not only with the oxide 230b but also with the oxide 230a.

[0062] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in regions closer to the channel formation region.

[0063] The oxide 230 (the oxide 230a and the oxide 230b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0064] The band gap of a metal oxide functioning as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. A transistor having a metal oxide in a channel formation region like this is called an OS transistor. Because the off-state current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0065] The oxide 230 preferably includes a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the oxide 230 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0066] The oxide 230 may be, for example, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), indium aluminum Examples of usable materials include zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples of usable materials include silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0067] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0068] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0069] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0070] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0071] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0072] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used for the oxide 230. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0073] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a into the oxide 230b.

[0074] The main component in a metal oxide refers to a metal element whose proportion relative to all metal elements contained in the metal oxide is, for example, 0.1 atomic % or more, or 1 atomic % or more.

[0075] In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. With this structure, the transistor 200 can have large on-state current and high frequency characteristics.

[0076] Furthermore, since the oxide 230 a and the oxide 230 b contain a common element other than oxygen as a main component, the density of defect states at the interface between the oxide 230 a and the oxide 230 b can be reduced, which reduces the effect of interface scattering on carrier conduction, and the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0077] Specifically, the oxide 230a can be a metal oxide having an atomic ratio of In:M:Zn = 1:3:2 or a similar composition, an atomic ratio of In:M:Zn = 1:3:4 or a similar composition, or an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition. The oxide 230b can be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M. Furthermore, when a single layer of oxide 230b is provided as oxide 230, the metal oxide that can be used for oxide 230a may be used for oxide 230b. Furthermore, the compositions of metal oxides that can be used for oxide 230a and oxide 230b are not limited to those described above. For example, the composition of a metal oxide that can be used for oxide 230a may be used for oxide 230b. Similarly, the composition of a metal oxide that can be used for oxide 230b may be used for oxide 230a.

[0078] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0079] The oxide 230b preferably has crystallinity. In particular, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0080] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230b, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Thus, even when heat treatment is performed, extraction of oxygen from the oxide 230b can be suppressed, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0081] For example, the oxide 230a and the oxide 230b can each be formed by a sputtering method.

[0082] [Oxide Semiconductor Layer] Details of an oxide semiconductor layer applicable to the oxide 230 will be described below. The oxide semiconductor includes a metal oxide.

[0083] When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids.

[0084] By using a crystalline metal oxide for an oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (poly-crystalline) structure, and a nanocrystalline (nc) structure.

[0085] The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention has a plurality of microcrystals. Furthermore, no clear grain boundary is observed between the plurality of microcrystals. The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention preferably has a crystal structure in which the plurality of microcrystals are connected without clear grain boundaries when observed from the orientation direction.

[0086] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a crystal structure different from either a single-crystal structure or a polycrystalline structure. In particular, the oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure.

[0087] The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected in the a-b plane without any clear grain boundaries. When a cross section of an oxide semiconductor layer having the CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, the oxide semiconductor layer having the CAAC structure can also be said to have a structure having layered crystal parts. The metal atoms arranged in a layered manner can be observed as a row of bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. The bright spots are arranged, for example, in a direction parallel to the surface on which the oxide semiconductor layer is formed.

[0088] In addition, a structure in which metal atoms in each of the multiple microcrystals are arranged in layers parallel or approximately parallel to the surface on which the metal atoms are formed, and the layers in which the metal atoms are arranged are stacked in a direction perpendicular or approximately perpendicular to the surface on which the metal atoms are formed, is sometimes referred to as a CAAC structure. If the microcrystals have such a configuration, the crystal structure of the microcrystals is not limited to a hexagonal system. For example, some of the multiple microcrystals may have a crystal structure other than a hexagonal system (e.g., a cubic system crystal structure).

[0089] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface on which the metal is formed. In the CAAC structure, metal atoms are arranged in layers parallel or approximately parallel to the surface on which the metal is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 110° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the metal is formed.

[0090] A polycrystalline structure has crystal grain boundaries. Furthermore, when a heat treatment is performed after forming an oxide semiconductor layer with a polycrystalline structure, tiny gaps (also referred to as nanocracks or microcracks) or tiny spaces (also referred to as nanospaces or microspaces) can be formed between crystalline portions. When tiny gaps or tiny spaces are formed in the oxide semiconductor layer, the electrical resistance of the oxide semiconductor layer increases. This is because the electrical resistance of the tiny gaps or tiny spaces is very high, for example, infinite. When an oxide semiconductor layer having tiny gaps or tiny spaces is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. In contrast, in the CAAC structure, crystal grain boundaries are not clearly observed in the a-b plane, so a highly reliable semiconductor device can be realized. Furthermore, because there are fewer crystal grain boundaries, the energy barrier against carrier conduction in the transistor channel is small, and an improvement in on-current is expected. Furthermore, it is expected that an increase in the electrical resistance of a semiconductor layer of a transistor using an oxide semiconductor layer can be suppressed or the initial characteristics (particularly on-state current) of the transistor can be improved, making the transistor suitable for high-speed operation.

[0091] A metal oxide that increases the on-state current of a transistor is preferably used for the channel formation region of the transistor. To increase the on-state current of the transistor, it is preferable to increase the carrier mobility of the metal oxide used in the transistor. To increase the carrier mobility of a metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of a transistor can be increased.

[0092] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0093] When an oxide semiconductor layer having a CAAC structure is subjected to electron diffraction, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to a normal vector of a surface on which the oxide semiconductor layer is formed or a normal vector of the surface of the oxide semiconductor layer.

[0094] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0095] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT process is performed on each region in the cross-sectional TEM image to create an FFT pattern. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. Regions in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0096] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the layer has crystallinity. Furthermore, in a Voronoi diagram created by image analysis of a TEM image obtained by observing an oxide semiconductor layer having a CAAC structure in a direction perpendicular to the surface on which it is formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, and hexagonal Voronoi regions are typically observed. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0097] A method for creating a Voronoi diagram will now be described. First, image analysis of a TEM image involves performing FFT processing, filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT-filtered image. Lattice points are extracted from the created FFT-filtered image, and perpendicular bisectors of line segments connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal regions enclosed by the lines connecting the Voronoi points are defined as Voronoi regions. In this way, a Voronoi diagram can be created.

[0098] An example of the observation range of the TEM in creating a Voronoi diagram is a rectangular region of 50 nm in length and 50 nm in width, although the observation range is not limited to this.

[0099] Furthermore, when the distribution of the orientation of the hexagonal lattice is analyzed using lattice points extracted by image analysis of a planar TEM image, the difference in the orientation of the hexagonal lattice at the boundary between two structures with different hexagonal lattice orientations is small, and the boundary is observed to be blurred, and it appears that the two structures are connected in a manner that makes them intertwine. In other words, no clear boundary is observed in the CAAC structure.

[0100] The orientation of the hexagonal lattice can be calculated by calculating the orientation of a hexagon formed by the six lattice points closest to each lattice point.

[0101] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not limited. The oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0102] In a cross section of the oxide semiconductor layer observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction parallel or substantially parallel to the surface on which the oxide semiconductor layer is formed. In the TEM image, the metal atoms arranged in layers are observed as a row of bright spots. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Furthermore, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0103] [Method for Forming Oxide Semiconductor Layer] An example of a method for forming an oxide semiconductor layer according to one embodiment of the present invention will be described below. Here, an example in which a metal oxide is formed by two film formation methods will be described.

[0104] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a metal oxide having a CAAC structure is deposited. At this time, a sputtering method can be used as a deposition method, thereby forming a metal oxide having high crystallinity. Alternatively, a pulsed laser deposition (PLD) method or another deposition method may be used.

[0105] When a metal oxide is formed using the above-described film formation method (hereinafter referred to as the first film formation method), a mixed layer (also referred to as "mixing") may be formed at the interface between the metal oxide and the surface to be formed. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide. By forming a first layer of metal oxide on the surface to be formed using a film formation method (hereinafter referred to as the second film formation method) that causes less damage than the sputtering method, PLD method, or the like, which are described as the first film formation method, and then providing a second layer of metal oxide using the first film formation method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the surface to be formed can be suppressed. Furthermore, impurities contained in the surface to be formed can be suppressed from being mixed into the second layer. These factors can further enhance the crystallinity of the second layer.

[0106] Atomic layer deposition (ALD) and chemical vapor deposition (CVD) are suitable as the second film formation method because they can suppress damage to the surface to be formed compared to sputtering. Examples of the second film formation method include molecular beam epitaxy (MBE) and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The MBE method is a film formation method that grows a thin film with a crystalline structure that reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes little damage to the surface on which the film is formed.The wet method is also one of the film formation methods that causes little damage to the surface on which the film is formed.An example of a wet method is a spray coating method.

[0107] A third layer can be further formed on the second layer, for example, by the second film formation method.

[0108] After the oxide semiconductor layer is formed, heat treatment is preferably performed.

[0109] In the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the second layer (i.e., CAAC) having high crystallinity can be used as a nucleus or seed to increase the crystallinity of an oxide semiconductor layer in contact with the second layer. This increases the crystallinity of the entire oxide semiconductor layer. In other words, the second layer can be used as a nucleus or seed to cause solid-phase growth of a metal oxide in the oxide semiconductor layer in contact with the second layer, thereby forming an oxide semiconductor layer with high crystallinity. An oxide semiconductor layer formed by such a film formation method, specifically, an oxide semiconductor layer having a CAAC structure, can be referred to as an axial growth CAAC (AG CAAC). The AG CAAC structure refers to an oxide semiconductor layer having a two-layer structure of at least a first layer and a second layer, and may have a stacked structure of three or more layers.

[0110] Even when a method that easily forms a metal oxide with high crystallinity is not used as a method for forming the first layer and the third layer, the crystallinity of the first layer and the third layer can be increased by using the method for forming an oxide semiconductor layer of one embodiment of the present invention. Furthermore, heat treatment has a function of assisting in increasing the crystallinity of the first layer and the third layer.

[0111] An example of a method for manufacturing the oxide semiconductor 90 will be described below with reference to FIGS. 5A to 5D.

[0112] First, a layer 92 is formed. The layer 92 corresponds to an insulating film or a conductive film included in the semiconductor device. For example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film can be used as the layer 92. Alternatively, for example, a conductive film that functions as an electrode of the semiconductor device can be used as the layer 92. The layer 92 does not need to be crystalline. In other words, the layer 92 may have an amorphous structure. Furthermore, when the layer 92 is crystalline, it may have a crystal structure that has low lattice matching with the metal oxide included in the oxide semiconductor 90.

[0113] Next, an oxide semiconductor 90a is formed on the layer 92 (FIG. 5A).

[0114] In a manufacturing method of one embodiment of the present invention, the oxide semiconductor 90b is formed by a sputtering method, as described later. When a metal oxide film is formed by a sputtering method, a mixed layer (also called alloying) of components of the metal oxide film to be formed and components of a layer on which the film is to be formed may be formed due to sputtering particles emitted from a target or the like, or energy applied to the substrate by the sputtering particles or the like. The alloying may hinder the crystallization of the oxide semiconductor layer thereover. Furthermore, when the alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. There is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor.

[0115] Therefore, before forming the oxide semiconductor 90b, the oxide semiconductor 90a is formed in advance using a film formation method that causes minimal damage to the surface on which the oxide semiconductor 90b is to be formed. This suppresses alloying of the components contained in the oxide semiconductor 90 and the components contained in the layer 92, and makes the thickness of the alloyed region thin, or makes the alloyed region thin enough that it cannot be observed. Here, the oxide semiconductor 90a is formed using the ALD method.

[0116] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0117] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Because the ALD method can deposit atoms layer by layer, it has the following advantages: it is possible to form an ultrathin film; it is possible to form a film on a surface with a high aspect ratio or a large step; it is possible to form a film with few defects such as pinholes; it is possible to form a film with excellent coverage; and it is possible to form a film at a low temperature. By using the ALD method for the oxide semiconductor 90a and the oxide semiconductor 90c (described later), the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well coated on steps, openings, and the like with a high aspect ratio.

[0118] Furthermore, the PEALD method may be preferable because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods.

[0119] Here, a method for forming an In-M-Zn oxide as the oxide semiconductor 90a by ALD will be described.

[0120] First, a source gas containing a precursor containing indium is introduced into the chamber, and the precursor is adsorbed onto the surface of layer 92. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than indium while leaving indium adsorbed on the substrate, thereby forming a layer in which indium and oxygen are combined.

[0121] Next, a source gas containing a precursor having element M is introduced into the chamber and adsorbed onto the layer of indium and oxygen. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer of element M and oxygen.

[0122] Next, a source gas containing a zinc-containing precursor is introduced into the chamber and adsorbed onto the layer in which element M and oxygen are bonded. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0123] By repeating the above-described method, an In-M-Zn oxide can be formed as the oxide semiconductor 90a on the layer 92 by the ALD method.

[0124] The substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, the substrate heating temperature is, for example, 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0125] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the chamber, and then discharge excess precursor, reaction products, etc. from the chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the chamber, and then discharge excess reactant, reaction products, etc. from the chamber.

[0126] Furthermore, in the present specification and elsewhere, unless otherwise specified, when ozone, oxygen, or water is used as a reactant or oxidant, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, and ion state.

[0127] When the oxide semiconductor 90a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than that of a CAAC structure, may be formed.

[0128] Next, an In-M-Zn oxide is formed as an oxide semiconductor 90b on the oxide semiconductor 90a by sputtering (FIG. 5B). The oxide semiconductor 90b preferably has a composition suitable for forming a CAAC structure.

[0129] When the oxide semiconductor 90b is formed by sputtering, a mixed layer 91 is formed on or near the surface of the oxide semiconductor 90a. Furthermore, sputtering particles or energy imparted to the substrate by the sputtering particles or the like during the formation of the oxide semiconductor 90b may form minute crystalline regions in the mixed layer 91. In a subsequent heat treatment step, the mixed layer 91 or the minute crystalline regions formed in the mixed layer 91 may act as nuclei, causing at least a portion of the oxide semiconductor 90a to crystallize.

[0130] Sputtering methods include RF sputtering, which uses a high-frequency power supply as a sputtering power supply; DC sputtering, which uses a direct-current power supply; and pulsed DC sputtering, which changes the voltage applied to an electrode in a pulsed manner. DC sputtering can be suitably used to form a metal conductive film and can improve productivity due to its high film formation rate. Pulsed DC sputtering can be suitably used to form a metal conductive film and a semiconductor film. RF sputtering can be suitably used to form an insulating film. Compounds such as oxides, nitrides, and carbides can be formed by reactive sputtering using a reactive gas. The metal oxide used for the oxide semiconductor layer of one embodiment of the present invention can be formed by a method appropriately selected from these methods depending on the conductivity of the sputtering target and the like.

[0131] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0132] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0133] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0134] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease by up to about 50% compared to the sputtering target.

[0135] In the formation of the oxide semiconductor 90b by a sputtering method, it is preferable to heat the substrate. In the formation of the metal oxide, a metal oxide with high crystallinity can be formed by increasing the substrate temperature (stage temperature) during the formation of the metal oxide. In the formation of the oxide semiconductor 90b by a sputtering method, the substrate heating temperature is preferably 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0136] Here, a model for forming a CAAC structure using a sputtering method will be described. First, microcrystals are formed during sputtering film formation. The microcrystals may be formed by energy imparted to the substrate by sputtered particles (sometimes referred to as atomic particles) or gas particles. Alternatively, planar or pellet-shaped sputtered particles (sometimes referred to as nanoclusters) that peel off from the sputtering target and deposit on the surface to be formed may become the microcrystals. Subsequently, sputtered particles are adsorbed onto the ends of the microcrystals, causing the microcrystals to grow laterally (in a direction substantially parallel to the surface to be formed). As the microcrystals grow laterally, adjacent microcrystals connect to each other, eliminating the ends of the microcrystals. Once the ends of the microcrystals are eliminated, sputtered particles are adsorbed onto the microcrystals, causing the microcrystals to grow vertically (in a direction substantially perpendicular to the surface to be formed). Sputtered particles are adsorbed onto the ends of the vertically grown microcrystals, causing the microcrystals to grow laterally. In this way, the CAAC structure is formed by the microcrystals repeatedly growing laterally and vertically. That is, the CAAC structure is formed by the growth of microcrystals contained in an oxide semiconductor, using the microcrystals as nuclei or seeds.

[0137] Note that a CAAC structure is difficult to form in an oxide semiconductor containing impurities such as silicon, carbon, or water. Therefore, the oxide semiconductor 90b is preferably formed using a deposition method that prevents the above-described impurities from being mixed in. Sputtering is suitable for forming the oxide semiconductor 90b because it can form an oxide semiconductor with a low impurity concentration by using a sputtering target with a reduced impurity concentration and a deposition gas with a reduced impurity amount.

[0138] Next, an oxide semiconductor 90c is formed on the oxide semiconductor 90b (FIG. 5C). Here, the oxide semiconductor 90c is formed by an ALD method. For the formation of the oxide semiconductor 90c by the ALD method, the method for forming the oxide semiconductor 90a can be referred to.

[0139] When an oxide semiconductor 90c having a lower crystallinity than the CAAC structure is formed on an oxide semiconductor 90b having a CAAC structure by an ALD method, the oxide semiconductor 90c may grow epitaxially around the oxide semiconductor 90b as a nucleus. Thus, when the oxide semiconductor 90c is formed, the oxide semiconductor 90c may have a region having the CAAC structure. Preferably, the region having the CAAC structure is formed over the entire oxide semiconductor 90c.

[0140] The oxide semiconductor 90c can be used, for example, as a layer in contact with a gate insulating layer of a transistor. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is on.

[0141] Furthermore, by forming the oxide semiconductor 90c using the ALD method, damage to the oxide semiconductor 90b is reduced, and the oxide semiconductor 90 can have high crystallinity throughout.

[0142] By using the ALD method, which has high coverage, as a method for forming the oxide semiconductors 90a and 90c, the oxide semiconductor layer as a whole can have coverage. Furthermore, by forming the oxide semiconductor 90b with high crystallinity using a sputtering method, the crystallinity of the oxide semiconductor layers above and below (the oxide semiconductor 90a and the oxide semiconductor 90c) can be increased by epitaxial growth from the oxide semiconductor 90b. This allows the crystallinity of the oxide semiconductor 90 to be increased throughout the entire layer. Therefore, the oxide semiconductor 90 can have both high coverage and high crystallinity.

[0143] Next, a heat treatment step may be carried out.

[0144] The heat treatment may be performed at a temperature of, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. Typically, the heat treatment may be performed at 400° C.±25° C. (375° C. to 425° C.). The treatment time may be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When a rapid thermal annealing (RTA) apparatus is used, the treatment time may be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level gaps in the crystal portions of the CAAC structure of the oxide semiconductor 90b with the oxide semiconductor 90c (in other words, crystal molecules formed by the ALD method).

[0145] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0146] The heat treatment step may enhance the crystallinity of the region having the CAAC structure in the oxide semiconductor 90c. Furthermore, if the region is formed only below the oxide semiconductor 90c after the ALD deposition, the heat treatment step may cause the region to expand upward ( FIG. 5D ). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer of the oxide semiconductor 90c.

[0147] Furthermore, the heat treatment process may further repair the oxide semiconductor 90b by the oxide semiconductor 90c (in other words, the crystal molecules formed by the ALD method) filling gaps in the atomic-level crystal portions of the CAAC structure of the oxide semiconductor 90b.

[0148] Furthermore, it is preferable that at least a portion of the oxide semiconductor 90a is converted into CAAC by the heat treatment ( FIG. 5D ). It is expected that the CAAC conversion is facilitated by the mixed layer 91 formed in the oxide semiconductor 90a during the deposition of the oxide semiconductor 90b, which acts as a nucleus or seed. It is preferable that the region in the oxide semiconductor 90a that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the layer 92.

[0149] Furthermore, because the CAAC is formed from the top to the bottom of the oxide semiconductor 90a, the CAAC can be formed up to the vicinity of the layer 92 regardless of the material or crystallinity of the layer 92. For example, even if the layer 92 has an amorphous structure, the oxide semiconductor 90a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0150] After the oxide semiconductor 90c is formed, microwave treatment may be performed.

[0151] Here, microwave processing refers to processing using a device with a power source that generates high-density plasma using microwaves, for example. Furthermore, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave processing can also be called microwave-excited high-density plasma processing.

[0152] By performing microwave treatment in an atmosphere containing oxygen, the impurity concentration in the oxide semiconductor 90 can be reduced. Examples of impurities include hydrogen and carbon. Although the above example illustrates a structure in which microwave treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave treatment may be performed on an insulating film, more specifically, a silicon oxide film, located near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave treatment may increase the crystallinity of the oxide semiconductor layer.

[0153] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, and more preferably from 300 to 700 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0154] When performing microwave treatment, the substrate may be heated to a temperature of at least room temperature (e.g., 25°C), at least 100°C, at least 200°C, at least 300°C, or at least 400°C, and preferably at most 500°C or at most 450°C.

[0155] Alternatively, after the microwave treatment, a heat treatment may be performed successively without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0156] The microwave treatment can be performed using, for example, oxygen gas and argon gas. By performing the microwave treatment in an atmosphere containing oxygen, the oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the oxide semiconductor layer. By the action of plasma, microwaves, or the like, defects in which hydrogen has entered oxygen vacancies in the oxide semiconductor layer (hereinafter referred to as V Ｏ By splitting V (sometimes referred to as H) into oxygen vacancies and hydrogen, the hydrogen impurities can be removed from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave treatment. Furthermore, oxygen radicals generated by the oxygen plasma can be supplied to oxygen vacancies formed in the oxide semiconductor layer, thereby further reducing the oxygen vacancies in the oxide semiconductor layer.

[0157] Oxygen to be implanted into the oxide semiconductor layer can be in various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having an unpaired electron, also referred to as O radicals). Note that the oxygen to be implanted into the oxide semiconductor layer may be in one or more of the above forms, and is particularly preferably an oxygen radical.

[0158] In this manner, the impurities in the oxide semiconductor layer can be reduced. When crystal growth is performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, the crystallinity can be further improved.

[0159] Note that one or both of the heat treatment and the microwave treatment may be performed directly on the oxide semiconductor layer or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0160] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness or both than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0161] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0162] In the oxide semiconductor 90, it is preferable that a region having a CAAC structure is widely present throughout the entire layer including the oxide semiconductor 90a and the oxide semiconductor 90c. FIG. 6A shows the crystallization of the oxide semiconductor 90a, the oxide semiconductor 90b, and the oxide semiconductor 90c. The crystals of the region having the CAAC structure in the oxide semiconductor 90a are connected to the crystals of the region having the CAAC structure in the oxide semiconductor 90b. The crystals of the region having the CAAC structure in the oxide semiconductor 90c are connected to the crystals of the region having the CAAC structure in the oxide semiconductor 90b. The oxide semiconductor 90 can sometimes be expressed as a single layer with no clearly observed interface. The oxide semiconductor 90 can sometimes be expressed as a single layer.

[0163] The regions having the CAAC structure in the oxide semiconductors 90a, 90b, and 90c can be observed as bright spots aligned parallel to the surface on which they are formed, for example, in cross-sectional observation using a high-resolution TEM. Furthermore, the c-axes of the CAAC structures in the oxide semiconductors 90a, 90b, and 90c are preferably approximately parallel to the normal direction of the surface on which the oxide semiconductor layers are formed.

[0164] Furthermore, there are cases where a portion of the oxide semiconductor 90a or the oxide semiconductor 90c is not crystallized. The example shown in Fig. 6B shows a state in which the vicinity of the interface with the layer 92 in the oxide semiconductor 90a is not crystallized. Fig. 6C shows a state in which the vicinity of the surface in the oxide semiconductor 90c is not crystallized. Fig. 6D shows a state in which the vicinity of the interface with the layer 92 in the oxide semiconductor 90a and the vicinity of the surface of the oxide semiconductor 90c are not crystallized.

[0165] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor 90, the boundaries between the stacked oxide semiconductors 90a, 90b, and 90c may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed by, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0166] Furthermore, it is preferable that the lattice mismatch between the crystals of the oxide semiconductor 90b and the crystals of the oxide semiconductor 90a or the oxide semiconductor 90c is small. This allows the oxide semiconductor 90a or the oxide semiconductor 90c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 90b. In this case, for example, when a cross section of the oxide semiconductor 90 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the surface on which they are formed are observed in the oxide semiconductor 90a or the oxide semiconductor 90c.

[0167] The crystal structure of the oxide semiconductor 90a or the oxide semiconductor 90c is not particularly limited as long as the lattice mismatch between the crystal of the oxide semiconductor 90b and the crystal of the oxide semiconductor 90a or the oxide semiconductor 90c is small. The crystal structure of the oxide semiconductor 90a or the oxide semiconductor 90c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0168] When the oxide semiconductor 90 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor 90 is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. Furthermore, in a transistor used in a smaller semiconductor device, the thickness of the oxide semiconductor 90 is preferably 1 nm to 20 nm, more preferably 3 nm to 15 nm, and further preferably 5 nm to 12 nm.

[0169] The oxide semiconductor 90b preferably has a thickness of, for example, 200 nm or less. When the oxide semiconductor 90b has a layer shape, the thickness is preferably, for example, 1 nm to 200 nm, more preferably 1 nm to 100 nm, and even more preferably 2 nm to 100 nm.

[0170] Alternatively, if the oxide semiconductor 90b can function as a crystal nucleus, the oxide semiconductor 90b may not exist as a layer but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the oxide semiconductor 90b exist discretely.

[0171] The oxide semiconductor 90a and the oxide semiconductor 90c each have a thickness of, for example, 1 nm to 50 nm, preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and more preferably 2 nm to 20 nm.

[0172] The thickness of the region where the component contained in the oxide semiconductor 90 and the component contained in the layer 92 are alloyed is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that Figures 5A and 5B show an example in which no alloy region is formed between the layer 92 and the oxide semiconductor 90a.

[0173] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0174] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor 90a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor 90a contains In) that is the main component of the oxide semiconductor 90a but is not the main component of the layer that will become the surface (here, layer 92) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor 90a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor 90a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0175] For example, when a silicon oxide layer is used as the layer 92 and an SIMS analysis is performed on the oxide semiconductor 90 formed on the layer 92, the interface is defined as a depth at which the silicon concentration is 50% of the maximum concentration of the layer 92, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 0.5 nm and the interface is defined as thickness t_s. The thickness t_s is preferably 3 nm or less, and more preferably 2 nm or less.

[0176] Note that by reducing the alloyed region, it is possible to form the CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of the oxide semiconductor 90 that is approximately perpendicular to the formation surface and is located between more than 0 nm and 3 nm, preferably more than 0 nm and 2 nm, more preferably 1 nm or more and 2 nm, inclusive.

[0177] The oxide semiconductor 90a has a region located, for example, at a depth of 0 nm to 3 nm from the top surface of the layer 92. The oxide semiconductor 90c is located, for example, at a depth of 0 nm to 3 nm from the top surface of the oxide semiconductor 90. The oxide semiconductors 90a, 90b, and 90c have, for example, approximately the same thickness. Alternatively, the oxide semiconductors 90a, 90b, and 90c may have different thicknesses.

[0178] Although the oxide semiconductor 90 has a three-layer structure including oxide semiconductors 90a to 90c in the above description, the present invention is not limited to this. The oxide semiconductor 90 may have a two-layer structure or a stacked structure of four or more layers.

[0179] For example, in the case of a two-layer structure in which oxide semiconductor 90a and oxide semiconductor 90b are stacked in this order, alloying of the components contained in oxide semiconductor 90 and the components contained in layer 92 can be suppressed, and the thickness of the alloyed region can be reduced, or the thickness can be made so thin that the alloyed region cannot be observed.

[0180] When the oxide semiconductor 90 has a five-layer structure, for example, the first, third, and fifth oxide semiconductor layers are preferably formed by an ALD method. The second and fourth oxide semiconductor layers are preferably formed by a sputtering method. This promotes crystal growth from one or both of the second and fourth oxide semiconductor layers, even when the third oxide semiconductor layer has a composition that makes it difficult to form a CAAC structure, thereby improving the crystallinity of the third oxide semiconductor layer.

[0181] When the oxide semiconductor 90 has a stacked structure, it is preferable to deposit each layer successively without exposing the layer to the air. For example, each layer may be deposited successively using a multi-chamber deposition apparatus. This can prevent impurities from being mixed in during deposition of the oxide semiconductor 90.

[0182] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0183] The CAAC structure of an oxide semiconductor layer can sometimes be evaluated from a map showing crystal orientation. For example, in a region having the CAAC structure, it is observed that crystals are c-axis oriented.

[0184] A map showing the crystal orientation can be obtained, for example, by acquiring a cross-sectional TEM image, performing FFT processing on each region within the cross-sectional TEM image to create an FFT pattern, and calculating the crystal axis direction of each region. Specifically, for example, two spots of high intensity are observed in the FFT pattern of a region having layered crystalline portions. The crystal axis direction of the region can be obtained from the angle of the line segment connecting the two spots. The FFT pattern reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0185] The c-axis orientation rate can be calculated by calculating the proportion of c-axis oriented regions in a map showing the crystal orientation.

[0186] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by performing TEM observation of a cross section or a plan view of the oxide semiconductor layer and using the map showing the crystal orientation described above. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0187] Furthermore, when performing analysis using a cross-sectional TEM image, the observation range of the cross-sectional TEM image may be, for example, a region with a width of 100 nm in the horizontal direction, with the direction perpendicular to the surface to be formed being the vertical direction. However, the observation range is not limited to this.

[0188] In the oxide semiconductor layer of one embodiment of the present invention, when the c-axis orientation rate is calculated as the percentage of regions whose orientation is within 20° of the c-axis, the c-axis orientation rate is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0189] The c-axis orientation rates of the region where the oxide semiconductor 90a is formed, the region where the oxide semiconductor 90b is formed, and the region where the oxide semiconductor 90c is formed are denoted by Rc1, Rc2, and Rc3, respectively. Here, the c-axis orientation rate is calculated as, for example, the percentage of regions where the difference from the c-axis is within 20°. Rc2 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0190] [Composition of Oxide Semiconductor Layer] The oxide semiconductor 90a preferably has a different composition from the oxide semiconductor 90b. The oxide semiconductor 90c preferably has a different composition from the oxide semiconductor 90b. The oxide semiconductor 90a may have the same composition as the oxide semiconductor 90c. Alternatively, the oxide semiconductor 90a and the oxide semiconductor 90c may have different compositions.

[0191] The oxide semiconductor 90b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 90b preferably contains, for example, zinc. By including zinc, the oxide semiconductor 90b becomes a metal oxide with high crystallinity. Furthermore, the oxide semiconductor 90b preferably contains, in addition to zinc, the element M. By including the element M in the oxide semiconductor 90b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Specifically, the oxide semiconductor 90b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:1:0.5, In:M:Zn=1:1:2, In:M:Zn=4:2:3, In:M:Zn=1:3:2, or In:M:Zn=1:3:4, or a composition close to these ratios. As the element M, it is preferable to use one or more of gallium, tin, yttrium, and aluminum.

[0192] The oxide semiconductor 90b may not contain the element M. For example, it may be an In-Zn oxide. Specifically, the composition may be In:Zn=1:1 (atomic ratio), In:Zn=2:1 (atomic ratio), or In:Zn=4:1 (atomic ratio), or a composition in the vicinity thereof. Alternatively, indium oxide may be used. Furthermore, the oxide semiconductor 90b may contain a trace amount of the element M. For example, the composition may be In:Ga:Zn=4:0.1:1 (atomic ratio), In:Ga:Zn=2:0.1:1 (atomic ratio), or a composition in the vicinity thereof. Furthermore, the composition may be In:Sn:Zn=4:0.1:1 (atomic ratio), In:Sn:Zn=2:0.1:1 (atomic ratio), or a composition in the vicinity thereof.

[0193] The oxide semiconductor 90a and the oxide semiconductor 90c can be metal oxides having a high proportion of In. It is particularly preferable that the oxide semiconductor 90a and the oxide semiconductor 90c be metal oxides having a higher proportion of In than the oxide semiconductor 90b. The oxide semiconductor 90a and the oxide semiconductor 90c can be formed by, for example, an ALD method. It is particularly preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, the on-state current of the transistor can be increased and the frequency characteristics can be improved.

[0194] An oxide semiconductor with a high In content tends to be polycrystalline. A polycrystalline metal oxide adversely affects the initial characteristics or reliability of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the crystal orientation of the oxide semiconductor 90b can be reflected in the oxide semiconductors 90a and 90c with a high In content. Therefore, even when a metal oxide with a high In content is used for the oxide semiconductors 90a and 90c, polycrystallization can be suppressed.

[0195] Alternatively, the oxide semiconductor 90a and the oxide semiconductor 90c may not contain the element M.

[0196] Furthermore, the oxide semiconductors 90a and 90c can be metal oxides with a high Ga content, such as metal oxides with a higher Ga content than the oxide semiconductor 90b. For example, the oxide semiconductors 90a and 90c preferably have a composition of In:Ga:Zn = 1:1:1 (atomic ratio), In:Ga:Zn = 1:3:2 (atomic ratio), or In:Ga:Zn = 1:3:4 (atomic ratio), or compositions close to these. Increasing the Ga content can sometimes increase the band gaps of the oxide semiconductors 90a and 90c compared to the oxide semiconductor 90b. By sandwiching the oxide semiconductor 90b between the oxide semiconductors 90a and 90c with larger band gaps, the oxide semiconductor 90b can function primarily as a current path (channel). Furthermore, trap levels at and near the interface of the oxide semiconductor 90b can be reduced. This allows a buried-channel transistor in which the channel is spaced away from the insulating layer interface to be realized. Furthermore, the influence of interface states that may be formed on the back channel side is reduced, light degradation of the transistor (for example, negative bias light degradation) can be suppressed, and the reliability of the transistor can be improved.

[0197] Alternatively, one of the oxide semiconductors 90a and 90c may be a metal oxide having a higher In content than the oxide semiconductor 90b, and the other may be a metal oxide having a higher Ga content than the oxide semiconductor 90b.

[0198] The oxide semiconductor 90a, the oxide semiconductor 90b, and the oxide semiconductor 90c may each have a stack of layers having the above-described compositions. For example, the oxide semiconductor 90c may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0199] The oxide semiconductors 90a and 90c may be made of a metal oxide having the same composition as the oxide semiconductor 90b. Using the same composition may make it easier for CAAC to occur after heat treatment.

[0200] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 90a and 90c have compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs with the oxide semiconductor 90b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 90a and 90c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductor 90a and the oxide semiconductor 90c and in a region including the oxide semiconductor 90b.

[0201] The composition of the metal oxide used in the oxide semiconductor 90 can be analyzed by, for example, EDX, X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy.

[0202] [Impurities in Oxide Semiconductor] The influence of each impurity in an oxide semiconductor will be described below. The impurities contained in an oxide semiconductor can be quantified using XPS, SIMS, EDX, ICP-MS, ICP-AES, or the like.

[0203] It is preferable that the channel formation region in the oxide semiconductor have fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source and drain regions. Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. ＯBy forming H and generating electrons that serve as carriers, the transistor tends to have normally-on characteristics. Therefore, in the channel formation region, not only oxygen vacancies but also V Ｏ It is preferable that H is also reduced. In this way, the channel formation region of the transistor is preferably a high-resistance region with a low carrier concentration, and can be said to be i-type (intrinsic) or substantially i-type.

[0204] Therefore, reducing the impurity concentration in an oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in an oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, elements with a concentration of less than 1 atomic % or less than 0.1 atomic % may be referred to as impurities.

[0205] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0206] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0207] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Furthermore, hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10１９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0208] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0209] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0210] This concludes the explanation of impurities.

[0211] The average thickness of the oxide semiconductor 90 in the channel formation region is preferably 30 nm or less, more preferably 15 nm or less, and further preferably 10 nm or less.

[0212] The oxide semiconductor 90a is an oxide semiconductor layer formed on a surface to be formed. The thickness of the oxide semiconductor 90a is preferably 0.5 nm or more and 3 nm or less.

[0213] In addition, in the semiconductor device of one embodiment of the present invention, when a cross section of the oxide 230 is observed, it may be possible to see that metal atoms of the metal oxide are arranged in a layered manner in a region having a CAAC structure. In this case, for example, the metal atoms are arranged in a direction perpendicular or approximately perpendicular to the substrate surface.

[0214] The metal atoms arranged in a layered manner in the region having the CAAC structure can be observed as an arrangement of bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. Therefore, in the semiconductor device of one embodiment of the present invention, when a cross section of the oxide 230 is observed, it may be possible to confirm that the bright spots are arranged in a direction perpendicular or substantially perpendicular to the substrate surface.

[0215] The oxide semiconductor 90, which is AG CAAC, can be used for the oxide 230 of the transistor 200. For example, the oxide semiconductor 90a can correspond to the oxide 230a of the oxide 230, and the oxide semiconductor 90b can correspond to the oxide 230b. The oxide 230 can also have a three-layer structure using oxide semiconductors 90a, 90b, and 90c. Furthermore, the oxide 230 can have a stacked structure of four or more layers.

[0216] By using the oxide 230, which is AG CAAC, in the channel formation region of the transistor 200, a transistor with favorable on-state current, field-effect mobility, S value, frequency characteristics, and reliability can be provided.

[0217] In the transistor 200, by providing the insulator 226 having a barrier property against hydrogen in contact with the bottom surface of the oxide 230 and using the oxide 230 having an AG-CAAC structure that makes mixing difficult, the impurities contained in the channel formation region of the transistor 200 can be significantly reduced. As a result, the transistor 200 can have extremely high reliability. Here, for example, if a high-mobility material is used for the oxide 230, the carrier concentration in the channel formation region may increase, resulting in an increase in off-state current. However, in one embodiment of the present invention, the impurity concentration in the channel formation region of the transistor 200 can be significantly reduced. Therefore, even if a high-mobility material, specifically, an oxide semiconductor material with a high indium content, is used for the oxide 230, favorable electrical characteristics (low off-state current) can be obtained. Therefore, the transistor 200 can be realized, which can increase the on-state current and is suitable for high-speed operation.

[0218] The channel formation region of the oxide semiconductor preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ On the other hand, it is preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. The transistor 200 preferably has a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like and has high conductivity. Note that hydrogen in the oxide semiconductor is converted into V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0219] Therefore, in this embodiment, the semiconductor device is configured to reduce the hydrogen concentration in the channel formation region, suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, and suppress reduction in the hydrogen concentration in the source and drain regions.

[0220] The insulator 250 in contact with the channel formation region in the oxide 230b preferably has a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide 230b. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0221] 3A, the insulator 250 preferably has a layered structure of an insulator 250a in contact with the oxide 230, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. In this case, it is preferable that the insulator 250a has the function of capturing and fixing hydrogen.

[0222] Examples of insulators that have the function of capturing and fixing hydrogen include metal oxides with an amorphous structure. For example, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium as the insulator 250a. In such metal oxides with an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides with an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0223] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulator 250a. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulator 250a makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0224] For the above reasons, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 250a, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure. In this embodiment, an aluminum oxide film is used as the insulator 250a. In this case, the insulator 250a is an insulator containing at least oxygen and aluminum. Furthermore, the aluminum oxide has an amorphous structure. In this case, the insulator 250a has an amorphous structure.

[0225] Alternatively, the insulator 250a may be an insulating film having a barrier property against hydrogen similar to that of the insulator 226. This allows the channel formation region of the oxide 230 to be surrounded by the insulator 226 and the insulator 250a, each of which has a barrier property against hydrogen, thereby effectively preventing hydrogen from being mixed into the oxide 230. Preferably, silicon nitride can be used for the insulator 250a.

[0226] Next, it is preferable to use an insulator with a thermally stable structure, such as silicon oxide or silicon oxynitride, for the insulator 250b. Note that in this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0227] 3C, a structure may be adopted in which an insulator 250d is provided on the insulator 250b. In this case, the insulator 250d may be an insulator that can be used for the insulator 250a. For example, hafnium oxide may be used for the insulator 250d. Here, by providing the insulator 250d between the insulator 250c and the insulator 250b, hydrogen contained in the insulator 250b and the like can be more effectively captured and fixed.

[0228] In order to suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide a barrier insulator against oxygen near each of the conductor 242a, the conductor 242b, and the conductor 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulator 250a, the insulator 250c, the insulator 250d, the insulator 255, and the insulator 275.

[0229] Examples of the oxygen barrier insulator include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulators 250a, 250c, 250d, 255, and 275 each preferably have a single-layer structure or a stacked-layer structure of the oxygen barrier insulators.

[0230] The insulators 250a and 255 preferably have barrier properties against oxygen. The insulators 250a and 255 are preferably at least less permeable to oxygen than the insulator 280. The insulator 250a has a region in contact with the side surface of the conductor 242a1 and the side surface of the conductor 242b1. The insulator 255 has a region in contact with the top surface of the conductor 242a1, the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2. The insulator 250a also contacts the top surface and side surface of the insulator 255. The insulators 250a and 255 have barrier properties against oxygen, which can prevent the side surfaces of the conductors 242a and 242b from being oxidized and oxide films from being formed on the side surfaces. This can prevent a decrease in the on-state current or field-effect mobility of the transistor 200.

[0231] The insulator 250a is provided in contact with the top surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 226, the side surfaces of the insulator 224, and the top surface of the insulator 222. The insulator 250a has a barrier property against oxygen, which can prevent oxygen from being released from the channel formation region of the oxide 230b when heat treatment or the like is performed. Therefore, the formation of oxygen vacancies in the oxide 230a and the oxide 230b can be reduced.

[0232] Furthermore, by providing the insulators 250a and 255, even if the insulator 280 contains an excessive amount of oxygen, the oxygen can be prevented from being excessively supplied to the oxides 230a and 230b, and an appropriate amount of oxygen can be supplied to the oxides 230a and 230b. Therefore, excessive oxidation of the source and drain regions can be prevented, which can cause a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0233] An oxide containing one or both of aluminum and hafnium has a barrier property against oxygen and can therefore be suitably used as the insulator 250a. Silicon nitride also has a barrier property against oxygen and can therefore be suitably used as the insulator 255.

[0234] The insulator 250c preferably has a barrier property against oxygen. The insulator 250c is provided between the channel formation region of the oxide 230 and the conductor 260, and between the insulator 280 and the conductor 260. This structure can prevent oxygen contained in the channel formation region of the oxide 230 from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide 230. Furthermore, it can prevent oxygen contained in the oxide 230 and oxygen contained in the insulator 280 from diffusing to the conductor 260 and oxidizing the conductor 260. The insulator 250c is preferably at least less permeable to oxygen than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250c. In this case, the insulator 250c is an insulator containing at least nitrogen and silicon.

[0235] The insulator 250c preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide 230b.

[0236] The insulator 275 preferably has a barrier property against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a, and between the insulator 280 and the conductor 242b. This configuration can prevent oxygen contained in the insulator 280 from diffusing into the conductor 242a and the conductor 242b. Therefore, it is possible to prevent the conductor 242a and the conductor 242b from being oxidized by the oxygen contained in the insulator 280, thereby increasing their resistivity and reducing their on-state current. The insulator 275 is preferably at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0237] To prevent a decrease in the hydrogen concentration in the source and drain regions in the oxide 230, it is preferable to provide a barrier insulator against hydrogen near each of the source and drain regions. In the semiconductor device described in this embodiment, the barrier insulator against hydrogen is, for example, the insulator 275.

[0238] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 is preferably a single-layer structure or a stacked structure of the above-mentioned barrier insulator against hydrogen.

[0239] By providing the insulator 275 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentration in the source and drain regions, thereby making it possible to make the source and drain regions n-type.

[0240] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0241] The insulators 250a to 250d function as part of the first gate insulator. The insulators 250a to 250d, together with the insulator 255 and the conductor 260, are provided in an opening formed in the insulator 280. To miniaturize the transistor 200, the thicknesses of the insulators 250a to 250d are preferably small. The thicknesses of the insulators 250a to 250d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulators 250a to 250d may have a region with the above thickness at least in part.

[0242] To achieve the above-described thin film thicknesses of the insulators 250a to 250d, it is preferable to deposit the insulators 255 and 250 by the ALD method, which allows the insulators 255 and 250 to be deposited to the above-described thin film thicknesses with good coverage on the side surfaces of the openings formed in the insulator 280 and the side ends of the conductors 242a and 242b.

[0243] Although the above description has been given of a structure in which the insulator 250 has a three-layer structure of insulators 250a to 250c or a four-layer structure of insulators 250a to 250d, the present invention is not limited to this. The insulator 250 can also have a structure including at least one of the insulators 250a to 250d. By configuring the insulator 250 as one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0244] For example, as shown in FIG. 3B , the insulator 250 may have a two-layer structure. In this case, it is preferable that the insulator 250 has a stacked structure of an insulator 250a and an insulator 250c on the insulator 250a. A high-k material can be used for at least one of the insulators 250a and 250c. This allows the equivalent oxide thickness (EOT) to be reduced while maintaining the thicknesses of the insulators 250a and 250c at a level that suppresses leakage current.

[0245] 3B , in the transistor 200 according to this embodiment, a region overlapping with the insulator 250 in contact with the side surface of the conductor 242a1 and a region overlapping with the insulator 250 in contact with the side surface of the conductor 242b1 (hereinafter referred to as an Loff region) are formed in the oxide 230b. The Loff region does not overlap with the conductor 242a1 or the conductor 242b1 and does not properly overlap with the conductor 260 via the insulator 250, and therefore functions as a resistor. By providing the Loff region between the channel formation region and the source region or the drain region of the transistor 200, hot carrier degradation can be suppressed.

[0246] In the transistor 200 shown in FIG. 3B , the insulator 250 is formed only by the insulator 250 a and the insulator 250 c, and the thicknesses of the insulators 250 a and 250 c can be thinned as described above. For example, the insulator 250 a can be formed using aluminum oxide to a thickness of 2.0 nm, and the insulator 250 c can be formed using silicon nitride to a thickness of 1.5 nm, resulting in a thickness of the insulator 250 of 3.5 nm. By thinning the thickness of the insulator 250 in this manner, the width of the Loff region can also be reduced. Therefore, the frequency characteristics of the transistor 200 can be improved, and the operating speed of the semiconductor device according to one embodiment of the present invention can be increased.

[0247] Furthermore, in this embodiment, an insulator 255 is provided between the insulator 250 and the conductor 242a, and between the insulator 250 and the conductor 242b. This allows the distance between the conductor 260 and the conductor 242a and the distance between the conductor 260 and the conductor 242b to be increased by the thickness of the insulator 255. Therefore, the film thickness of the insulator 250 can be made thinner to reduce the Loff region while reducing the parasitic capacitance between the conductor 260 and the conductor 242a and between the conductor 242b and the conductor 242b.

[0248] In addition to the above structure, in this embodiment, the semiconductor device preferably has a structure that suppresses hydrogen from being mixed into the transistor 200 or the like. For example, an insulator that has a function of suppressing hydrogen diffusion is preferably provided so as to cover one or both of the top and bottom of the transistor 200 or the like. In the semiconductor device described in this embodiment, the insulator is, for example, an insulator 282 or an insulator 283. Furthermore, the insulator 215 provided under the transistor 200 may have a structure similar to either or both of the insulators 282 and 283. In this case, the insulator 215 may have a stacked structure of the insulators 282 and 283, or may have a structure in which the insulator 282 is on the bottom and the insulator 283 is on the top, or may have a structure in which the insulator 282 is on the top and the insulator 283 is on the bottom.

[0249] It is preferable that one or more of the insulators 282 and 283 function as a barrier insulator that prevents impurities such as water and hydrogen from diffusing from the substrate side or from above the transistor 200 to the transistor 200. Therefore, one or more of the insulators 282 and 283 may be a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0250] The insulators 282 and 283 preferably have an insulator that suppresses the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulator 283 is preferably made of silicon nitride, which has a higher hydrogen barrier property. Furthermore, the insulator 282 preferably includes aluminum oxide or magnesium oxide, which has a high hydrogen capture and fixation function. This can suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film disposed outside the insulator 283 to the transistor 200 or the like. Furthermore, oxygen contained in the insulator 280 or the like can be suppressed from diffusing upward from the transistor 200 or the like through the insulator 282 or the like. Furthermore, by using the insulator 215 in the same structure as one or both of the insulators 282 and 283, the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 or the like through the insulator 215 can be suppressed. Furthermore, oxygen contained in the insulator 224 or the like can be prevented from diffusing toward the substrate. In this manner, it is preferable to have a structure in which the top and bottom of the transistor 200 or the like are surrounded by insulators that have a function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0251] In the transistor 200, the conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. Furthermore, the conductor 205 is preferably provided to extend in the channel width direction as shown in FIGS. 1A and 1C . With this structure, when a plurality of transistors are provided, the conductor 205 functions as a wiring.

[0252] The conductor 205 may have a single-layer structure or a multilayer structure. In FIG. 1 and other figures, the conductor 205 includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to fill a recess in the conductor 205a formed along the opening. Here, the height of the upper surface of the conductor 205 is approximately the same as the height of the upper surface of the insulator 216.

[0253] Here, the conductor 205a is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0254] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 216, etc. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single-layer structure or a multilayer structure of the above conductive materials. For example, the conductor 205a preferably contains titanium nitride.

[0255] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0256] The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0257] Furthermore, the electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. Furthermore, the film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby suppressing the diffusion of the impurities into the oxide 230.

[0258] Insulator 222, insulator 224, and insulator 226 function as a second gate insulator.

[0259] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). The insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0260] The insulator 222 preferably includes an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator. Alternatively, an oxide containing hafnium and zirconium, such as hafnium zirconium oxide, is preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with oxygen contained in the insulator 224 and the oxide 230.

[0261] Alternatively, the insulator may be doped with, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on the insulator.

[0262] The insulator 222 may have a single-layer structure or a multi-layer structure of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. The insulator 222 may also be made of lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), (Ba,Sr)TiO ３ In some cases, a material with a high dielectric constant such as (BST) can be used.

[0263] Insulator 224 preferably comprises, for example, silicon oxide or silicon oxynitride.

[0264] The insulator 224 functions as a spacer for positioning the bottom surface of the oxide 230b higher than the bottom surface of the conductor 260. Therefore, it is preferable to form the insulator 224 relatively thick, and it is preferable to use an insulator whose deposition rate can be easily increased, such as silicon oxide or silicon oxynitride. However, impurities such as hydrogen easily diffuse into such insulators, so it is important to provide an insulator 226 having barrier properties against hydrogen between the insulator 224 and the oxide 230.

[0265] The insulator 224 is preferably processed into an island shape, similar to the insulator 226 and the oxide 230. This means that when multiple transistors 200 are provided, each transistor 200 has an insulator 224 of approximately the same size. However, this is not limiting, and similar to the insulator 222, the insulator 224 may also be configured not to be patterned.

[0266] Each of the insulators 222, 224, and 226 may have a stacked structure of two or more layers. In this case, the stacked structures are not limited to those made of the same material, and may be stacked structures made of different materials. Note that a configuration may be adopted in which either or both of the insulators 224 and 222 are not included.

[0267] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen as the conductors 242a, 242b, and 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductors 242a, 242b, and 260. When a conductive material containing metal and nitrogen is used as the conductors 242a, 242b, and 260, the conductors 242a, 242b, and 260 are conductors that contain at least metal and nitrogen.

[0268] In FIG. 1B, the conductors 242a and 242b are shown as a two-layer structure. The conductor 242a is a laminated film of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b is a laminated film of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the layer in contact with the oxide 230b (the conductor 242a1 and the conductor 242b1). This can prevent the conductivity of the conductors 242a and 242b from decreasing. In addition, it can prevent oxygen from being extracted from the oxide 230b, thereby preventing excessive oxygen vacancies from being formed. Furthermore, it is preferable to use a material that easily absorbs (extracts) hydrogen for the layers in contact with the oxide 230b (the conductor 242a1 and the conductor 242b1), since this can reduce the hydrogen concentration in the oxide 230b.

[0269] For the conductors 242a1 and 242b1, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0270] Note that hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a1 or the conductor 242b1. In particular, by using a nitride containing tantalum for the conductors 242a1 and 242b1, hydrogen contained in the oxide 230b and the like is likely to diffuse into the conductor 242a1 or the conductor 242b1, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a1 or the conductor 242b1. In other words, hydrogen contained in the oxide 230b and the like may be absorbed by the conductor 242a1 or the conductor 242b1.

[0271] Furthermore, it is preferable that the conductors 242a2 and 242b2 have higher conductivity than the conductors 242a1 and 242b1. For example, it is preferable that the film thickness of the conductors 242a2 and 242b2 be greater than the film thickness of the conductors 242a1 and 242b1. Conductors that can be used for the conductor 205b may be used for the conductors 242a2 and 242b2. By using the above structure, the resistance of the conductors 242a2 and 242b2 can be reduced. This can improve the operating speed of the semiconductor device according to this embodiment.

[0272] For example, tantalum nitride or titanium nitride can be used as the conductors 242a1 and 242b1, and tungsten can be used as the conductors 242a2 and 242b2.

[0273] Furthermore, to prevent a decrease in the conductivity of the conductors 242a and 242b, it is preferable to use a crystalline oxide such as CAAC-OS as the oxide 230b. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. The use of CAAC-OS can prevent the conductor 242a or the conductor 242b from extracting oxygen from the oxide 230b. Furthermore, a decrease in the conductivity of the conductors 242a and 242b can be prevented.

[0274] 1B and 1C , the insulator 255 is disposed in an opening formed in the insulator 280, etc., and contacts the side surface of the insulator 280, the side surface of the insulator 275, the side surface of the insulator 271a, the side surface of the insulator 271b, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the top surface of the conductor 242a1, the top surface of the conductor 242b1, and the top surface of the insulator 222. In other words, the insulator 255 has openings formed therein so as to expose the island-shaped oxide 230. Furthermore, in the region where the openings are formed in the insulator 255, the insulator 250 contacts the oxide 230 and the insulator 222. Note that in FIG. 1C , the insulator 255 has openings only near the oxide 230, but the present invention is not limited to this. The insulator 255 only needs to have an opening in at least the region of the oxide 230b that is sandwiched between the conductors 242a1 and 242b1. Therefore, for example, the insulator 255 may have almost no region in contact with the insulator 222 and may be formed in a sidewall shape in the opening formed in the insulator 280.

[0275] The insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, and is an inorganic insulator that protects the conductors 242a2 and 242b2. Because the insulator 255 is exposed to an oxidizing atmosphere, it is preferable that the insulator 255 be an inorganic insulator that is resistant to oxidation. Furthermore, because the insulator 255 is in contact with the conductors 242a2 and 242b2, it is preferable that the insulator 255 be an inorganic insulator that is resistant to oxidation of the conductors 242a2 and 242b2. Therefore, it is preferable that the insulator 255 be made of an insulating material that can be used for the insulator 250c that has oxygen barrier properties. For example, silicon nitride can be used as the insulator 255.

[0276] By using such an insulator 255, the conductors 242a2 and 242b2 are not excessively oxidized even if heat treatment is performed in an oxygen-containing atmosphere after separating the conductors 242a1 and 242b1 and before forming the insulator 250. For example, the thickness of the oxide film on the side surfaces of the conductors 242a2 and 242b2 near the conductor 260 can be set to 0.5 nm or more and 5 nm or less, preferably 0.5 nm or more and 3 nm or less, and more preferably 0.5 nm or more and 2 nm or less.

[0277] The insulator 255 is preferably thicker than any one of the insulators 250a to 250d. The thickness of the insulator 255 is preferably 1 nm to 20 nm, more preferably 1 nm to 15 nm, and even more preferably 3 nm to 10 nm. For example, the thickness can be approximately 5 nm. By setting the thickness of the insulator 255 as described above, the distance between the conductor 260 and the conductor 242a and the distance between the conductor 260 and the conductor 242b can be increased. Therefore, parasitic capacitance can be reduced. Note that the insulator 255 only needs to have a region with the above thickness in at least a portion. Furthermore, since the insulator 255 is provided in the opening formed in the insulator 280, it is preferable to form the insulator 255 using an ALD method or the like, which has good coverage.

[0278] The insulator 255 may also have a stacked structure of two or more layers using the above-mentioned inorganic insulator that is resistant to oxidation. For example, the insulator 255 may have a two-layer structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film. When the insulator 255 has a stacked structure of two or more layers, at least one layer may be the above-mentioned inorganic insulator that is resistant to oxidation. For example, the insulator 255 may have a two-layer structure of a silicon nitride film and a silicon oxide film on the silicon nitride film. For example, the insulator 255 may have a two-layer structure of an aluminum oxide film and a silicon oxide film on the aluminum oxide film. For example, the insulator 255 may have a two-layer structure of a silicon oxide film and a silicon nitride film on the silicon oxide film. For example, the insulator 255 may have a two-layer structure of a silicon oxide film and an aluminum oxide film on the silicon oxide film. For example, the insulator 255 may have a two-layer structure of a silicon oxide film and a silicon oxide film on the silicon oxide film. For example, the insulator 255 may have a two-layer structure of a silicon oxide film and an aluminum oxide film on the silicon oxide film.

[0279] Furthermore, the insulator 255 functions as part of a mask when dividing the conductor 242a1 and the conductor 242b1. Therefore, as shown in FIG. 1B , in a cross-sectional view of the transistor 200, it is preferable that the side edges of the insulator 255 substantially coincide with the side edges of the conductor 242a1 and the conductor 242b1.

[0280] In addition, when the side edges are aligned or approximately aligned in a cross-sectional view, and when the top surface shapes are aligned or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a top view. For example, this includes a case where the lower portion of the side edge of the upper layer contacts the upper portion of the side edge of the lower layer. It also includes a case where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In this case, too, it is said that the side edges are approximately aligned or the top surface shapes are approximately aligned.

[0281] Possible paths for hydrogen diffusion into the oxide 230 include the conductor 242a and the conductor 242b in contact with the oxide 230 and the insulator 250 in contact with the oxide 230. Therefore, it is preferable to use a film having a barrier property against hydrogen for the insulator 275 located over the conductor 242a and the conductor 242b and the insulator 255 located between the insulator 250 and the insulator 280. Furthermore, the insulator 275 is also located between the side surface of the oxide 230 and the insulator 280 and has the function of preventing hydrogen from diffusing directly from the insulator 280 to the oxide 230. This not only provides the insulator 226 with a film having a barrier property against hydrogen in contact with the underside of the oxide 230, but also prevents hydrogen from diffusing into a film that could serve as a diffusion path for hydrogen into the oxide 230. With this structure, hydrogen can be prevented from entering the oxide semiconductor as much as possible, thereby achieving a highly reliable transistor 200.

[0282] Here, the portion of the conductor 242a1 on whose upper surface the insulator 255 is formed protrudes more toward the conductor 260 than the conductor 242a2. Similarly, the portion of the conductor 242b1 on whose upper surface the insulator 255 is formed protrudes more toward the conductor 260 than the conductor 242b2. As shown in FIG. 3A , in a cross-sectional view of the transistor 200 in the channel length direction, the distance L2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L1 between the conductor 242a2 and the conductor 242b2.

[0283] The distance L2 between the conductor 242a1 and the conductor 242b1 is preferably small because it affects the channel length of the transistor 200. For example, the distance L2 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and is preferably 1 nm or more, or 5 nm or more. For example, the distance L2 is more preferably approximately 2 nm or more and 20 nm or less. This configuration makes it possible to further shorten the distance between the source and drain, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. In this way, miniaturization of the semiconductor device can provide a semiconductor device with improved operating speed.

[0284] 3A, the opposing side surfaces of the conductor 242a1 and the conductor 242b1 are substantially perpendicular to the top surface of the oxide 230b, but the present invention is not limited to this. For example, as shown in FIG. 4A, the opposing side surfaces of the conductor 242a1 and the conductor 242b1 may be tapered. By adopting such a shape, the distance between the conductor 260 and the oxide 230b is reduced near the side ends of the conductor 242a1 and the conductor 242b1, thereby reducing the influence of the Loff region.

[0285] Furthermore, as shown in FIG. 4B, the opposing side surfaces of the conductors 242a1 and 242b1 may be tapered, and the opposing side surfaces of the conductors 242a2 and 242b2 may also be tapered.

[0286] 4C , the taper angles of the conductors 242a1 and 242b1 may be configured to be more acute than the taper angles of the conductors 242a2 and 242b2. By using such a shape, the distance between the conductor 260 and the oxide 230b becomes smaller near the side ends of the conductor 242a1 and the conductor 242b1, thereby reducing the influence of the Loff region.

[0287] The insulators 271a and 271b are inorganic insulators that function as etching stoppers and protect the conductors 242a2 and 242b2 when processing the conductors 242a2 and 242b2. The insulator 271a contacts the conductor 242a2, and the insulator 271b contacts the conductor 242b2. Therefore, it is preferable that the insulators 271a and 271b be inorganic insulators that are less likely to oxidize the conductors 242a and 242b. Therefore, as shown in FIG. 3A , it is preferable that the insulator 271a has a layered structure of an insulator 271a1 and an insulator 271a2 on the insulator 271a1, and the insulator 271b has a layered structure of an insulator 271b1 and an insulator 271b2 on the insulator 271b1. Here, the insulators 271a1 and 271b1 are preferably made of a nitride insulator that can be used for the insulator 250c so as to prevent oxidation of the conductors 242a2 and 242b2, and the insulators 271a2 and 271b2 are preferably made of an oxide insulator that can be used for the insulator 250b so as to function as an etching stopper.

[0288] Here, the insulator 271a1 is in contact with the upper surface of the conductor 242a2 and a portion of the insulator 275, and the insulator 271b1 is in contact with the upper surface of the conductor 242b2 and a portion of the insulator 275. The insulator 271a2 is in contact with the upper surface of the insulator 271a1 and a lower surface of the insulator 275, and the insulator 271b2 is in contact with the upper surface of the insulator 271b1 and a lower surface of the insulator 275. For example, silicon nitride can be used for the insulators 271a1 and 271b1, and silicon oxide can be used for the insulators 271a2 and 271b2.

[0289] Because the insulators that form the insulators 271a and 271b function as masks for the conductors that form the conductors 242a and 242b, the conductors 242a and 242b do not have curved surfaces between their side surfaces and top surfaces. As a result, the ends where the side surfaces and top surfaces of the conductors 242a and 242b intersect are angular. Because the ends where the side surfaces and top surfaces of the conductors 242a and 242b intersect are angular, the cross-sectional areas of the conductors 242a and 242b are larger than when the ends have curved surfaces. Furthermore, using a nitride insulator that does not easily oxidize metals for the insulators 271a1 and 271b1 can prevent the conductors 242a and 242b from being excessively oxidized. As a result, the resistance of the conductors 242a and 242b is reduced, thereby increasing the on-state current of the transistor.

[0290] 1B and 1C, the conductor 260 is disposed in an opening formed in the insulator 280 and the insulator 275. The conductor 260 is disposed in the opening so as to cover, via the insulator 250, the side surface of the insulator 224, the side surface of the insulator 226, the side surface of the oxide 230a, the side surface of the oxide 230b, and the top surface of the oxide 230b. Note that a portion of the conductor 260 is disposed so as to overlap the conductor 242a1 and the conductor 242b1. The conductor 260 is disposed so that its top surface is approximately flush with the top of the insulator 250 and the top surface of the insulator 280.

[0291] In the opening in which the conductor 260 and the insulator 250 are disposed, the sidewall of the opening may be approximately perpendicular to the upper surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, the coverage of the insulators 255 and 250, etc., provided in the opening of the insulator 280 is improved, and defects such as voids can be reduced.

[0292] The conductor 260 functions as a first gate electrode of the transistor 200. Here, the conductor 260 is preferably provided to extend in the channel width direction, as shown in Figures 1A and 1C. With this configuration, when a plurality of transistors are provided, the conductor 260 functions as a wiring.

[0293] 1C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as a rounded shape).

[0294] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductors 242a and 242b, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably 1 nm or larger and 15 nm or smaller, and more preferably 2 nm or larger and 10 nm or smaller. By using such a shape, the coverage of the oxide 230b by the insulator 250 and the conductor 260 can be improved.

[0295] In this specification, a transistor structure in which a channel formation region is electrically surrounded by the electric field of at least the first gate electrode is referred to as a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification is different from the Fin structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification can also be considered as a type of Fin structure. In this specification, a Fin structure refers to a structure in which a gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By employing the Fin structure and the S-channel structure, resistance to the short channel effect can be increased, in other words, a transistor in which the short channel effect is less likely to occur can be obtained.

[0296] By forming the transistor 200 in the S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming the transistor 200 in the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be improved, which is expected to improve the on-state current or the field-effect mobility of the transistor.

[0297] In this embodiment, the insulators 224 and 226 are provided in an island shape. Therefore, as shown in FIG. 1C , at least a portion of the lower surface of the conductor 260 can be provided below the lower surface of the oxide 230b. This allows the conductor 260 to be provided facing the upper surface and side surface of the oxide 230b, and therefore the electric field of the conductor 260 can be applied to the upper surface and side surface of the oxide 230b. By providing the insulators 224 and 226 in an island shape in this way, the transistor 200 can have an S-channel structure.

[0298] 1C illustrates an example of a transistor with an S-channel structure, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistor structure that can be used in one embodiment of the present invention may be one or more selected from a planar structure, a Fin structure, and a GAA structure.

[0299] In Figure 1B and other figures, the conductor 260 is shown as having a two-layer structure. Here, the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to surround the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260a.

[0300] The conductor 260a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0301] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 280, etc. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0302] The conductor 260b is preferably made of a highly conductive material. For example, the conductor 260b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0303] In the transistor 200, the conductor 260 is formed in a self-aligned manner to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be arranged to overlap the region between the conductor 242a1 and the conductor 242b1 without alignment.

[0304] The insulators 216 and 280 preferably have a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced.

[0305] For example, it is preferable that the insulators 216 and 280 each have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0306] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0307] Furthermore, the top surfaces of the insulators 216 and 280 may each be flattened.

[0308] It is preferable that the concentration of impurities such as water and hydrogen be reduced in the insulator 280. For example, it is preferable that the insulator 280 have an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0309] <Constituent Materials of Semiconductor Device> Constituent materials that can be used for the semiconductor device will be described below. Each layer that constitutes the semiconductor device may have a single layer structure or a multilayer structure.

[0310] <<Substrate>> Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include semiconductor substrates having an insulator region within the semiconductor substrate, such as SOI (Silicon-On-Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having metal nitrides, substrates having metal oxides, substrates in which a conductor or semiconductor is provided on an insulator substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductor substrate. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0311] <<Insulator>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0312] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material depending on the function of the insulator.

[0313] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0314] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0315] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0316] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0317] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. Examples of the conductor include tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0318] When a conductor with a layered structure is used, for example, a layered structure combining the material containing the metal element described above and a conductive material containing oxygen, a layered structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0319] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0320] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive materials containing the metal element and nitrogen described above may be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0321] 7A to 18D, an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Here, the case of manufacturing the semiconductor device illustrated in FIGS. 1A to 1D will be described as an example.

[0322] Each figure (A) except for Figures 12 and 15 shows a plan view. Each figure (B) is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in each figure (A), and is also a cross-sectional view of the transistor 200 in the channel length direction. Each figure (C) is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in each figure (A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Each figure (D) is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A5-A6 in each figure (A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted from the plan view in each figure (A) for clarity. Each of Figures 12A to 12D and Figures 15A to 15D is an enlarged cross-sectional view of the transistor 200 in the channel length direction.

[0323] In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed as a film by appropriately using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0324] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0325] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0326] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0327] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0328] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0329] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0330] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0331] First, a substrate (not shown) is prepared, and an insulator 215 is formed on the substrate (see FIGS. 7A to 7D ). As described above, the insulator 215 can be formed using an insulator similar to one or more of the insulators 224, 282, and 283. The insulator 215 can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. Sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, is preferable because it can reduce the hydrogen concentration in the insulator 215.

[0332] Next, the insulator 216 is deposited over the insulator 215. The insulator 216 is preferably deposited by a sputtering method. The hydrogen concentration in the insulator 216 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. However, the deposition of the insulator 216 is not limited to a sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate. In this embodiment, silicon oxide is deposited as the insulator 216 by a sputtering method.

[0333] The insulators 215 and 216 are preferably successively formed without exposure to the air. For example, a multi-chamber film formation apparatus can be used. This allows the insulators 215 and 216 to be formed with reduced hydrogen content and reduces the amount of hydrogen mixed into the films between film formation steps.

[0334] Next, an opening is formed in the insulator 216, reaching the insulator 215. The opening may be formed by wet etching, but dry etching is preferable for fine processing. Furthermore, it is preferable to select an insulator for the insulator 215 that functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 215 may be made of silicon nitride, aluminum oxide, hafnium oxide, or the like.

[0335] After the opening is formed, a conductive film that becomes the conductor 205a is formed. The conductive film that becomes the conductor 205a preferably includes a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film can be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film that becomes the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0336] In this embodiment, titanium nitride is formed as the conductive film that becomes the conductor 205a. By using such a metal nitride for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like. Furthermore, even if a metal that easily diffuses, such as copper, is used for the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0337] Next, a conductive film to be the conductor 205b is formed. As the conductive film to be the conductor 205b, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film to be the conductor 205b.

[0338] Next, chemical mechanical polishing (CMP) is performed to remove a portion of the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216 (see FIGS. 7A to 7D). As a result, the conductor 205a and the conductor 205b remain only in the openings. Note that the CMP process may remove a portion of the insulator 216.

[0339] Next, an insulator 222 is formed over the insulator 216 and the conductor 205 (see FIGS. 8A to 8D).

[0340] The insulator 222 may be an insulator containing one or both of aluminum and hafnium oxides. As the insulator containing one or both of aluminum and hafnium oxides, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. When the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in structures provided around the transistor are prevented from diffusing into the inside of the transistor through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0341] Alternatively, the insulator 222 can be a stacked film of an insulator containing an oxide of one or both of aluminum and hafnium, and silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide.

[0342] The insulator 222 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, hafnium oxide is formed as the insulator 222 by an ALD method. Alternatively, the insulator 222 may be a stacked film of silicon nitride formed by a PEALD method and hafnium oxide formed by an ALD method.

[0343] Next, an insulating film 224f is formed over the insulator 222 (see FIGS. 8A to 8D). As the insulating film 224f, an insulator corresponding to the insulator 224 may be used.

[0344] The insulating film 224f can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon oxide is formed as the insulating film 224f by sputtering. By using sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 224f can be reduced. Since the insulating film 224f will come into contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0345] Note that heat treatment may be performed before the formation of the insulating film 224f. The heat treatment may be performed under reduced pressure, and the insulating film 224f may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 222 can be removed and the moisture and hydrogen concentrations in the insulator 222 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0346] Subsequently, an insulating film 226f is formed on the insulating film 224f (see FIGS. 8A to 8D). The insulating film 226f may be made of an insulator corresponding to the insulator 226. In particular, it is preferable to use silicon nitride, aluminum oxide, hafnium oxide, or tantalum oxide as the insulating film 226f.

[0347] The insulating film 226f can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. It is particularly preferable to form the insulating film 226f by ALD. This allows the insulating film 226f to be dense and thin, and provides good barrier properties against hydrogen.

[0348] For example, when a silicon nitride film is formed using the PEALD method, it is preferable to use a precursor containing a halogen such as fluorine, chlorine, bromine, or iodine. ２ , N ２ O, N.H. ３ , NO, NO ２ , and N ２ O ２By performing a plasma treatment in an atmosphere containing a nitriding agent such as nitriding agent, a high-quality silicon nitride film can be formed.

[0349] Silicon nitride has a barrier property against hydrogen if its film thickness is, for example, 2 nm or more, and has a high barrier property against hydrogen if its film thickness is, for example, 3 nm or more. Therefore, it is preferable to form the insulating film 226f using a silicon nitride film having a film thickness of 2 nm or more, preferably 3 nm or more. In this embodiment, a silicon nitride film having a thickness of 2 nm is formed as the insulating film 226f by the PEALD method.

[0350] Next, an oxide film 230af is formed on the insulating film 226f, and an oxide film 230bf is formed on the oxide film 230af (see FIGS. 8A to 8D ). The oxide film 230af may be a metal oxide corresponding to the oxide 230a, and the oxide film 230bf may be a metal oxide corresponding to the oxide 230b. It is preferable to form the oxide films 230af and 230bf consecutively without exposing them to the air. By forming the films without exposing them to the air, it is possible to prevent impurities or moisture from the air from adhering to the oxide films 230af and 230bf, and to keep the vicinity of the interface between the oxide films 230af and 230bf clean.

[0351] The oxide film 230af and the oxide film 230bf can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In the following, an example in which the oxide film 230af and the oxide film 230bf are formed by a sputtering method will be described.

[0352] For example, when the oxide film 230af and the oxide film 230bf are formed by sputtering, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, an In-M-Zn oxide target or the like can be used.

[0353] When the oxide film 230bf is formed by a sputtering method, an oxygen-excess oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230bf is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0354] As a more specific example, the oxide film 230af is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:2 or an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4. The oxide film 230bf is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1, an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2, an oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1, or an oxide target with an atomic ratio of In:Ga:Zn = 1:1:2. The oxide films 230a and 230b can be formed according to the desired characteristics of the oxides 230a and 230b by appropriately selecting the film formation conditions and atomic ratios.

[0355] It is preferable to form the oxide film 230af and the oxide film 230bf by sputtering without exposing them to the atmosphere. For example, it is preferable to use a multi-chamber film forming apparatus. This can reduce the incorporation of hydrogen into the oxide film 230af and the oxide film 230bf between film forming steps.

[0356] Furthermore, the above-described film having the AG CAAC structure can be applied to the oxide 230. In this case, the above-described method for forming a film having the AG CAAC structure can be applied instead of the method for forming the oxide film 230af and the oxide film 230bf. In this case, the insulating film 226f and the first layer of the oxide 230 are preferably formed successively by an ALD method (including a PEALD method) without exposure to the atmosphere. For example, it is preferable to form the films using a multi-chamber film formation apparatus. Alternatively, when the film formation temperature is the same, these films may be formed successively using the same film formation chamber by changing the gas introduced.

[0357] Next, heat treatment is preferably performed within a temperature range in which the oxide film 230af and the oxide film 230bf are not polycrystallized. The temperature of the heat treatment is preferably 100° C. or higher, 250° C. or higher, or 350° C. or higher, and 650° C. or lower, 600° C. or lower, or 550° C. or lower.

[0358] The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0359] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the oxide film 230af and the oxide film 230bf as much as possible.

[0360] In this embodiment, the heat treatment is performed at 450° C. for 1 hour with a nitrogen gas / oxygen gas flow ratio of 4:1. This heat treatment using oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230af and the oxide film 230bf. Reducing the impurities in the film in this manner improves the crystallinity of the oxide film 230bf, resulting in a denser, more compact structure. This increases the crystalline regions in the oxide film 230af and the oxide film 230bf, reducing the in-plane variation of the crystalline regions in the oxide film 230af and the oxide film 230bf. This reduces the in-plane variation of the electrical characteristics of the transistor.

[0361] Furthermore, by performing the heat treatment, hydrogen in the oxide film 230af and the oxide film 230bf is released to the outside. At this time, since the insulating film 226f is provided, the hydrogen in the oxide film 230af and the oxide film 230bf does not diffuse to the insulating film 224f side, and therefore can be efficiently released to the outside. Furthermore, by performing the heat treatment, hydrogen in the insulator 216 and the insulating film 224f moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the insulator 216 and the insulating film 224f diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216 and the insulating film 224f decrease.

[0362] The insulating film 224f (later insulator 224) has a region that functions as a second gate insulator of the transistor 200. The oxide film 230af and the oxide film 230bf (later oxide 230a and oxide 230b) have a region that functions as a channel formation region of the transistor 200. The transistor 200 formed using the insulating film 224f, the oxide film 230af, and the oxide film 230bf in which the hydrogen concentrations are reduced has good reliability and is therefore preferable.

[0363] Next, a conductive film 242_1f is formed on the oxide film 230bf, and a conductive film 242_2f is formed on the conductive film 242_1f (see FIGS. 8A to 8D ). Conductors corresponding to the conductors 242a1 and 242b1 may be used as the conductive film 242_1f, and conductors corresponding to the conductors 242a2 and 242b2 may be used as the conductive film 242_2f. By forming the conductive film 242_1f on and in contact with the oxide film 230bf without performing an etching process or the like after the oxide film 230bf is formed, the top surface of the oxide film 230bf can be protected by the conductive film 242_1f. This can reduce diffusion of impurities into the oxide 230 that constitutes the transistor, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0364] The conductive films 242_1f and 242_2f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0365] In this embodiment, tantalum nitride is deposited as the conductive film 242_1f and tungsten is deposited as the conductive film 242_2f by a sputtering method. Note that heat treatment may be performed before the formation of the conductive film 242_1f. The heat treatment may be performed under reduced pressure, and the conductive film 242_1f may be deposited successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0366] Next, an insulating film 271f is formed over the conductive film 242_2f (see FIGS. 8A to 8D ). The insulating film 271f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271f is preferably an insulating film that has a function of suppressing oxygen permeation. For example, the insulating film 271f may be formed by a sputtering method to form a stacked film of a silicon nitride film and a silicon oxide film over the silicon nitride film.

[0367] Here, when the insulating film 271f is a stacked film, it is preferable to deposit the films successively without exposing them to the air. By depositing the films without exposing them to the air, the vicinity of the interface of the stacked film of the insulating film 271f can be kept clean. It is more preferable to deposit the conductive film 242_1f to the insulating film 271f successively without exposing them to the air.

[0368] Note that heat treatment may be performed before the formation of the insulating film 271f. The heat treatment may be performed under reduced pressure, and the insulating film 271f may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surfaces of the conductive films 242_1f and 242_2f can be removed, and the moisture and hydrogen concentrations in the conductive films 242_1f and 242_2f can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0369] Next, using lithography, the insulating film 224f, the insulating film 226f, the oxide film 230af, the oxide film 230bf, the conductive film 242_1f, the conductive film 242_2f, and the insulating film 271f are processed into island shapes to form the insulator 224, the insulator 226, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 (see Figures 9A to 9D).

[0370] For the above processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. The insulating film 224f, the insulating film 226f, the oxide film 230af, the oxide film 230bf, the conductive film 242_1f, the conductive film 242_2f, and the insulating film 271f may be processed under different conditions.

[0371] Here, the insulating film 224f, the insulating film 226f, the oxide film 230af, the oxide film 230bf, the conductive film 242_1f, the conductive film 242_2f, and the insulating film 271f are preferably collectively processed into an island shape. In this case, the side ends of the conductor 242_1 and the conductor 242_2 preferably substantially coincide with the side ends of the oxide 230a and the oxide 230b. Furthermore, the side ends of the insulator 224 and the insulator 226 preferably substantially coincide with the side end of the oxide 230. Furthermore, the side end of the insulator 271 preferably substantially coincides with the side end of the conductor 242_2. Such a structure can reduce the number of steps required for manufacturing a semiconductor device according to one embodiment of the present invention. Therefore, a highly productive method for manufacturing a semiconductor device can be provided.

[0372] The insulator 224, the insulator 226, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 are formed so as to at least partially overlap with the conductor 205. The insulator 222 is exposed in regions that do not overlap with the insulator 224, the insulator 226, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, or the insulator 271.

[0373] 9B , the side surfaces of the insulator 224, the insulator 226, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may be tapered. The taper angle of the side surfaces of the insulator 224, the insulator 226, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may be, for example, greater than or equal to 60° and less than 90°. By tapering the side surfaces in this manner, the coverage of the insulator 275 and the like can be improved in subsequent processes, and defects such as voids can be reduced.

[0374] Furthermore, without being limited to the above, the side surfaces of the insulator 224, the insulator 226, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may be approximately perpendicular to the top surface of the insulator 222. With such a structure, a reduction in area and a high density can be achieved when providing multiple transistors.

[0375] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left behind using a developer to form a resist mask. Next, an etching process is performed through the resist mask, allowing a conductor, semiconductor, or insulator to be processed into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask may not be required.

[0376] Note that the resist mask that is no longer needed after processing can be removed by performing a dry etching process such as ashing using oxygen plasma treatment, a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0377] Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as the hard mask material is formed on the insulating film 271f, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of the desired shape. Etching of the insulating film 271f and the like may be performed after removing the resist mask, or may be performed while leaving the resist mask in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the oxide film 230bf and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0378] Alternatively, a configuration may be adopted in which an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film are formed between the workpiece and the resist mask. Using the SOC film and the SOG film as a mask can improve adhesion with the resist mask and improve the durability of the mask pattern. The configuration in which an SOC film, an SOG film, and a resist mask are sequentially formed on the workpiece and then lithography is performed is described in the steps shown in FIGS. 12A to 12D and 15A to 15D, which will be described later, and therefore the descriptions in those sections may be referenced.

[0379] As the etching gas for the dry etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, the etching gas may contain C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ gas, or BBr ３ Gases such as fluorine-containing gases can be used alone or in combination of two or more gases. Oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above-mentioned etching gas as appropriate. Depending on the object to be dry-etched, gases containing hydrocarbon gas or hydrogen gas but not containing halogen gas can be used as the etching gas. Examples of hydrocarbons used in the etching gas include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ The etching conditions can be appropriately set depending on the target to be etched.

[0380] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used. The etching apparatus can be appropriately configured depending on the object to be etched.

[0381] Furthermore, in the etching process, the insulator 271 can function as an etching stopper that protects the conductor 242_2. For example, if a metal hard mask is formed on the insulator 271 in the etching process, it may be difficult to obtain an etching selectivity with respect to the conductor 242_2 when removing the hard mask. However, by forming the insulator 271 on the conductor 242_2, the insulator 271 can function as an etching stopper that protects the conductor 242_2 in the etching process for removing the hard mask. This prevents a curved surface from being formed between the side surface and the top surface of the conductor 242_2, so that the conductors 242a2 and 242b2, which will be formed later, have angular ends where the side surface and the top surface intersect. The angular ends where the side surface and the top surface of the conductor 242_2 intersect increase the cross-sectional area of ​​the conductor 242_2 compared to when the ends have a curved surface. Furthermore, excessive oxidation of the conductor 242_2 can be prevented by using a nitride insulator that does not easily oxidize metal for the insulator 271. This reduces the resistance of the conductor 242a2 and the conductor 242b2, thereby increasing the on-state current of the transistor.

[0382] Furthermore, by processing the insulator 224 into an island shape, insulator 275 can be provided in contact with the side surface of insulator 224 and the top surface of insulator 222 in a process described later. In other words, insulator 224 can be separated from insulator 280, which will be formed in a later process, by insulator 275. This structure can prevent impurities such as excessive amounts of oxygen and hydrogen from being mixed into insulator 224 from insulator 280.

[0383] Next, an insulator 275 is formed to cover the insulator 224, the insulator 226, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271, and then an insulator 280 is formed over the insulator 275 (see FIGS. 10A to 10D). The insulators described above may be used for the insulators 275 and 280.

[0384] Here, it is preferable that the insulator 275 contacts the upper surface of the insulator 222 .

[0385] As the insulator 280, it is preferable to form an insulator with a flat upper surface by forming an insulating film to be the insulator 280 and performing CMP treatment on the insulating film. Note that it is also possible to form a silicon nitride film on the insulator 280 by, for example, a sputtering method and perform CMP treatment on the silicon nitride until it reaches the insulator 280.

[0386] The insulators 275 and 280 can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0387] It is preferable to use an insulator having a function of suppressing oxygen permeation for the insulator 275. For example, it is preferable to form a silicon nitride film by a PEALD method as the insulator 275. Alternatively, it is preferable to form an aluminum oxide film by a sputtering method and then form a silicon nitride film thereon by a PEALD method as the insulator 275. By using the above structure for the insulator 275, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0388] In this manner, the oxide 230a, the oxide 230b, the conductor 242_1, and the conductor 242_2 can be covered with the insulator 275, which has a function of suppressing oxygen diffusion. This can suppress direct diffusion of oxygen from the insulator 280 or the like to the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, and the conductor 242_2 in a later step.

[0389] Furthermore, it is preferable to form a silicon oxide film as the insulator 280 by a sputtering method. The insulating film to be the insulator 280 can be formed by sputtering in an oxygen-containing atmosphere, thereby forming the insulator 280 containing excess oxygen. Furthermore, the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Heat treatment may be performed before the deposition of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275, etc., can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the insulator 224 can be further reduced. The heat treatment conditions described above can be used for the heat treatment.

[0390] Next, the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 are processed using lithography to form openings that reach the conductor 242_1 and the insulator 222 (see FIGS. 11A to 11D ). Here, the conductor 242_2 is divided to form the conductor 242a2 and the conductor 242b2, and the insulator 271 is divided to form the insulator 271a and the insulator 271b. The opening that reaches the conductor 242_1 is formed in a region where the oxide 230b and the conductor 205 overlap. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening is L1, which corresponds to the distance L1 between the conductor 242a2 and the conductor 242b2. That is, the width L1 of the opening is greater than the distance L2 between the conductor 242a1 and the conductor 242b1.

[0391] The lithography method can be any of the above-mentioned methods, as appropriate. In order to finely process the openings in the insulator 280, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.

[0392] Below, specific examples of processing the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 will be described with reference to FIGS. 12A to 12D.

[0393] First, a coating film 277f is formed on the insulator 280, and then a coating film 278f is formed ( FIG. 12A ). The coating films 277f and 278f may have the function of improving adhesion with a resist mask. The coating films 277f and 278f may be formed using, for example, a spin coating method. A non-photosensitive organic resin may be used as the coating films 277f and 278f. In this embodiment, an SOC film is formed as the coating film 277f, and an SOG film is formed as the coating film 278f. Here, the coating films 277f and 278f contain an organic solvent such as alcohol during application. However, the organic matter contained therein may be reduced or removed during subsequent processes or when the semiconductor device is completed. Note that the coating film may be provided as needed. The coating film may be configured as a single layer, or if a resist mask, as described below, is sufficient, a coating film may not be provided.

[0394] Next, a resist mask 279 is formed on the coating film 278f using lithography ( FIG. 12A ). The resist mask 279 has an opening with a width L1 when viewed cross-sectionally in the channel length direction. The resist mask 279 may be made of a photosensitive organic resin also known as photoresist. For example, a positive photoresist or a negative photoresist may be used. The photoresist that becomes the resist mask 279 can be formed to a uniform thickness by, for example, forming the resist mask 279 using a spin coating method or the like.

[0395] 12B to 12D, the structure shown in FIG. 12A is etched using a dry etching method. Because dry etching allows anisotropic etching, it is suitable for forming an opening with a width L1 and a high aspect ratio. The conditions for the dry etching method and the dry etching apparatus can be found above. The etching of the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 may be performed under different conditions.

[0396] First, a coating film 278f is processed using a resist mask 279 to form a coating film 278, and then a coating film 277f is processed to form a coating film 277 (FIG. 12B). Here, openings with a width L1 are formed in the coating films 278 and 277. For example, when an SOG film is used for the coating film 278f, CF ４ For example, when an SOC film is used as the coating film 277f, H ２ and N ２ can be used as the etching gas.

[0397] The resist mask 279 may disappear before the coating film 277 is formed. If the resist mask 279 remains after the coating film 277 is formed, the resist mask 279 may be removed.

[0398] Next, using the coating film 277 as a mask, the insulator 280 is processed to form an opening with a width L1, and the insulator 275 is further processed to form an opening with a width L1 (FIG. 12C). For example, when silicon oxide is used for the insulator 280, ４ F ８ and C ４ F ６ and O ２ For example, when silicon nitride is used for the insulator 275, CH ２ F ２ and O ２ and Ar can be used as etching gases.

[0399] Next, using the coating film 277 as a mask, the insulator 271 is processed and divided to form insulators 271a and 271b (FIG. 12C). Here, the region between the insulators 271a and 271b overlaps with an opening of width L1, and the distance between the insulators 271a and 271b is L1. For example, when a stacked film of silicon nitride and silicon oxide is used for the insulator 271, the insulator 271 is formed by etching with CHF ３ and O ２ The etching process can be carried out using the above as an etching gas.

[0400] Next, the coating film 277 is used as a mask to process and divide the conductor 242_2, forming the conductor 242a2 and the conductor 242b2 (FIG. 12D). Here, the region between the conductor 242a2 and the conductor 242b2 overlaps with an opening of width L1, and the distance between the conductor 242a2 and the conductor 242b2 is L1. For example, when tungsten is used for the conductor 242_2 and tantalum nitride is used for the conductor 242_1, CF ４ and Cl ２ and O ２ The etching process can be carried out using the above as an etching gas.

[0401] Here, in order to form conductors 242a1 and 242b1, which are spaced apart by L2, below conductors 242a2 and 242b2 in a later step, the etching process in this step needs to be stopped at the top surface of conductor 242_1. Therefore, in this step, the etching process is performed using an ICP etching device under conditions where the etching rate of conductor 242_2 is greater than the etching rate of conductor 242_1 (hereinafter referred to as the etching selectivity of conductor 242_2).

[0402] By lowering the bias power applied to the lower electrode of the ICP etching apparatus, the ion incident energy can be reduced, and the etching rate of the conductor 242_1 can be reduced. For example, the bias power applied to the lower electrode of the ICP etching apparatus can be set to less than 50 W, preferably about 25 W or less.

[0403] Also, CF ４ and Cl ２ and O ２ As an etching gas, the tungsten of the conductor 242_2 is etched with WF ６, or WOCl, resulting in a highly volatile reaction product, which increases the etching rate. On the other hand, tantalum nitride on the surface of the conductor 242_1 becomes a very low-volatility reaction product, such as tantalum oxide or tantalum oxynitride, which suppresses etching. Therefore, by increasing the flow rate ratio of oxygen gas in the etching gas, the etching selectivity of the conductor 242_2 can be increased. For example, the flow rate ratio of oxygen gas in the etching gas may be set to be greater than 35%, approximately 48% or greater.

[0404] By performing the etching process on the conductor 242_2 under the above conditions, the etching selectivity of the conductor 242_2 can be increased. Therefore, the conductor 242_1 can be divided into the conductor 242a2 and the conductor 242b2 without being excessively etched. This allows processing as designed even in a semiconductor device having a fine structure.

[0405] The coating film 277 may be removed by performing a dry etching process such as ashing using oxygen plasma, a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0406] Furthermore, the processing of the insulator 271 and the conductor 242_2 and the removal of the coating film 277 can be performed successively without exposure to the outside air. For example, the processing can be performed using a multi-chamber etching apparatus without exposure to the outside air.

[0407] In this manner, the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 can be processed to form an opening with a width L1.

[0408] Next, an insulating film 255A is formed to cover the insulator 280, the conductor 242_1, and the insulator 222 (see FIGS. 13A to 13D ). The insulating film 255A is an insulating film that will become the insulator 255 in a later process, and any of the above-described insulators can be used. The insulating film 255A can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0409] The insulating film 255A preferably has good coverage because it is formed along the openings formed in the conductor 242a2, the conductor 242b2, the insulator 271, the insulator 275, and the insulator 280. Therefore, the insulating film 255A is preferably formed by an ALD method or the like, which has good coverage. For example, it is preferable to form the insulating film 255A using silicon nitride by a PEALD method.

[0410] Next, the conductor 242_1 and the insulating film 255A are processed using lithography within the opening formed in the insulator 280 to form an opening reaching the oxide 230b (see FIGS. 14A to 14D ). Here, an insulator 255 having an opening is formed from the insulating film 255A, and the conductor 242_1 is divided to form the conductor 242a1 and the conductor 242b1. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening is L2, which corresponds to the distance L2 between the conductor 242a1 and the conductor 242b1. Because the opening is formed inside the opening formed in the insulator 280, the distance L2 between the conductor 242a1 and the conductor 242b1 is shorter than the distance L1 between the conductor 242a2 and the conductor 242b2.

[0411] The lithography method can be any of the above-described methods, as appropriate. In order to finely process the openings in the insulator 255, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

[0412] 14A and 14C , the insulator 255 has an opening formed therein so as to expose the island-shaped oxide 230, but the present invention is not limited to this. In this process, it is sufficient that the conductors 242a1 and 242b1 are separated by a distance L2. Therefore, for example, an opening substantially identical to the opening formed in the insulator 280 may be formed in the insulator 255, except for the portions contacting the upper surfaces of the conductors 242a1 and 242b1. In this case, however, the insulator 255 may be formed in a sidewall shape in contact with the sidewall of the opening formed in the insulator 280.

[0413] Below, specific examples of processing the conductor 242_1 and the insulating film 255A will be described with reference to FIGS. 15A to 15D.

[0414] First, a coating film 287f is formed on the insulating film 255A, and then a coating film 288f is formed ( FIG. 15A ). Here, the coating film 287f is provided so as to fill the recesses in the insulating film 255A. Note that the coating film 287f can have the same configuration as the coating film 277f, and the coating film 288f can have the same configuration as the coating film 278f, so the above descriptions can be referenced.

[0415] Next, a resist mask 289 is formed on the coating film 288f by lithography (FIG. 15A). An opening with a width L2 is formed in the resist mask 289 when viewed cross-sectionally in the channel length direction. The resist mask 289 is formed so that the opening with a width L2 is located inside the opening of the insulator 280 when viewed from above and overlaps with the oxide 230b. Note that the resist mask 289 can have the same structure as the resist mask 279, and therefore the above description can be referred to.

[0416] 15B to 15D, the structure shown in FIG. 15A is etched using a dry etching method. Because dry etching allows anisotropic etching, it is suitable for forming an opening with a width L2 and a high aspect ratio. The conditions for the dry etching method and the dry etching apparatus can be found above. The etching of the conductor 242_2 and the etching of the insulating film 255A may be performed under different conditions.

[0417] First, using a resist mask 289, the coating film 288f is processed to form the coating film 288, and then the coating film 287f is processed to form the coating film 287 ( FIG. 15B ). Here, openings with a width L2 are formed in the coating films 288 and 287, exposing the insulating film 255A. Note that the processing of the coating films 288f and 287f is similar to the processing of the coating films 278f and 277f, and therefore the above description can be referenced.

[0418] Next, using the coating film 287 as a mask, the insulating film 255A is processed to form an opening, and the insulator 255 is formed (FIG. 15C). Here, the width of the opening in the insulator 255 is L2. For example, when silicon nitride is used for the insulating film 255A, the insulating film 255A is formed by etching with CHF ３ and O ２ The etching process can be carried out using the above as an etching gas.

[0419] Next, the conductor 242_1 is processed and divided using the coating film 287 and the insulator 255 as a mask to form the conductor 242a1 and the conductor 242b1 (FIG. 15D). For example, when tantalum nitride is used for the conductor 242_1, Cl ２ The etching process can be performed using Ar as an etching gas.

[0420] Here, the region between the conductor 242a1 and the conductor 242b1 overlaps with the opening of width L2, and the distance between the conductor 242a1 and the conductor 242b1 is L2. By processing the insulating film 255A and the conductor 242_1 using the same mask in this manner, the side edges of the insulator 255A are formed to approximately coincide with the side edges of the conductor 242a1 and the conductor 242b1 in a cross-sectional view of the transistor 200.

[0421] The coating film 287 may be removed by performing a dry etching process such as ashing using oxygen plasma, a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0422] Furthermore, the processing of the insulating film 255A and the conductor 242_1 and the removal of the coating film 287 can be performed successively without exposure to the outside air. For example, the processing can be performed using a multi-chamber etching apparatus without exposure to the outside air.

[0423] In this manner, the conductors 242a1 and 242b1, which are spaced apart by a distance L2, can be formed below the conductors 242a2 and 242b2, which are spaced apart by a distance L1. This configuration shortens the distance between the source and drain of the transistor 200, thereby improving the frequency characteristics of the transistor 200 and the operating speed of the semiconductor device.

[0424] The etching process may result in impurities adhering to the side surfaces of the oxide 230a, the top and side surfaces of the oxide 230b, and the side surfaces of the conductors 242a and 242b, or diffusing into these surfaces. A process for removing such impurities may be performed. Furthermore, the dry etching may result in damaged regions being formed on the surface of the oxide 230b. Such damaged regions may be removed. Examples of such impurities include those derived from components contained in the insulators 280, 275, 271a and 271b, and the conductors 242a and 242b, components contained in the components of the device used to form the openings, and components contained in the gas or liquid used in etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0425] In particular, impurities such as aluminum and silicon may reduce the crystallinity of the oxide 230b. Therefore, it is preferable to remove impurities such as aluminum and silicon from the surface of the oxide 230b and its vicinity. It is also preferable to reduce the concentration of these impurities. For example, the concentration of aluminum atoms on the surface of the oxide 230b and its vicinity is preferably 5.0 atomic % or less, more preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0426] In addition, in the region where the crystallinity of the oxide 230b is low due to impurities such as aluminum and silicon, the density of the crystal structure is reduced. ＯA large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the region of low crystallinity in the oxide 230b be reduced or removed.

[0427] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the oxide 230b has the CAAC structure up to the bottom end of the drain. Here, in the transistor, it is preferable that the conductor 242a or the conductor 242b functions as the drain. In other words, it is preferable that the oxide 230b near the bottom end of the conductor 242a or the conductor 242b has the CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the low-crystalline region of the oxide 230b is removed, and by having the CAAC structure, fluctuations in the electrical characteristics of the transistor can be further suppressed. Furthermore, the reliability of the transistor can be improved.

[0428] In order to remove impurities and the like that have adhered to the surface of the oxide 230b during the etching process, a cleaning process is performed. Cleaning methods include wet cleaning using a cleaning solution (also called wet etching), plasma processing using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0429] Wet cleaning may be performed using an aqueous solution of one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid diluted with carbonated water or pure water, pure water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0430] In this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration, temperature, etc. of the aqueous solution are adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0431] In addition, ultrasonic cleaning preferably uses a frequency of 200 kHz or more, and more preferably uses a frequency of 900 kHz or more, since use of such a frequency can reduce damage to the oxide 230b and the like.

[0432] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0433] In this embodiment, the cleaning process is performed by wet cleaning using diluted ammonia water. By performing this cleaning process, impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.

[0434] It is preferable to perform heat treatment after the etching or cleaning. The temperature of the heat treatment is preferably 100°C or higher, 250°C or higher, or 350°C or higher, and 650°C or lower, 600°C or lower, 550°C or lower, or 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. The heat treatment is preferably performed in an atmosphere containing oxygen, for example, at a temperature of 350°C for 1 hour with a flow ratio of nitrogen gas to oxygen gas of 4:1. This allows oxygen to be supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen vacancies. Furthermore, performing such heat treatment can improve the crystallinity of the oxide 230b. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide 230a and the oxide 230b, converting the hydrogen into H ２ As a result, hydrogen remaining in the oxide 230a and the oxide 230b is recombined with the oxygen vacancies to form V. Ｏ The formation of H can be suppressed. This can improve the electrical characteristics of the transistor provided with the oxide 230 and improve reliability. Furthermore, it can suppress variations in the electrical characteristics of multiple transistors formed on the same substrate. Note that the heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0435] When heat treatment is performed with the conductor 242a and the conductor 242b in contact with the oxide 230b, the sheet resistance may decrease in the region of the oxide 230b that overlaps with the conductor 242a and the region of the oxide 230b that overlaps with the conductor 242b. The carrier concentration may also increase. Therefore, the resistance of the region of the oxide 230b that overlaps with the conductor 242a and the region of the oxide 230b that overlaps with the conductor 242b can be reduced in a self-aligned manner.

[0436] As described above, the insulator 255, which has an inorganic insulator that is resistant to oxidation, is provided in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. This prevents the conductors 242a2 and 242b2 from being excessively oxidized by the heat treatment, even if the conductors 242a2 and 242b2 are made of a tungsten film that is relatively easily oxidized.

[0437] Next, an insulating film 250A that will become the insulator 250 is formed so as to have a region located within the opening formed in the insulator 280 (see FIGS. 16A to 16D). Here, the insulating film 250A is formed so as to be in contact with the insulator 255, but in the region where the opening is formed in the insulator 255, the insulating film 250A is in contact with the insulators 222, 224, 226, oxide 230a, and oxide 230b.

[0438] The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, the insulating film 250A is preferably formed using an ALD method. Like the insulator 250 described above, the insulating film 250A is preferably formed to a thin film thickness, and it is necessary to minimize film thickness variation. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer) are alternately introduced. The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Furthermore, the insulating film 250A must be formed with good coverage on the bottom and side surfaces of the opening. By using the ALD method, atomic layers can be deposited one by one on the bottom and side surfaces of the opening, allowing the insulating film 250A to be formed with good coverage on the opening.

[0439] When the insulating film 250A is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ ) as an oxidizing agent, hydrogen diffusing into the oxide 230b can be reduced.

[0440] The insulator 250 can have a stacked structure, as shown in FIG. 3A and the like. In the structure shown in FIG. 3A, an insulating film to be the insulator 250a can be formed by thermal ALD using aluminum oxide, an insulating film to be the insulator 250b can be formed by PEALD using silicon oxide, and an insulating film to be the insulator 250c can be formed by PEALD using silicon nitride. In the structure shown in FIG. 3B, an insulating film to be the insulator 250a can be formed by thermal ALD using aluminum oxide, and an insulating film to be the insulator 250c can be formed by PEALD using silicon nitride. In addition, in the structure shown in Figure 3C, aluminum oxide can be deposited by thermal ALD as the insulating film that becomes insulator 250a, silicon oxide can be deposited by PEALD as the insulating film that becomes insulator 250b, hafnium oxide can be deposited by thermal ALD as the insulating film that becomes insulator 250d, and silicon nitride can be deposited by PEALD as the insulating film that becomes insulator 250c.

[0441] Next, microwave treatment is preferably performed in an oxygen-containing atmosphere. Here, microwave treatment refers to treatment using, for example, a device with a power source that generates high-density plasma using microwaves. Furthermore, in this specification and elsewhere, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. However, when the insulator 250 has a stacked structure, the microwave treatment does not necessarily need to be performed after the formation of all of the insulating films 250A. For example, in the structure shown in FIG. 3A , microwave treatment may be performed after the formation of the insulating film that will become insulator 250a and the insulating film that will become insulator 250b, and then the insulating film that will become insulator 250c may be formed. Furthermore, in the structure shown in FIG. 3B , microwave treatment may be performed after the formation of the insulating film that will become insulator 250a, and then the insulating film that will become insulator 250c may be formed. 3C , for example, a microwave treatment may be performed after forming an insulating film to be insulator 250 a and an insulating film to be insulator 250 b, and then a microwave treatment may be performed after forming an insulating film to be insulator 250 d, and then an insulating film to be insulator 250 c may be formed. In this way, the microwave treatment in an oxygen-containing atmosphere may be performed multiple times (at least two times or more).

[0442] In the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves to the microwave treatment device is preferably 1000 W or more and 10,000 W or less, and preferably 2000 W or more and 5,000 W or less. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the oxide 230b.

[0443] The microwave treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or higher and 1000 Pa or lower, and more preferably being 300 Pa or higher and 700 Pa or lower. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C or higher and 750°C or lower, and more preferably 300°C or higher and 500°C or lower.

[0444] Furthermore, for example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%. ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ +Ar)) is set to 10% or more and 30% or less. In this way, by performing microwave treatment in an atmosphere containing oxygen, the carrier concentration in the oxide 230b can be reduced. Furthermore, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, an excessive reduction in the carrier concentration in the oxide 230b can be prevented.

[0445] By performing microwave processing in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region of the oxide 230b between the conductors 242a and 242b. ＯThe H can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. Here, when the structure shown in FIGS. 3A to 3C is used, it is preferable to use an insulating film (such as aluminum oxide) that has the function of capturing and fixing hydrogen as the insulating film that becomes the insulator 250a. With such a structure, hydrogen generated by microwave treatment can be captured or fixed to the insulator 250a. In this way, V included in the channel formation region can be removed. Ｏ As a result, oxygen vacancies in the channel formation region and V Ｏ By supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be lowered.

[0446] The oxygen implanted into the channel formation region can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also called O radicals). The oxygen implanted into the channel formation region may take one or more of the above forms, and oxygen radicals are particularly preferred. Furthermore, the film quality of the insulator 250 can be improved, thereby improving the reliability of the transistor.

[0447] On the other hand, the oxide 230b has a region that overlaps with either the conductors 242a or 242b. This region can function as a source region or a drain region. Here, the conductors 242a and 242b preferably function as a shielding film against the effects of microwaves, high-frequency waves such as RF, oxygen plasma, and the like when performing microwave treatment in an oxygen-containing atmosphere. Therefore, the conductors 242a and 242b preferably have the function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0448] Conductors 242a and 242b shield the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc., so that these effects do not reach the regions of oxide 230b that overlap with either of conductors 242a and 242b. This allows microwave processing to prevent V Ｏ Since the amount of H is reduced and an excessive amount of oxygen is not supplied, a decrease in the carrier concentration can be prevented.

[0449] Furthermore, insulators 255 and 250, which have a barrier property against oxygen, are provided in contact with the side surfaces of the conductors 242a and 242b, thereby making it possible to prevent an oxide film from being formed on the side surfaces of the conductors 242a and 242b by microwave treatment.

[0450] In this manner, oxygen vacancies and V Ｏ By removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions that function as source or drain regions can be suppressed, and the conductivity (low resistance region state) before the microwave treatment can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor, and suppresses variations in the electrical characteristics of the transistor within the substrate surface.

[0451] In microwave treatment, thermal energy may be transferred directly to the oxide 230b due to electromagnetic interaction between the microwaves and molecules in the oxide 230b. This thermal energy may heat the oxide 230b. This type of heat treatment is sometimes called microwave annealing. Performing microwave treatment in an oxygen-containing atmosphere may produce an effect equivalent to oxygen annealing. Furthermore, if the oxide 230b contains hydrogen, it is thought that this thermal energy is transferred to the hydrogen in the oxide 230b, thereby activating and releasing the hydrogen from the oxide 230b.

[0452] It is to be noted that the microwave treatment may be performed before the insulating film 250A is formed, rather than after the insulating film 250A is formed.

[0453] Furthermore, after the microwave treatment following the formation of the insulating film 250A, a heat treatment may be performed while maintaining the reduced pressure. By performing such a treatment, hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be efficiently removed. Some of the hydrogen may be gettered to the conductors 242a and 242b. Alternatively, a heat treatment step may be performed multiple times while maintaining the reduced pressure after the microwave treatment. Repeated heat treatments can more efficiently remove hydrogen from the insulating film, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. The microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be performed.

[0454] Furthermore, by modifying the film quality of the insulating film 250A by microwave treatment, the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. via the insulator 250 can be suppressed by post-processing such as film formation of a conductive film that becomes the conductor 260, or by post-treatment such as heat treatment. In this way, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0455] Next, a conductive film 260A to be the conductor 260a and a conductive film 260B to be the conductor 260b are formed in this order (see FIGS. 17A to 17D ). The conductive films 260A and 260B can be formed by, for example, sputtering, CVD, MBE, PLD, plating, or ALD. In this embodiment, titanium nitride is formed as the conductive film 260A by ALD, and tungsten is formed as the conductive film 260B by CVD.

[0456] Next, the insulator 255, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP treatment until the insulator 280 is exposed. That is, the portions of the insulator 255, the insulating film 250A, the conductive film 260A, and the conductive film 260B exposed from the openings are removed. As a result, the insulator 255, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) are formed in the openings overlapping the conductor 205 (see FIGS. 18A to 18D).

[0457] As a result, the insulator 255 is provided in contact with the sidewall and part of the bottom surface of the opening formed in the insulator 280. The insulator 250 is also provided in the opening in contact with the insulator 255 and the oxide 230, insulator 226, insulator 224, and insulator 222 exposed from the insulator 255. The conductor 260 is also arranged to fill the opening with the insulator 250 interposed therebetween. In this manner, the transistor 200 is formed.

[0458] Next, the insulator 282 is formed over the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0459] Furthermore, by depositing the insulator 282 in an oxygen-containing atmosphere by using a sputtering method, oxygen can be added to the insulator 280 during deposition. This allows the insulator 280 to contain excess oxygen. In this case, it is preferable to deposit the insulator 282 while heating the substrate.

[0460] In this embodiment, aluminum oxide is deposited as the insulator 282 by sputtering using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen implanted into the layer below the insulator 282 can be controlled by the magnitude of the RF power applied to the substrate during sputtering. For example, the smaller the RF power, the less oxygen is implanted into the layer below the insulator 282, and the amount of oxygen is likely to saturate even if the insulator 282 is thin. Furthermore, the larger the RF power, the more oxygen is implanted into the layer below the insulator 282. Reducing the RF power can suppress the amount of oxygen implanted into the insulator 282. Alternatively, the insulator 282 may be deposited to have a two-layer stacked structure. In this case, for example, the lower layer of the insulator 282 is deposited without applying RF power to the substrate, and the upper layer of the insulator 282 is deposited by applying RF power to the substrate.

[0461] The RF frequency is preferably 10 MHz or higher, typically 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0462] Alternatively, heat treatment may be performed before the formation of the insulator 282. The heat treatment may be performed under reduced pressure, and the insulator 282 may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be removed and the moisture and hydrogen concentrations in the insulator 280 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0463] Next, the insulator 283 is formed over the insulator 282. The insulator 283 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, silicon nitride is formed as the insulator 283 by a sputtering method.

[0464] Here, it is preferable to successively deposit the insulators 282 and 283 without exposing them to the air environment. Depositing the insulators 282 and 283 without exposing them to the air environment can prevent impurities or moisture from the air environment from adhering to the insulators 282 and 283, and can keep the vicinity of the interface between the insulators 282 and 283 clean.

[0465] In this manner, the semiconductor device shown in FIG. 1 can be manufactured.

[0466] The semiconductor device according to this embodiment has a two-layer structure of conductors on an oxide semiconductor, in which a conductor that is resistant to oxidation is used in the lower layer and a conductor with high conductivity is used in the upper layer. This structure provides conductors that function as electrodes or wirings in contact with the top surface of the oxide semiconductor. The conductors function as source and drain electrodes of an OS transistor. The semiconductor device according to this embodiment has a shorter distance between the conductors in the lower layers of the source and drain electrodes than the distance between the conductors in the upper layers of the source and drain electrodes, thereby achieving miniaturization. This allows the semiconductor device to have improved frequency characteristics and operating speed. Furthermore, the semiconductor device according to this embodiment has an insulator that functions as a protective film in contact with the side surfaces of the conductors in the upper layers of the source and drain electrodes. This structure prevents excessive oxidation of the upper layers of the source and drain electrodes.

[0467] The semiconductor device according to this embodiment includes an OS transistor. The OS transistor has a small off-state current, which enables a semiconductor device or storage device with low power consumption. Furthermore, the OS transistor has high frequency characteristics, which enables a semiconductor device or storage device with high operation speed. Furthermore, by using an OS transistor, a semiconductor device with favorable electrical characteristics, a semiconductor device with little variation in the electrical characteristics of transistors, a semiconductor device with large on-state current, and a highly reliable semiconductor device or storage device can be realized.

[0468] The semiconductor device according to this embodiment has a structure in which the bottom surface of the oxide semiconductor is in contact with an insulator having a barrier property against hydrogen. Furthermore, an insulator having a barrier property against hydrogen is provided between the gate insulating layer and the interlayer insulating layer, both of which are in contact with the oxide semiconductor, and between the source electrode or the drain electrode and the interlayer insulating layer, both of which are in contact with the oxide semiconductor. This structure prevents hydrogen from entering the oxide semiconductor as much as possible, thereby realizing a highly reliable transistor.

[0469] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0470] Embodiment 2 In this embodiment, a memory device including a transistor of one embodiment of the present invention will be described with reference to FIGS. 19 to 25C.

[0471] This embodiment will describe a configuration example of a memory device using a memory cell including the transistor described in the above embodiment, in which a layer including a functional circuit having a function of amplifying and outputting a data potential held in the memory cell is provided between layers including stacked memory cells.

[0472] [Configuration Example of Storage Device] FIG. 19 illustrates a block diagram of a storage device of one embodiment of the present invention.

[0473] 19 includes a drive circuit 21 and a memory array 20. The memory array 20 includes a plurality of memory cells 10 and a functional layer 50 including a plurality of functional circuits 51.

[0474] 19 shows an example in which the memory array 20 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more). Also, Fig. 19 shows an example in which a functional circuit 51 is provided for each wiring BL that functions as a bit line, and an example in which the functional layer 50 has a plurality of functional circuits 51 provided corresponding to the n wirings BL.

[0475] In FIG. 19 , the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1], and the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n]. In addition, in the present embodiment and the like, an arbitrary row may be referred to as row i. In addition, an arbitrary column may be referred to as column j. Therefore, i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to n. In addition, in the present embodiment and the like, the memory cell 10 in the ith row and jth column is indicated as memory cell 10[i,j]. In addition, in the present embodiment and the like, when "i+α" (α is a positive or negative integer) is indicated, "i+α" is not less than 1 or more than m. Similarly, when "j+α" is indicated, "j+α" is not less than 1 or more than n.

[0476] The memory array 20 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n].

[0477] The memory cells 10 in the i-th row are electrically connected to the wiring WL in the i-th row (wiring WL[i]) and the wiring PL in the i-th row (wiring PL[i]). The memory cells 10 in the j-th column are electrically connected to the wiring BL in the j-th column (wiring BL[j]).

[0478] The memory array 20 may be a DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM having 1T (transistor) 1C (capacitor) type memory cells, with the access transistor being an OS transistor. The current flowing between the source and drain of an OS transistor in the off state, i.e., leakage current, is extremely small. By turning off (non-conducting) the access transistor, DOSRAM can retain charge corresponding to data stored in a capacitance element (capacitor) for a long period of time. Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAMs composed of transistors having silicon in their channel formation regions (Si transistors). As a result, power consumption can be reduced. Furthermore, the high frequency characteristics of OS transistors enable high-speed read and write operations. This allows for a memory device with high operating speed.

[0479] 19, multiple memory arrays 20[1] to 20[m] can be stacked. The memory arrays 20[1] to 20[m] included in the memory array 20 can be arranged in the vertical direction of the substrate surface on which the drive circuit 21 is provided, thereby improving the memory density of the memory cells 10.

[0480] The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on / off (conduction state or non-conduction state) of an access transistor functioning as a switch. The wiring PL functions as a constant potential line connected to a capacitor. Note that a wiring CL (not shown) can be separately provided as a wiring that has a function of transmitting a back-gate potential to the back-gate of an OS transistor that is an access transistor. The wiring PL may also have a function of transmitting the back-gate potential.

[0481] The memory cells 10 included in each of the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 via wiring BL. The wiring BL can be arranged in a direction perpendicular to the substrate surface on which the driver circuit 21 is provided. By arranging the wiring BL extending from the memory cells 10 included in the memory arrays 20[1] to 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. This shortens the signal propagation distance between two circuits connected to the bit line, significantly reducing the resistance and parasitic capacitance of the bit line, thereby realizing reduced power consumption and signal delay. Furthermore, the memory cells 10 can be operated even if the capacitance of the capacitive element included in the memory cell 10 is reduced.

[0482] The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 of the driver circuit 21 via a wiring GBL (not shown), which will be described later. This configuration allows a slight potential difference in the wiring BL to be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the driver circuit 21 is provided, similar to the wiring BL. By arranging the wirings BL and GBL extending from the memory cells 10 of the memory arrays 20[1] to 20[m] in a direction perpendicular to the surface of the substrate, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, the signal propagation distance between two circuits connected to the wiring GBL can be shortened, and the resistance and parasitic capacitance of the wiring GBL are significantly reduced, thereby realizing reduced power consumption and signal delay.

[0483] The wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a region functioning as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a conductor provided in contact with a region functioning as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. In other words, the wiring BL can be said to be a wiring for electrically connecting one of the source or the drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.

[0484] The memory array 20 can be provided overlapping the drive circuit 21. By providing the drive circuit 21 and the memory array 20 overlapping, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. This reduces the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20, thereby realizing reductions in power consumption and signal delay. In addition, the storage device 300 can be made smaller.

[0485] The functional circuit 51 is configured with OS transistors similar to the transistors included in the DOSRAM memory cells 10, and can be freely arranged on a circuit using Si transistors similar to the memory arrays 20[1] to 20[m], thereby facilitating integration. The signal amplification configuration in the functional circuit 51 allows for the miniaturization of subsequent circuits such as the sense amplifier 46, thereby enabling the miniaturization of the memory device 300.

[0486] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0487] In the storage device 300, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0488] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 32.

[0489] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0490] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0491] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 41 is also a circuit for outputting various signals for controlling the functional circuit 51. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0492] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 10, the function of reading data from the memory cell 10, the function of holding the read data, etc.

[0493] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is a signal RDA.

[0494] The PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. The PSW23 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW22 is controlled by the signal PON1, and the on / off of the PSW23 is controlled by the signal PON2. In FIG. 19, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0495] The memory array 20 having memory arrays 20[1] to 20[m] (m is an integer of 2 or more) and a functional layer 50 can be provided by stacking multiple layers of memory arrays 20 on a drive circuit 21. By stacking multiple layers of memory arrays 20, the memory density of the memory cells 10 can be increased. Figure 20A shows a perspective view of a storage device 300 having a functional layer 50 and five layers (m = 5) of memory arrays 20[1] to 20[5] stacked on a drive circuit 21.

[0496] 20A, the memory array 20 provided in the first layer is shown as memory array 20[1], the memory array 20 provided in the second layer is shown as memory array 20[2], and the memory array 20 provided in the fifth layer is shown as memory array 20[5]. Also shown in FIG. 20A are wiring WL and wiring PL extending in the X direction, and wiring BL extending in the Z direction (the direction perpendicular to the substrate surface on which the drive circuit is provided). Note that, to make the drawing easier to understand, the wiring WL and wiring PL of each memory array 20 are partially omitted.

[0497] 20B is a schematic diagram illustrating a configuration example of a functional circuit 51 connected to the wiring BL illustrated in FIG. 20A and memory cells 10 included in the memory arrays 20[1] to 20[5] connected to the wiring BL. Also, FIG. 20B illustrates a wiring GBL provided between the functional circuit 51 and the driver circuit 21. Note that a configuration in which multiple memory cells (memory cells 10) are electrically connected to one wiring BL is also referred to as a "memory string." Note that in the drawings, the wiring GBL may be illustrated with a thick line to improve visibility.

[0498] 20B illustrates an example of a circuit configuration of a memory cell 10 connected to a wiring BL. The memory cell 10 includes a transistor 11 and a capacitor 12. The transistor 11, the capacitor 12, and the wirings (such as a wiring BL and a wiring WL) may also be referred to as wirings BL[1] and wirings WL[1], for example. Here, the transistor 11 corresponds to the transistor 200 described in Embodiment 1.

[0499] In the memory cell 10, one of the source and the drain of the transistor 11 is connected to a wiring BL. The other of the source and the drain of the transistor 11 is connected to one electrode of a capacitor 12. The other electrode of the capacitor 12 is connected to a wiring PL. The gate of the transistor 11 is connected to a wiring WL. The back gate of the transistor 11 is connected to a wiring CL.

[0500] The wiring PL is a wiring that applies a constant potential to maintain the potential of the capacitor 12. The wiring CL is a wiring that applies a constant potential to control the threshold voltage of the transistor 11. The wiring PL and the wiring CL may have the same potential. In this case, by connecting the two wirings, the number of wirings connected to the memory cell 10 can be reduced.

[0501] The wiring GBL shown in Fig. 20B is provided to electrically connect the driver circuit 21 and the functional layer 50. Fig. 21A shows a schematic diagram of a memory device 300 in which a functional circuit 51 and memory arrays 20[1] to 20[m] are repeated as a repeating unit 70. Note that although Fig. 21A shows one wiring GBL, the wiring GBL may be provided as needed depending on the number of functional circuits 51 provided in the functional layer 50.

[0502] The wiring GBL is provided in contact with a semiconductor layer of a transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a conductor that is provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 51. In other words, the wiring GBL can be said to be a wiring for electrically connecting one of the source or the drain of a transistor included in the functional circuit 51 in the functional layer 50 to the driver circuit 21 in the vertical direction.

[0503] The repeating unit 70 including the functional circuit 51 and the memory arrays 20[1] to 20[m] may be further stacked. The memory device 300A of one embodiment of the present invention can have repeating units 70[1] to 70[p] (p is an integer of 2 or more) as shown in FIG. 21B . The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be provided as appropriate depending on the number of functional circuits 51.

[0504] In one embodiment of the present invention, OS transistors are stacked, and wirings functioning as bit lines are arranged perpendicular to the surface of a substrate on which the driver circuit 21 is provided. By providing the wirings functioning as bit lines extending from the memory array 20 perpendicular to the surface of the substrate, the length of the wiring between the memory array 20 and the driver circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit lines can be significantly reduced.

[0505] In one embodiment of the present invention, a layer in which the memory array 20 is provided includes a functional layer 50 having a functional circuit 51 that has a function of amplifying and outputting a data potential held in the memory cell 10. With this structure, a slight potential difference of the wiring BL that functions as a bit line can be amplified when reading data, and the sense amplifier 46 included in the driver circuit 21 can be driven. Since circuits such as a sense amplifier can be miniaturized, the memory device 300 can be miniaturized. Furthermore, the memory device 300 can operate even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced.

[0506] Although the above description illustrates an example in which the memory cell 10 has a 1T (transistor) 1C (capacitor) configuration, the present invention is not limited to this. For example, as shown in FIG. 25A, a 2T1C memory cell may be used in a storage device. The memory cell shown in FIG. 25A includes transistors 11a, 11b, and 11c and a capacitor 12a. Here, the transistors 11a, 11b, and 11c may have the same configuration as the transistor 11, and the capacitor 12a may have the same configuration as the capacitor 12. A RAM with such a configuration may be called NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM).

[0507] 25A , one of the source and drain of transistor 11a is electrically connected to one electrode of capacitor 12a and the first gate of transistor 11b. One of the source and drain of transistor 11b is electrically connected to one of the source and drain of transistor 11c. Wiring may be provided as appropriate in the first gate, the other of the source and drain, and the second gate of transistor 11a, the other of the source and drain and the second gate of transistor 11b, the first gate, the other of the source and drain, and the second gate of transistor 11c, and the other electrode of capacitor 12a. The structure of the memory device can also be modified as appropriate in accordance with these wirings.

[0508] Also, as shown in FIG. 25B, the transistor 11c may not be provided, and the configuration may include only the transistors 11a and 11b and the capacitance element 12a.

[0509] 25C, if the parasitic capacitance of the transistors 11a and 11b is sufficiently large, the capacitance element 12a may not be provided, in which case the memory cell is formed only by the transistors 11a and 11b.

[0510] 22 will be used to describe a configuration example of the functional circuit 51 described with reference to FIGS. 19 to 21B and a configuration example of the sense amplifier 46 included in the memory array 20 and the driver circuit 21. In FIG. 22, the driver circuit 21 is connected to wirings GBL (wirings GBL_A and GBL_B) that are connected to functional circuits 51 (functional circuits 51_A and 51_B) that are connected to memory cells 10 (memory cells 10_A and 10_B) that are connected to different wirings BL (wirings BL_A and BL_B). As the driver circuit 21 illustrated in FIG. 22, in addition to the sense amplifier 46, precharge circuits 71_A, precharge circuits 71_B, switch circuits 72_A, switch circuits 72_B, and a write / read circuit 73 are illustrated.

[0511] Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are illustrated as the functional circuits 51_A and 51_B. The transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b illustrated in FIG. 22 are OS transistors, similar to the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be stacked in the same manner as the memory arrays 20[1] to 20[m].

[0512] The wiring BL_A is connected to the gate of the transistor 52_a, and the wiring BL_B is connected to the gate of the transistor 52_b. The wiring GBL_A is connected to one of the sources or drains of the transistors 53_a and 54_a. The wiring GBL_B is connected to one of the sources or drains of the transistors 53_b and 54_b. The wirings GBL_A and GBL_B are provided in the vertical direction like the wirings BL_A and BL_B, and are connected to the transistors included in the driver circuit 21. As shown in FIG. 22 , the selection signal MUX, the control signal WE, and the control signal RE are applied to the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b, respectively.

[0513] 22 are configured with Si transistors. Switches 83_A to 83_D that configure switch circuits 72_A and 72_B can also be configured with Si transistors. One of the sources or drains of transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistors or switches that configure precharge circuits 71_A, 71_B, sense amplifier 46, and switch circuit 72_A.

[0514] The precharge circuit 71_A includes n-channel transistors 81_1 to 81_3. The precharge circuit 71_A is a circuit for precharging the wirings BL_A and BL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between a high power supply potential (VDD) and a low power supply potential (VSS) in response to a precharge signal applied to a precharge line PCL1.

[0515] The precharge circuit 71_B includes n-channel transistors 81_4 to 81_6. The precharge circuit 71_B is a circuit for precharging the wirings GBL_A and GBL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in response to a precharge signal applied to a precharge line PCL2.

[0516] The sense amplifier 46 includes p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to a wiring VHH or a wiring VLL. The wiring VHH or the wiring VLL has a function of supplying VDD or VSS. The transistors 82_1 to 82_4 are transistors that form an inverter loop. The potentials of the precharged wirings BL_A and BL_B change when the memory cells 10_A and 10_B are selected, and the potentials of the wirings GBL_A and GBL_B are set to VDD or VSS in response to the change. The potentials of the wirings GBL_A and GBL_B can be output to the outside via the switches 83_C and 83_D and the write / read circuit 73. The wirings BL_A and BL_B, and the wirings GBL_A and GBL_B correspond to bit line pairs. The write / read circuit 73 controls the writing of data signals in response to the signal EN_data.

[0517] The switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wirings GBL_A and GBL_B. The switch circuit 72_A is switched on or off under the control of a switching signal CSEL1. When the switches 83_A and 83_B are n-channel transistors, the switching signal CSEL1 is turned on at a high level and turned off at a low level. The switch circuit 72_B is a circuit for controlling the conduction state between the write / read circuit 73 and the bit line pair connected to the sense amplifier 46. The switch circuit 72_B is switched on or off under the control of a switching signal CSEL2. The switches 83_C and 83_D may be configured in the same manner as the switches 83_A and 83_B.

[0518] 22 , the memory device 300 can be configured such that the memory cells 10, the functional circuits 51, and the sense amplifiers 46 are connected via wirings BL and GBL that are provided in the vertical direction, which is the shortest distance. Although the number of functional layers 50 having transistors that configure the functional circuits 51 increases, the load on the wirings BL is reduced, which shortens the write time and makes it easier to read data.

[0519] 22 , each transistor included in the functional circuits 51_A and 51_B is controlled in response to control signals WE and RE and a selection signal MUX. In response to the control signal and the selection signal, each transistor can output the potential of the wiring BL to the driver circuit 21 via the wiring GBL. The functional circuits 51_A and 51_B can function as sense amplifiers including OS transistors. This configuration allows a slight potential difference in the wiring BL to be amplified during read operation, thereby driving the sense amplifier 46 using Si transistors.

[0520] <Configuration Example of Memory Cell> A configuration example of the memory cell 10 used in the memory device will be described with reference to FIG.

[0521] In FIG. 23, the X direction is parallel to the channel length direction of the illustrated transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions.

[0522] As shown in FIG. 23 , the memory cell 10 includes a transistor 11 and a capacitor 12. An insulator 285 is provided over the transistor 11, and an insulator 284 is provided over the insulator 285. The insulators 285 and 284 may be the same as those that can be used for the insulator 216. The transistor 11 has a structure similar to that of the transistor 200 described in the above embodiment, and the same components are denoted by the same reference numerals. For details of the transistor 200, the above embodiment can be referred to. A conductor 240 is provided in contact with one of the source and drain (conductor 242 a) of the transistor 11. The conductor 240 extends in the Z direction and functions as a wiring BL.

[0523] The capacitor 12 includes a conductor 153 on the conductor 242b, an insulator 154 on the conductor 153, and a conductor 160 (conductor 160a and conductor 160b) on the insulator 154.

[0524] At least a portion of the conductor 153, the insulator 154, and the conductor 160 is disposed inside the openings formed in the insulators 271b, 275, 280, 282, 283, and 285. The ends of the conductors 153, 154, and 160 are located at least on the insulator 282, and preferably on the insulator 285. The insulator 154 is disposed so as to cover the end of the conductor 153. This allows the conductors 153 and 160 to be electrically insulated from each other.

[0525] The deeper the openings provided in the insulators 271b, 275, 280, 282, 283, and 285 are (that is, the thicker one or more of the insulators 271b, 275, 280, 282, 283, and 285 are), the larger the capacitance of the capacitor 12. Increasing the capacitance per unit area of ​​the capacitor 12 allows for miniaturization or high integration of the semiconductor device.

[0526] The conductor 153 has a region that functions as one electrode (lower electrode) of the capacitor 12. The insulator 154 has a region that functions as a dielectric of the capacitor 12. The conductor 160 has a region that functions as the other electrode (upper electrode) of the capacitor 12. The capacitor 12 constitutes a metal-insulator-metal (MIM) capacitor.

[0527] In addition, the conductor 242 b provided so as to overlap the oxide 230 functions as a wiring electrically connected to the conductor 153 of the capacitor 12 .

[0528] The conductor 153 and the conductor 160 included in the capacitor 12 can be formed using any of the conductors that can be used for the conductor 205 or the conductor 260. The conductor 153 and the conductor 160 are preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method. For example, the conductor 153 can be formed using titanium nitride or tantalum nitride formed by an ALD method or a CVD method.

[0529] The upper surface of the conductor 242b2 is in contact with the lower surface of the conductor 153. Here, by using a conductive material with good conductivity as the conductor 242b2, the contact resistance between the conductor 153 and the conductor 242b can be reduced.

[0530] Alternatively, the conductor 160a may be made of titanium nitride formed by ALD or CVD, and the conductor 160b may be made of tungsten formed by CVD. Note that if the adhesion of tungsten to the insulator 154 is sufficiently high, the conductor 160 may have a single-layer structure of tungsten formed by CVD.

[0531] A high-dielectric (high-k) material (a material with a high relative dielectric constant) is preferably used for the insulator 154 of the capacitor 12. The insulator 154 is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.

[0532] Examples of high-dielectric-constant (high-k) insulators include oxides, oxynitrides, oxynitrides, and nitrides containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. Silicon may also be contained in the oxides, oxynitrides, oxynitrides, or nitrides. Insulators made of the above materials may also be stacked.

[0533] For example, examples of insulators made of high dielectric constant (high-k) materials include aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, oxides containing silicon and zirconium, oxynitrides containing silicon and zirconium, oxides containing hafnium and zirconium, and oxynitrides containing hafnium and zirconium. By using such high-k materials, the insulator 154 can be made thick enough to suppress leakage current and ensure sufficient capacitance of the capacitor 12.

[0534] Furthermore, it is preferable to use a laminated structure of insulators made of the above materials, and it is preferable to use a laminated structure of a high-dielectric constant (high-k) material and a material having a higher dielectric strength than the high-dielectric constant (high-k) material. For example, an insulator formed by laminating zirconium oxide, aluminum oxide, and zirconium oxide in this order can be used as the insulator 154. Alternatively, an insulator formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order can be used. Alternatively, an insulating film formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order can be used. By using a laminated structure of an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitance element 12 can be suppressed.

[0535] The deeper the openings in the insulators 271b, 275, 280, 282, 283, and 285 are (i.e., the thicker one or more of the insulators 271b, 275, 280, 282, 283, and 285 are), the larger the capacitance of the capacitor 12 can be. Here, since the insulators 271b, 275, 282, and 283 function as barrier insulators, it is preferable to set their thicknesses according to the barrier properties required for the semiconductor device. Furthermore, since the thickness of the insulator 280 determines the thickness of the conductor 260 that functions as a gate electrode, it is preferable to set the thickness of the insulator 280 according to the thickness of the conductor 260 required for the semiconductor device.

[0536] Therefore, it is preferable to set the capacitance of the capacitor 12 by adjusting the film thickness of the insulator 285. For example, the film thickness of the insulator 285 may be set in the range of 50 nm to 250 nm, and the depth of the opening may be set to approximately 150 nm to 350 nm. Forming the capacitor 12 in such a range allows the capacitor 12 to have sufficient capacitance, and prevents the height of one layer from becoming excessively high in a semiconductor device in which multiple memory cell layers are stacked. Note that a configuration may be adopted in which the capacitance of the capacitor provided in each memory cell is different in each of the multiple memory cell layers. In such a configuration, for example, the film thickness of the insulator 285 provided in each memory cell layer may be different.

[0537] In the opening provided in the insulator 285 or the like in which the capacitor element 12 is arranged, the sidewall of the opening may be approximately perpendicular to the top surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, the coverage of the conductor 153 or the like provided in the opening of the insulator 285 or the like can be improved, and defects such as voids can be reduced.

[0538] Furthermore, the conductor 242a provided so as to overlap the oxide 230 functions as wiring that is electrically connected to the conductor 240. For example, in Fig. 23, the upper surface and side end portions of the conductor 242a are electrically connected to the conductor 240 extending in the Z direction. In particular, in Fig. 23, the upper surface and side end portions of the conductor 242a2 and the side end portions of the conductor 242a1 are in contact with the conductor 240.

[0539] By directly contacting the conductor 240 with at least one of the upper surface and side end of the conductor 242a, there is no need to provide a separate connection electrode, thereby reducing the area occupied by the memory array. Furthermore, the integration density of memory cells is improved, thereby increasing the memory capacity of the memory device. It is preferable that the conductor 240 contacts a portion of the upper surface and side end of the conductor 242a. By contacting multiple surfaces of the conductor 242a, the contact resistance between the conductor 240 and the conductor 242a can be reduced. In particular, as shown in FIG. 23 , by contacting a portion of the upper surface and side end of the highly conductive conductor 242a2, the contact resistance between the conductor 240 and the conductor 242a can be further reduced.

[0540] Conductor 240 is disposed within openings formed in insulators 216 , 222 , 275 , 280 , 282 , 283 , 285 and 284 .

[0541] The conductor 240 preferably has a layered structure of conductor 240a and conductor 240b. For example, as shown in FIG. 23 , the conductor 240 can be structured such that conductor 240a is provided in contact with the inner wall of the opening, and conductor 240b is provided further inside. That is, conductor 240a is arranged closer to insulators 216, 222, 275, 280, 282, 283, 285, and 284 than conductor 240b. Furthermore, conductor 240a contacts the upper surface and side end of conductor 242a.

[0542] The conductor 240a is preferably made of a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen. The conductor 240a can have a single-layer structure or a multi-layer structure using one or more of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide, for example. This can suppress impurities such as water and hydrogen from entering the oxide 230 through the conductor 240.

[0543] Furthermore, since the conductor 240 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 240b can be made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0544] For example, it is preferable to use titanium nitride as the conductor 240a and tungsten as the conductor 240b. In this case, the conductor 240a is a conductor containing titanium and nitrogen, and the conductor 240b is a conductor containing tungsten.

[0545] The conductor 240 may have a single layer structure or a laminated structure of three or more layers.

[0546] 23 , it is preferable that an insulator 241 be provided in contact with the side surface of the conductor 240. Specifically, the insulator 241 is provided in contact with the inner walls of the openings of the insulators 216, 222, 275, 280, 282, 283, 285, and 284. The insulator 241 is also formed on the side surfaces of the insulators 224, 226, oxide 230, and conductor 242a, which are formed to protrude into the openings. Here, at least a portion of the conductor 242a is exposed from the insulator 241 and is in contact with the conductor 240. In other words, the conductor 240 is provided so as to fill the interior of the opening via the insulator 241.

[0547] 23, the uppermost portion of the insulator 241 formed below the conductor 242a is preferably located below the upper surface of the conductor 242a. This configuration allows the conductor 240 to contact at least a portion of the side end of the conductor 242a. The insulator 241 formed below the conductor 242a preferably has an area that contacts the side surface of the oxide 230. This configuration can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductor 240.

[0548] The insulator 241 may be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. This structure can prevent impurities such as water and hydrogen contained in the insulator 280, etc. from mixing into the oxide 230 through the conductor 240. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240.

[0549] 23 shows the structure in which the insulator 241 is a single layer, the present invention is not limited to this. The insulator 241 may have a stacked structure of two or more layers.

[0550] When the insulator 241 has a two-layer stacked structure, a first layer in contact with the inner wall of the opening of the insulator 280 or the like may be a barrier insulating film against oxygen, and a second layer inside the first layer may be a barrier insulating film against hydrogen. For example, the first layer may be made of aluminum oxide deposited by the ALD method, and the second layer may be made of silicon nitride deposited by the PEALD method. This structure can suppress oxidation of the conductor 240 and further reduce the intrusion of hydrogen from the conductor 240 into the oxide 230 or the like. This can improve the electrical characteristics and reliability of the transistor 11.

[0551] In the opening where the conductor 240 and the insulator 241 are disposed, the sidewall of the opening may be approximately perpendicular to the top surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, coverage of the insulator 241 and the like provided in the opening is improved.

[0552] <Configuration Example of Storage Device 300> A configuration example of the storage device 300 will be described with reference to FIG.

[0553] The memory device 300 includes a driver circuit 21, which is a layer including a transistor 310 and the like; a functional layer 50, which is a layer including transistors 52, 53, 54, 55, and the like, on the driver circuit 21; and memory arrays 20[1] to 20[m] (only memory arrays 20[1] and 20[2] are shown in FIG. 24 ) on the functional layer 50. Note that the transistor 52 corresponds to the transistors 52_a and 52_b, the transistor 53 corresponds to the transistors 53_a and 53_b, the transistor 54 corresponds to the transistors 54_a and 54_b, and the transistor 55 corresponds to the transistors 55_a and 55_b.

[0554] 24 illustrates a transistor 310 included in the driver circuit 21. The transistor 310 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 310 may be a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single crystal silicon substrate.

[0555] Here, in the transistor 310 shown in FIG. 24 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI (silicon-on-insulator) substrate.

[0556] Note that the transistor 310 illustrated in FIG. 24 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0557] A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. A plurality of wiring layers may be provided depending on the design. In this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0558] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 310. A conductor 328 or the like is embedded in the insulators 320 and 322. A conductor 330 or the like is embedded in the insulators 324 and 326. The conductors 328 and 330 function as contact plugs or wirings.

[0559] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0560] 24 also illustrates transistors 52, 53, and 55 included in the functional layer 50. The transistors 52, 53, and 55 have the same configuration as the transistor 11 included in the memory cell 10. The sources and drains of the transistors 52, 53, and 55 are connected in series.

[0561] An insulator 208 is provided over the transistors 52, 53, and 55, and a conductor 207 is provided in an opening formed in the insulator 208. Furthermore, an insulator 210 is provided over the insulator 208, and a conductor 209 is provided in an opening formed in the insulator 210. Furthermore, an insulator 212 is provided over the insulator 210, and an insulator 214 is provided over the insulator 212. Parts of a conductor 240 provided in the memory array 20[1] are buried in the openings formed in the insulators 212 and 214. Here, the insulators 208 and 210 can be made of an insulator that can be used for the insulator 216. The insulator 212 can be made of an insulator that can be used for the insulator 283. The insulator 214 can be made of an insulator that can be used for the insulator 282.

[0562] The bottom surface of the conductor 207 is in contact with the top surface of the conductor 260 of the transistor 52. The top surface of the conductor 207 is in contact with the bottom surface of the conductor 209. The top surface of the conductor 209 is in contact with the bottom surface of the conductor 240 provided in the memory array 20[1]. With this structure, the conductor 240 corresponding to the wiring BL can be electrically connected to the gate of the transistor 52.

[0563] Each of the memory arrays 20[1] to 20[m] includes a plurality of memory cells 10. The conductor 240 of each memory cell 10 is electrically connected to the conductor 240 in the upper layer and the conductor 240 in the lower layer.

[0564] 24, adjacent memory cells 10 share a conductor 240. In addition, in the adjacent memory cells 10, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductor 240.

[0565] Here, the conductor 160 functioning as the upper electrode of the capacitor 12 in the lower layer (e.g., the layer of the memory array 20[1]) and the conductor 261 functioning as the second gate electrode of the transistor 11 in the upper layer (e.g., the layer of the memory array 20[2]) can be formed in the same layer. In other words, the conductor 160 of the capacitor 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer can be formed so as to be embedded in an opening formed in the same insulator 216. The conductor 160 of the capacitor 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer are formed by processing a single conductive film, resulting in the above-described configuration. In this case, the conductor 160 of the capacitor 12 in the lower layer has the same material as the conductor 261 of the transistor 11 in the upper layer.

[0566] As described above, by simultaneously forming the conductor 160 of the capacitor 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer, the manufacturing process of the memory device according to this embodiment can be reduced, and the productivity of the memory device can be improved.

[0567] In the memory array 20 described above, multiple memory arrays 20[1] to 20[m] can be stacked. The memory arrays 20[1] to 20[m] included in the memory array 20 can be arranged in the vertical direction of the substrate surface on which the drive circuit 21 is provided, thereby improving the memory density of the memory cells 10. Furthermore, the memory array 20 can be fabricated using the same manufacturing process repeatedly in the vertical direction. The storage device 300 can reduce the manufacturing cost of the memory array 20.

[0568] This embodiment mode can be combined with other embodiment modes as appropriate.

[0569] Embodiment 3 In this embodiment, an example of a chip on which a memory device of one embodiment of the present invention is mounted will be described with reference to FIGS. 26A and 26B.

[0570] 26A and 26B, multiple circuits (systems) are implemented on a chip 1200. The technology for integrating multiple circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0571] As shown in FIG. 26A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0572] Chip 1200 is provided with bumps (not shown), which are connected to a first surface of package substrate 1201 as shown in Fig. 26B. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of package substrate 1201, which are connected to motherboard 1203.

[0573] The motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222. For example, the DOSRAM described in the above embodiment can be used as the DRAM 1221. This allows the DRAM 1221 to have low power consumption, high speed, and large capacity.

[0574] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the G...

Claims

A first insulator; a second insulator on the first insulator; and an oxide semiconductor in contact with an upper surface of the second insulator; a pair of first conductors in contact with a top surface of the oxide semiconductor and spaced apart from each other on the oxide semiconductor; a pair of second conductors respectively positioned on the pair of first conductors; the first insulator comprises silicon and oxygen; the second insulator has a barrier property against hydrogen; a distance between the pair of second conductors is greater than a distance between the pair of first conductors; Semiconductor device. 　 In claim 1, a fourth insulator located on the second insulator and having an opening between the pair of first conductors that reaches the oxide semiconductor; a fifth insulator in contact with a side surface of the fourth insulator and an upper surface of the first conductor within the opening; a sixth insulator in contact with an upper surface of the oxide semiconductor in the opening; a third conductor overlapping an upper surface of the oxide semiconductor via the sixth insulator in the opening; The fifth insulator has a barrier property against hydrogen. Semiconductor device. 　 In claim 2, the sixth insulator has a laminated structure in which a plurality of layers including an insulator are laminated, Among the plurality of layers, a layer in contact with the oxide semiconductor has an oxide containing one or both of aluminum and hafnium. Semiconductor device. 　 In claim 1, a third insulator in contact with upper surfaces of the pair of second conductors, parts of side surfaces of the pair of first conductors, and parts of side surfaces of the oxide semiconductor; The third insulator has a barrier property against hydrogen. Semiconductor device. 　 In claim 1, the second insulator comprises silicon nitride, aluminum oxide, hafnium oxide, or tantalum oxide; Semiconductor device. 　 In claim 1, the oxide semiconductor has a first layer in contact with the second insulator, and a second layer located on the first layer and in contact with the first conductor; The first layer and the second layer have different compositions, The first layer is thinner than the second layer. Semiconductor device. 　 In claim 1, the second conductor is more conductive than the first conductor; The second conductor is thicker than the first conductor. Semiconductor device. 　 In claim 1, the first conductor comprises tantalum nitride; Semiconductor device. 　 In claim 1, the first conductor comprises tantalum nitride; the second conductor comprises tungsten. Semiconductor device.

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