DC-DC converter

Abstract

In an H-bridge type buck-boost DC-DC converter, when the lower side of an upper and lower range of a reference signal for buck is zero or less and the upper side of an upper and lower range of a reference signal for boost is zero or more at the start of one switching cycle, a control unit maintains a fourth switching element in an Off-state for a predetermined period from the start of one switching cycle. This buck-boost DC-DC converter prevents an increase in loss caused by a boost circuit performing an unintentional switching operation, outside an overlap region, under a condition where the DC-DC converter should operate only in a buck mode.

Description

DC / DC converter

[0001] The present disclosure relates to a DC / DC converter capable of step-up and step-down.

[0002] One type of DC / DC converter is an H-bridge buck-boost DC / DC converter that can seamlessly switch between boost and buck operations (see, for example, Patent Document 1). H-bridge buck-boost DC / DC converters are often used in DC power supplies with fluctuating voltages, such as storage batteries and solar cells.

[0003] When performing step-down operation with an H-bridge step-up / step-down DC / DC converter, it is common to fix the high-side switching element on the output side to the on state and the low-side switching element to the off state, and control the ratio of the on-period to the off-period of the high-side switching element on the input side.When performing step-up operation with an H-bridge step-up / step-down DC / DC converter, it is common to fix the high-side switching element on the input side to the on state and the low-side switching element to the off state, and control the ratio of the on-period to the off-period of the low-side switching element on the output side.

[0004] Some H-bridge type buck-boost DC / DC converters have an overlap region at the boundary between the buck operation region and the boost operation region, and in the overlap region, they support buck-boost operation, which involves both buck operation by the high-side switching element on the input side and boost operation by the low-side switching element on the output side.

[0005] Japanese Patent Application Laid-Open No. 2000-166223

[0006] When an H-bridge buck-boost DC / DC converter with an overlap region is configured in peak current mode, if a heavy load occurs during buck operation, a delay in current detection may cause the current to be determined to be zero at the start of one switching period, triggering boost operation as well, resulting in buck-boost operation.When current is detected, the converter returns from buck-boost operation to buck operation, but switching to buck-boost operation at the start of one switching period is unnecessary switching and leads to losses.

[0007] A DC / DC converter according to one aspect of the present disclosure includes: a first arm including a first switching element and one of a second switching element and a second rectifier element, wherein the first switching element is connected in series to the one of the second switching element and the second rectifier element at a first connection point and is connected in parallel to a DC power source; a second arm including a third switching element and one of the third rectifier element and a fourth switching element, wherein the one of the third switching element and the third rectifier element is connected in series to the fourth switching element at a second connection point and is connected in parallel to a DC bus; a reactor connected to the first connection point of the first arm and the second connection point of the second arm; and a control unit that controls the first switching element, the second switching element, the third switching element, and the fourth switching element, or that controls the first switching element and the fourth switching element. The control unit generates a sawtooth-wave-shaped step-up reference signal by adding slope compensation to an error signal corresponding to the difference between the output voltage or output current to the DC bus and a reference value, and generates a sawtooth-wave-shaped step-down reference signal by adding a step-down sawtooth wave obtained by shifting the step-up reference signal upward, the step-down sawtooth wave having a lower side having a certain overlap region with the upper side of the step-up sawtooth wave, to the error signal, and turns on the first switching element when a current detection value obtained by detecting a current flowing through the reactor at the start of one switching period is within an upper or lower range of the step-down reference signal. When the current detection value matches the step-down reference signal, the first switching element is turned off; when the current detection value is within the upper and lower range of the step-up reference signal at the start of one switching period, the fourth switching element is turned on; thereafter, when the current detection value matches the step-up reference signal, the fourth switching element is turned off; when, at the start of one switching period, the lower side of the upper and lower range of the step-down reference signal is equal to or less than zero and the upper side of the upper and lower range of the step-up reference signal is equal to or greater than zero, the fourth switching element is maintained in an off state for a predetermined period from the start of one switching period.

[0008] According to the present disclosure, in an H-bridge buck-boost DC / DC converter, it is possible to prevent an increase in loss that occurs due to the boost circuit performing unintentional switching operation under conditions where the converter should operate only in buck operation, not in the overlap region.

[0009] FIG. 1 is a diagram illustrating an example of the configuration of an H-bridge buck-boost DC / DC converter according to an embodiment. FIG. 2 is a diagram illustrating an example of the circuit configuration of a control unit according to a comparative example (voltage mode). FIG. 3 is a diagram illustrating an example of the circuit configuration of a control unit according to an embodiment (peak current mode). FIG. 4 is a diagram illustrating an example of a timing chart of a current detection value, a step-down reference signal, a step-up reference signal, and gate-source voltages of a first switching element and a fourth switching element, for explaining the basic operation of an H-bridge buck-boost DC / DC converter according to an embodiment. FIGS. 5(a) and 5(b) are diagrams illustrating a schematic diagram of a current flow during step-up operation. FIGS. 6(a) and 6(b) are diagrams illustrating a schematic diagram of a current flow during step-down operation. FIGS. 7(a) and 7(b) are diagrams illustrating a reverse current flow from the output side to the input side. FIG. 8 is a diagram illustrating an example of a timing chart of a current detection value, a step-down reference signal, a step-up reference signal, and gate-source voltages of a first switching element and a fourth switching element when the third switching element is fixed to a constantly off state. FIG. 9 is a timing chart showing an example of the current detection value, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element and the fourth switching element when a reverse current occurs during step-up operation. FIG. 10 is a timing chart showing an example of the current detection value, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element and the fourth switching element when a reverse current occurs during step-down operation. FIG. 11 is a timing chart showing an example of the current detection value, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element and the fourth switching element when a reverse current countermeasure according to the embodiment is implemented. FIG. 12 is a timing chart showing an example of the current detection value, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element and the fourth switching element when a light load is applied during step-down operation and no delay occurs in the current detection value. FIG. 13 is a diagram showing an example of a timing chart of the current detection value, the reference signal for step-down, the reference signal for step-up, and the gate-source voltages of the first switching element and the fourth switching element when there is a heavy load during step-down operation and no delay occurs in the current detection value.FIG. 14 is a timing chart showing an example of the detected current value, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element and the fourth switching element when a delay occurs in the detected current value under a light load during step-down operation. FIG. 15 is a timing chart showing an example of the detected current value, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element and the fourth switching element when a delay occurs in the detected current value under a heavy load during step-down operation. FIG. 16 is a timing chart showing a first example of the detected current value, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element and the fourth switching element when the upper end of the upper and lower ranges of the step-up reference signal is equal to or greater than zero during step-down operation. FIG. 17 is a timing chart showing a second example of the detected current value, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element and the fourth switching element when the upper end of the upper and lower ranges of the step-up reference signal is equal to or greater than zero during step-down operation. FIG. 18 is a diagram showing an example of the configuration of a step-up / step-down DC / DC converter according to a modified example.

[0010] 1 is a diagram showing an example of the configuration of an H-bridge type buck-boost DC / DC converter 10 according to an embodiment. A DC power supply 1 is connected to the input side of the buck-boost DC / DC converter 10, and a DC bus Bdc is connected to the output side. A load 2 is connected to the DC bus Bdc. For example, the load 2 may be a server or storage device in a data center. The DC power supply 1 may be a storage battery. In this case, the storage battery functions as a backup power source for the server or storage device.

[0011] The step-up / step-down DC / DC converter 10 includes a first capacitor C1, a reactor L1, a first switching element Q1 to a fourth switching element Q4, a second capacitor C2, a first drive circuit dr1 to a fourth drive circuit dr4, and a control unit 20. For example, electrolytic capacitors can be used for the first capacitor C1 and the second capacitor C2. For the first switching element Q1 to the fourth switching element Q4, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors) can be used.

[0012] A first smoothing capacitor C1 is connected between the positive and negative wiring of the DC power supply 1. A first arm including a first switching element Q1 and a second switching element Q2 connected in series is connected in parallel to the DC power supply 1 and the first capacitor C1. A voltage sensor V1 and a second smoothing capacitor C2 are connected between the positive and negative wiring of the DC bus Bdc. A second arm including a third switching element Q3 and a fourth switching element Q4 connected in series is connected in parallel to the DC bus Bdc and the second capacitor C2.

[0013] The first switching element Q1 functions as a high-side switching element for stepping down, the second switching element Q2 functions as a low-side switching element for stepping down, the third switching element Q3 functions as a high-side switching element for stepping up, and the fourth switching element Q4 functions as a low-side switching element for stepping up.

[0014] A reactor L1 is connected between the midpoint of the first arm (a connection point N1 where the first switching element Q1 and the second switching element Q2 are connected in series to each other) and the midpoint of the second arm (a connection point N2 where the third switching element Q3 and the fourth switching element Q4 are connected in series to each other).

[0015] A first diode D1 to a fourth diode D4 are formed or connected in anti-parallel to the first switching element Q1 to the fourth switching element Q4, respectively, as body diodes. When N-channel MOSFETs are used for the first switching element Q1 to the fourth switching element Q4, parasitic diodes formed in the source-drain direction can be used as the first diode D1 to the fourth diode D4. When IGBTs are used for the first switching element Q1 to the fourth switching element Q4, external diodes are connected as the first diode D1 to the fourth diode D4.

[0016] The first drive circuit dr1 to the fourth drive circuit dr4 generate drive signals for the first switching element Q1 to the fourth switching element Q4 based on control signals for the first switching element Q1 to the fourth switching element Q4 input from the control unit 20, respectively, to drive the first switching element Q1 to the fourth switching element Q4. When the switching elements are MOSFETs, the drive circuits generate gate-source voltages and apply them between the gate and source of the MOSFETs.

[0017] The current sensor A1 detects the current flowing through the reactor L1 and outputs the detected current to the control unit 20. The current sensor A1 is composed of, for example, a shunt resistor and a current amplifier that amplifies and outputs the voltage across the shunt resistor. The current sensor A1 may also be composed of a Hall element and an amplifier that converts the magnetic field generated in the Hall element into a voltage. While FIG. 1 shows an example in which the current sensor A1 is installed in the positive wiring between the DC power supply 1 and the first switching element Q1, the current sensor A1 may also be installed upstream or downstream of the reactor L1.

[0018] The voltage sensor V1 detects the output voltage of the step-up / step-down DC / DC converter 10 and outputs the detected output voltage to the control unit 20. The voltage sensor V1 is formed of, for example, a resistive voltage dividing circuit.

[0019] The control unit 20 performs PWM (Pulse Width Modulation) control of the first switching element Q1 to the fourth switching element Q4 based on the output voltage of the step-up / step-down DC / DC converter 10 and the current flowing through the reactor L1.

[0020] 2 is a diagram showing an example of the circuit configuration of the control unit 20 according to a comparative example (voltage mode). The voltage mode is a system in which only a voltage error signal relative to a reference value is fed back. The error amplifier 21 amplifies and outputs the difference between the output voltage detected by the voltage sensor V1 and a reference voltage (target voltage) Vref.

[0021] The boost-side comparator 22 compares the error voltage output from the error amplifier 21 with the boost sawtooth wave (ramp wave) to determine the pulse width of the PWM signal that controls the fourth switching element Q4. When the error voltage is within the upper or lower range of the boost sawtooth wave and the error voltage is lower than the boost sawtooth wave, the boost-side comparator 22 outputs a high-level signal. When the error voltage is higher than the boost sawtooth wave, the boost-side comparator 22 outputs a low-level signal.

[0022] The buck-side comparator 23 compares the error voltage output from the error amplifier 21 with the buck sawtooth wave to determine the pulse width of the PWM signal that controls the first switching element Q1. When the error voltage is within the upper or lower range of the buck sawtooth wave, and the error voltage is higher than the buck sawtooth wave, the buck-side comparator 23 outputs a high-level signal. When the error voltage is lower than the buck sawtooth wave, the buck-side comparator 23 outputs a low-level signal.

[0023] The control logic circuit 24 outputs the PWM signal for the fourth switching element Q4 output from the boost-side comparator 22 to the fourth drive circuit dr4, and outputs a PWM signal of the opposite phase to the PWM signal for the fourth switching element Q4 output from the boost-side comparator 22 to the third drive circuit dr3. The control logic circuit 24 outputs the PWM signal for the first switching element Q1 output from the buck-side comparator 23 to the first drive circuit dr1, and outputs a PWM signal of the opposite phase obtained by inverting the PWM signal for the first switching element Q1 output from the buck-side comparator 23 to the second drive circuit dr2.

[0024] In the step-up / step-down DC / DC converter 10, by providing a certain overlap region between the step-up sawtooth wave and the step-down sawtooth wave, step-down and step-up operation can be performed in a region where the input voltage and output voltage are close to each other. This prevents chattering, which occurs when the step-down operation and step-up operation frequently switch between them in a region where the input voltage and output voltage are close to each other, and enables seamless switching between the step-down operation and step-up operation. However, in the voltage mode of the comparative example, a double pole is generated by an LC filter composed of a reactor L1 and a second capacitor C2, making phase compensation complicated.

[0025] 3 is a diagram showing an example of the circuit configuration of the control unit 20 according to the embodiment (peak current mode). The peak current mode is a method of feeding back a voltage error signal and a reactor current. The error amplifier 21 amplifies and outputs the difference between the output voltage detected by the voltage sensor V1 and the reference voltage Vref.

[0026] The buck-side adder 25 adds the buck sawtooth wave to the error voltage output from the error amplifier 21 and outputs the result as a sawtooth-wave buck reference signal. The boost-side adder 26 adds the boost sawtooth wave to the error voltage output from the error amplifier 21 and outputs the result as a sawtooth-wave boost reference signal. The buck sawtooth wave and the boost sawtooth wave are both downward-sloping (down-sloping) sawtooth waves. The buck sawtooth wave is a sawtooth wave obtained by shifting the boost sawtooth wave upward, and a certain overlap region is formed below the buck sawtooth wave and above the boost sawtooth wave. In these sawtooth waves, the rising edge and the subsequent down-slope form a switching cycle in which the switching element is switched based on the PWM signal, and the switching cycle is repeated in the sawtooth wave.

[0027] The width of the overlap region can be set by the designer. The wider the overlap region, the wider the range of input / output voltages over which the step-up / step-down operation can be performed. For example, if the input / output voltage fluctuates during step-up / step-down operation, the operating mode will not switch, allowing for stable operation. However, if the overlap region is set too wide, the step-up / step-down operation will be less efficient than step-up only or step-down only operation, and the range of input / output voltages over which the efficiency drops will be wider.

[0028] The buck-side comparator 27 compares the buck reference signal output from the buck-side adder 25 with the current value detected by the current sensor A1 (hereinafter referred to as the detected current value) to determine the pulse width of the PWM signal that controls the first switching element Q1. When the detected current value is within the upper and lower ranges of the buck reference signal and is lower than the buck reference signal, the buck-side comparator 27 outputs a high-level signal. When the detected current value increases and matches the buck reference signal, the buck-side comparator 27 outputs a low-level signal.

[0029] The boost-side comparator 28 compares the boost reference signal output from the boost-side adder 26 with the current detection value to determine the pulse width of the PWM signal that controls the fourth switching element Q4. When the current detection value is within the upper and lower ranges of the boost reference signal and is lower than the boost reference signal, the boost-side comparator 28 outputs a high-level signal. When the current detection value increases and matches the boost reference signal, the boost-side comparator 28 outputs a low-level signal.

[0030] The control logic circuit 29 outputs the PWM signal for the first switching element Q1 output from the buck-side comparator 27 to the first drive circuit dr1, and outputs a PWM signal of opposite phase obtained by inverting the PWM signal for the first switching element Q1 output from the buck-side comparator 27 to the second drive circuit dr2. The control logic circuit 29 outputs the PWM signal for the fourth switching element Q4 output from the boost-side comparator 28 to the fourth drive circuit dr4, and in principle outputs a PWM signal of opposite phase to the PWM signal for the fourth switching element Q4 output from the boost-side comparator 28 to the third drive circuit dr3. It is also possible to control the PWM signal output to the third drive circuit dr3 to be fixed at a low level.

[0031] The step-down sawtooth wave or step-up sawtooth wave is added to the error voltage output from the error amplifier 21 in order to suppress subharmonic oscillations that occur when the duty is 50% or higher when the detected current value is directly compared with the error voltage. When the duty is 50% or higher, the slope of the falling detected current value becomes larger than the slope of the rising detected current value, and the range of change in the detected current value between periods gradually increases, leading to oscillation. In this embodiment, slope compensation is performed by adding a downslope to the error voltage. Even when the duty is 50% or higher, an increase in the on-time can be suppressed, preventing oscillation.

[0032] The circuit functional blocks shown in Figures 2 and 3 can also be implemented using digital control by a microcontroller. In this case, the output voltage detected by the voltage sensor V1 and the current value detected by the current sensor A1 must each be converted into a digital value by an A / D converter.

[0033] In the peak current mode according to the embodiment, a double pole due to an LC filter on the output side does not occur, so phase compensation can be simplified. In particular, when digital control is used, the amount of calculation can be significantly reduced compared to the voltage mode. Furthermore, the peak current mode has high responsiveness to sudden fluctuations in the DC power supply 1, and is suitable for controlling discharge from a storage battery, which has large voltage fluctuations.

[0034] Fig. 4 is a diagram showing an example of a timing chart of a current detection value, a step-down reference signal, a step-up reference signal, and gate-source voltages of the first switching element and the fourth switching element, for explaining the basic operation of the H-bridge step-up / step-down DC / DC converter 10 according to the embodiment. Figs. 5(a) and 5(b) are diagrams showing a schematic diagram of a current flow in a step-up operation. Figs. 6(a) and 6(b) are diagrams showing a schematic diagram of a current flow in a step-down operation.

[0035] In the step-down operation of the step-up / step-down DC / DC converter 10 (see FIGS. 6(a)-(b)), the control unit 20 fixes the fourth switching element Q4 to the off state and, in principle, fixes the third switching element Q3 to the on state. The control unit 20 causes the first switching element Q1 and the second switching element Q2 to operate in a complementary manner. When the first switching element Q1 is in the on state and the second switching element Q2 is in the off state, power is transmitted from the DC power source 1 to the output side while charging the reactor L1 (transmission state, see (2) in FIG. 4 and FIG. 6(a)). When the first switching element Q1 is in the off state and the second switching element Q2 is in the on state, the DC power source 1 and the reactor L1 are disconnected, and the power stored in the reactor L1 is transmitted to the output side (commutation state, see period (3) in FIG. 4 and FIG. 6(b)).

[0036] When the detected current value is within the upper and lower ranges of the reference signal for step-down at the start of one switching period, the control unit 20 turns on the first switching element Q1 and turns off the second switching element Q2 to control the transmission state. After that, when the detected current value matches the reference signal for step-down, the control unit 20 turns off the first switching element Q1 and turns on the second switching element Q2 to control the commutation state, and this state continues until the end of one switching period.

[0037] In the step-up operation of the step-up / step-down DC / DC converter 10 (see FIGS. 5(a)-(b)), the control unit 20 fixes the first switching element Q1 in the ON state and fixes the second switching element Q2 in the OFF state. In principle, the control unit 20 causes the third switching element Q3 and the fourth switching element Q4 to operate in a complementary manner. When the fourth switching element Q4 is in the ON state and the third switching element Q3 is in the OFF state, power transmission from the input side to the output side is stopped and the reactor L1 is charged from the DC power source 1 (storage state, period (1) in FIG. 4, see FIG. 5(a)). When the fourth switching element Q4 is in the OFF state and the third switching element Q3 is in the ON state, power is transmitted to the output side from both the DC power source 1 and the reactor L1 (transmission state, period (2) in FIG. 4, see FIG. 5(b)).

[0038] When the detected current value is within the upper and lower limits of the reference signal for boosting at the start of one switching period, the control unit 20 turns on the fourth switching element Q4 and turns off the third switching element Q3 to control the storage state. After that, when the detected current value matches the reference signal for boosting, the control unit 20 turns off the fourth switching element Q4 and turns on the third switching element Q3 to control the transmission state, and this state continues until the end of one switching period.

[0039] In the step-up / step-down operation of the step-up / step-down DC / DC converter 10 (see FIG. 4 ), the step-down operation and step-up operation coexist. At the start of one switching period, if the detected current value is within the upper and lower ranges of the step-down reference signal and within the upper and lower ranges of the step-up reference signal, the control unit 20 turns on the first switching element Q1 and the fourth switching element Q4 and turns off the second switching element Q2 and the third switching element Q3. When the detected current value subsequently matches the step-up reference signal, the control unit 20 turns off the fourth switching element Q4 and turns on the third switching element Q3, continuing these operations until the end of one switching period. When the detected current value matches the step-down reference signal, the control unit 20 turns off the first switching element Q1 and turns on the second switching element Q2, continuing these operations until the end of one switching period.

[0040] 7(a) and 7(b) are diagrams showing the flow of reverse current from the output side to the input side. Fig. 7(a) shows a state in which reverse current occurs during the transmission state of the boost operation. During the boost operation, the voltage of the DC power supply 1 is lower than the voltage of the DC bus Bdc, so there is a risk of reverse current if the current from the DC power supply 1 to the DC bus Bdc becomes small.

[0041] Figure 7(b) shows a state in which a reverse current occurs in the commutation state of the step-down operation. During the step-down operation, the voltage of the DC power supply 1 is higher than the voltage of the DC bus Bdc, so a reverse current should not occur. However, a second capacitor C2 is connected to the DC bus Bdc. From the second capacitor C2, the first switching element Q1 and the second switching element Q2 appear as a step-up converter. In the transmission state of the step-down operation (similar to Figure 7(a)), there is a risk of power flowing back to the input side from both the second capacitor C2 and the reactor L1.

[0042] Even if a large amount of power is not stored in the second capacitor C2, if a charger is connected to the DC bus Bdc or if another step-up / step-down DC / DC converter is connected in parallel to the step-up / step-down DC / DC converter 10, there is a risk of power flowing back from the charger or the other step-up / step-down DC / DC converter.

[0043] Backflow to the storage battery can cause damage or deterioration of the storage battery, and is therefore an event that should be avoided even for a short period of time on the order of milliseconds. Therefore, in order to prevent backflow of current from the DC bus Bdc to the DC power supply 1, it is possible to control the third switching element Q3 to be fixed to a constant off state.

[0044] 8 is a diagram showing an example of a timing chart of the current detection value Idet, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element Q1 and the fourth switching element Q4 when the third switching element Q3 is fixed to a constantly off state. By fixing the gate-source voltage of the third switching element Q3 to a low level, the third switching element Q3 is fixed to a constantly off state. As a result, the lower limit of the current detection value Idet is clamped to 0 A, and reverse current from the DC bus Bdc to the DC power supply 1 is prevented.

[0045] If the third switching element Q3 is always fixed to the off state, current flows from at least one of the DC power source 1 and the reactor L1 to the DC bus Bdc through the third diode D3 during the transmission state during step-down operation and step-up operation. If the third diode D3 is a parasitic diode of a MOSFET, a large current flowing through the third diode D3 may generate a large amount of heat, which may result in smoke or fire. Furthermore, when current flows through the third diode D3 (diode rectification), power loss is greater than when current flows with the third switching element Q3 turned on (synchronous rectification), resulting in lower conversion efficiency. The larger the current flowing through the third diode D3, the greater the power loss generated by the third diode D3.

[0046] Therefore, one possible control method is to maintain synchronous rectification by keeping the third switching element Q3 on under heavy load conditions, and to turn off the third switching element Q3 to switch to diode rectification under light load conditions. For example, one possible control method is to provide a current sensor on the output side of the step-up / step-down DC / DC converter 10 to detect the output current of the step-up / step-down DC / DC converter 10, and to turn off the third switching element Q3 when it is determined that the output current is sufficiently small.

[0047] In this control, if the output current subsequently increases and the third switching element Q3 is turned on again, the power stored in the second capacitor C2 may flow back to the input side. This reverse current is particularly likely to occur in situations where sudden changes in the load 2 occur repeatedly.

[0048] 9 is a timing chart showing an example of the current detection value Idet, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element Q1 and the fourth switching element Q4 when a reverse current occurs during step-up operation. In the example shown in FIG. 9, after the third switching element Q3 switches from a light load mode (diode rectification mode) in which the third switching element Q3 is always off to a normal mode (synchronous rectification mode) in which the third switching element Q3 operates in a complementary manner to the fourth switching element Q4, the current detection value Idet enters a negative region.

[0049] 10 is a timing chart showing an example of the current detection value Idet, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element Q1 and the fourth switching element Q4 when a reverse current occurs during step-down operation. In the example shown in FIG. 10, after switching from the light load mode (diode rectification mode) in which the third switching element Q3 is always off to the normal mode (synchronous rectification mode) in which the third switching element Q3 is always on, the current detection value Idet enters the negative region.

[0050] Therefore, in this embodiment, the control unit 20 cancels the light load mode and switches to the normal mode on the condition that a current value equal to or greater than a predetermined constant value flows through the reactor L1.

[0051] In the step-up operation or the step-up / step-down operation, when the current detection value Idet is less than a certain value, the control unit 20 controls the third switching element Q3 to be constantly off (light load mode), and when the current detection value Idet is equal to or greater than the certain value, the control unit 20 controls the third switching element Q3 to operate in a complementary manner with respect to the fourth switching element Q4 (normal mode). The certain value is preset by the designer based on the results of experiments and simulations to a value that ensures backflow prevention.

[0052] In the step-down operation, when the current detection value Idet is less than a certain value, the control unit 20 controls the third switching element Q3 to be always off and the fourth switching element Q4 to be always off (light load mode), and when the current detection value Idet is equal to or greater than a certain value, the control unit 20 controls the third switching element Q3 to be always on and the fourth switching element Q4 to be always off (normal mode).

[0053] In any of the voltage step-up operation, voltage step-down operation, and voltage step-up / step-down operation, when the third switching element Q3 is in the on state, the control unit 20 forcibly turns off the third switching element Q3 if the current detection value Idet becomes zero.

[0054] FIG. 11 is a diagram showing an example of a timing chart of the current detection value Idet, the reference signal for step-down, the reference signal for step-up, and the gate-source voltages of the first switching element Q1 and the fourth switching element Q4 when the reverse current countermeasures according to the embodiment are implemented.

[0055] When the current detection value Idet reaches a certain value or more, the light load mode is released and the normal mode is entered, thereby preventing reverse current from flowing from the output side. In the normal mode, synchronous rectification is performed, which can improve conversion efficiency while suppressing heat generation.

[0056] In addition, in the peak current mode, the current flowing from the DC power supply 1 to the reactor L1 is constantly monitored, so there is no need to add a new current sensor for preventing backflow. Therefore, no additional hardware costs are incurred. In contrast, in the voltage mode, a new current sensor must be installed, which incurs additional hardware costs.

[0057] As described above, the buck-boost DC / DC converter 10 provides an offset between the boost reference signal and the buck reference signal, thereby providing a certain overlap region, enabling smooth switching between boost and buck operation. In the buck-boost DC / DC converter 10, the detected current value Idet may be delayed relative to the boost reference signal and the buck reference signal due to hardware factors. In particular, in digital control, delays may occur in the A / D converter of the current detection system. During buck operation, if there is a heavy load and the detected current value Idet is delayed relative to the reference signal, an unintended temporary switch from buck operation to buck-boost operation may occur.

[0058] 12 is a timing chart showing an example of the current detection value Idet, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element Q1 and the fourth switching element Q4 when a light load is applied during step-down operation and no delay occurs in the current detection value Idet. FIG. 13 is a timing chart showing an example of the current detection value Idet, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element Q1 and the fourth switching element Q4 when a heavy load is applied during step-down operation and no delay occurs in the current detection value Idet.

[0059] 14 is a timing chart showing an example of the current detection value Idet, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element Q1 and the fourth switching element Q4 when a delay occurs in the current detection value Idet under a light load during step-down operation. FIG. 15 is a timing chart showing an example of the current detection value Idet, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element Q1 and the fourth switching element Q4 when a delay occurs in the current detection value Idet under a heavy load during step-down operation.

[0060] As shown in Figure 13, when there is no delay in the current detection value Idet, even under a heavy load, the relative relationship between the current detection value Idet, the step-down reference signal, and the step-up reference signal remains constant, resulting in an overall increase, and therefore no boost operation is initiated. In contrast, as shown in Figure 15, when there is a delay in the current detection value Idet and a heavy load occurs, even if the step-down reference signal and the step-up reference signal increase, the current detection value Idet does not increase accordingly at the start of one switching cycle. As a result, the current detection value Idet falls within the upper and lower ranges of the step-up reference signal, triggering the boost operation. Subsequently, when the current detection value Idet exceeds the step-up reference signal, the boost operation transitions from the accumulation state to the transmission state. However, this boost operation at the start of one switching cycle is unnecessary switching and results in loss.

[0061] Therefore, during the voltage step-down operation, a blanking time is provided for the voltage step-up operation for a predetermined period from the start of one switching cycle. If, at the start of one switching cycle, the lower end of the upper and lower range of the voltage step-down reference signal is equal to or less than zero and the upper end of the upper and lower range of the voltage step-up reference signal is equal to or greater than zero, the control unit 20 keeps the fourth switching element Q4 in an off state for a predetermined period from the start of one switching cycle to disable the voltage step-up operation.

[0062] 16 is a diagram showing a first example of a timing chart of the current detection value Idet, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element Q1 and the fourth switching element Q4 when the upper side of the upper and lower ranges of the step-up reference signal is equal to or greater than zero during step-down operation. In the first example, when the lower side of the step-down reference signal is equal to or less than zero and the upper side of the step-up reference signal is equal to or greater than zero at the start of one switching period, the control unit 20 maintains the fourth switching element Q4 in the off state for the delay time required to detect the current flowing through the reactor L1, i.e., the predetermined period, from the start of one switching period.

[0063] Hereinafter, this delay time will be referred to as the first masking period M1. The designer derives the delay time of the current detection system in advance through experiments or simulations and sets it as the first masking period M1. When the step-up / step-down control is implemented by hardware control, a gate element is added to the control logic circuit 29 shown in FIG. 3 that fixes the PWM signal of the fourth switching element Q4 to a low level and fixes the PWM signal of the third switching element Q3 to a high level during the first masking period M1. When the step-up / step-down control is implemented by digital control, the comparison process between the PWM signal of the fourth switching element Q4 and the current detection value Idet is stopped during the first masking period M1.

[0064] 17 is a diagram showing a second example of a timing chart of the current detection value Idet, the step-down reference signal, the step-up reference signal, and the gate-source voltages of the first switching element Q1 and the fourth switching element Q4 when the upper side of the upper and lower ranges of the step-up reference signal is equal to or greater than zero during step-down operation. In the second example, when the lower side of the upper and lower ranges of the step-down reference signal is equal to or less than zero and the upper side of the upper and lower ranges of the step-up reference signal is equal to or greater than zero at the start of one switching period, the control unit 20 maintains the fourth switching element Q4 in the off state from the start of one switching period until the upper side of the upper and lower ranges of the step-up reference signal falls below zero.

[0065] Hereinafter, the period from the start of one switching cycle until the upper side of the upper and lower range of the boost reference signal falls below zero will be referred to as a second masking period M2. The second masking period M2 is a variable value.

[0066] In this way, by disabling the boost operation for a predetermined period when the upper side of the upper and lower ranges of the boost reference signal is equal to or greater than zero at the start of one switching cycle during the step-down operation, it is possible to prevent an unintended switch from the step-down operation to the step-up / step-down operation at the start of one switching cycle, thereby preventing unnecessary loss during the step-down operation.

[0067] When the first masking period M1 is used, the masking period can be set to a minimum, and when the second masking period M2 is used, the boost operation can be disabled until the boost reference signal falls below zero, so that switching to the boost / buck operation can be more reliably prevented.

[0068] The present disclosure has been described above based on the embodiments. The embodiments are merely examples, and it will be understood by those skilled in the art that various modifications are possible in the combination of the respective components and processing steps, and that such modifications are also within the scope of the present disclosure.

[0069] 18 is a diagram showing a configuration example of a step-up / step-down DC / DC converter according to a modified example. When bidirectional operation is not required, the second switching element Q2 can be replaced with a second diode D2, which is a passive element, and the third switching element Q3 can be replaced with a third diode D3, which is a passive element.

[0070] In the above-described embodiment, an example of CV discharge from the storage battery is assumed. That is, the error amplifier 21 amplifies the difference between the output voltage detected by the voltage sensor V1 and the reference voltage to generate an error signal for generating a reference signal. In contrast, when CC discharge from the storage battery is performed, a current sensor is provided on the output side of the step-up / step-down DC / DC converter 10. The error amplifier 21 amplifies the difference between the output current detected by the current sensor and the reference voltage corresponding to the target current, and generates an error signal corresponding to that difference for generating a reference signal. The subsequent processing is the same as in the case of CV discharge.

[0071] The embodiment may be specified by the following items.

[0072] [Item 1] A first arm including a first switching element (Q1), a second switching element (Q2), and a second rectifier element (D2), wherein the first switching element (Q1) is connected in series to one of the second switching element (Q2) and the second rectifier element (D2) at a first connection point (N1), and the first arm is connected in parallel to a DC power source (1); a second arm including one of a third switching element (Q3) and a third rectifier element (D3), and a fourth switching element (Q4), wherein the one of the third switching element (Q3) and the third rectifier element (D3) is connected in series to the fourth switching element (Q4) at a second connection point (N2), and the second arm is connected in parallel to a DC bus (Bdc); a reactor (L1) connected to the first connection point (N1) of the first arm and the second connection point (N2) of the second arm; a control unit (20) that controls the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4), or that controls the first switching element (Q1) and the fourth switching element (Q4), wherein the control unit (20) generates a sawtooth-wave step-up reference signal by adding slope compensation to an error signal between an output voltage or an output current to the DC bus (Bdc) and a reference value, and generates a sawtooth-wave step-down reference signal by adding a step-down sawtooth wave obtained by shifting the step-up reference signal upward, the lower side of which has a certain overlap region with the upper side of the step-up sawtooth wave, to the error signal, At the start of one switching period, if a current detection value obtained by detecting a current flowing through the reactor (L1) is within an upper or lower range of the reference signal for step-down, the first switching element (Q1) is turned on, and thereafter, if the current detection value coincides with the reference signal for step-down, the first switching element (Q1) is turned off; at the start of one switching period, if the current detection value is within an upper or lower range of the reference signal for step-up, the fourth switching element (Q4) is turned on, and thereafter, if the current detection value coincides with the reference signal for step-up, the fourth switching element (Q4) is turned off;the fourth switching element (Q4) is maintained in an off state for a predetermined period from the start of one switching cycle, when, at the start of one switching cycle, a lower side of an upper and lower range of the step-down reference signal is equal to or less than zero and an upper side of an upper and lower range of the step-up reference signal is equal to or greater than zero.

[0073] This makes it possible to prevent switching from voltage step-down operation to voltage step-up / step-down operation at the start of one switching period, and to prevent unnecessary loss from occurring during voltage step-down operation.

[0074] [Item 2] The DC / DC converter (10) according to Item 1, wherein, when a lower side of an upper and lower range of the step-down reference signal is equal to or less than zero and an upper side of an upper and lower range of the step-up reference signal is equal to or greater than zero at the start of one switching period, the control unit (20) maintains the fourth switching element (Q4) in an off state from the start of one switching period until a delay time required for detecting a current flowing through the reactor (L1).

[0075] This makes it possible to minimize the period during which the boosting operation is disabled.

[0076] [Item 3] The DC / DC converter (10) according to Item 1, wherein, when a lower side of an upper and lower range of the voltage-down reference signal is equal to or less than zero and an upper side of an upper and lower range of the voltage-boost reference signal is equal to or greater than zero at a start of one switching period, the control unit (20) maintains the fourth switching element (Q4) in an off state from the start of one switching period until the upper side of the upper and lower range of the voltage-boost reference signal falls below zero.

[0077] This makes it possible to more reliably prevent switching to the step-up / step-down operation.

[0078] [Item 4] The DC / DC converter (10) according to any one of Items 1 to 3, wherein the control unit (20) sets the amplitude of the sawtooth wave of the voltage-boosting reference signal and the amplitude of the sawtooth wave of the voltage-bucking reference signal to different values.

[0079] This allows the width of the overlap region to be adjusted arbitrarily.

[0080] REFERENCE SIGNS LIST 1 DC power supply 2 Load 10 Step-up / step-down DC / DC converter 20 Control unit 21 Error amplifier 22 Step-up side comparator 23 Step-down side comparator 24 Control logic circuit 25 Step-down side adder 26 Step-up side adder 27 Step-down side comparator 28 Step-up side comparator 29 Control logic circuit Bdc DC bus L1 Reactor Q1-Q4 Switching elements D1-D4 Diodes C1-C2 Capacitors dr1-dr4 Drive circuit A1 Current sensor V1 Voltage sensor

Claims

1. A power supply device comprising: a first arm including a first switching element and one of a second switching element and a second rectifier element, wherein the first switching element is connected in series to the one of the second switching element and the second rectifier element at a first connection point, and the first arm is connected in parallel to a DC power source; a second arm including a third switching element and one of a third rectifier element and a fourth switching element, wherein the one of the third switching element and the third rectifier element is connected in series to the fourth switching element at a second connection point, and the second arm is connected in parallel to a DC bus; a reactor connected to the first connection point of the first arm and the second connection point of the second arm; and a control unit that controls the first switching element, the second switching element, the third switching element, and the fourth switching element, or controls the first switching element and the fourth switching element, wherein the control unit generates a sawtooth-wave boost reference signal obtained by adding slope compensation to an error signal corresponding to a difference between an output voltage or an output current to the DC bus and a reference value, a step-down sawtooth wave obtained by shifting the step-up reference signal upward, the lower side of which has a certain overlap region with the upper side of the step-up sawtooth wave, is added to the error signal to generate a step-down reference signal having a sawtooth waveform; at the start of one switching period, if a current detection value obtained by detecting a current flowing through the reactor is within an upper or lower range of the step-down reference signal, the first switching element is turned on, and thereafter, if the current detection value matches the step-down reference signal, the first switching element is turned off; at the start of one switching period, if the current detection value is within an upper or lower range of the step-up reference signal, the fourth switching element is turned on, and thereafter, if the current detection value matches the step-up reference signal, the fourth switching element is turned off;maintains the fourth switching element in an off state for a predetermined period from the start of one switching period when, at the start of one switching period, a lower side of an upper and lower range of the voltage step-down reference signal is equal to or less than zero and an upper side of an upper and lower range of the voltage step-up reference signal is equal to or greater than zero.

2. The DC / DC converter as described in claim 1, characterized in that, when, at the start of one switching period, the lower end of the upper and lower range of the reference signal for step-down is equal to or less than zero and the upper end of the upper and lower range of the reference signal for step-up is equal to or greater than zero, the control unit maintains the fourth switching element in an off state from the start of one switching period for a delay time required for detecting the current flowing through the reactor.

3. The DC / DC converter as described in claim 1, characterized in that, when, at the start of one switching period, the lower side of the upper and lower range of the voltage step-down reference signal is below zero and the upper side of the upper and lower range of the voltage step-up reference signal is above zero, the control unit maintains the fourth switching element in an off state from the start of one switching period until the upper side of the upper and lower range of the voltage step-up reference signal falls below zero.

4. The DC / DC converter according to claim 1, wherein the control unit sets the amplitude of the sawtooth wave of the voltage step-up reference signal and the amplitude of the sawtooth wave of the voltage step-down reference signal to different values.

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