Electronic device and method for manufacturing electronic device

Abstract

The present invention improves bonding strength between chips without an accompanying increase in the planar size of the chips.　This electronic device comprises: a first chip to which a first bonding region is provided and in which a first recess is formed in a portion of the first bonding region; and a second chip which is bonded to the first chip with a second bonding region facing the first bonding region. The first recess may be disposed as discrete recesses on the periphery of the first chip. The first recess may be a continuous groove formed on the periphery of the first chip. The second chip may comprise a second recess formed in a portion of the second bonding region. The second chip may comprise a device region located inward of the second bonding region.

Description

Electronic device and method for manufacturing the same

[0001] The present technology relates to an electronic device and a method for manufacturing the electronic device, and more particularly to an electronic device having a recessed portion in a bonding region and a method for manufacturing the electronic device.

[0002] As the planar size of the chips to be bonded together decreases, it becomes more difficult to ensure the bonding strength between the chips. For example, in order to improve the adhesion to the package that houses the solid-state image sensor, a configuration has been proposed in which the bonding surface of the cover glass installed in the package that houses the solid-state image sensor is rougher than the optically effective surface (see, for example, Patent Document 1).

[0003] JP 2015-211190 A

[0004] However, in the above-mentioned conventional technology, when the planar size of the chips to be bonded together is reduced, the planar size of the bonding surface also decreases, which may make it difficult to ensure the bonding strength between the chips.

[0005] This technology was developed in light of these circumstances, and aims to improve the bonding strength between chips without increasing the planar size of the chips.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an electronic device including a first chip having a first bonding region and a first recess formed in a part of the first bonding region, and a second chip bonded to the first chip via a second bonding region facing the first bonding region, thereby providing an effect of suppressing conduction of heat generated around the first chip at the position of the first recess.

[0007] In the first aspect, the first recesses may be arranged discretely around the periphery of the first chip, thereby providing an effect of reducing thermal conductivity around the chip.

[0008] In the first aspect, the first recess may be a groove formed continuously around the periphery of the first chip, thereby reducing thermal conductivity around the entire periphery of the chip.

[0009] The first side surface may further include an adhesive layer interposed between the first chip and the second chip, thereby enabling a device to be formed at a position higher than the first bonding region and bonding the first chip to the second chip.

[0010] The first side surface may further include a hard layer formed on the surface of the adhesive layer in a position corresponding to the opening of the first recess, thereby preventing the adhesive layer from entering the first recess.

[0011] In the first aspect, the first chip and the second chip may be directly bonded to each other, thereby achieving the effect of bonding the first chip and the second chip without an adhesive layer therebetween.

[0012] The first side surface may further include a light-shielding film formed on the inner surface of the first recess, thereby suppressing the intrusion of light from the periphery of the chip into the inside.

[0013] In the first aspect, the pressure in the first recess may be lower than atmospheric pressure, thereby increasing the bonding strength between the first chip and the second chip.

[0014] The first side surface may further include a gas sealed in the first recess, thereby providing an effect of adjusting the optical characteristics around the chip.

[0015] In the first aspect, a transparent substrate may be used for the first chip and a semiconductor substrate may be used for the second chip, whereby the second chip is sealed by the first chip, light is incident on the second chip through the first chip, and heat conduction is suppressed at the position of the recess formed in the transparent substrate.

[0016] In addition, in the first aspect, a filter layer may be further provided on the first chip, whereby a specific wavelength band is extracted by the filter layer and made incident on the second chip.

[0017] The first side surface may further include a cavity formed inside the second bonding region, thereby achieving the effect of thinning the device region formed inside the first bonding region while ensuring the film thickness of the first bonding region.

[0018] In the first aspect, the second chip may include a second recess formed in a part of the second bonding region, thereby suppressing conduction of heat generated around the second chip at the position of the second recess.

[0019] In the first aspect, the second chip may include a device region located inside the first junction region, thereby reducing the effect of heat generated around the first chip while forming a device on the first chip.

[0020] In a first aspect, the second chip may include a third chip having a first wiring layer formed on a first semiconductor substrate, a fourth chip having a second wiring layer formed on a second semiconductor substrate and stacked on the third chip so that the first wiring layer and the second wiring layer face each other, and a through electrode that penetrates the first semiconductor substrate and is connected to the first wiring layer, thereby suppressing conduction of heat generated around the first chip at the position of the first recess and allowing an electrode to be drawn out from the opposite side of the second junction region.

[0021] In the first aspect, the second recess may be formed in the first semiconductor substrate so as to penetrate the fourth chip and the first wiring layer, thereby suppressing conduction of heat generated around the first chip and the second chip at the positions of the first recess and the second recess.

[0022] In the first aspect, the through electrode may be provided at a position different from a horizontal position of the second recess, thereby providing an effect that the second recess and the through electrode are formed in the first semiconductor substrate.

[0023] In a first aspect, the second chip may include a third chip having a first wiring layer formed on a first semiconductor substrate, a fourth chip having a second wiring layer formed on a second semiconductor substrate and stacked on the third chip such that the first wiring layer and the second wiring layer face each other, and a through electrode that penetrates the first semiconductor substrate and is connected to the first wiring layer, the through electrode being formed to at least partially overlap the first recess, thereby suppressing an increase in the area of ​​the second bonding region and suppressing conduction of heat generated around the first chip at the position of the first recess, and providing the effect of leading an electrode from the opposite side of the second bonding region.

[0024] A second aspect of the present invention is an electronic device including an optical chip provided with an optical system and a sensor chip provided with a sensor element, the optical chip and the sensor chip being bonded together via a bonding surface having a plurality of surfaces, thereby increasing the bonding area of ​​the bonding surface between the optical chip and the sensor chip.

[0025] In addition, in a second aspect, the optical chip may include a transparent substrate laminated on the sensor chip, and a groove may be provided between the sensor chip and the transparent substrate, continuously extending from a first end to a second end of the laminated structure of the sensor chip and the transparent substrate, thereby ensuring continuity of the path leading to the end of the laminated chip between the sensor chip and the transparent substrate and increasing the bonding area between the sensor chip and the transparent substrate.

[0026] In the second aspect, the groove may be provided in the transparent substrate, thereby ensuring the continuity of the groove provided in the transparent substrate and increasing the bonding area between the sensor chip and the transparent substrate.

[0027] In addition, in a second aspect, the optical chip and the sensor chip may further include a transparent resin layer that bonds the optical chip and the sensor chip, and an intermediate resin layer that is provided between the transparent substrate and the transparent resin layer or between the transparent resin layer and the sensor chip, thereby enabling the transparent resin to flow along grooves provided in the intermediate resin layer and increasing the bonding area of ​​the transparent resin layer.

[0028] In the second aspect, the refractive index of the transparent resin layer and the refractive index of the intermediate resin layer may be equal to each other, thereby providing an effect that the grooves are disposed over the effective pixel area of ​​the sensor chip without degrading image quality.

[0029] In a second aspect, the groove may be positioned so as to cross the wafer before the laminated chips of the sensor chip and the transparent substrate are solidified, thereby ensuring a flow path for the transparent resin to reach the edge of the laminated wafer and increasing the bonding area of ​​the transparent resin layer.

[0030] In the second aspect, one or more grooves may be provided in the laminated chip of the sensor chip and the transparent substrate, thereby improving the bonding strength between the sensor chip and the transparent substrate.

[0031] In the second aspect, the grooves may be disposed on the effective pixel region or the peripheral region of the sensor chip, or on both the effective pixel region and the peripheral region, thereby expanding the area in which grooves can be disposed.

[0032] In the second aspect, the depth of the groove may be equal to or less than the thickness of the transparent resin layer, thereby suppressing voids from remaining in the groove.

[0033] In a second aspect, the optical chip may be packaged based on wafer level optics (WLO), and the sensor chip may be packaged based on wafer level chip size package (WLCSP), thereby miniaturizing the sensor chip and the optical chip while suppressing a decrease in bonding strength between the sensor chip and the optical chip.

[0034] In the second aspect, the optical system may include a lens, thereby providing the effect of miniaturizing the optical chip and disposing the lens on the sensor chip.

[0035] In the second aspect, the optical system may include a laminated structure of a plurality of lens-equipped substrates, thereby providing the effect of arranging a plurality of lenses on the sensor chip while miniaturizing the optical chip.

[0036] In addition, in the second aspect, the plurality of lens-equipped substrates may include lenses and substrates on which the lenses are formed, and the lenses and the substrates may be made of the same or different materials, thereby improving the variety of lenses that can be arranged on the sensor chip.

[0037] In the second aspect, the optical system may include at least one of a diaphragm, a light-shielding film, a spacer, and an optical filter, thereby diversifying the functions of the optical system while suppressing an increase in the chip size of the optical chip.

[0038] In addition, in the second aspect, a bonding layer that bonds the optical chip and the sensor chip may be further provided, whereby the optical chip and the sensor chip are bonded together by interposing the bonding layer therebetween.

[0039] In the second aspect, the bonding layer may be made of one or more materials, which brings about the effect of adjusting the optical characteristics while suppressing a decrease in bonding strength.

[0040] In the second aspect, the bonding surface may include at least one of a recess, a protrusion, and a rough surface, thereby increasing the bonding area of ​​the bonding surface between the sensor chip and the optical chip.

[0041] In the second aspect, at least one of the recessed portion, the protruding portion, and the roughened surface may be located on the sensor surface of the sensor chip, thereby reducing restrictions on the arrangement positions of the recessed portion, the protruding portion, and the roughened surface.

[0042] In the second aspect, the bonding surface having the plurality of surfaces may be provided on at least one of the optical chip and the sensor chip, thereby alleviating restrictions on the arrangement positions of the plurality of surfaces and increasing the bonding area of ​​the bonding surface between the sensor chip and the optical chip.

[0043] In the second aspect, the sensor element may be a photoelectric conversion element, thereby providing an effect that the sensor element can be used as an imaging element.

[0044] In addition, in the second aspect, the sensor chip may include a semiconductor substrate on which the sensor element is formed, and a transparent encapsulation substrate bonded to the semiconductor substrate, thereby suppressing an increase in chip size while encapsulating the sensor element.

[0045] In a second aspect, the optical chip may include a transparent support substrate that supports the optical system, and the bonding surface having the plurality of surfaces may be provided on at least one of the transparent sealing substrate and the transparent support substrate, thereby improving the bonding strength between the sensor chip and the optical chip without affecting the optical characteristics of the optical system.

[0046] In the second aspect, the plurality of surfaces may include surfaces having different wettability, thereby providing an effect of controlling the bondability of the bonding surfaces between the optical chip and the sensor chip.

[0047] In a second aspect, the optical chip may include a transparent substrate laminated on the sensor chip via a transparent resin layer, the transparent substrate including an opposing region facing the sensor region of the sensor chip and an adjacent region adjacent to the opposing region, the opposing region having a higher wettability than the adjacent region, thereby achieving the effect of expelling voids generated in the transparent resin layer when the sensor chip and the transparent substrate are bonded from above the sensor region.

[0048] In the second aspect, the facing region may include a film-formed layer, a surface-modified layer, or an ion-implanted layer having higher wettability than the surface of the adjacent region, thereby improving the wettability of the facing region while ensuring the transparency of the facing region of the transparent substrate.

[0049] In the second aspect, the adjacent region may include a film-formed layer, a surface-modified layer, an ion-implanted layer, or a roughened surface layer having a lower wettability than the surface of the facing region, thereby increasing the wettability of the facing region relative to the adjacent region without reducing the transparency of the facing region of the transparent substrate.

[0050] In a second aspect, the sensor chip may include a sensor region and an adjacent region adjacent to the sensor region, and the wettability of the sensor region may be higher than the wettability of the adjacent region, thereby achieving the effect of expelling voids that occur in the transparent resin layer when the sensor chip and the transparent substrate are bonded to the periphery of the sensor region.

[0051] In a second aspect, the sensor region may include a film-formed layer, a surface-modified layer, or an ion-implanted layer having higher wettability than the surface of the adjacent region, thereby improving the wettability of the sensor region while minimizing any adverse effects on the optical properties of the sensor region.

[0052] In the second aspect, the adjacent region may include a film-formed layer, a surface-modified layer, an ion-implanted layer, or a roughened surface layer that has a lower wettability than the surface of the sensor region, thereby increasing the wettability of the sensor region relative to the adjacent region without affecting the optical properties of the sensor region.

[0053] A third aspect of the present invention is a method for manufacturing an electronic device, comprising the steps of: forming a first recess in a first bonding region provided for each partitioned region of a first wafer; bonding a second wafer to the first wafer through a second bonding region provided at a position opposite to the first bonding region; and solidifying the laminated structure formed by bonding the first and second wafers into individual partitioned regions, thereby suppressing the conduction of heat generated when cutting the laminated wafers of the first and second wafers at the positions of the first recess.

[0054] In addition, in the third aspect, the second wafer may be bonded to the first wafer under reduced pressure or in an ambient gas, thereby making the pressure in the first recess lower than atmospheric pressure or sealing a gas in the first recess.

[0055] 10A and 10B are diagrams illustrating a configuration example of an electronic device according to a first embodiment; FIG. 11A is a first diagram illustrating an example of a manufacturing method of an electronic device according to the first embodiment; FIG. 12B is a second diagram illustrating an example of a manufacturing method of an electronic device according to the first embodiment; FIG. 13B is a third diagram illustrating an example of a manufacturing method of an electronic device according to the first embodiment; FIG. 14A is a diagram illustrating a configuration example of an electronic device according to a second embodiment; FIG. 15A is a diagram illustrating a configuration example of an electronic device according to a third embodiment; FIG. 16A is a diagram illustrating a configuration example of an electronic device according to a fourth embodiment; FIG. 17A is a diagram illustrating a configuration example of an electronic device according to a fifth embodiment; FIG. 18A is a diagram illustrating a configuration example of an electronic device according to a sixth embodiment; FIG. 19A is a diagram illustrating a configuration example of an electronic device according to a seventh embodiment; FIG. 20A is a diagram illustrating a configuration example of an electronic device according to an eighth embodiment; FIG. 21A is a diagram illustrating a configuration example of an electronic device according to a ninth embodiment; FIG. 21B is a diagram illustrating a configuration example of an electronic device according to a tenth embodiment; FIG. 22A is a diagram illustrating a configuration example of an electronic device according to an eleventh embodiment; FIG. 22B is a diagram illustrating a configuration example of an electronic device according to a twelfth embodiment; FIG. 23A is a diagram illustrating a configuration example of an electronic device according to a thirteenth embodiment; FIG. 24A is a diagram illustrating a configuration example of an electronic device according to a fourteenth embodiment; FIG. 25A is a plan view illustrating a configuration example of an electronic device in a wafer state according to the fourteenth embodiment; and FIG. 26A is a cross-sectional view illustrating an example of a manufacturing method of an electronic device according to the fourteenth embodiment. 16 is a cross-sectional view showing another example of a method for manufacturing an electronic device according to the fourteenth embodiment. FIG. 17 is a cross-sectional view showing an example of a configuration of an electronic device according to the fifteenth embodiment. FIG. 18 is a cross-sectional view showing an example of a configuration of an electronic device according to the sixteenth embodiment. FIG. 19 is a cross-sectional view showing an example of a configuration of an electronic device according to the seventeenth embodiment. FIG. 20 is a cross-sectional view showing another example of the configuration of an electronic device according to the seventeenth embodiment. FIG. 21 is a plan view showing an example of a configuration of an electronic device according to the eighteenth embodiment. FIG. 22 is a plan view showing another example of the configuration of an electronic device according to the eighteenth embodiment. FIG. 23 is a cross-sectional view showing yet another example of the configuration of an electronic device according to the eighteenth embodiment. FIG. 24 is a cross-sectional view showing an example of a configuration of an electronic device according to the nineteenth embodiment. FIG. 25 is a cross-sectional view showing an example of a method for manufacturing an electronic device according to the nineteenth embodiment.20. A cross-sectional view showing an example of a method for manufacturing an electronic device according to a nineteenth embodiment. A cross-sectional view showing an example of a method for manufacturing an electronic device according to a nineteenth embodiment. A cross-sectional view showing another example of the configuration of an electronic device according to a nineteenth embodiment. A cross-sectional view showing yet ... plan view showing an example of the configuration of an electronic device according to a twentieth embodiment. A plan view showing yet another example of the configuration of an electronic device according to a twentieth embodiment. A plan view showing yet another example of the configuration of an electronic device according to a twentieth embodiment. A plan view showing yet another example of the configuration of an electronic device according to a twentieth embodiment. A plan view showing yet another example of the configuration of an electronic device according to a twentieth embodiment. A cross-sectional view showing yet another example of the configuration of an electronic device according to a twentieth embodiment. A cross-sectional view showing yet another example of the configuration of an electronic device according to a twentieth embodiment. 22. A cross-sectional view showing a configuration example of an electronic device according to a twenty-second embodiment. 23. A cross-sectional view showing a configuration example of an electronic device according to a twenty-third embodiment. 24. A cross-sectional view showing a configuration example of an electronic device according to a twenty-fifth embodiment. 26. A cross-sectional view showing a configuration example of an electronic device according to a twenty-sixth embodiment. 27. A cross-sectional view showing a configuration example of an electronic device according to a twenty-eighth embodiment. 28. A cross-sectional view showing an example of a method for manufacturing an electronic device according to a twenty-eighth embodiment. 29. A cross-sectional view showing an example of a method for manufacturing an electronic device according to a twenty-eighth embodiment. 30. A cross-sectional view showing another example of the method for manufacturing an electronic device according to a twenty-eighth embodiment.20 is a cross-sectional view showing yet another example of a method for manufacturing an electronic device according to the twenty-eighth embodiment. 21 is a plan view showing yet another example of a configuration of an electronic device according to the twenty-eighth embodiment. 22 is a cross-sectional view showing yet another example of a configuration of an electronic device according to the twenty-ninth embodiment. 23 is a cross-sectional view showing yet another example of a configuration of an electronic device according to the twenty-ninth embodiment. 24 is a cross-sectional view showing yet another example of a configuration of an electronic device according to the twenty-ninth embodiment. 25 is a plan view showing yet another example of a configuration of an electronic device according to the twenty-ninth embodiment. 26 is a cross-sectional view showing yet another example of a configuration of an electronic device according to the twenty-ninth embodiment. 27 is a cross-sectional view showing yet another example of a configuration of an electronic device according to the twenty-ninth embodiment. 28 is a cross-sectional view showing yet another example of a configuration of an electronic device according to the thirty-first embodiment. 29 is a cross-sectional view showing yet another example of a configuration of an electronic device according to the thirty-first embodiment. 29 is a cross-sectional view showing yet another example of a configuration of a recess of an electronic device according to the thirty-second embodiment. 29 is a cross-sectional view showing an example of a method for manufacturing a recess of an electronic device according to the thirty-second embodiment. 29 is a cross-sectional view showing yet another example of a configuration of a recess of an electronic device according to the thirty-second embodiment. 29 is a cross-sectional view showing yet another example of a configuration of a recess of an electronic device according to the thirty-third embodiment. 33. A cross-sectional view showing another configuration example of a recess in an electronic device according to the thirty-third embodiment. A diagram showing a configuration example of a recess in an electronic device according to the thirty-fourth embodiment. A cross-sectional view showing an example of a method for manufacturing a recess in an electronic device according to the thirty-fourth embodiment. A cross-sectional view showing an example of a method for manufacturing a recess in an electronic device according to the thirty-fourth embodiment. A cross-sectional view showing an example of a method for manufacturing a recess in an electronic device according to the thirty-fifth embodiment. A cross-sectional view showing an example of a method for manufacturing a recess in an electronic device according to the thirty-fifth embodiment. A cross-sectional view showing an example of a configuration example of a recess in an electronic device according to the thirty-sixth embodiment. A cross-sectional view showing an example of a configuration example of a recess in an electronic device according to the thirty-seventh embodiment. A cross-sectional view showing an example of a method for manufacturing a recess in an electronic device according to the thirty-seventh embodiment.37. A cross-sectional view showing an example of a method for manufacturing a recess in an electronic device according to a thirty-seventh embodiment. A diagram showing an example of a configuration of a recess in an electronic device according to a thirty-eighth embodiment. A cross-sectional view showing an example of a method for manufacturing ... diagram showing an example of a configuration of an electronic device according to a thirty-ninth embodiment. A cross-sectional view showing an example of a method for manufacturing an electronic device according to a thirty-ninth embodiment. A cross-sectional view showing an example of a method for manufacturing an electronic device according to a thirty-ninth embodiment. A perspective view showing an example of a configuration of a recess in an electronic device according to a thirty-ninth embodiment. A plan view showing an example of a configuration of an electronic device according to a thirty-ninth embodiment. A diagram showing an example of a configuration of an electronic device according to a fortieth embodiment. A diagram showing another example of a configuration of an electronic device according to a fortieth embodiment. A diagram showing yet another example of a configuration of an electronic device according to a fortieth embodiment. A cross-sectional view showing an example of a method for manufacturing an electronic device according to a fortieth embodiment. A cross-sectional view showing an example of a method for manufacturing an electronic device according to a fortieth embodiment. A cross-sectional view showing an example of a method for manufacturing an electronic device according to a fortieth embodiment. A cross-sectional view showing an example of a configuration of an electronic device according to a fortieth embodiment. A cross-sectional view showing an example of a method for manufacturing an electronic device according to a fortieth embodiment. 42. A cross-sectional view showing an example of a method for manufacturing an electronic device according to the forty-second embodiment. 43. A cross-sectional view showing an example of a configuration of an electronic device according to the forty-third embodiment. 44. A cross-sectional view showing an example of a method for manufacturing an electronic device according to the forty-fourth embodiment. 44. A cross-sectional view showing an example of a method for manufacturing an electronic device according to the forty-fourth embodiment. 45. A cross-sectional view showing an example of a method for manufacturing an electronic device according to the forty-fifth embodiment. 45. A cross-sectional view showing an example of a method for manufacturing an electronic device according to the forty-fifth embodiment. 46. A cross-sectional view showing an example of a configuration of an electronic device according to the forty-sixth embodiment. 46. A cross-sectional view showing an example of a method for manufacturing an electronic device according to the forty-fifth embodiment.46. ​​A cross-sectional view showing an example of a manufacturing method for an electronic device according to a forty-sixth embodiment. A diagram showing an example of a configuration of an electronic device according to a forty-seventh embodiment. A cross-sectional view showing an example of a manufacturing method for an electronic device according to a forty-seventh embodiment. A cross-sectional view showing an example of a manufacturing method for an electronic device according to a forty-seventh embodiment. A cross-sectional view showing an example of a configuration of a jaggy of an electronic device according to a forty-seventh embodiment. A diagram showing an example of a configuration of an electronic device according to a forty-eighth embodiment. A cross-sectional view showing an example of a manufacturing method for an electronic device according to a forty-eighth embodiment. A cross-sectional view showing an example of a manufacturing method for an electronic device according to a forty-eighth embodiment. A cross-sectional view showing an example of a manufacturing method for an electronic device according to a forty-ninth embodiment. A cross-sectional view showing an example of a configuration of an electronic device according to a fiftieth ...

[0056] Modes for carrying out the present technology (hereinafter referred to as embodiments) will be described below. The descriptions will be made in the following order: 1. First embodiment (an example in which a recess is provided on the bonding surface of a semiconductor chip and a bonding surface of a transparent substrate, respectively, and the transparent substrate is bonded to the semiconductor chip via an adhesive layer having a through-hole provided therein) 2. Second embodiment (an example in which a recess is provided on the bonding surface of a transparent substrate, and the transparent substrate is bonded to the semiconductor chip via an adhesive layer) 3. Third embodiment (an example in which a recess is provided on the bonding surface of a semiconductor chip, and the transparent substrate is bonded to the semiconductor chip via an adhesive layer) 4. Fourth embodiment (an example in which a recess is provided on the bonding surface of a semiconductor chip and a bonding surface of a transparent substrate, respectively, and the transparent substrate is bonded to the semiconductor chip via an adhesive layer) 5. Fifth embodiment (an example in which a recess is provided on the bonding surface of a transparent substrate, and the transparent substrate is bonded to the semiconductor chip via an adhesive layer having a hard layer provided on its surface) 6. 6. Sixth embodiment (an example in which a recess is provided on each of the bonding surfaces of a semiconductor chip and a transparent substrate, the transparent substrate is bonded to the semiconductor chip via an adhesive layer having through holes, and a filter layer is formed on the surface of the transparent substrate) 7. Seventh embodiment (an example in which a recess is provided on each of the bonding surfaces of a semiconductor chip having a cavity and a transparent substrate, and the transparent substrate is bonded to the semiconductor chip via an adhesive layer) 8. Eighth embodiment (an example in which a recess is provided on each of the bonding surfaces of a semiconductor chip having a cavity and a transparent substrate, and the transparent substrate is directly bonded to the semiconductor chip) 9. Ninth embodiment (an example in which a recess is provided on each of the bonding surfaces of a semiconductor chip and a transparent substrate, a light-shielding film is provided on the inner surface of the recess on the bonding surface of the transparent substrate, and the transparent substrate is bonded to the semiconductor chip via an adhesive layer having through holes) 10. Tenth embodiment (an example in which a through electrode is provided at a position different from the horizontal position of the recess provided on each of the bonding surfaces of a semiconductor chip and a transparent substrate) 11. Eleventh embodiment (an example in which a through electrode is provided at a position that coincides with the horizontal position of a recess provided on the bonding surface of a transparent substrate) 12. Twelfth embodiment (an example in which a recess is provided on each bonding surface of each semiconductor chip to be stacked on top of each other, and these semiconductor chips are directly bonded together)13. Thirteenth embodiment (an example in which a first semiconductor chip is directly bonded to a second semiconductor chip such that the horizontal positions of recesses formed on the bonding surface of the first semiconductor chip and the horizontal positions of through electrodes formed on the second semiconductor chip are aligned with each other) 14. Fourteenth embodiment (an example in which a groove is provided so as to traverse a transparent substrate bonded to a sensor chip via a transparent resin layer) 15. Fifteenth embodiment (an example in which a rectangular groove is provided so as to traverse a transparent substrate bonded to a sensor chip via a transparent resin layer) 16. Sixteenth embodiment (an example in which a fine groove is provided on the surface of a groove provided so as to traverse a transparent substrate bonded to a sensor chip via a transparent resin layer) 17. Seventeenth embodiment (an example in which a groove is provided so as to traverse an intermediate resin layer intervening in the bonding between a sensor chip and a transparent substrate via a transparent resin layer) 18. Eighteenth embodiment (an example in which the number or orientation of grooves provided so as to traverse a transparent substrate bonded to a sensor chip via a transparent resin layer is varied) 19. 19th embodiment (an example in which a sensor chip and an optical chip having a bonding surface formed with a plurality of surfaces are bonded via a bonding layer, and through electrodes are formed on the sensor chip) 20. 20th embodiment (an example in which the number, size, shape, or orientation of concave or convex portions provided on the bonding surface are made different) 21. 21st embodiment (an example in which a sensor chip and an optical chip having a bonding surface formed with a plurality of surfaces are bonded via a bonding layer, and side contacts are formed on the sensor chip) 22. 22nd embodiment (an example in which a sensor chip and an optical chip are directly bonded via a bonding surface having a plurality of surfaces) 23. 23rd embodiment (an example in which a recess is provided on each of the bonding surfaces of the sensor chip and the optical chip, and the optical chip is bonded to the sensor chip via a bonding layer in which a through hole is provided) 24. 24th embodiment (an example in which a recess is provided on the bonding surface of the transparent sealing substrate of the sensor chip) 25. 25th embodiment (an example in which a recess is provided on the support surface of the transparent support substrate of the optical chip) 26. 26. Twenty-sixth embodiment (an example in which the chip size of the optical chip is smaller than the chip size of the sensor chip) 27. Twenty-seventh embodiment (an example in which the chip size of the optical chip is smaller than the chip size of the sensor chip, and the bonding layer protrudes onto the side surface of the optical chip)28. 28th embodiment (an example in which, in a transparent substrate bonded to a sensor chip via a transparent resin, the wettability of an opposing region facing the sensor region of the sensor chip is higher than the wettability of an adjacent region adjacent to the opposing region) 29. 29th embodiment (an example in which, in a transparent substrate bonded to a sensor chip via a transparent resin, the wettability of an adjacent region adjacent to the opposing region facing the sensor region of the sensor chip is lower than the wettability of the opposing region) 30. 30th embodiment (an example in which, in a sensor chip bonded to a transparent substrate via a transparent resin, the wettability of the sensor region of the sensor chip is higher than the wettability of an adjacent region adjacent to the sensor region) 31. 31st embodiment (an example in which, in a sensor chip in which the sensor region is sealed with a transparent resin, the wettability of the sensor region of the sensor chip is higher than the wettability of an adjacent region adjacent to the sensor region) 32. 32nd embodiment (an example in which a film is formed on the inner surface of a recess provided on the bonding surface of a transparent substrate) 33. 33rd embodiment (an example in which concaves and convexes are formed on the inner surface of a recess provided on the bonding surface of a transparent substrate) 34. 34th embodiment (an example in which a film formed on the inner surface of a recess provided on the bonding surface of a transparent substrate is extended outside the bottom surface of the recess) 35. 35th embodiment (an example in which a film formed on the inner surface of a recess provided on the bonding surface of a transparent substrate is extended outside the opening of the recess) 36. 36th embodiment (an example in which a recess is provided on the bonding surface of a transparent substrate, and a buried layer embedded outside the recess is extended outside the bottom surface of the recess) 37. 37th embodiment (an example in which a recess is provided on the bonding surface of a transparent substrate, and a buried layer embedded outside the recess is extended outside the opening of the recess) 38. 38th embodiment (an example in which a lid is provided to close the bottom surface of a recess formed on the bonding surface of a transparent substrate) 39. 39th embodiment (an example in which a tapered recess is provided on the bonding surface of a transparent substrate) 40. 40th embodiment (an example in which recesses arranged in a shifted position are provided on the bonding surface of a transparent substrate) 41. 41. EMBODIMENT 41 (an example in which recesses provided on the bonding surface of the semiconductor chip and the bonding surface of the transparent substrate are arranged so as not to overlap) 42. EMBODIMENT 42 (an example in which recesses and through holes arranged on the bonding surface of the transparent substrate are alternately arranged) 43. EMBODIMENT 43 (an example in which recesses are arranged in a multiple-circumferential manner on the bonding surface of the transparent substrate)44. Forty-fourth embodiment (an example in which a recess is provided on the bonding surface of a transparent substrate, and a buried layer is buried outside the recess) 45. Forty-fifth embodiment (an example in which a recess is provided on the bonding surface of a transparent substrate, and fine grooves are provided on both sides of the recess) 46. Forty-sixth embodiment (an example in which a recess with a widened tip is provided on the bonding surface of a transparent substrate) 47. Forty-seventh embodiment (an example in which a recess is provided on the bonding surface of a transparent substrate, and jaggies are provided inside the inner surface of the recess) 48. Forty-eighth embodiment (an example in which a recess is provided on the bonding surface of a transparent substrate, and a moth-eye structure is provided inside the recess) 49. Forty-ninth embodiment (an example in which a recess is provided on the bonding surface of a transparent substrate, and a sealing layer is formed from the side surface of the semiconductor chip to the side surface of the transparent substrate, via the side surface of the adhesive layer) 50. Fiftieth embodiment (an example in which a recess is provided on the bonding surface of a transparent substrate, and a sealing layer is formed from the side surface of the semiconductor chip to the side surface of the transparent substrate, via the side surface of the adhesive layer, to a position higher than the recess) 51. 51. Embodiment 51 (an example in which a recess is provided on the bonding surface of a transparent substrate, and a sealing layer is formed from the side surface of the semiconductor chip, via the side surface of the adhesive layer, to the side surface of the transparent substrate, and the sealing layer penetrates inward from the side surface of the adhesive layer) 52. Embodiment 52 (an example in which a recess is provided on the bonding surface of a transparent substrate, and a sealing layer is formed from the side surface of the semiconductor chip, via the side surface of the adhesive layer, to the side surface of the transparent substrate, and the sealing layer is also used as an underfill) 53. Embodiment 53 (an example in which a sealing layer is formed from the side surface of the semiconductor chip, via the side surface of the adhesive layer, to the side surface of the transparent substrate) 54. Embodiment 54 (an example in which a sealing layer is formed from the side surface of the semiconductor chip, via the side surface of the adhesive layer, to the side surface of the transparent substrate, and the sealing layer penetrates inward from the side surface of the adhesive layer) 55. Embodiment 55 (an example in which a sealing layer is formed from the side surface of the semiconductor chip, via the side surface of the adhesive layer, to the side surface of the transparent substrate, so as to cover the edge of the top surface of the transparent substrate) 56. Application to a moving body

[0057] 1. First Embodiment FIG. 1 is a diagram showing an example of the configuration of an electronic device according to a first embodiment. In the figure, "a" is a cross-sectional view showing the example of the configuration of an electronic device 100 cut vertically, "b" is a plan view showing the example of the configuration of the electronic device 100, and "c" is a plan view showing the example of the configuration of an electronic device 100'. In the figure, "a" is cut along line A1-A2 of "b" and "c" in the figure. In the drawings used in the following description, the scale and shape may differ from the actual structure to make each configuration easier to understand.

[0058] In the figure, the electronic device 100 includes a stacked chip P1. The stacked chip P1 includes a chip 101 and a transparent substrate 102. The transparent substrate 102 is stacked on the chip 101. At this time, the transparent substrate 102 is bonded to the chip 101 via an adhesive layer 103. Here, the transparent substrate 102 is divided into chips so that the chips are the same size as the chip 101. At this time, the positions of the horizontal edges of the transparent substrate 102 can be aligned with the positions of the horizontal edges of the chip 101. This allows the stacked chip P1 to form a wafer-level chip size package (WLCSP). The transparent substrate 102 is an example of a first chip as defined in the claims. The chip 101 is an example of a second chip as defined in the claims.

[0059] A semiconductor element, an optical element, or a MEMS (Micro Electro Mechanical Systems) may be formed on the chip 101. The substrate used for the chip 101 may be a semiconductor substrate, a dielectric substrate, or an organic substrate.

[0060] The optical element may be an image sensor such as a CCD (Charged Coupled Device) sensor, a CMOS (Complementary Metal-Oxide Semiconductor) sensor, or a SPAD (Single Photon Avalanche Diode) sensor. The light received by the image sensor may be visible light, near infrared light (NIR: Near Infrared), short wavelength infrared light (SWIR: Short Wavelength Infrared), ultraviolet light, or X-rays. The optical element may be a light receiving element such as a PD (Photo Diode), or a light emitting element such as an LD (Laser Diode), an LED (Light Emitting Diode), or a VCSEL (Vertical Cavity Surface Emitting Laser). The optical element may be an optical switch, a DMD (Digital Micromirror Device), or the like. The material used for the optical element may be a semiconductor such as Si, GaAs, or InGaAs, or LiNbO ３ , or may be a dielectric material such as glass or transparent resin.

[0061] The semiconductor element may include a transistor, a resistor, a capacitor, etc. The semiconductor element may form a memory, a processor, a signal processing circuit, a data processing circuit, or an interface circuit. The semiconductor element may form a hardware circuit such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). The material used for the semiconductor element may be Si, GaAs, SiC, GaN, InGaAsP, etc.

[0062] The transparent substrate 102 may be a glass substrate, a quartz substrate, or a transparent resin substrate such as an acrylic or polycarbonate substrate. The transparent substrate 102 is made of Al or Al2O3 in accordance with the wavelength detected by the optical element formed on the chip 101. ２ O ３ , CaF ２, MgF ２ Alternatively, LiF or the like may be used.

[0063] In the following description, a back-illuminated solid-state imaging element is formed on the chip 101. In this case, a CMOS sensor or a CCD sensor may be formed on the chip 101.

[0064] Here, the chip 101 is provided with a light-receiving region R0 and a junction region R1. The light-receiving region R0 has pixels and pixel transistors arranged in a matrix along the row and column directions. A photodiode can be formed in the pixel. The pixel transistor may include a reset transistor that resets the pixel, a selection transistor that selects the pixel, a transfer transistor that transfers charge accumulated in the pixel, and an amplifier transistor that forms a source follower between the pixel and the pixel.

[0065] The bonding region R1 is used to bond the chip 101 and the transparent substrate 102. At this time, the bonding strength of the chip 101 can be ensured via the bonding region R1. In a back-illuminated solid-state imaging element, the bonding region R1 is provided on the back side of the chip 101. A recess 111 is formed in the bonding region R1. The three-dimensional shape of the recess 111 may be a square prism, a cylinder, or a truncated cone. However, in order to uniformly distribute stress on the outer periphery of the recess 111, the three-dimensional shape of the recess 111 is preferably a cylinder or a truncated cone. The depth of the recess 111 can be set so as to prevent cracks from occurring in the chip 101.

[0066] A color filter 104 is formed for each pixel on the light receiving region R0. An on-chip lens 105 is formed for each pixel on the color filter 104. The material of the color filter 104 and the on-chip lens 105 is, for example, SiO ２The color filter 104 may be an insulating film such as SiN or SiCN, or a transparent resin such as acrylic or polycarbonate. The color filter 104 may contain a pigment. The color filter 104 may have, for example, a Bayer array or a Quad Bayer array. The color filter 104 may include an RGB filter, a complementary color filter, or a white filter.

[0067] Protruding electrodes 106 are formed on the surface side of the chip 101. The protruding electrodes 106 can be electrically connected to wiring formed on the surface side of the chip 101. The protruding electrodes 106 can be used as external connection terminals for connecting the chip 101 to a motherboard or the like. The protruding electrodes 106 may be, for example, ball electrodes such as solder balls, or pillar electrodes made of a conductor.

[0068] A bonding region R2 is provided on the transparent substrate 102. The bonding region R2 can be provided at a position opposite the bonding region R1. The bonding region R2 is used to bond the chip 101 and the transparent substrate 102. A recess 112 is formed in the bonding region R2. The three-dimensional shape of the recess 112 may be a rectangular prism, a cylinder, or a truncated cone. However, in order to uniformly distribute stress on the outer periphery of the recess 112, the three-dimensional shape of the recess 112 is preferably a cylinder or a truncated cone. The three-dimensional shape of the recess 112 may be the same as or different from the three-dimensional shape of the recess 111. The opening size of the recess 111 may be the same as or different from the opening size of the recess 112. Furthermore, the horizontal position of the recess 112 may be offset from the horizontal position of the recess 111. However, in order to suppress an increase in layout area when forming each of the recesses 111 and 112, it is desirable to make the horizontal position of the recess 112 coincide with the horizontal position of the recess 111. The depth of the recess 112 can be set so as to prevent cracks from occurring in the transparent substrate 102.

[0069] The adhesive layer 103 is positioned between the chip 101 and the transparent substrate 102. At this time, the positions of the horizontal ends of the adhesive layer 103 can be aligned with the positions of the horizontal ends of the chip 101. The adhesive layer 103 can be cured so as not to infiltrate into the recesses 111 and 112. A through-hole 113 is formed in the adhesive layer 103. The horizontal position of the through-hole 113 can be aligned with the horizontal position of the recess 111. The planar shape of the through-hole 113 can be aligned with the planar shape of the recess 111. The material of the adhesive layer 103 can be a transparent resin such as acrylic. At this time, the material of the adhesive layer 103 can be selected so as to ensure a refractive index difference between the adhesive layer 103 and the on-chip lens 105.

[0070] Here, in the electronic device 100, as shown in b in the figure, recesses 111 may be arranged discretely around the chip 101, and recesses 112 may be arranged discretely around the transparent substrate 102. By arranging the recesses 112 discretely around the transparent substrate 102, it is possible to reduce the thermal conductivity around the chip 101 while suppressing a decrease in the strength around the chip 101.

[0071] Alternatively, in the electronic device 100', as shown in c in the figure, recesses 111' may be continuously arranged around the chip 101, and recesses 112' may be continuously arranged around the transparent substrate 102. In this case, each of the recesses 111', 112' may be a groove. By continuously arranging the recesses 112' around the transparent substrate 102, the thermal conductivity around the chip 101 can be made uniform while reducing the thermal conductivity around the chip 101.

[0072] In the stacked chip P1, the recesses 111 and 112 and the through-hole 113 are hollowed. At this time, the pressure in the recesses 111 and 112 and the through-hole 113 can be made lower than atmospheric pressure. For example, the pressure in the recesses 111 and 112 and the through-hole 113 can be made lower than atmospheric pressure. －５ In this case, the components in the recesses 111, 112 and the through-hole 113 may be the same as or different from the components of the atmosphere. ３The gas to be filled in the recesses 111, 112 and the through-hole 113 can be selected appropriately depending on the application of the electronic device 100. In this case, the gas pressure in the recesses 111, 112 and the through-hole 113 is 1×10 －２ Here, the O 2 concentration in the recesses 111 and 112 and the through-hole 113 may be less than 0.05 Pa. ３ By filling the transparent substrate 102 with the adhesive layer 103, it is possible to absorb light with a wavelength of 300 nm. This makes it possible to suppress reflected light from the interface between the transparent substrate 102 and the adhesive layer 103, the surface of the chip 101, and the like, thereby reducing flare.

[0073] The dimensions of each part of the electronic device 100 can be set, for example, as follows: Planar size of the chip 101 and the transparent substrate 102: 1.0 × 1.0 mm Thickness of the chip 101: 85 μm Thickness of the transparent substrate 102: 300 μm Thickness of the adhesive layer 103: 50 μm Planar size of the light-receiving region R0: 700 × 700 μm Width of each of the bonding regions R1, R2: 150 μm Height of the protruding electrode 106: 150 μm Planar size of each of the recesses 111, 112: 50 × 50 μm Overall height of the recesses 111, 112 and the through-hole 113: 270 μm Horizontal distance between the recess 112 and the transparent substrate 102: 20 μm Horizontal distance between the recess 112 and the light-receiving region R0: 80 μm Width of each of the recesses 111′, 112′: 50 × 50 μm Total height of the recesses 111′, 112′ and the through-hole 113′: 270 μm

[0074] In this case, the adhesive strength between the chip 101 and the transparent substrate 102 when there are no recesses 111, 112 is 0.5 kgf. The adhesive strength between the chip 101 with 24 recesses 111, 112 formed therein and the transparent substrate 102 is 60.5 kgf. The adhesive strength between the chip 101' with recesses 111', 112' formed therein and the transparent substrate 102' is 182.4 kgf. However, the pressure inside each of the recesses 111, 112, 111', 112' is 1×10 －５ Pa. As a result, the strength magnification can be increased to 121 times by providing the recesses 111 and 112. The strength magnification can be increased to 365 times by providing the recesses 111' and 112'.

[0075] Furthermore, the thermal conductivity when the recesses 111 and 112 are a vacuum is 0.002 W / m·K, and the thermal conductivity when the recesses 111 and 112 are filled with air is 0.02 W / m·K. On the other hand, the thermal conductivity of the adhesive layer 103 is 0.2 W / m·K, the thermal conductivity of glass is 1.0 W / m·K, and the thermal conductivity of Si is 50 W / m·K. Therefore, by making the recesses 111 and 112 hollow, the thermal conductivity at the positions of the recesses 111 and 112 can be reduced.

[0076] 2 to 4 are diagrams showing an example of a method for manufacturing an electronic device according to the first embodiment.

[0077] 2A, partitioned regions 102R are provided on a transparent substrate wafer 102W. A transparent substrate 102 is cut out from each partitioned region 102R. Each partitioned region 102R is partitioned along a scribe line 102D. A bonding region R2 is provided in each partitioned region 102R.

[0078] 2b, a partitioned region 101R is provided on a semiconductor wafer 101W. At this time, the partitioned regions 101R and 102R can be overlapped with each other. A chip 101 is cut out from each partitioned region 101R. Each partitioned region 101R is partitioned along a scribe line 101D. A solid-state imaging element is formed in each partitioned region 101R. At this time, a light-receiving region R0 and a bonding region R1 are provided in each partitioned region 101R. Furthermore, a color filter 104 and an on-chip lens 105 are formed for each pixel in the light-receiving region R0. Furthermore, a wiring layer and a through electrode connected to the protruding electrode 106 are formed on the semiconductor wafer 101W.

[0079] 3A, a resist pattern 122 is formed on the transparent substrate wafer 102W by lithography. An opening 132 is formed in the resist pattern 122 for each partitioned region 102R. The opening 132 can be positioned above the formation position of the recess 112.

[0080] An adhesive layer 103 is also formed on the semiconductor wafer 101W. At this time, the adhesive layer 103 can be formed uniformly on the semiconductor wafer 101W so as to cover the on-chip lenses 105. The adhesive layer 103 may be formed by coating. Then, a resist pattern 121 is formed on the adhesive layer 103 based on lithography. An opening 131 is formed in the resist pattern 121 for each partitioned region 101R. The opening 131 can be positioned above the formation position of the recess 111.

[0081] Next, as shown in FIG. 3b, the transparent substrate wafer 102W is etched in the depth direction using the resist pattern 122 as an etching mask, to form recesses 112 in the transparent substrate wafer 102W for each partitioned region 102R.

[0082] Using the resist pattern 121 as an etching mask, the adhesive layer 103 and the semiconductor wafer 101W are etched in the depth direction to form through-holes 113 in the adhesive layer 103 and recesses 111 in the semiconductor wafer 101W for each partitioned region 101R.

[0083] Next, as shown in Figure 3c, the transparent substrate wafer 102W and the semiconductor wafer 101W are bonded together via the adhesive layer 103 so that the bonding regions R1 and R2 face each other, thereby forming the laminated wafer 100W. The adhesive layer 103 may be a thermosetting resin or an ultraviolet-curing resin. If the adhesive layer 103 is a thermosetting resin, the adhesive layer 103 can be cured by heat treatment. If the adhesive layer 103 is an ultraviolet-curing resin, the adhesive layer 103 can be cured by ultraviolet irradiation.

[0084] At this time, the horizontal positions of the recesses 111, 112 and the through-hole 113 may be aligned with each other. Furthermore, the scribe lines 101D, 102D may overlap each other. The bonding of the transparent substrate wafer 102W and the semiconductor wafer 101W may be performed under reduced pressure. At this time, the pressure inside the recesses 111, 112 and the through-hole 113 is set to 1×10 －５Alternatively, the bonding of the transparent substrate wafer 102W and the semiconductor wafer 101W may be performed in an atmospheric gas. The atmospheric gas may be, for example, O ３ At this time, the pressure in the recesses 111 and 112 and the through-hole 113 may be 1×10 －２ It may be set to be equal to or less than Pa.

[0085] 4A, the semiconductor wafer 101W below the laminated wafer 100W is thinned from the front surface side. The semiconductor wafer 101W may be thinned by chemical mechanical polishing (CMP) or by etch-back.

[0086] 4B, the transparent substrate wafer 102W on the upper layer of the laminated wafer 100W is thinned from the front surface side. The transparent substrate wafer 102W may be thinned by CMP or etch-back.

[0087] Next, as shown in FIG. 4c, protruding electrodes 106 are formed in each of the partitioned regions 101R on the front surface of the semiconductor wafer 101W below the laminated wafer 100W.

[0088] Next, as shown in FIG. 1A, the laminated wafer 100W is cut along the scribe lines 101D and 102D to cut out the laminated chip P1, in which the chip 101 and the transparent substrate 102 are stacked. The laminated wafer 100W may be cut using dicing or a laser cutter. When the laminated wafer 100W is cut, heat is generated at the cut surface. Here, the recesses 111 and 112 and the through-hole 113 are maintained in a vacuum or under low pressure, and the thermal conductivity of the recesses 111, 112 and the through-hole 113 is lower than that of semiconductors or glass. Therefore, the conduction of heat generated at the cut surface of the laminated chip P1 can be suppressed at the positions of the recesses 111, 112 and the through-hole 113.

[0089] As described above, in the first embodiment, the recess 111 is provided in the bonding region R1 of the chip 101, and the recess 112 is provided in the bonding region R2 of the transparent substrate 102. This makes it possible to suppress the conduction of heat generated around the chip 101 and the transparent substrate 102 at the positions of the recesses 111, 112 and the through-hole 113, making it difficult for heat to be transmitted to the light-receiving region R0. This makes it possible to suppress thermal damage to the light-receiving region R0 and prevent deterioration of the color filter 104 and the on-chip lens 105.

[0090] Furthermore, by maintaining the recesses 111, 112 and the through-hole 113 in a vacuum state or under low pressure, the transparent substrate 102 can be pressed against the chip 101 by the action of atmospheric pressure. This improves the bonding strength between the transparent substrate 102 and the chip 101, thereby ensuring the reliability of the electronic device 100 while reducing the chip size. Furthermore, moisture that has penetrated through the interface between the transparent substrate 102 and the adhesive layer 103 and the interface between the chip 101 and the adhesive layer 103 can be vaporized in the recesses 111, 112 and at the position of the through-hole 113, thereby preventing moisture from penetrating into the interior of the stacked chip P1.

[0091] Here, by arranging the through hole 113 formed in the adhesive layer 103 between the recesses 111 and 112, it is possible to prevent the adhesive layer 103 from entering the recesses 111 and 112, and to maintain low thermal conductivity of the recesses 111 and 112. Note that in order to prevent the adhesive layer 103 from entering the recesses 111 and 112, the diameter of the through hole 113 may be made larger than the diameter of each of the recesses 111 and 112.

[0092] Furthermore, the recesses 111, 112 and the through-hole 113 can deform in accordance with the difference in thermal expansion coefficients between the chip 101, the transparent substrate 102, and the adhesive layer 103. This allows stress on the stacked chip P1 to be alleviated, thereby improving the reliability of the electronic device 100.

[0093] 2. Second Embodiment In the first embodiment described above, the recess 111 is provided in the bonding region R1 of the chip 101, and the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this second embodiment, the recess 112 is provided in the bonding region R2 of the transparent substrate 102.

[0094] 5A and 5B are diagrams illustrating an example of the configuration of an electronic device according to the second embodiment, in which a is a cross-sectional view illustrating the example of the configuration of an electronic device 200 cut vertically, b is a plan view illustrating the example of the configuration of the electronic device 200, and c is a plan view illustrating the example of the configuration of an electronic device 200′.

[0095] In the figure, the electronic device 200 includes a stacked chip P2 instead of the stacked chip P1 of the first embodiment described above. The rest of the configuration of the electronic device 200 of the second embodiment is the same as the configuration of the electronic device 100 of the first embodiment described above.

[0096] The stacked chip P2 includes a chip 201 and an adhesive layer 203 instead of the chip 101 and the adhesive layer 103 of the first embodiment described above. The other configurations of the stacked chip P2 of the second embodiment are the same as the configurations of the stacked chip P1 of the first embodiment described above.

[0097] The chip 201 is the same as the chip 101 of the first embodiment described above, except that the recess 111 is omitted. The other configuration of the chip 201 of the second embodiment is the same as the configuration of the chip 101 of the first embodiment described above.

[0098] The adhesive layer 203 does not have the through-holes 113 of the adhesive layer 103 of the first embodiment described above. In this case, it is not necessary to form the through-holes 113 in the adhesive layer 203 before the adhesive layer 203 is cured, and a material that is difficult to process before curing can be used for the adhesive layer 203. Other configurations of the adhesive layer 203 of the second embodiment are the same as those of the adhesive layer 103 of the first embodiment described above.

[0099] In this case, in the electronic device 200, recesses 112 may be arranged discretely around the periphery of the transparent substrate 102, as shown in FIG.

[0100] Alternatively, in the electronic device 200', recesses 112' may be arranged continuously around the periphery of the transparent substrate 102, as shown in FIG.

[0101] As described above, in the second embodiment, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. This makes it possible to suppress the conduction of heat generated around the transparent substrate 102 at the position of the recess 112, making it difficult for heat to be transmitted to the light-receiving region R0. This makes it possible to suppress thermal damage to the light-receiving region R0 and prevent deterioration of the color filter 104 and the on-chip lens 105.

[0102] Furthermore, by maintaining the inside of the recess 112 in a vacuum state or under low pressure, the transparent substrate 102 can be pressed against the chip 201 by the action of atmospheric pressure. This improves the bonding strength between the transparent substrate 102 and the chip 201, and ensures the reliability of the electronic device 200 while reducing the chip size.

[0103] It is also possible to suspend fine particles in at least one of the recesses 111 and 112. The diameter of the fine particles can be set so that they suspend in the recesses 111 and 112. The fine particles may be reactive with outgassed particles released from the adhesive layer 103, may have light-blocking properties, may have wavelength selectivity, or may have adsorptivity. For example, fine particle pigments can impart light-blocking properties without reducing adhesion. Metal fine particles can react with outgassed particles and maintain vacuum strength.

[0104] 3. Third Embodiment In the first embodiment described above, the recess 111 is provided in the bonding region R1 of the chip 101, and the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this third embodiment, the recess 111 is provided in the bonding region R1 of the chip 101.

[0105] 6A and 6B are diagrams illustrating an example of the configuration of an electronic device according to the third embodiment, in which a is a cross-sectional view illustrating the example of the configuration of an electronic device 300 cut vertically, b is a plan view illustrating the example of the configuration of the electronic device 300, and c is a plan view illustrating the example of the configuration of an electronic device 300′.

[0106] In the figure, the electronic device 300 includes a stacked chip P3 instead of the stacked chip P1 of the first embodiment. The other configuration of the electronic device 300 of the third embodiment is the same as the configuration of the electronic device 100 of the first embodiment.

[0107] The stacked chip P3 includes a transparent substrate 302 and an adhesive layer 203 instead of the transparent substrate 102 and the adhesive layer 103 of the first embodiment described above. The other configurations of the stacked chip P3 of the third embodiment are the same as the configurations of the stacked chip P1 of the first embodiment described above.

[0108] The transparent substrate 302 does not have the recess 112 of the transparent substrate 102 of the first embodiment described above. In this case, it is not necessary to form the recess 112 in the transparent substrate 302, and a material that is difficult to process can be used for the transparent substrate 302. Other configurations of the transparent substrate 302 of the third embodiment are similar to those of the transparent substrate 102 of the first embodiment described above.

[0109] In this case, in the electronic device 300, recesses 111 may be arranged discretely around the chip 101 as shown in FIG.

[0110] Alternatively, in the electronic device 300', recesses 111' may be arranged continuously around the periphery of the chip 101, as shown in FIG.

[0111] As described above, in the third embodiment, the recess 111 is provided in the bonding region R1 of the chip 101. This makes it possible to suppress the conduction of heat generated around the chip 101 at the position of the recess 111, making it difficult for heat to be transmitted to the light-receiving region R0. This makes it possible to suppress thermal damage to the light-receiving region R0 and prevent deterioration of the color filter 104 and the on-chip lens 105.

[0112] Furthermore, by maintaining the inside of the recess 111 in a vacuum state or under low pressure, the chip 101 can be pressed against the transparent substrate 102 by the action of atmospheric pressure. This improves the bonding strength between the transparent substrate 102 and the chip 101, and ensures the reliability of the electronic device 300 while reducing the chip size.

[0113] 4. Fourth Embodiment In the above-described first embodiment, the through-hole 113 between the recess 111 provided in the bonding region R1 of the chip 101 and the recess 112 provided in the bonding region R2 of the transparent substrate 102 is formed in the adhesive layer 103. In this fourth embodiment, the through-hole 113 between the recess 111 provided in the bonding region R1 of the chip 101 and the recess 112 provided in the bonding region R2 of the transparent substrate 102 is removed.

[0114] 7A and 7B are diagrams illustrating an example of the configuration of an electronic device according to the fourth embodiment, in which a vertical cross-sectional view of an electronic device 400 is shown, b is a plan view of the electronic device 400, and c is a plan view of the electronic device 400′.

[0115] In the figure, the electronic device 400 includes a stacked chip P4 instead of the stacked chip P1 of the first embodiment described above. The rest of the configuration of the electronic device 400 of the fourth embodiment is the same as the configuration of the electronic device 100 of the first embodiment described above.

[0116] The stacked chip P4 includes the adhesive layer 203 of the second embodiment described above, instead of the adhesive layer 103 of the first embodiment described above. In this case, it is possible to vacuum-attach the chip 101 and the transparent substrate 102 to the adhesive layer 203 via the recesses 111, 112, while eliminating the need to form through-holes 113 in the adhesive layer 203. The rest of the configuration of the stacked chip P4 of the fourth embodiment is the same as the configuration of the stacked chip P1 of the first embodiment described above.

[0117] In this case, in the electronic device 400, as shown in b in the figure, recesses 111 may be arranged discretely around the chip 101, and recesses 112 may be arranged discretely around the transparent substrate 102. In this case, the horizontal positions of the recesses 111 and the horizontal positions of the recesses 112 may be equal to or different from each other.

[0118] Alternatively, in the electronic device 400', as shown in FIG. 4c, recesses 111' may be arranged continuously around the chip 101, and recesses 112' may be arranged continuously around the transparent substrate 102.

[0119] As described above, in the fourth embodiment, the recess 111 is provided in the bonding region R1 of the chip 101, and the recess 112 is provided in the bonding region R2 of the transparent substrate 102. This makes it possible to suppress the conduction of heat generated around the chip 101 and the transparent substrate 102 at the positions of the recesses 111 and 112, making it difficult for heat to be transmitted to the light-receiving region R0. This makes it possible to suppress thermal damage to the light-receiving region R0 and prevent deterioration of the color filter 104 and the on-chip lens 105.

[0120] Furthermore, by maintaining the insides of the recesses 111 and 112 in a vacuum state or under low pressure, the transparent substrate 102 and the chip 101 can be pressed against the adhesive layer 203 by the action of atmospheric pressure. This improves the bonding strength between the transparent substrate 102 and the chip 101 via the adhesive layer 203, and ensures the reliability of the electronic device 100 while reducing the chip size.

[0121] 5. Fifth Embodiment In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this fifth embodiment, the recess 112 is provided in the bonding region R2 of the transparent substrate 102, and the transparent substrate 102 is bonded to the chip 201 via an adhesive layer having a hard layer provided on its surface.

[0122] 8 is a diagram illustrating a configuration example of an electronic device according to the fifth embodiment, in which a is a cross-sectional view illustrating the configuration example of an electronic device 500 cut vertically, b is a plan view illustrating the configuration example of the electronic device 500, and c is a plan view illustrating the configuration example of an electronic device 500′.

[0123] In the figure, the electronic device 500 includes a stacked chip P5 instead of the stacked chip P2 of the second embodiment. The other configuration of the electronic device 500 of the fifth embodiment is the same as the configuration of the electronic device 200 of the fifth embodiment.

[0124] The stacked chip P5 has an adhesive layer 503 instead of the adhesive layer 103 of the first embodiment described above. The other configurations of the stacked chip P5 of the fifth embodiment are the same as the configurations of the stacked chip P2 of the second embodiment described above.

[0125] The adhesive layer 503 includes a hard layer 513. The hard layer 513 can be formed on the surface of the adhesive layer 503 in a position corresponding to the opening position of the recess 112. The hard layer 513 may be a layer that has been altered by heating. In this case, the hard layer 513 may be formed by irradiating the surface of the adhesive layer 503 with a laser. Other configurations of the adhesive layer 503 of the fifth embodiment are the same as those of the adhesive layer 203 of the fifth embodiment described above.

[0126] In this case, in the electronic device 500, as shown in b in the figure, the recesses 112 may be arranged discretely around the periphery of the transparent substrate 102. The hard layer 513 may be formed around the light receiving region R0 so as to surround the opening positions of the recesses 112.

[0127] Alternatively, in the electronic device 500′, as shown in FIG. 1C, the recesses 112′ may be continuously arranged around the periphery of the transparent substrate 102. The hard layer 513′ may be formed around the light receiving region R0 so as to surround the opening position of the recesses 112′.

[0128] As described above, in the fifth embodiment, the recess 112 is provided in the bonding region R2 of the transparent substrate 102, and the transparent substrate 102 is bonded to the chip 201 via the adhesive layer 503 having the hard layer 513 on its surface. This makes it possible to prevent the adhesive layer 503 and outgassing from the adhesive layer 503 from entering the recess 112. This makes it possible to suppress a decrease in the degree of vacuum within the recess 112, and to suppress an increase in the thermal conductivity of the recess 112 while also suppressing a decrease in the bonding strength via the recess 112.

[0129] In the fifth embodiment described above, the hard layer 513 is formed on the surface of the adhesive layer 503 in correspondence with the opening position of the recess 112. In the third or fourth embodiment described above, a hard layer may be formed on the bottom surface of the adhesive layer 503 in correspondence with the opening position of the recess 111.

[0130] 6. Sixth Embodiment In the first embodiment described above, the recess 111 is provided in the bonding region R1 of the chip 101, and the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this sixth embodiment, a filter layer is formed on the transparent substrate having the recess provided in the bonding region R2.

[0131] 9A and 9B are diagrams illustrating an example of the configuration of an electronic device according to the sixth embodiment, in which a vertical cross-sectional view of an electronic device 600 is shown, b is a plan view of the electronic device 600, and c is a plan view of the electronic device 600′.

[0132] In the figure, the electronic device 600 includes a stacked chip P6 instead of the stacked chip P1 of the first embodiment described above. The other configuration of the electronic device 600 of the sixth embodiment is the same as the configuration of the electronic device 100 of the first embodiment described above.

[0133] The laminated chip P6 includes a transparent substrate 602 instead of the transparent substrate 102 of the first embodiment described above. Furthermore, the laminated chip P6 includes a filter layer 604 in addition to the laminated chip P1 of the first embodiment described above. The other configurations of the laminated chip P6 of the sixth embodiment are the same as the configuration of the laminated chip P1 of the first embodiment described above.

[0134] The transparent substrate 602 has a through hole 612 as the recess 112 of the first embodiment described above. The through hole 612 passes through the transparent substrate 602 and is connected to the through hole 113. Other configurations of the transparent substrate 602 of the sixth embodiment are similar to the configuration of the transparent substrate 102 of the first embodiment described above.

[0135] In this case, in the electronic device 600, the through holes 612 may be arranged discretely around the periphery of the transparent substrate 602 as shown in FIG.

[0136] Alternatively, in the electronic device 600', through-holes 612' may be arranged continuously around the periphery of the transparent substrate 602, as shown in FIG.

[0137] The filter layer 604 is formed on the transparent substrate 602. At this time, the filter layer 604 can cover the opening of the through-hole 612. When the sensitivity of the light receiving region R0 is set to the visible region, the filter layer 604 may be an infrared cut filter or an ultraviolet cut filter. The filter layer 604 can be made of a dielectric multilayer film. For example, the filter layer 604 may be made by alternately laminating high-refractive index dielectric layers 604A and low-refractive index dielectric layers 604B. The high-refractive index dielectric layers 604A may be made of, for example, TiO ２ , Nb ２ O ５ , Ta ２ O ５ The low refractive index dielectric layer 604B can be selected from materials such as SiO ２ , MgF ２ The thickness of the filter layer 604 can be set within a range of 100 to 500 μm. In this case, for example, the high refractive index dielectric layer 604A can be set to a thickness of 20 μm, and the low refractive index dielectric layer 604B can be set to a thickness of 21 μm, and 4 to 15 layers can be stacked.

[0138] The filter layer 604 can be formed on the transparent substrate 602 without an adhesive layer. In this case, after the through-holes 612 are formed in the transparent substrate wafer bonded to the transparent substrate wafer 102W, the filter layer 604 may be attached to the transparent substrate wafer under reduced pressure. The filter layer 604 can be cut out in accordance with the cutting of the stacked chips P6.

[0139] In this manner, in the sixth embodiment described above, the filter layer 604 is formed on the transparent substrate 602 having the through-hole 612 formed in the bonding region R2. This makes it possible to attenuate unnecessary incident light and sharpen captured images without increasing the chip size.

[0140] In the sixth embodiment described above, the electronic device 600 is configured to include the transparent substrate 602 in which the through-holes 612 are formed. In any of the first to fifth embodiments described above, the filter layer 604 may be formed on the transparent substrate 102. In this case, for example, the filter layer 604 may be formed on the transparent substrate wafer 102W after the step b in FIG. 4 . The filter layer 604 may be formed by sputtering or CVD (Chemical Vapor Deposition).

[0141] 7. Seventh Embodiment In the above-described fourth embodiment, the light receiving region R0 is provided inside the bonding region R1 in which the recess 111 is formed. In this seventh embodiment, a cavity is provided inside the bonding region R1 in which the recess 111 is formed, and the light receiving region R0 is formed in the cavity.

[0142] 10 is a diagram illustrating a configuration example of an electronic device according to the seventh embodiment, in which a is a cross-sectional view illustrating the configuration example of an electronic device 700 cut vertically, b is a plan view illustrating the configuration example of the electronic device 700, and c is a plan view illustrating the configuration example of an electronic device 700′.

[0143] In the figure, the electronic device 700 includes a stacked chip P7 instead of the stacked chip P4 of the fourth embodiment. The other configuration of the electronic device 700 of the seventh embodiment is the same as the configuration of the electronic device 400 of the fourth embodiment.

[0144] The stacked chip P7 includes a chip 701 instead of the chip 101 of the first embodiment described above. The other configurations of the stacked chip P7 of the seventh embodiment are the same as the configurations of the stacked chip P4 of the fourth embodiment described above.

[0145] The chip 701 is obtained by adding a cavity 703 to the chip 101 of the above-described fourth embodiment. The other configuration of the chip 701 of the seventh embodiment is the same as the configuration of the chip 101 of the above-described fourth embodiment.

[0146] The cavity 703 is located inside the bonding region R1. A light-receiving region R0 is formed in the cavity 703. Here, in order to form the cavity 703 in the chip 701, a step 702 located between the bonding region R1 and the light-receiving region R0 can be formed in the chip 701. An adhesive layer 103 can be filled into the cavity 703. At this time, the adhesive layer 203 can also adhere to the step 702, thereby increasing the adhesive area of ​​the adhesive layer 203 and improving adhesive strength. Furthermore, the depth of the recess 111 can be increased in accordance with the step 702, thereby suppressing a decrease in the degree of vacuum within the recess 111.

[0147] The cavity 703 can be formed in the chip 701 before forming the photodiode, by etching the chip 701 using a resist pattern formed based on lithography as an etching mask.

[0148] In this case, in the electronic device 700, as shown in FIG. 7b, recesses 111 may be arranged discretely around the chip 701, and recesses 112 may be arranged discretely around the transparent substrate 102.

[0149] Alternatively, in the electronic device 700', as shown in FIG. 7c, recesses 111' may be arranged continuously around the chip 701, and recesses 112' may be arranged continuously around the transparent substrate 102.

[0150] In this way, in the seventh embodiment described above, the light receiving region R0 is formed in the cavity 703 provided inside the bonding region R1 where the recess 111 is formed. This makes it possible to thin the light receiving region R0 while suppressing a decrease in the strength of the chip 101, and makes it easier to form a through electrode in the light receiving region R0.

[0151] In the seventh embodiment, a cavity 703 is added to the chip 101 of the fourth embodiment. In any of the first, second, third, fifth and sixth embodiments, the cavity 703 may be added to the chip.

[0152] 8. Eighth Embodiment In the seventh embodiment described above, the chip 701 and the transparent substrate 102 are bonded together via the adhesive layer 103. In this eighth embodiment, the chip 701 and the transparent substrate 102 are bonded together directly without the adhesive layer 103 interposed therebetween.

[0153] 11 is a diagram illustrating a configuration example of an electronic device according to the eighth embodiment, in which a is a cross-sectional view illustrating the configuration example of an electronic device 800 cut vertically, b is a plan view illustrating the configuration example of the electronic device 800, and c is a plan view illustrating the configuration example of an electronic device 800′.

[0154] In the figure, the electronic device 800 includes a stacked chip P8 instead of the stacked chip P7 of the seventh embodiment. The rest of the configuration of the electronic device 800 of the eighth embodiment is the same as the configuration of the electronic device 700 of the seventh embodiment.

[0155] The laminated chip P8 is obtained by removing the adhesive layer 203 from the laminated chip P7 of the seventh embodiment described above. Here, the transparent substrate 102 and the chip 701 are directly bonded via bonding regions R1 and R2. At this time, the depth of the cavity 703 (the height of the step 702) can be set so that the transparent substrate 102 does not come into contact with the on-chip lens 105. The other configurations of the laminated chip P8 of the eighth embodiment are the same as those of the laminated chip P7 of the seventh embodiment described above. At this time, the cavity 703 may be depressurized or may be filled with gas.

[0156] Compression bonding can be used for direct bonding between the transparent substrate 102 and the chip 701. This compression bonding can be performed at a temperature of 250° C. or less, for example, after plasma activation of the bonding surfaces.

[0157] For example, in plasma activation using glass as the transparent substrate 102, oxygen plasma or nitrogen plasma can be irradiated onto the bonding surfaces to hydrophilize them. Then, the bonding surfaces can be bonded together based on hydrogen bonds between OH groups formed on the bonding surfaces by adsorption of moisture from the air. Then, heat treatment decomposes the OH groups, and the resulting hydrogen diffuses into the interface layer, achieving direct bonding based on Si-O-Si bonds mediated by oxygen. Plasma activation of the bonding surfaces before heat treatment can improve the moisture adsorption properties of the bonding surfaces, and even heat treatment at temperatures below 250°C can achieve the bonding strength required to ensure the reliability of the electronic device 800.

[0158] In the direct bonding between the transparent substrate 102 and the chip 701, oxide films may be bonded together, or metals may be bonded together. In this case, an oxide film or a metal film may be formed on the bonding surfaces of the transparent substrate 102 and the chip 701.

[0159] In the electronic device 800, as shown in FIG. 8b, recesses 111 may be arranged discretely around the chip 701, and recesses 112 may be arranged discretely around the transparent substrate 102.

[0160] Alternatively, in the electronic device 800', as shown in FIG. 8c, recesses 111' may be arranged continuously around the chip 701, and recesses 112' may be arranged continuously around the transparent substrate 102.

[0161] In this way, in the above-described eighth embodiment, the chip 701 is directly bonded to the transparent substrate 102. This makes it possible to prevent the adhesive layer 103 and outgassing from the adhesive layer 103 from entering the recesses 111 and 112, and to suppress a decrease in the bonding strength between the chip 701 and the transparent substrate 102.

[0162] In the above-described eighth embodiment, the chip 701 of the above-described seventh embodiment is directly bonded to the transparent substrate 102. In any of the above-described second, third, and sixth embodiments, a cavity 703 may be added to the chip, and the chip may be directly bonded to the transparent substrate.

[0163] 9. Ninth Embodiment In the first embodiment described above, the recess 111 is provided in the bonding region R1 of the chip 101, and the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this ninth embodiment, a light-shielding film is provided on the inner surface of the recess 112 formed in the bonding region R2 of the transparent substrate 102.

[0164] 12 is a diagram illustrating a configuration example of an electronic device according to a ninth embodiment, in which a is a cross-sectional view illustrating the configuration example of an electronic device 900 cut in a vertical direction, b is a plan view illustrating the configuration example of the electronic device 900, and c is a plan view illustrating the configuration example of an electronic device 900′.

[0165] In the figure, the electronic device 900 includes a stacked chip P9 instead of the stacked chip P1 of the first embodiment described above. The rest of the configuration of the electronic device 900 of the ninth embodiment is the same as the configuration of the electronic device 100 of the first embodiment described above.

[0166] The stacked chip P9 includes a transparent substrate 902 instead of the transparent substrate 102 of the first embodiment described above. The other configurations of the stacked chip P9 of the ninth embodiment are the same as the configurations of the stacked chip P1 of the first embodiment described above.

[0167] The transparent substrate 902 is the same as the transparent substrate 102 of the first embodiment described above, except that a light-shielding film 912 is added. The other configuration of the transparent substrate 902 of the ninth embodiment is the same as the configuration of the transparent substrate 102 of the first embodiment described above.

[0168] The light-shielding film 912 can be formed on the inner surface of the recess 112. In this case, the light-shielding film 912 may cover the entire inner surface of the recess 112. The material of the light-shielding film 912 may be a metal such as Al, Cu, Ag, Ti, or W. The material of the light-shielding film 912 may be a heat-absorbing material or a heat-conducting material. In this case, the light-shielding film 912 may also be used as a heat-dissipating material that dissipates heat generated within the stacked chip P9 to the outside.

[0169] In the electronic device 900, as shown in FIG. 9B, recesses 112 may be arranged discretely around the periphery of the transparent substrate 902. A light-shielding film 912 may be formed around the light-receiving region R0 so as to cover the inner surfaces of the recesses 112.

[0170] Alternatively, in the electronic device 900′, as shown in FIG. 1C, the recesses 112′ may be continuously arranged around the periphery of the transparent substrate 902. Furthermore, the light-shielding film 912′ may be formed around the light-receiving region R0 so as to cover the inner surface of the recesses 112′.

[0171] As described above, in the ninth embodiment, the light-shielding film 912 is provided on the inner surface of the recess 112 formed in the bonding region R2 of the transparent substrate 102. This improves the bonding strength between the chip 101 and the transparent substrate 102 based on the vacuum suction between the chip 101 and the transparent substrate 102, while suppressing the incidence of unnecessary light and the reflected light from the interface between the transparent substrate 102 and the adhesive layer 103, thereby reducing flare.

[0172] In the ninth embodiment described above, the light-shielding film 912 is provided on the inner surface of the recess 112 formed in the bonding region R2 of the transparent substrate 102 in the first embodiment described above. In any of the second to eighth embodiments described above, the light-shielding film 912 may be provided on the inner surface of the recess formed in the bonding region R2 of the transparent substrate.

[0173] 10. Tenth Embodiment In the first embodiment described above, the recess 111 is provided in the bonding region R1 of the chip 101, and the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this tenth embodiment, a through electrode is provided in the chip to be bonded to the transparent substrate 102, the through electrode being disposed at a position different from the horizontal position of the recess 112 provided in the bonding region R2 of the transparent substrate 102.

[0174] 13 is a diagram illustrating a configuration example of an electronic device according to a tenth embodiment, in which a portion a is a cross-sectional view illustrating the configuration example of the electronic device 1000 cut vertically, b is a plan view illustrating the configuration example of the electronic device 1000, and c is an enlarged cross-sectional view illustrating a region RA of a portion a in the figure.

[0175] In the figure, the electronic device 1000 includes a stacked chip P10 instead of the stacked chip P1 of the first embodiment described above. The other configuration of the electronic device 1000 of the tenth embodiment is the same as the configuration of the electronic device 100 of the first embodiment described above.

[0176] The stacked chip P10 includes chips P51 and P52. The chip P52 is stacked on the chip P51. A transparent substrate 102 is bonded onto the chip P52 via an adhesive layer 103.

[0177] Each of the chips P51 and P52 may have a semiconductor element, an optical element, or a MEMS formed thereon. The substrate used for each of the chips P51 and P52 may be a semiconductor substrate, a dielectric substrate, or an organic substrate.

[0178] In the following description, an example is taken in which a semiconductor element is formed on chip P51 and a back-illuminated solid-state imaging element is formed on chip P52. The semiconductor element on chip P51 may be formed with a logic circuit, a memory, a processor, a signal processing circuit, or an interface circuit.

[0179] The chip P51 includes a semiconductor substrate 1011, a wiring layer 1012, and a backside wiring layer 1017. The wiring layer 1012 is formed on the front side of the semiconductor substrate 1011, and the backside wiring layer 1017 is formed on the backside of the semiconductor substrate 1011. The wiring layer 1012 is provided with wiring 1031 embedded in an insulating layer and a pad electrode 1033. The wiring layer 1012 is also provided with a via 1032 used for interlayer connection. The pad electrode 1033 can be used for direct bonding between the chips P51 and P52.

[0180] The back wiring layer 1017 is provided with back wiring 1015 embedded in an insulating layer such as a solder resist. On the back wiring layer 1017, a protruding electrode 1016 connected to the back wiring 1015 is formed.

[0181] Furthermore, a gate electrode 1034 embedded in an insulating layer is formed on the front surface side of the semiconductor substrate 1011. At this time, a channel region located below the gate electrode 1034 and impurity diffusion layers located on both sides of the channel region can be formed in the semiconductor substrate 1011. Furthermore, a through electrode 1014 is formed in the semiconductor substrate 1011, penetrating the semiconductor substrate 1011 in the depth direction. The through electrode 1014 is connected to the wiring 1031 and the back surface wiring 1015.

[0182] The planar size and shape of the chip P52 can be made equal to those of the chip P51. The chip P52 includes a semiconductor substrate 1021 and a wiring layer 1022. The wiring layer 1022 is formed on the front surface side of the semiconductor substrate 1021. The wiring layer 1022 is provided with wiring 1041 embedded in an insulating layer and a pad electrode 1043. The wiring layer 1022 is also provided with a via 1042 used for interlayer connection. The pad electrode 1043 can be used for direct bonding between the chips P51 and P52. Hybrid bonding can be used for direct bonding between the chips P51 and P52. In this case, the pad electrodes 1033 and 1043 are positioned opposite each other. The pad electrodes 1033 and 1043 can be bonded to each other based on metal bonding such as Cu-Cu bonding.

[0183] Furthermore, a gate electrode 1044 embedded in an insulating layer is formed on the front surface side of the semiconductor substrate 1021. At this time, a channel region located below the gate electrode 1044 and impurity diffusion layers located on both sides of the channel region can be formed in the semiconductor substrate 1021. Furthermore, a photodiode PD is formed for each pixel on the back surface side of the semiconductor substrate 1021.

[0184] Here, the chip P52 is provided with a light receiving region R0 and a junction region R1. In the light receiving region R0, pixels and pixel transistors are arranged in a matrix along the row and column directions.

[0185] The bonding region R1 is used to bond the chip P52 and the transparent substrate 102. A through hole 1023 connected to the recess 1013 in the depth direction is formed in the bonding region R1. The through hole 1023 penetrates the semiconductor substrate 1021 and the wiring layer 1022, and is connected to the recess 112 in the depth direction via the through hole 113. The recess 1013 penetrates the wiring layer 1012 and is formed in the semiconductor substrate 1011. The recess 1013 can be positioned at a position different from the horizontal position of the through electrode 1014.

[0186] A color filter 104 is formed for each pixel on the light receiving region R0. An on-chip lens 105 is formed for each pixel on the color filter 104. In this case, the photodiode can be disposed on the back surface side of the semiconductor substrate 1021.

[0187] The insulating layer material used for each of the wiring layers 1012 and 1022 and the back surface wiring layer 1017 is, for example, SiO ２ , SiN, or SiCN can be used. The wirings 1031, 1041, the back wiring 1015, the vias 1032, 1042, and the pad electrodes 1033, 1043 can be made of a metal such as Al, Cu, AlCu, AlSiCu, or Co. The through electrode 1014 can be made of a metal such as Cu, Ti, Ta, Al, W, Ni, Ru, or Co, and may have a laminated structure of multiple materials.

[0188] In the electronic device 1000, as shown in b in the figure, recesses 1013 may be arranged discretely around the chip P51, and through-holes 1023 may be arranged discretely around the chip P52. In this case, through-electrodes 1014 may be arranged discretely along the boundary of the light-receiving region R0 at positions horizontally offset from the recesses 1013.

[0189] The dimensions of each part of the electronic device 100 can be set, for example, as follows: Planar size of chips P51, P52 and transparent substrate 102: 1.0 × 1.0 mm Thickness of chip P51: 10 μm Thickness of chip P52: 95 μm Thickness of semiconductor substrate 1011: 85 μm Thickness of wiring layer 1012: 10 μm Thickness of transparent substrate 102: 300 μm Thickness of adhesive layer 103: 50 μm Planar size of light receiving region R0: 700 × 700 μm Width of each bonding region R1, R2: 150 μm Height of protruding electrode 106 from semiconductor substrate 1011: 150 μm Planar size of each recess 111, 112: 50 × 50 μm Depth of recess 111 in semiconductor substrate 1011: 50 μm Depth of recess 112 in transparent substrate 102: 200 μm Horizontal distance between the recess 112 and the transparent substrate 102: 20 μm Horizontal distance between the recess 112 and the light receiving region R0: 80 μm

[0190] As described above, in the tenth embodiment, the chip P51 is provided with the through electrode 1014 that is located at a position different from the horizontal position of the recess 112 provided in the bonding region R2 of the transparent substrate 102. This makes it possible to suppress the conduction of heat generated around the transparent substrate 102 and the chips P51 and P52 at the positions of the recesses 112 and 1013, while also making it possible to connect the back surface of the chip P51 to the wiring layer 1012.

[0191] In the above-described tenth embodiment, the chip P52 is bonded to the transparent substrate 102 of the above-described first embodiment via the adhesive layer 103. In any of the above-described second to ninth embodiments, a stacked chip provided with a through electrode 1014 may be bonded to the transparent substrate.

[0192] 11. Eleventh Embodiment In the above-described tenth embodiment, the chip P51 is provided with the through electrode 1014 that is disposed at a position different from the horizontal position of the recess 112 provided in the bonding region R2 of the transparent substrate 102. In this eleventh embodiment, the through electrode is provided at a position that coincides with the horizontal position of the recess 112 provided in the bonding region R2 of the transparent substrate 102.

[0193] 14 is a diagram illustrating a configuration example of an electronic device according to an eleventh embodiment, in which a portion a is a cross-sectional view illustrating the configuration example of the electronic device 1100 cut in the vertical direction, and b is a plan view illustrating the configuration example of the electronic device 1100.

[0194] In the figure, the electronic device 1100 includes a stacked chip P11 instead of the stacked chip P10 and adhesive layer 103 of the above-described tenth embodiment. The rest of the configuration of the electronic device 1100 of the eleventh embodiment is the same as the configuration of the electronic device 1000 of the above-described tenth embodiment.

[0195] The stacked chip P11 includes chips P21 and P22. The chip P22 is stacked on the chip P21. The transparent substrate 102 is bonded onto the chip P22 via an adhesive layer 203.

[0196] Each of the chips P21 and P22 may have a semiconductor element, an optical element, or a MEMS formed thereon. The substrate used for each of the chips P21 and P22 may be a semiconductor substrate, a dielectric substrate, or an organic substrate.

[0197] In the following description, an example is taken in which a semiconductor element is formed on chip P21 and a back-illuminated solid-state imaging element is formed on chip P22. The semiconductor element on chip P21 may be formed with a logic circuit, a memory, a processor, a signal processing circuit, or an interface circuit.

[0198] The chip P21 is obtained by removing the recess 1013 from the chip P51 of the above-described tenth embodiment. Furthermore, the chip P21 is provided with a through electrode 1114 instead of the through electrode 1014 of the above-described tenth embodiment. The other configurations of the chip P21 of the eleventh embodiment are the same as the configurations of the chip P51 of the above-described tenth embodiment.

[0199] The chip P22 is the chip P52 of the above-described tenth embodiment without the through-hole 1023. The other configuration of the chip P22 of the eleventh embodiment is the same as the configuration of the chip P52 of the above-described tenth embodiment.

[0200] The through electrodes 1114 can be arranged discretely around the chip P21, as shown in b in the figure. In this case, the through electrodes 1114 can be arranged so as to coincide with the horizontal position of the recess 112. Note that the through electrodes 1114 may also be arranged so that a portion of the through electrodes 1114 coincides with the horizontal position of the recess 112.

[0201] As described above, in the eleventh embodiment, the chip P21 is provided with the through electrodes 1114 arranged at positions that coincide with the horizontal positions of the recesses 112 provided in the bonding region R2 of the transparent substrate 102. This makes it possible to suppress the conduction of heat generated around the transparent substrate 102 at the positions of the recesses 112 while suppressing an increase in the area of ​​the bonding region R1, and also makes it possible to establish a connection from the back side of the chip P21 to the wiring layer 1012.

[0202] In the eleventh embodiment, the chip P22 is bonded to the transparent substrate 102 of the second embodiment via the adhesive layer 203. The transparent substrate structures of the fifth, sixth, and ninth embodiments may also be applied.

[0203] 12. Twelfth Embodiment In the first embodiment described above, chip 101 having recess 111 formed therein and transparent substrate 102 having recess 112 formed therein are bonded via adhesive layer 103. In this twelfth embodiment, a recess is provided on the bonding surface of each chip on which an electronic device is formed, and these chips are directly bonded together.

[0204] 15 is a diagram illustrating a configuration example of an electronic device according to a twelfth embodiment, in which a portion a is a cross-sectional view illustrating the configuration example of an electronic device 1200 cut in a vertical direction, and b is a plan view illustrating the configuration example of the electronic device 1200.

[0205] In the figure, the electronic device 1200 includes a stacked chip P12 instead of the stacked chip P10 of the above-described tenth embodiment. The other configuration of the electronic device 1200 of the twelfth embodiment is the same as the configuration of the electronic device 1000 of the above-described tenth embodiment.

[0206] The stacked chip P12 includes chips P31 and P32. The chip P32 is stacked on the chip P31. The chip P32 is directly bonded to the chip P31.

[0207] Each of the chips P31 and P32 may have a semiconductor element, an optical element, or a MEMS formed thereon. The semiconductor element may have a logic circuit, a memory, a processor, a signal processing circuit, or an interface circuit formed thereon. The substrate used for each of the chips P31 and P32 may be a semiconductor substrate, a dielectric substrate, or an organic substrate.

[0208] In the following description, an example will be taken in which a semiconductor element is formed on each of the chips P31 and P32.

[0209] The chip P31 includes a semiconductor substrate 1211, a wiring layer 1212, and a backside wiring layer 1217. The wiring layer 1212 is formed on the front side of the semiconductor substrate 1211, and the backside wiring layer 1217 is formed on the backside of the semiconductor substrate 1211. The wiring layer 1212 is provided with wiring 1231 embedded in an insulating layer and a pad electrode 1233. The wiring layer 1212 is also provided with a via 1232 used for interlayer connection. The pad electrode 1233 can be used for direct bonding between the chips P31 and P32.

[0210] A back surface wiring 1215 embedded in an insulating layer is provided on the back surface wiring layer 1217. A protruding electrode 1216 connected to the back surface wiring 1215 is formed on the back surface wiring layer 1217.

[0211] Here, the chip P31 is provided with a device region R3 and a junction region R1. In the device region R3, a channel region and an impurity diffusion layer used in a transistor can be formed.

[0212] The bonding region R1 is used to bond the chips P31 and P32 together. A recess 1123 is formed in the bonding region R1. The recess 1123 penetrates the wiring layer 1212 and is formed in the semiconductor substrate 1211. Furthermore, a through electrode 1214 is formed in the semiconductor substrate 1211, penetrating the semiconductor substrate 1211 in the depth direction. The through electrode 1214 is connected to the wiring 1231 and the back surface wiring 1215.

[0213] The planar size and shape of the chip P32 can be made equal to those of the chip P31. The chip P32 includes a semiconductor substrate 1221 and a wiring layer 1222. The wiring layer 1222 is formed on the front surface side of the semiconductor substrate 1221. The wiring layer 1222 is provided with wiring 1241 embedded in an insulating layer and a pad electrode 1243. The wiring layer 1222 is also provided with a via 1242 used for interlayer connection. The pad electrode 1243 can be used for direct bonding between the chips P31 and P32. Hybrid bonding can be used for direct bonding between the chips P31 and P32. In this case, the pad electrodes 1233 and 1243 are positioned opposite each other. The pad electrodes 1233 and 1243 can be bonded to each other based on metal bonding such as Cu-Cu bonding.

[0214] Here, the chip P32 is provided with a device region R4 and a junction region R2. In the device region R4, a channel region and an impurity diffusion layer used in a transistor can be formed.

[0215] The bonding region R2 is used to bond the chips P31 and P32 together. A recess 1223 is formed in the bonding region R2. The recess 1223 penetrates the wiring layer 1222 and is formed in the semiconductor substrate 1221.

[0216] In the electronic device 1200, as shown in b in the figure, recesses 1123 may be arranged discretely around the chip P31, and recesses 1223 may be arranged discretely around the chip P32. In this case, through electrodes 1214 may be arranged discretely along the boundary of the device region R3 at positions horizontally offset from the recesses 1123.

[0217] In this way, in the above-described twelfth embodiment, the through electrode 1214 is provided in the chip P31 at a position different from the horizontal position of the recess 1223 provided in the bonding region R2 of the chip P32. This makes it possible to suppress the conduction of heat generated around the chips P31 and P32 at the positions of the recesses 1123 and 1223, while also making it possible to establish connection from the back surface side of the chip P31 to the wiring layer 1212.

[0218] 13. Thirteenth Embodiment In the above-described twelfth embodiment, the chip P31 having the recess 1123 formed therein is directly bonded to the chip P32 having the recess 1223 formed therein. In this thirteenth embodiment, the first semiconductor chip and the second semiconductor chip are directly bonded to each other such that the horizontal positions of the recesses formed on the bonding surface of the first semiconductor chip and the horizontal positions of the through electrodes formed on the second semiconductor chip are aligned with each other.

[0219] 16 is a diagram illustrating a configuration example of an electronic device according to a thirteenth embodiment, in which a portion a is a cross-sectional view illustrating the configuration example of an electronic device 1300 cut in a vertical direction, and b is a plan view illustrating the configuration example of the electronic device 1300.

[0220] In the figure, the electronic device 1300 includes a stacked chip P13 instead of the stacked chip P12 of the twelfth embodiment described above. The rest of the configuration of the electronic device 1300 of the thirteenth embodiment is the same as the configuration of the electronic device 1200 of the twelfth embodiment described above.

[0221] The stacked chip P13 includes chips P41 and P32. The chip P32 is stacked on the chip P41. The chip P32 is directly bonded to the chip P41.

[0222] The chip P41 may have a semiconductor element, an optical element, or a MEMS formed thereon. The semiconductor element may have a logic circuit, a memory, a processor, a signal processing circuit, or an interface circuit formed thereon. The substrate used for the chip P41 may be a semiconductor substrate, a dielectric substrate, or an organic substrate.

[0223] In the following description, a case where a semiconductor element is formed on the chip P41 will be taken as an example.

[0224] The chip P41 is obtained by removing the recess 1123 from the chip P31 of the twelfth embodiment described above. The chip P41 also includes a through electrode 1314 instead of the through electrode 1214 of the twelfth embodiment described above. The other configurations of the chip P41 of the thirteenth embodiment are the same as those of the chip P31 of the twelfth embodiment described above.

[0225] The through electrodes 1314 can be arranged discretely around the chip P41, as shown in b in the figure. In this case, the through electrodes 1314 can be arranged so as to coincide with the horizontal position of the recess 1223. Note that the through electrodes 1314 may also be arranged so that a portion of the through electrodes 1314 coincides with the horizontal position of the recess 1223.

[0226] In this way, in the above-described thirteenth embodiment, the through electrodes 1314 are provided in the chip P41 at positions that coincide with the horizontal positions of the recesses 1223 provided in the bonding region R2 of the chip P32. This makes it possible to suppress the conduction of heat generated around the chip P32 at the positions of the recesses 1223 while suppressing an increase in the areas of the bonding regions R1 and R2, and also makes it possible to establish a connection from the back surface side of the chip P41 to the wiring layer 1212.

[0227] 14. Fourteenth Embodiment In the first embodiment described above, the recess 111 is provided in the bonding region R1 of the chip 101, and the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this fourteenth embodiment, a groove is provided so as to traverse the transparent substrate that is bonded to the sensor chip via a transparent resin layer.

[0228] 17 is a diagram illustrating a configuration example of an electronic device according to a fourteenth embodiment, in which a portion a is a cross-sectional view illustrating the configuration example of an electronic device 1400 cut in a vertical direction, and a portion b is a plan view illustrating the configuration example of the electronic device 1400.

[0229] In the same figure, the electronic device 1400 includes a stacked chip P14. The stacked chip P14 includes a sensor chip 1401 and a transparent substrate 1402. The transparent substrate 1402 is stacked on the sensor chip 1401. At this time, the transparent substrate 1402 is bonded to the sensor chip 1401 via a transparent resin layer 1403. Here, at least one bonding surface between the transparent substrate 1402 and the sensor chip 1401 has multiple surfaces whose normal directions are different from each other. For example, a groove MZ1 is provided between the sensor chip 1401 and the transparent substrate 1402. The groove MZ1 can be provided continuously across different ends of the stacked chip P14. Here, the transparent substrate 1402 is divided into chips so as to be the same size as the sensor chip 1401. At this time, the positions of the horizontal ends of the transparent substrate 1402 can be aligned with the positions of the horizontal ends of the sensor chip 1401. This allows the stacked chip P14 to form a WLCSP. The transparent substrate 1402 can be used as an optical system that transmits light on the sensor chip 1401 .

[0230] The transparent substrate 1402 includes a groove MZ1. The groove MZ1 is disposed on the bonding surface side with the transparent resin layer 1403. The groove MZ1 is disposed so as to cross the transparent substrate 1402. The groove MZ1 can be disposed at a position that allows it to cross the wafer before the stacked chips P14 are separated into a single piece. One or more grooves MZ1 can be provided in the transparent substrate 1402. In this case, the groove MZ1 may be disposed on the pixel region RG of the sensor chip 1401. The pixel region RG may include an effective pixel region and an ineffective pixel region. In this case, the groove MZ1 may be disposed on the effective pixel region of the sensor chip 1401, on the peripheral region around the pixel region RG, or on both the effective pixel region and the peripheral region. The width and depth of the groove MZ1 can be constant. By maintaining the width and depth of the groove MZ1 constant, voids can be prevented from remaining in the groove MZ1. In this case, the depth of the groove MZ1 can be set to be equal to or less than the thickness of the transparent resin layer 1403. More preferably, the depth of the groove MZ1 is set to be equal to or less than half the thickness of the transparent resin layer 1403. The width of the groove MZ1 should be as narrow as possible within the range that allows the transparent resin layer 1403 to penetrate. The arrangement density of the grooves MZ1 should be as high as possible. The cross-sectional shape of the groove MZ1 may include curves or straight lines. For example, the cross-sectional shape of the groove MZ1 may be wavy or rectangular. Furthermore, the planar shape of the groove MZ1 is preferably configured with straight lines or smooth curves so as not to hinder the flow of voids.

[0231] The transparent substrate 1402 may be a glass substrate, a quartz substrate, or a transparent resin substrate such as an acrylic or polycarbonate substrate. ２ O ３ , CaF ２ , MgF ２ Alternatively, LiF or the like may be used.

[0232] The sensor chip 1401 includes a pixel region RG. A peripheral region is provided around the pixel region RG. In the pixel region RG, pixels and pixel transistors are arranged in a matrix along the row and column directions. Photodiodes can be formed in the pixels. The peripheral region may be provided with a DRAM (Dynamic Random Access Memory) or a signal processing circuit that processes pixel signals output from the effective pixel region. The sensor chip 1401 may be a back-illuminated solid-state imaging element. A color filter 104 is formed on the pixel region RG for each pixel. An on-chip lens 105 is formed on the color filter 104 for each pixel.

[0233] The transparent resin layer 1403 is positioned between the sensor chip 1401 and the transparent substrate 1402. The horizontal end positions of the transparent resin layer 1403 can be aligned with the horizontal end positions of the sensor chip 1401. The transparent resin layer 1403 can bond the sensor chip 1401 and the transparent substrate 1402 while infiltrating into the groove MZ1 of the transparent substrate 1402. By infiltrating into the groove MZ1 of the transparent substrate 1402, the transparent resin layer 1403 can increase the bonding area with the transparent substrate 1402 and increase the bonding strength. By arranging the groove MZ1 on the pixel region RG of the sensor chip 1401, the restrictions on the placement of the groove MZ1 can be relaxed compared to a method in which the groove MZ1 is arranged only around the pixel region RG. This allows the bonding area with the transparent substrate 1402 to be increased while still allowing for a reduction in the chip size of the stacked chip P14.

[0234] Furthermore, by arranging the groove MZ1 so as to traverse the transparent substrate 1402, it is possible to ensure a flow path for the transparent resin layer 1403 that extends from the center to the edge of the laminated chip P14, while bonding the sensor chip 1401 and the transparent substrate 1402 via the transparent resin layer 1403. Therefore, the transparent resin layer 1403 progresses uniformly through the flow path, thereby bonding the sensor chip 1401 and the transparent substrate 1402 and preventing voids from remaining in the transparent resin layer 1403.

[0235] The transparent resin layer 1403 can be made of a transparent resin such as a siloxane-based resin, an acrylic-based resin, or an epoxy-based resin. In this case, the material of the transparent resin layer 1403 can be selected so as to ensure a refractive index difference between the on-chip lens 105 and the transparent resin layer 1403. The transparent resin layer 1403 may contain an inorganic or organic filler to improve reliability. A resin material with adjusted optical properties (such as refractive index and extinction coefficient) may be selected for the transparent resin layer 1403 so that light can be received effectively in the effective pixel area. In particular, a material with a refractive index of approximately 0.5 to 3.0 can be used for the transparent resin layer 1403, but a refractive index close to that of the transparent substrate 1402 is more preferable. Additionally, a small extinction coefficient for the transparent resin layer 1403 is preferable, but a refractive index close to 0 is even more preferable. For example, when the groove MZ1 is disposed above the effective pixel area, the refractive index difference between the transparent substrate 1402 and the transparent resin layer 1403 is preferably set so as not to degrade the image quality of the image generated by the sensor chip 1401. In this case, the refractive index of the transparent substrate 1402 and the refractive index of the transparent resin layer 1403 may be equal to each other.

[0236] FIG. 18 is a plan view showing a configuration example of electronic devices in a wafer state according to the fourteenth embodiment.

[0237] In the figure, a transparent substrate wafer 1402W is laminated on a semiconductor wafer 1401W with a transparent resin layer 1403 interposed therebetween, and is then cut out into laminated chips P14.

[0238] Grooves MZ1 are formed in the transparent substrate wafer 1402W. The grooves MZ1 can be arranged to cross the transparent substrate wafer 1402W. This allows the transparent resin layer 1403 to uniformly progress through the flow path, thereby bonding the transparent substrate wafer 1402W and the semiconductor wafer 1401W via the transparent resin layer 1403. The grooves MZ1 may be formed radially in the transparent substrate wafer 1402W. Here, by forming the grooves MZ1 radially in the transparent substrate wafer 1402W, the center and edges of the transparent substrate wafer 1402W can be connected via the shortest path, allowing voids to be efficiently moved from the center to the edges of the transparent substrate wafer 1402W. The arrangement density of the grooves MZ1 can be set so that one or more grooves MZ1 overlap each stacked chip P14.

[0239] The semiconductor wafer 1401W is provided with partitioned regions 1401R. A sensor chip 1401 is cut out from each partitioned region 1401R. Each partitioned region 1401R is partitioned along a scribe line 1401D. In each partitioned region 1401R, a color filter 104 and an on-chip lens 105 are arranged for each pixel.

[0240] 19A to 19C are cross-sectional views illustrating an example of a method for manufacturing an electronic device according to the fourteenth embodiment.

[0241] In FIG. 14A, a resist pattern 1421 is formed on the transparent substrate wafer 1402W by lithography. An opening 1422 is formed in the resist pattern 1421 at a position where the groove MZ1 is to be formed.

[0242] Next, as shown in b in the figure, the transparent substrate wafer 1402W is etched in the depth direction using the resist pattern 1421 as an etching mask to form a groove MZ1 that traverses the transparent substrate wafer 1402W. Isotropic etching such as plasma etching or wet etching can be used to etch the transparent substrate wafer 1402W. The groove MZ1 may also be formed by mechanical processing.

[0243] Next, as shown in FIG. 1C, the resist pattern 1421 is removed from the transparent substrate wafer 1402W by ashing or other methods.

[0244] Next, as shown in d of the figure, a transparent resin layer 1403 is formed on the semiconductor wafer 1401W so as to cover the on-chip lens 105. The transparent resin layer 1403 can be formed on the semiconductor wafer 1401W by a method such as coating. Then, before the transparent resin layer 1403 is hardened, the transparent substrate wafer 1402W is positioned so that the groove MZ1 faces the transparent resin layer 1403.

[0245] Next, as shown in FIG. 17A, the transparent substrate wafer 1402W is brought into contact with the transparent resin layer 1403 so that the transparent resin layer 1403 is embedded in the groove MZ1. The transparent resin layer 1403 is then cured to bond the transparent substrate wafer 1402W onto the semiconductor wafer 1401W. At this time, the transparent resin layer 1403 may be made of an ultraviolet-curable resin or a thermosetting resin. Bonding of the transparent substrate wafer 1402W and the semiconductor wafer 1401W may be performed in a vacuum environment. The laminated structure of the transparent substrate wafer 1402W and the semiconductor wafer 1401W is then cut along the scribe lines 1401D to separate the laminated chips P14.

[0246] Fig. 20 is a diagram showing another example of the configuration of the electronic device according to the fourteenth embodiment, in which Fig. 20a is a cross-sectional view showing the example of the configuration of the electronic device 1400' cut in the vertical direction, and Fig. 20b is a plan view showing the example of the configuration of the electronic device 1400'.

[0247] 20, an electronic device 1400′ includes a stacked chip P14′. The stacked chip P14′ is obtained by adding an intermediate layer 1404 to the stacked chip P14′ of FIG. 17. The other configuration of the stacked chip P14′ is the same as the configuration of the electronic device 1400 of FIG.

[0248] The intermediate layer 1404 has a refractive index between the refractive index of the transparent substrate 1402 and the refractive index of the transparent resin layer 1403. The refractive index of the intermediate layer 1404 may be equal to the refractive index of the transparent substrate 1402. The intermediate layer 1404 is located between the transparent substrate 1402 and the transparent resin layer 1403. In this case, the intermediate layer 1404 can be embedded in the groove MZ1. The surface of the intermediate layer 1404 can be planarized. The intermediate layer 1404 can be made of an organic material such as a transparent resin.

[0249] At this time, the refractive index of the intermediate layer 1404 can be made closer to the refractive index of the transparent substrate 1402. Therefore, the stress and strain applied to the transparent substrate 1402 can be reduced compared to when the transparent resin layer 1403 is directly bonded to the transparent substrate 1402, and the intermediate layer 1404 can penetrate into the groove MZ1 more easily than the transparent resin layer 1403. Therefore, it is possible to suppress the generation of voids in the groove MZ1 and to improve the bonding strength due to the anchor effect.

[0250] FIG. 21 is a cross-sectional view showing another example of the method for manufacturing an electronic device according to the fourteenth embodiment.

[0251] In FIG. 14A, a resist pattern 1421 is formed on the transparent substrate wafer 1402W by lithography. In the resist pattern 1421, an opening 1422 is formed at the position where the groove MZ1 is to be formed.

[0252] Next, as shown in FIG. 14B, the transparent substrate wafer 1402W is etched in the depth direction using the resist pattern 1421 as an etching mask to form a groove MZ1 that traverses the transparent substrate wafer 1402W.

[0253] Next, as shown in c in the figure, the resist pattern 1421 is removed from the transparent substrate wafer 1402W by ashing or other methods. Then, an intermediate layer 1404 is formed on the transparent substrate wafer 1402W so as to fill the grooves MZ1. At this time, the surface of the intermediate layer 1404 can be planarized. The intermediate layer 1404 may be formed by coating, spin coating, or dispensing.

[0254] Next, as shown in d of the figure, a transparent resin layer 1403 is formed on the semiconductor wafer 1401W so as to cover the on-chip lens 105. Then, the transparent substrate wafer 1402W is positioned so that the intermediate layer 1404 faces the transparent resin layer 1403.

[0255] 20A, the intermediate layer 1404 is brought into contact with the transparent resin layer 1403. The transparent resin layer 1403 and the intermediate layer 1404 are then cured to bond the transparent substrate wafer 1402W onto the semiconductor wafer 1401W. The laminated structure of the transparent substrate wafer 1402W and the semiconductor wafer 1401W is then cut along the scribe lines 1401D to cut out laminated chips P14'.

[0256] As described above, in the fourteenth embodiment, the groove MZ1 is provided so as to cross the transparent substrate 1402 bonded to the sensor chip 1401 via the transparent resin layer 1403. This allows the transparent resin layer 1403 to flow along the groove MZ1 provided in the transparent substrate 1402 to the edge of the stacked chip P41, while increasing the bonding area between the transparent substrate 1402 and the transparent resin layer 1403. This makes it possible to improve the bonding strength between the sensor chip 1401 and the transparent substrate 1402 and prevent voids from remaining in the transparent resin layer 1403. Here, by forming the cross-sectional shape of the groove MZ1 into a smooth curve, the flow of voids along the groove MZ1 can be smoothed, making it easier to discharge the voids.

[0257] 15. Fifteenth Embodiment In the above-described fourteenth embodiment, the wavy groove MZ1 is provided so as to traverse the transparent substrate 1402 that is bonded to the sensor chip 1401 via the transparent resin layer 1403. In this fifteenth embodiment, a rectangular groove is provided so as to traverse the transparent substrate that is bonded to the sensor chip 1401 via the transparent resin layer.

[0258] FIG. 22 is a cross-sectional view illustrating a configuration example of an electronic device according to the fifteenth embodiment.

[0259] In the figure, the electronic device 1500 includes a stacked chip P15 instead of the stacked chip P14 of the above-described fourteenth embodiment. The other configuration of the electronic device 1500 of the fifteenth embodiment is the same as the configuration of the electronic device 1400 of the above-described fourteenth embodiment.

[0260] The laminated chip P15 includes a transparent substrate 1502 and a transparent resin layer 1503 instead of the transparent substrate 1402 and the transparent resin layer 1403 of the above-described fourteenth embodiment. The other configurations of the laminated chip P15 of the fifteenth embodiment are the same as the configurations of the laminated chip P14 of the above-described fourteenth embodiment.

[0261] The transparent substrate 1502 has a groove MZ2. The cross section of the groove MZ2 is rectangular. The other configuration of the groove MZ2 is the same as the configuration of the groove MZ1 in the above-described fourteenth embodiment.

[0262] The transparent resin layer 1503 penetrates into the groove MZ2 of the transparent substrate 1502 and bonds the sensor chip 1401 to the transparent substrate 1502. Other configurations of the transparent resin layer 1503 are similar to the configuration of the transparent resin layer 1403 in the above-described fourteenth embodiment.

[0263] As described above, in the fifteenth embodiment, the groove MZ2 is provided so as to cross the transparent substrate 1502 bonded to the sensor chip 1401 via the transparent resin layer 1503. This allows the transparent resin layer 1503 to flow along the groove MZ2 provided in the transparent substrate 1502 to the edge of the stacked chip P15, while increasing the bonding area between the transparent substrate 1502 and the transparent resin layer 1503. This makes it possible to improve the bonding strength between the sensor chip 1401 and the transparent substrate 1502 and prevent voids from remaining in the transparent resin layer 1503. Here, by making the cross-sectional shape of the groove MZ2 rectangular, the anchor effect of the groove MZ2 is increased, thereby improving the bonding strength between the sensor chip 1401 and the transparent substrate 1502.

[0264] 16. Sixteenth Embodiment In the above-described fourteenth embodiment, the groove MZ1 is provided so as to traverse the transparent substrate 1402 that is bonded to the sensor chip 1401 via the transparent resin layer 1403. In this sixteenth embodiment, a fine groove is provided on the surface of the groove that is provided so as to traverse the transparent substrate that is bonded to the sensor chip 1401 via the transparent resin layer.

[0265] FIG. 23 is a cross-sectional view illustrating a configuration example of an electronic device according to the sixteenth embodiment.

[0266] In the figure, the electronic device 1600 includes a stacked chip P16 instead of the stacked chip P14 of the above-described fourteenth embodiment. The other configuration of the electronic device 1600 of the sixteenth embodiment is the same as the configuration of the electronic device 1600 of the above-described sixteenth embodiment.

[0267] The laminated chip P16 includes a transparent substrate 1602 and a transparent resin layer 1603 instead of the transparent substrate 1402 and the transparent resin layer 1403 of the above-described fourteenth embodiment. The other configurations of the laminated chip P16 of the sixteenth embodiment are the same as the configurations of the laminated chip P14 of the above-described fourteenth embodiment.

[0268] The transparent substrate 1602 has a groove MZ3. A fine groove SM3 is provided on the surface of the groove MZ3. The other configuration of the groove MZ3 is the same as the configuration of the groove MZ1 in the above-described fourteenth embodiment.

[0269] The microgroove SM3 can be formed along the groove MZ3. In this case, the microgroove SM3 can be arranged continuously so as to cross the transparent substrate 1602. The width of the microgroove SM3 can be narrower than the width of the groove MZ3. The width and depth of the microgroove SM3 can be constant. Note that instead of providing the microgroove SM3 on the surface of the groove MZ3, the surface of the groove MZ3 may be roughened.

[0270] The transparent resin layer 1603 penetrates into the groove MZ3 of the transparent substrate 1602 and bonds the sensor chip 1401 to the transparent substrate 1602. Other configurations of the transparent resin layer 1603 are similar to the configuration of the transparent resin layer 1403 in the above-described fourteenth embodiment.

[0271] As described above, in the sixteenth embodiment, the fine grooves SM3 are provided on the surface of the grooves MZ3 provided across the transparent substrate 1602 bonded to the sensor chip 1401 via the transparent resin layer 1603. This allows the transparent resin layer 1603 to flow along the grooves MZ3 provided in the transparent substrate 1602 to the edge of the stacked chip P16, while increasing the bonding area between the transparent substrate 1602 and the transparent resin layer 1603. This makes it possible to prevent voids from remaining in the transparent resin layer 1603, while increasing the bonding strength between the transparent substrate 1602 and the transparent resin layer 1603.

[0272] 17. Seventeenth Embodiment In the above-described fourteenth embodiment, the groove MZ1 is provided so as to traverse the transparent substrate 1402 bonded to the sensor chip 1401 via the transparent resin layer 1403. In this seventeenth embodiment, the groove is provided so as to traverse the intermediate resin layer interposed in the bonding between the sensor chip 1401 and the transparent substrate via the transparent resin layer.

[0273] 24 and 25 are cross-sectional views showing configuration examples of an electronic device according to the seventeenth embodiment. In addition, "a" in Fig. 24 shows a first example of the configuration of the electronic device according to the seventeenth embodiment. "b" in Fig. 24 shows a second example of the configuration of the electronic device according to the seventeenth embodiment. "a" in Fig. 25 shows a third example of the configuration of the electronic device according to the seventeenth embodiment. "b" in Fig. 25 shows a fourth example of the configuration of the electronic device according to the seventeenth embodiment.

[0274] 24A, the electronic device 1700 includes a stacked chip P17A instead of the stacked chip P14 of the above-described fourteenth embodiment. The other configuration of the electronic device 1700 is the same as the configuration of the electronic device 1400 of the above-described fourteenth embodiment.

[0275] The laminated chip P17A includes a transparent substrate 1702 and a transparent resin layer 1703 instead of the transparent substrate 1402 and the transparent resin layer 1403 of the above-described fourteenth embodiment. Furthermore, the laminated chip P17A includes an intermediate resin layer 1704 in addition to the laminated chip P14 of the above-described fourteenth embodiment. The rest of the configuration of the laminated chip P17A is the same as the configuration of the laminated chip P14 of the above-described fourteenth embodiment.

[0276] The transparent substrate 1702 is the same as the transparent substrate 1402 of the fourteenth embodiment except that the groove MZ1 has been removed. In this case, the transparent substrate 1702 may be formed of a flat plate. The other configurations of the transparent substrate 1702 are the same as those of the transparent substrate 1402 of the fourteenth embodiment.

[0277] The intermediate resin layer 1704 is formed on the transparent substrate 1702. The intermediate resin layer 1704 is located between the transparent substrate 1702 and the transparent resin layer 1703. The material of the intermediate resin layer 1704 may be the same as or different from the material of the transparent resin layer 1703. In this case, it is preferable to use a material having optical properties similar to those of the transparent resin layer 1703 for the intermediate resin layer 1704 to avoid the influence of the groove MZ4A on the optical properties. For example, when the groove MZ4A is disposed above the effective pixel area, it is preferable to set the difference in refractive index between the intermediate resin layer 1704 and the transparent resin layer 1703 so as not to degrade the quality of the image generated by the sensor chip 1401. In this case, the refractive index of the intermediate resin layer 1704 and the refractive index of the transparent resin layer 1703 may be equal to each other. In order to improve bonding strength, the adhesive strength of the intermediate resin layer 1704 may be greater than the adhesive strength of the transparent resin layer 1703.

[0278] The intermediate resin layer 1704 includes a groove MZ4A. The groove MZ4A is arranged to cross the intermediate resin layer 1704. Here, the groove MZ4A can penetrate the intermediate resin layer 1704. In this case, the depth of the groove MZ4A can match the thickness of the intermediate resin layer 1704. The groove MZ4A can be arranged at a position that allows it to cross the wafer before the stacked chip P17A is solidified. In this case, the groove MZ4A may be arranged above the pixel region RG of the sensor chip 1401. The width and depth of the groove MZ4A can be constant. In this case, the depth of the groove MZ4A can be set to be equal to or less than the thickness of the transparent resin layer 1703. More preferably, the depth of the groove MZ4A is set to be equal to or less than half the thickness of the transparent resin layer 1703. The cross-sectional shape of the groove MZ4A may include a curve or a straight line. For example, the cross-sectional shape of the groove MZ4A may be wavy or rectangular. Moreover, the planar shape of the groove MZ4A is preferably formed of a straight line or a smooth curve so as not to hinder the flow of voids.

[0279] The transparent resin layer 1703 bonds the sensor chip 1401 and the transparent substrate 1702 while entering the groove MZ4A of the intermediate resin layer 1704. Other configurations of the transparent resin layer 1703 are similar to the configuration of the transparent resin layer 1403 in the above-described fourteenth embodiment.

[0280] 24b, an electronic device 1710 includes a stacked chip P17B instead of the stacked chip P17A described above. The rest of the configuration of the electronic device 1710 is the same as the configuration of the electronic device 1700 described above.

[0281] The stacked chip P17B includes a transparent resin layer 1713 and an intermediate resin layer 1714 instead of the transparent resin layer 1703 and intermediate resin layer 1704. The rest of the configuration of the stacked chip P17B is the same as the configuration of the stacked chip P17A.

[0282] The intermediate resin layer 1714 has a groove MZ4B instead of the groove MZ4A of the intermediate resin layer 1704. Other configurations of the intermediate resin layer 1714 are the same as those of the intermediate resin layer 1704 described above.

[0283] The bottom of the groove MZ4B is located in the intermediate resin layer 1714. In this case, the depth of the groove MZ4B can be made shallower than the thickness of the intermediate resin layer 1714. Other configurations of the groove MZ4B are the same as the configuration of the groove MZ4A described above.

[0284] 25A, an electronic device 1720 includes a stacked chip P17C instead of the stacked chip P17A described above. The rest of the configuration of the electronic device 1720 is the same as the configuration of the electronic device 1700 described above.

[0285] The stacked chip P17C includes a transparent resin layer 1723 and an intermediate resin layer 1724 instead of the transparent resin layer 1703 and intermediate resin layer 1704. The rest of the configuration of the stacked chip P17C is the same as that of the stacked chip P17A.

[0286] The intermediate resin layer 1724 is formed on the sensor chip 1401. The intermediate resin layer 1724 is located between the sensor chip 1401 and the transparent resin layer 1723. The material of the intermediate resin layer 1724 may be the same as or different from the material of the transparent resin layer 1723. However, when the groove MZ4C is disposed on the effective pixel region, it is preferable to set the difference in refractive index between the intermediate resin layer 1724 and the transparent resin layer 1723 so as not to degrade the quality of the image generated by the sensor chip 1401. For example, the refractive index of the intermediate resin layer 1724 and the refractive index of the transparent resin layer 1723 may be equal to each other. In this case, the refractive index of the intermediate resin layer 1724 can be made different from the refractive index of the on-chip lens 105.

[0287] The intermediate resin layer 1724 includes a groove MZ4C. The groove MZ4C is arranged to cross the intermediate resin layer 1724. Here, the groove MZ4C can penetrate the intermediate resin layer 1724. In this case, the depth of the groove MZ4C can match the thickness of the intermediate resin layer 1724. The groove MZ4C can be arranged at a position that allows it to cross the wafer before the stacked chip P17C is solidified. In this case, the groove MZ4C may be arranged above the pixel region RG of the sensor chip 1401. The width and depth of the groove MZ4C can be constant. In this case, the depth of the groove MZ4C can be set to be equal to or less than the thickness of the transparent resin layer 1723. More preferably, the depth of the groove MZ4C is set to be equal to or less than half the thickness of the transparent resin layer 1723. The cross-sectional shape of the groove MZ4C may include a curve or a straight line. For example, the cross-sectional shape of the groove MZ4C may be wavy or rectangular. Moreover, the planar shape of the groove MZ4C is preferably formed by a straight line or a smooth curve so as not to hinder the flow of the transparent resin.

[0288] The transparent resin layer 1723 bonds the sensor chip 1401 and the transparent substrate 1702 while entering the groove MZ4C of the intermediate resin layer 1724. Other configurations of the transparent resin layer 1723 are similar to the configuration of the transparent resin layer 1403 in the above-described fourteenth embodiment.

[0289] 25b, an electronic device 1730 includes a stacked chip P17D instead of the stacked chip P17C described above. The rest of the configuration of the electronic device 1730 is the same as the configuration of the electronic device 1720 described above.

[0290] The stacked chip P17D includes a transparent resin layer 1733 and an intermediate resin layer 1734 instead of the transparent resin layer 1723 and intermediate resin layer 1724. The rest of the configuration of the stacked chip P17D is the same as the configuration of the stacked chip P17C described above.

[0291] The intermediate resin layer 1734 has a groove MZ4D instead of the groove MZ4C of the intermediate resin layer 1724. The intermediate resin layer 1734 is located between the sensor chip 1401 and the transparent resin layer 1733. Other than that, the configuration of the intermediate resin layer 1734 is the same as the configuration of the intermediate resin layer 1724 described above.

[0292] The bottom of the groove MZ4D is located in the intermediate resin layer 1734. In this case, the depth of the groove MZ4D can be made shallower than the thickness of the intermediate resin layer 1734. Other configurations of the groove MZ4D are the same as the configuration of the groove MZ4C described above.

[0293] As described above, in the seventeenth embodiment, grooves are provided across the intermediate resin layer interposed in the bonding between the sensor chip 1401 and the transparent substrate 1702 via the transparent resin layer. This allows the transparent resin layer to flow along the grooves provided in the intermediate resin layer, while increasing the bonding area between the transparent substrate 1702 and the transparent resin layer. This makes it possible to improve the bonding strength between the sensor chip 1401 and the transparent substrate 1702, and also prevents voids from remaining in the transparent resin layer.

[0294] In the above-described laminated chips P17C and P17D, the groove MZ1 of the above-described fourteenth embodiment may be formed in the transparent substrate 1702. In addition, in the above-described laminated chips P17C and P17D, the intermediate resin layers 1704 and 1714 of the above-described respective laminated chips P17A and P17B may be formed on the transparent substrate 1702.

[0295] 18. Eighteenth Embodiment In the above-described fourteenth embodiment, the grooves MZ1 are provided so as to traverse the transparent substrate 1402 bonded to the sensor chip 1401 via the transparent resin layer 1403. In this eighteenth embodiment, the number or orientation of the grooves provided so as to traverse the transparent substrate bonded to the sensor chip 1401 via the transparent resin layer 1403 is changed.

[0296] 26 to 28 are plan views showing configuration examples of an electronic device according to the eighteenth embodiment. In addition, "a" in FIG. 26 shows a first example of the configuration of the electronic device according to the eighteenth embodiment. "b" in FIG. 26 shows a second example of the configuration of the electronic device according to the eighteenth embodiment. "a" in FIG. 27 shows a third example of the configuration of the electronic device according to the eighteenth embodiment. "b" in FIG. 27 shows a fourth example of the configuration of the electronic device according to the eighteenth embodiment. "a" in FIG. 28 shows a fifth example of the configuration of the electronic device according to the eighteenth embodiment. "b" in FIG. 28 shows a sixth example of the configuration of the electronic device according to the eighteenth embodiment.

[0297] 26A, an electronic device 1800 includes a transparent substrate 1801 instead of the transparent substrate 1402 of the above-described fourteenth embodiment. The other configuration of the electronic device 1800 is the same as the configuration of the electronic device 1400 of the above-described fourteenth embodiment.

[0298] The transparent substrate 1801 has grooves MZ5A. A plurality of the grooves MZ5A are arranged around the pixel region RG. The other configurations of the grooves MZ5A are the same as the configuration of the grooves MZ1 in the above-described fourteenth embodiment.

[0299] 26b, an electronic device 1810 includes a transparent substrate 1811 instead of the transparent substrate 1402 of the above-described fourteenth embodiment. The other configurations of the electronic device 1810 are similar to the configurations of the electronic device 1400 of the above-described fourteenth embodiment.

[0300] The transparent substrate 1811 has grooves MZ5B. A plurality of the grooves MZ5B are arranged parallel to the sides of the transparent substrate 1811 so as to overlap the pixel region RG. The rest of the configuration of the grooves MZ5B is the same as the configuration of the grooves MZ1 in the above-described fourteenth embodiment.

[0301] 27A, an electronic device 1820 includes a transparent substrate 1821 instead of the transparent substrate 1402 of the above-described fourteenth embodiment. The other configuration of the electronic device 1820 is similar to the configuration of the electronic device 1400 of the above-described fourteenth embodiment.

[0302] The transparent substrate 1821 has grooves MZ5C. A plurality of the grooves MZ5C are arranged parallel to the sides of the transparent substrate 1821 so as to overlap the pixel region RG and intersect at right angles with each other. The rest of the configuration of the grooves MZ5C is the same as the configuration of the grooves MZ1 in the above-described fourteenth embodiment.

[0303] 27b, an electronic device 1830 includes a transparent substrate 1831 instead of the transparent substrate 1402 of the above-described fourteenth embodiment. The other configurations of the electronic device 1830 are similar to the configurations of the electronic device 1400 of the above-described fourteenth embodiment.

[0304] The transparent substrate 1831 has grooves MZ5D. A plurality of the grooves MZ5D are arranged diagonally with respect to the sides of the transparent substrate 1831 so as to overlap the pixel region RG and intersect with each other. The rest of the configuration of the grooves MZ5D is the same as the configuration of the grooves MZ1 in the above-described fourteenth embodiment.

[0305] 28A, an electronic device 1840 includes a transparent substrate 1841 instead of the transparent substrate 1402 of the above-described fourteenth embodiment. The other configuration of the electronic device 1840 is the same as the configuration of the electronic device 1400 of the above-described fourteenth embodiment.

[0306] The transparent substrate 1841 has grooves MZ5E. A plurality of the grooves MZ5E are arranged in a curved line so as to overlap the pixel region RG. The rest of the configuration of the grooves MZ5E is the same as the configuration of the grooves MZ1 in the above-described fourteenth embodiment.

[0307] 28b, an electronic device 1850 includes a transparent substrate 1851 instead of the transparent substrate 1402 of the above-described fourteenth embodiment. The other configurations of the electronic device 1850 are similar to the configurations of the electronic device 1400 of the above-described fourteenth embodiment.

[0308] The transparent substrate 1851 has grooves MZ5F. A plurality of the grooves MZ5F are arranged around the pixel region RG in parallel to the sides of the transparent substrate 1851. Other configurations of the grooves MZ5F are the same as the configuration of the grooves MZ1 in the above-described fourteenth embodiment.

[0309] In this way, in the above-described 18th embodiment, the number of grooves provided across the transparent substrate bonded to the sensor chip 1401 via the transparent resin layer 1403 is set to two or four or more, or the grooves are set to have different orientations. This makes it possible to optimize the arrangement of the grooves depending on the chip size or the viscosity of the transparent resin, and improve the bonding strength while preventing voids from remaining in the transparent resin layer.

[0310] 19. Nineteenth Embodiment In the first embodiment described above, a recess 111 is provided in the bonding region R1 of the chip 101, and a recess 112 is provided in the bonding region R2 of the transparent substrate 102, and the pressure inside the recesses 111 and 112 is reduced. In this nineteenth embodiment, a sensor chip and an optical chip, each having a bonding surface with a plurality of surfaces, are bonded together via a bonding layer, and through electrodes are formed in the sensor chip.

[0311] FIG. 29 is a cross-sectional view showing a configuration example of an electronic device according to the nineteenth embodiment.

[0312] In the figure, the electronic device 1900 includes a stacked chip P19. The stacked chip P19 includes a sensor chip P61 and an optical chip P62. The optical chip P62 is stacked on the sensor chip P61. At this time, the optical chip P62 is bonded to the sensor chip P61 via a bonding layer 1951. Here, at least one bonding surface between the optical chip P62 and the sensor chip P61 has multiple surfaces with different normal directions. For example, a bonding surface having multiple surfaces may include at least one of a concave portion, a convex portion, and a rough surface. A bonding surface having multiple surfaces may include a mixture of concave portions and convex portions, a mixture of concave portions and rough surfaces, or a mixture of concave portions, convex portions, and rough surfaces. A bonding surface having multiple surfaces may also include a mixture of flat and curved surfaces.

[0313] The optical chip P62 is chipped to have the same size as the sensor chip P61. At this time, the horizontal end positions of the optical chip P62 can be aligned with the horizontal end positions of the sensor chip P61. This allows the sensor chip P61 to constitute a wafer-level packaged WLCSP, and the optical chip P62 to constitute a wafer-level packaged WLO (Wafer Level Optics). Note that the chip sizes of the sensor chip P61 and the optical chip P62 do not necessarily have to be equal; the chip size of the sensor chip P61 may be larger or smaller than the chip size of the optical chip P62.

[0314] A sensor element is formed on the sensor chip P61. The sensor element may be a photoelectric conversion element. Pixels may be arranged in a matrix along the row and column directions on the sensor chip P61. The sensor chip P61 may be a back-illuminated solid-state imaging element. In this case, the sensor chip P61 may be provided with a pixel region RG and a peripheral region RA. The sensor chip P61 may also be formed with a memory such as a DRAM (Dynamic Random Access Memory) and a signal processing circuit that processes pixel signals output from the effective pixel region.

[0315] The sensor chip P61 includes a support substrate 1911, a semiconductor substrate 1921, a wiring layer 1922, and a back surface wiring layer 1917. A wiring layer 1922 is formed on the front surface side of the semiconductor substrate 1921. The wiring layer 1922 is provided with wiring 1941 embedded in an insulating layer. The wiring layer 1922 is also provided with vias 1942 used for interlayer connection.

[0316] In the pixel region RG, a color filter 104 is formed for each pixel on the back surface side of the semiconductor substrate 1921. An on-chip lens 105 is formed for each pixel on the color filter 104. In this case, a photodiode can be disposed on the back surface side of the semiconductor substrate 1921.

[0317] Furthermore, a transparent sealing substrate 1923 is bonded to the back surface side of the semiconductor substrate 1921 via a transparent resin layer 1403. The transparent sealing substrate 1923 can be disposed so as to be spaced apart from the on-chip lens 105. A recess EA1 is formed in the transparent sealing substrate 1923. The recess EA1 can be formed on the bonding surface with the optical chip P62. In this case, the recess EA21 can be disposed in the peripheral region RA of the sensor chip P61. The cross-sectional shape of the recess EA1 may be, for example, rectangular.

[0318] The support substrate 1911 is bonded onto the wiring layer 1922. The support substrate 1911 and the wiring layer 1922 may be bonded together using an adhesive.

[0319] A back wiring layer 1917 is formed on the back surface side of the support substrate 1911. The back wiring layer 1917 is provided with back wiring 1915 embedded in an insulating layer such as a solder resist. A protruding electrode 1916 connected to the back wiring 1915 is formed on the back wiring layer 1917. In addition, a through electrode 1914 is formed in the support substrate 1911, penetrating the support substrate 1911 in the depth direction. The through electrode 1914 is connected to wiring 1941 and the back wiring 1915.

[0320] The material of the semiconductor substrate 1921 may be a semiconductor such as Si, GaAs, or InGaAs. The material of the insulating layer used for the wiring layer 1922 and the backside wiring layer 1917 may be, for example, SiO. ２ , SiN, or SiCN can be used. The wiring 1941, the back wiring 1915, and the via 1942 can be made of a metal such as Al, Cu, AlCu, AlSiCu, or Co. The through electrode 1914 can be made of a metal such as Cu, Ti, Ta, Al, W, Ni, Ru, or Co, or a laminated structure of multiple materials can be used. The support substrate 1911 can be made of a material such as a semiconductor, glass, or resin.

[0321] An optical system is formed on the optical chip P62. The optical chip P62 may be provided with a light-collecting region RL and a peripheral region RB. The optical system may include a lens. The optical system may include a stacked structure of multiple lens-equipped substrates. The optical system may include a transparent substrate, or may include at least one of an aperture, a light-shielding film, a spacer, and an optical filter. The optical system may include an optical component, or may include a metasurface. The optical system may include a lens, a color splitter, or a deflector made of a metasurface.

[0322] The optical chip P62 includes transparent support substrates 1952, 1955, 1958, and 1961 and lenses 1953, 1959, and 1960. The lenses 1953, 1959, and 1960 are formed on substrates 1953', 1959', and 1960', respectively. The lenses 1953, 1959, and 1960 can be disposed in the light-condensing region RL. The lens 1953 forms an image on the imaging plane. The lenses 1959 and 1960 widen the angle of view and correct chromatic aberration.

[0323] The substrate 1953' on which the lens 1953 is formed is supported on the transparent support substrate 1952 via a support member 1954 so that the lens 1953 is spaced apart from the transparent support substrate 1952. The support member 1954 can be disposed in the peripheral region RB of the optical chip P62. A recess EA2 is formed in the transparent support substrate 1952. The recess EA2 can be formed on the bonding surface with the sensor chip P61. In this case, the recess EA2 can be disposed in the peripheral region RB of the optical chip P62. The cross-sectional shape of the recess EA2 may be, for example, rectangular. Furthermore, the substrate 1953' on which the lens 1953 is formed is supported on a transparent support substrate 1955.

[0324] A substrate 1959' on which lenses 1959 are formed is supported on a transparent support substrate 1958. A substrate 1960' on which lenses 1960 are formed is supported on a transparent support substrate 1961. In addition, the substrate 1960' on which lenses 1960 are formed is bonded to the substrate 1959' on which lenses 1959 are formed.

[0325] The transparent supporting substrates 1955 and 1958 are bonded together via a bonding layer 1957. An aperture 1956 may be formed on the transparent supporting substrate 1955 at a position covered by the bonding layer 1957.

[0326] The bonding layer 1951 bonds the transparent sealing substrate 1923 and the transparent support substrate 1952. At this time, the bonding layer 1951 can penetrate into the recesses EA1 and EA2 and adhere to the opposing surfaces of the transparent sealing substrate 1923 and the transparent support substrate 1952 and the side surfaces of the recesses EA1 and EA2.

[0327] The materials of the lenses 1953, 1959, 1960 and the substrates 1953', 1959', 1960' may be transparent organic substrates such as acrylic or polycarbonate, or transparent inorganic materials such as sol-gel glass. In this case, the lenses 1953, 1959, 1960 may be formed by nanoimprinting. The materials of the lenses 1953, 1959, 1960 and the substrates 1953', 1959', 1960' may be the same as or different from each other.

[0328] The transparent support substrates 1952, 1955, 1958, and 1961 may be made of glass, or may be made of a transparent material such as sapphire, quartz, or a transparent organic substrate depending on the application. The aperture 1956 may be made of a black resin or a metal such as Cr.

[0329] The transparent sealing substrate 1923 may be a glass substrate, a quartz substrate, or a transparent resin substrate such as an acrylic or polycarbonate substrate. The transparent sealing substrate 1923 is made of Al or AlN, depending on the wavelength detected by the sensor element formed on the sensor chip P61. ２ O ３ , CaF ２ , MgF ２ Alternatively, LiF or the like may be used.

[0330] The bonding layer 1951 may be made of an organic material such as a siloxane resin, an acrylic resin, or an epoxy resin. A resin having adjusted optical properties (such as a refractive index or an extinction coefficient) may be selected for the bonding layer 1951 so that light can be received well in the effective pixel area. To improve reliability, the resin of the bonding layer 1951 may contain an inorganic or organic filler, or the bonding layer 1951 may be made of only an inorganic or metal material.

[0331] 30 to 32 are cross-sectional views showing an example of a method for manufacturing an electronic device according to the nineteenth embodiment.

[0332] 30A, partitioned regions 1901R are provided on a semiconductor wafer 1901W. Sensor chips P61 are cut out from each partitioned region 1901R. Each partitioned region 1901R is partitioned along scribe lines 1901D. A solid-state imaging element is formed in each partitioned region 1901R. At this time, the sensor chips P61 can be packaged at the wafer level to form a WLCSP.

[0333] 30b, a partitioned region 1902R is provided on an optical wafer 1902W. At this time, the partitioned regions 1901R and 1902R can be overlapped with each other. Optical chips P62 are cut out from each partitioned region 1902R. Each partitioned region 1902R is partitioned along a scribe line 1902D. The optical chips P62 can constitute a wafer-level packaged WLO.

[0334] 30A, a recess EA1 is formed in the transparent sealing substrate 1923. The recess EA1 can be formed based on lithography.

[0335] 31A, a transparent sealing substrate wafer 1923W is bonded to the back surface of a semiconductor wafer 1921W via a transparent resin layer 1403. At this time, the semiconductor wafer 1921W is supported by a support substrate wafer 1911W.

[0336] 31B, a resist pattern RP is formed on the transparent sealing substrate wafer 1923W based on lithography. An opening KA is formed in the resist pattern RP for each partitioned region 1901R. The opening KA can be arranged in the peripheral region RA for each partitioned region 1901R.

[0337] 31c, the transparent sealing substrate wafer 1923W is etched in the depth direction using the resist pattern RP as an etching mask to form recesses EA1 in the transparent sealing substrate wafer 1923W for each partitioned region 1901R. This etching may be, for example, RIE (Reactive Ion Etching).

[0338] Next, as shown in FIG. 32a, the resist pattern RP is removed from the transparent sealing substrate wafer 1923W by ashing or the like.

[0339] 32B, a bonding layer 1951 is formed on the transparent sealing substrate wafer 1923W in which the recess EA1 is formed. The bonding layer 1951 may be formed by applying a transparent resin or by attaching a transparent adhesive sheet.

[0340] 33 to 39 are cross-sectional views showing other examples of the configuration of the electronic device according to the nineteenth embodiment. Note that, in Fig. 33 to 39, the bonding layer 1951, the transparent sealing substrate 1923, and the transparent support substrate 1952 are selectively shown from the configuration of Fig. 29.

[0341] 33A, the electronic device 1900A includes recesses EB1 and EB2 instead of the recesses EA1 and EA2 of the electronic device 1900 described above. The cross-sectional shapes of the recesses EB1 and EB2 may be curved, for example, semicircular. By forming the cross-sectional shapes of the recesses EB1 and EB2 with curved surfaces, the filling ability of the bonding layer 1951 can be improved. The rest of the configuration of the electronic device 1900A is the same as that of the electronic device 1900 described above.

[0342] 33b, the electronic device 1900B has fine recesses EB1' and EB2' added to the electronic device 1900A. The fine recesses EB1' and EB2' may be provided in the recesses EB1 and EB2, or may be provided in regions other than the recesses EB1 and EB2. For example, to improve bonding strength, the fine recesses EB1' and EB2' may be provided on the entire bonding surface of the transparent sealing substrate 1923 and the entire bonding surface of the transparent support substrate 1952. In this case, the cross-sectional shapes of the fine recesses EB1' and EB2' may be curved, and may be, for example, semicircular. The rest of the configuration of the electronic device 1900B is the same as that of the electronic device 1900 described above.

[0343] 34A, the electronic device 1900C includes intermediate resin layers EC1 and EC2 instead of the recesses EA1 and EA2 of the electronic device 1900. The intermediate resin layers EC1 and EC2 are formed on a transparent sealing substrate 1923 and a transparent support substrate 1952, respectively. The intermediate resin layers EC1 and EC2 may be embedded in a bonding layer 1951. The material of the intermediate resin layers EC1 and EC2 may be the same as or different from the material of the bonding layer 1951. In this case, it is preferable to use a material with optical properties similar to those of the bonding layer 1951 to avoid any adverse effects on the optical properties. The refractive index of the intermediate resin layers EC1 and EC2 may be equal to that of the bonding layer 1951. To improve bonding strength, the adhesive strength of the intermediate resin layers EC1 and EC2 may be greater than that of the bonding layer 1951. The rest of the configuration of the electronic device 1900C is the same as that of the electronic device 1900 described above.

[0344] 34b, this electronic device 1900D has roughened surfaces ED1 and ED2 instead of the recesses EA1 and EA2 of the above-described electronic device 1900. In order to improve bonding strength, the roughened surfaces ED1 and ED2 may be provided on the entire bonding surface of the transparent sealing substrate 1923 and the entire bonding surface of the transparent support substrate 1952. Other than that, the configuration of the electronic device 1900D is the same as the configuration of the above-described electronic device 1900.

[0345] 35A, this electronic device 1900E has a recess EF instead of the recesses EA1 and EA2 of the electronic device 1900 described above. The recess EF can be formed on the bonding surface of the transparent support substrate 1952. In this case, the recess EF can be arranged in the light-condensing region RL of the optical chip P62 to reduce the effect on the optical characteristics. The rest of the configuration of the electronic device 1900E is the same as the configuration of the electronic device 1900 described above.

[0346] 35b, this electronic device 1900F has a protrusion EG1 and a recess EG2 instead of the recesses EA1 and EA2 of the electronic device 1900 described above. The protrusion EG1 and the recess EG2 can be formed on the bonding surface of the transparent sealing substrate 1923 and the bonding surface of the transparent support substrate 1952, respectively. The protrusion EG1 can be inserted into the recess EG2 with a gap therebetween. At this time, the transparent sealing substrate 1923 and the transparent support substrate 1952 can be self-aligned. The rest of the configuration of the electronic device 1900F is the same as the configuration of the electronic device 1900 described above.

[0347] 36 a, the recess EA2 of the electronic device 1900 described above has been removed from this electronic device 1900G. At this time, it is no longer necessary to form the recess EA2 in the transparent support substrate 1952, and the number of steps can be reduced. The rest of the configuration of the electronic device 1900G is the same as that of the electronic device 1900 described above.

[0348] 36B, the recess EA1 of the electronic device 1900 described above has been removed from the electronic device 1900H. At this time, it is no longer necessary to form the recess EA1 in the transparent sealing substrate 1923, thereby reducing the number of steps. The rest of the configuration of the electronic device 1900H is the same as that of the electronic device 1900 described above.

[0349] 37A, this electronic device 1900I has a recess EH instead of the recesses EA1 and EA2 of the electronic device 1900 described above. The recess EH may be provided on the entire bonding surface of the transparent support substrate 1952 to improve bonding strength. In this case, there is no need to form the recess EA1 in the transparent sealing substrate 1923, and the number of processes can be reduced. The rest of the configuration of the electronic device 1900I is the same as the configuration of the electronic device 1900 described above.

[0350] 37 b, this electronic device 1900J has a recess ED2 instead of the recess EA2 of the above-described electronic device 1900. Here, by making the shapes, sizes, and positions of the recesses different between the transparent sealing substrate 1923 and the transparent support substrate 1952, it is possible to improve the bonding strength while compensating for the optical characteristics. The rest of the configuration of the electronic device 1900J is the same as the configuration of the above-described electronic device 1900.

[0351] 38A, the electronic device 1900K includes bonding layers 1951A and 1951B instead of the bonding layer 1951 of the electronic device 1900 described above. The bonding layer 1951A is disposed at the position of the recesses EA1 and EA2, and the bonding layer 1951B is disposed between the bonding layers 1951A. The bonding layers 1951A and 1951B can be made of different materials. By varying the composition of the bonding layers 1951A and 1951B, the adhesive strength, Young's modulus, amount of cure shrinkage, and thermal shrinkage rate can be controlled, thereby increasing the bonding strength and preventing warping. The rest of the configuration of the electronic device 1900K is the same as that of the electronic device 1900 described above.

[0352] 38b, this electronic device 1900L includes bonding layers 1951C and 1951D instead of the bonding layer 1951 of the electronic device 1900 described above. Furthermore, the recess EA1 of the electronic device 1900 described above has been removed from this electronic device 1900L. The bonding layer 1951D is stacked on the bonding layer 1951C. By changing the composition of the bonding layers 1951C and 1951D, the adhesive strength, Young's modulus, amount of cure shrinkage, and thermal shrinkage rate can be controlled, thereby increasing the bonding strength and preventing warping. The rest of the configuration of the electronic device 1900L is the same as that of the electronic device 1900 described above.

[0353] 39 a, the electronic device 1900M has an optical filter layer 1965 added to the electronic device 1900 described above. The optical filter layer 1965 can be formed on the bonding surface of the transparent support substrate 1952 so as to cover the side and bottom surfaces of the recess EA2. At this time, the bonding layer 1951 is bonded to the transparent support substrate 1952 via the optical filter layer 1965. The optical filter layer 1965 may be a dielectric multilayer film. The rest of the configuration of the electronic device 1900M is the same as the configuration of the electronic device 1900 described above.

[0354] 39b, the electronic device 1900N has a cavity 1966 added to the electronic device 1900 described above. The cavity 1966 can be formed in a transparent support substrate 1952. In this case, the cavity 1966 can be disposed in the light-condensing region RL of the optical chip P62 to reduce the effect on the optical characteristics. The rest of the configuration of the electronic device 1900N is the same as the configuration of the electronic device 1900 described above.

[0355] As described above, in the nineteenth embodiment, the sensor chip P61 and the optical chip P62, each having a bonding surface with multiple surfaces, are bonded via the bonding layer 1951. This makes it possible to increase the bonding area of ​​the bonding surface between the sensor chip P61 and the optical chip P62 while suppressing an increase in the size of the electronic device 1900. This makes it possible to miniaturize the electronic device 1900 while suppressing a decrease in the reliability of the electronic device 1900.

[0356] 20. Twentieth Embodiment In the first embodiment described above, the sensor chip P61 and the optical chip P62, each having a bonding surface with multiple faces, are bonded via a bonding layer 1951. In this twentieth embodiment, the number, size, shape, or orientation of the recesses or protrusions provided on the bonding surfaces of the sensor chip P61 and the optical chip P62 are made different.

[0357] 40 to 44 are plan views showing configuration examples of an electronic device according to the twentieth embodiment.

[0358] 40 to 44 show an example in which a recess is formed in the transparent sealing substrate 1923, but a similar recess may also be formed in the transparent support substrate 1952. Furthermore, instead of forming a recess in the transparent sealing substrate 1923, a protrusion may be formed in the transparent sealing substrate 1923.

[0359] 40A, the electronic device 2000A includes a recess EA11. The recess EA11 can be disposed at the four corners of the bonding surface of the transparent sealing substrate 1923. The planar shape of the recess EA11 can be rectangular. The rest of the configuration of the electronic device 2000A is the same as the configuration of the electronic device 1900 described above.

[0360] 40 b, the electronic device 2000B includes a recess EA12. The recess EA12 can be disposed on both ends of the bonding surface of the transparent sealing substrate 1923. In this case, the recess EA12 may be a groove that traverses the transparent sealing substrate 1923. The recess EA12 may be disposed in the vertical direction or the horizontal direction. The other configurations of the electronic device 2000B are the same as those of the electronic device 1900 described above.

[0361] 41 a, the electronic device 2000C includes a recess EA13. The recess EA13 can be disposed in a corner of the bonding surface of the transparent sealing substrate 1923. In this case, the recess EA13 may be a groove that diagonally crosses the corner of the transparent sealing substrate 1923. Other configurations of the electronic device 2000C are similar to those of the electronic device 1900 described above.

[0362] 41 b, the electronic device 2000D includes a recess EA14. The recess EA14 can be disposed over the entire bonding surface of the transparent sealing substrate 1923 to improve bonding strength. In this case, the recess EA14 can be disposed in the pixel region RG and the peripheral region RA. For example, the recess EA14 may be grooves disposed at equal intervals in the transparent sealing substrate 1923. The recess EA14 may be disposed in the vertical direction or the horizontal direction. The rest of the configuration of the electronic device 2000D is the same as that of the electronic device 1900 described above.

[0363] 42 a, the electronic device 2000E includes a recess EA15. The recess EA15 can be disposed over the entire bonding surface of the transparent sealing substrate 1923 to improve bonding strength. In this case, the recess EA15 can be disposed in the pixel region RG and the peripheral region RA. The recess EA15 can be disposed in the vertical direction and the horizontal direction. For example, the recess EA15 may be a groove arranged in a lattice pattern. The rest of the configuration of the electronic device 2000E is the same as that of the electronic device 1900 described above.

[0364] 42 b, the electronic device 2000F includes a recess EA16. The recess EA16 can be disposed on the bonding surface of the transparent sealing substrate 1923 at a position overlapping the pixel region RG to avoid any influence on the optical characteristics. In this case, the planar shape of the recess EA16 can be rectangular. The rest of the configuration of the electronic device 2000F is the same as the configuration of the electronic device 1900 described above.

[0365] 43 a, the electronic device 2000G includes a recess EA17. The recess EA17 can be arranged along the edge of the bonding surface of the transparent sealing substrate 1923 to avoid any influence on the optical characteristics. In this case, the planar shape of the recess EA17 can be set to a range that surrounds the pixel region RG so as to contact the edge of the bonding surface of the transparent sealing substrate 1923. Other configurations of the electronic device 2000G are the same as those of the electronic device 1900 described above.

[0366] 43b, the electronic device 2000H includes a recess EA18. The recess EA18 can be arranged on the bonding surface of the transparent sealing substrate 1923 along the peripheral region RB of the sensor chip P61 to avoid any influence on the optical characteristics. In this case, the planar shape of the recess EA18 can be set to the range surrounded by the double line around the pixel region RG. The rest of the configuration of the electronic device 2000H is the same as the configuration of the electronic device 1900 described above.

[0367] 44, the electronic device 2000I includes a recess EA19. The recess EA19 can be arranged on the bonding surface of the transparent sealing substrate 1923 along the peripheral region RB of the sensor chip P61 to avoid any influence on the optical characteristics. An extension portion TAB is also added to the recess EA19. The extension portion TAB extends to the edge of the bonding surface of the sealing substrate 1923. The extension portion TAB can be used to control the filling amount of resin used in the bonding layer 1951. The rest of the configuration of the electronic device 2000I is similar to that of the electronic device 1900 described above.

[0368] In this way, in the twentieth embodiment described above, the number, size, shape, or orientation of the recesses or protrusions provided on the bonding surfaces of the sensor chip P61 and the optical chip P62 are made different, which makes it possible to adjust the bonding strength according to the chip size, prevent warping, and optimize the optical characteristics.

[0369] 21. Twenty-first embodiment In the nineteenth embodiment described above, the sensor chip P61 and the optical chip P62, each having a bonding surface with multiple faces, are bonded together via a bonding layer 1951, and the through electrodes 1914 are formed on the sensor chip P61. In this twenty-first embodiment, the sensor chip and the optical chip, each having a bonding surface with multiple faces, are bonded together via a bonding layer, and side contacts are formed on the sensor chip.

[0370] FIG. 45 is a cross-sectional view showing a configuration example of an electronic device according to the twenty-first embodiment.

[0371] 45, an electronic device 2000 includes a stacked chip P20 instead of the stacked chip P19 of the above-described nineteenth embodiment. The stacked chip P20 includes a sensor chip P71 and an optical chip P72 instead of the sensor chip P61 and the optical chip P62 of the above-described nineteenth embodiment. The sensor chip P71 and the optical chip P72 are bonded to each other via a bonding layer 1951. The chip size of the sensor chip P71 and the chip size of the optical chip P72 may be the same or different.

[0372] The sensor chip P71 has side wiring 2014 instead of the through electrode 1914 of the above-described nineteenth embodiment. The side wiring 2014 connects the back surface wiring 1915 to the wiring 1941 via the side surface of the support substrate 1911. The rest of the configuration of the stacked chip P20 of the twenty-first embodiment is the same as the configuration of the stacked chip P19 of the above-described nineteenth embodiment.

[0373] The optical chip P72 includes a support member 2004 instead of the support member 1954 of the above-described nineteenth embodiment. Furthermore, the optical chip P72 includes optical filters 2001 and 2002 and a light-shielding film 2003 in addition to the optical chip P62 of the above-described nineteenth embodiment.

[0374] The optical filter 2001 is formed on a transparent support substrate 1952. The optical filter 2001 can attenuate unnecessary wavelength components.

[0375] The support member 2004 supports the substrate 1953′ on the transparent support substrate 1952 so that the lens 1953 is spaced apart from the optical filter 2001. The support member 2004 can be disposed in the peripheral region RB of the optical chip P72. The inner peripheral surface of the support member 2004 may be inclined.

[0376] The light-shielding film 2003 is formed on the transparent support substrate 1961. The light-shielding film 2003 can be disposed in the peripheral region RB of the optical chip P72. The material of the light-shielding film 2003 may be a black resin or a metal such as Cr.

[0377] The optical filter 2002 is formed on the transparent support substrate 1961 so as to cover the light-shielding film 2003. The optical filter 2002 can attenuate unnecessary wavelength components.

[0378] FIG. 46 is a cross-sectional view showing an example of a method for manufacturing an electronic device according to the twenty-first embodiment.

[0379] As shown in FIG. 11A, the support member 2004 to which the transparent support substrate wafer 1955W is bonded is bonded to the substrate 1953′. An adhesive may be used for this bonding. A bonding layer 1951 is formed on the transparent sealing substrate wafer 1923W in which the recesses EA1 are formed for each partitioned region 1901R. The side wiring 2014 may be embedded in the support substrate wafer 1911W, or may be formed on the side surface of the sensor chip P71 after the sensor chip P71 is solidified. To form the side wiring 2014 on the side surface of the sensor chip P71, a molded interconnect device (MID) method or 3D printing may be used.

[0380] Next, as shown in FIG. 19B, the transparent sealing substrate wafer 1923W and the transparent support substrate wafer 1952W are bonded together via a bonding layer 1951.

[0381] 45, the laminated wafers bonded via the bonding layer 1951 are cut into individual laminated chips P21. The cutting of the laminated wafers may be performed using a blade dicing or a laser cutter.

[0382] As described above, in the twenty-first embodiment, the sensor chip P71 and the optical chip P72, each having a bonding surface with multiple surfaces, are bonded via the bonding layer 1951, and side contacts are formed on the sensor chip P71. This makes it possible to contact the sensor chip P71 with the outside without needing to form the through electrodes 1914, and also makes it possible to increase the bonding strength between the sensor chip P71 and the optical chip P72 while suppressing an increase in the size of the electronic device 2000.

[0383] 22. Twenty-Second Embodiment In the nineteenth embodiment described above, the sensor chip P61 and the optical chip P62, each having a bonding surface with multiple surfaces, are bonded via a bonding layer 1951. In this twenty-second embodiment, the sensor chip and the optical chip are directly bonded via the bonding surface with multiple surfaces.

[0384] FIG. 47 is a cross-sectional view illustrating a configuration example of an electronic device according to the twenty-second embodiment.

[0385] In the figure, an electronic device 2200 includes a stacked chip P22 instead of the stacked chip P19 of the above-described 19th embodiment. The stacked chip P22 includes a sensor chip P81 and an optical chip P82 instead of the sensor chip P61 and the optical chip P62 of the above-described 19th embodiment.

[0386] The sensor chip P81 has a convex portion PA1 instead of the concave portion EA1 of the above-described nineteenth embodiment. The optical chip P82 has a concave portion PA2 instead of the concave portion EA2 of the above-described nineteenth embodiment. The convex portion PA1 can be inserted into the concave portion PA2. At this time, the position from the side surface of the stacked chip P22 to the convex portion PA1 and the position from the side surface of the stacked chip P22 to the concave portion PA2 can be made equal to each other. Here, the sensor chip P81 and the optical chip P82 are directly bonded with the convex portion PA1 inserted into the concave portion PA2. The other configurations of the stacked chip P22 of the twenty-second embodiment are the same as the configuration of the stacked chip P19 of the above-described nineteenth embodiment.

[0387] Pressure bonding can be used to directly bond the sensor chip P81 and the optical chip P82. This pressure bonding can be performed, for example, at temperatures below 250°C after plasma activation of the bonding surfaces. This plasma activation can include SiO2 content on the bonding surfaces. Oxygen or nitrogen plasma can then be irradiated onto the bonding surfaces to hydrophilize them. The bonding surfaces can then be bonded together based on hydrogen bonds between OH groups formed on the bonding surfaces by adsorption of moisture from the air. Heat treatment can then decompose the OH groups, diffusing the resulting hydrogen into the interface layer, achieving direct bonding based on oxygen-mediated Si-O-Si bonds. Plasma activation of the bonding surfaces before heat treatment can improve the moisture adsorption properties of the bonding surfaces, enabling the bonding strength required to ensure the reliability of solid-state imaging devices to be achieved, even with heat treatment at temperatures below 250°C.

[0388] In this way, in the above-described 22nd embodiment, the sensor chip P81 and the optical chip P82 are directly bonded together with the convex portion PA1 inserted into the concave portion PA2, thereby improving the bonding strength between the sensor chip P81 and the optical chip P82 while easing restrictions on the temperature resistance and light transmittance of the bonding surfaces between the sensor chip P81 and the optical chip P82.

[0389] 23. Twenty-third embodiment In the nineteenth embodiment described above, the sensor chip P61 and the optical chip P62, each having a bonding surface with a plurality of faces, are bonded via a bonding layer 1951. In this twenty-third embodiment, a recess with a vacuum inside is provided on each of the bonding surface of the sensor chip and the bonding surface of the optical chip.

[0390] FIG. 48 is a cross-sectional view illustrating a configuration example of an electronic device according to the twenty-third embodiment.

[0391] In the figure, an electronic device 2300 includes a stacked chip P23 instead of the stacked chip P19 of the above-described 19th embodiment. The stacked chip P23 includes a sensor chip P91 and an optical chip P92 instead of the sensor chip P61 and the optical chip P62 of the above-described 19th embodiment.

[0392] The sensor chip P91 has a recess HA1 instead of the recess EA1 of the above-described nineteenth embodiment. The optical chip P92 has a recess HA2 instead of the recess EA2 of the above-described nineteenth embodiment. A through-hole HA3 is formed in the adhesive layer 103. The horizontal position of the through-hole HA3 can be aligned with the horizontal position of the recess HA1. The recesses HA1, HA2, and through-hole HA3 can be configured similarly to the recesses 111, 112, and through-hole 113 of the above-described first embodiment, respectively.

[0393] The recesses HA1 and HA2 and the through-hole HA3 are hollowed out. At this time, the pressure in the recesses HA1 and HA2 and the through-hole HA3 can be set lower than atmospheric pressure. For example, the pressure in the recesses HA1 and HA2 and the through-hole HA3 can be set lower than atmospheric pressure. －５ In this case, the components in the recesses HA1, HA2 and through-hole HA3 may be the same as or different from the components of the atmosphere. ３ It may be filled with a gas such as

[0394] As described above, in the 23rd embodiment, the bonding surfaces of the sensor chip P91 and the optical chip P92 are provided with evacuated recesses HA1 and HA2, respectively. This makes it possible to suppress the conduction of heat generated around the sensor chip P91 and the optical chip P92 at the positions of the recesses HA1 and HA2, making it difficult for heat to be transmitted to the pixel region RG. This makes it possible to suppress thermal damage to the pixel region RG and prevent deterioration of the color filter 104 and the on-chip lens 105.

[0395] Furthermore, by maintaining the interiors of the recesses HA1 and HA2 in a vacuum state or under low pressure, the optical chip P92 can be pressed against the sensor chip P91 by the action of atmospheric pressure, which improves the bonding strength between the optical chip P92 and the sensor chip P91, thereby ensuring the reliability of the electronic device 2300 while reducing the chip size.

[0396] 24. Twenty-fourth embodiment In the nineteenth embodiment described above, the sensor chip P61 and the optical chip P62, each having a bonding surface with a plurality of faces, are bonded via a bonding layer 1951. In this twenty-fourth embodiment, a recess is provided in the bonding surface of the transparent sealing substrate of the sensor chip.

[0397] FIG. 49 is a cross-sectional view showing a configuration example of an electronic device according to the twenty-fourth embodiment.

[0398] In the figure, an electronic device 2400 includes a stacked chip P24 instead of the stacked chip P19 of the above-described nineteenth embodiment. The stacked chip P24 includes a sensor chip P101 instead of the sensor chip P61 of the above-described nineteenth embodiment.

[0399] The sensor chip P101 includes a transparent sealing substrate 2023 instead of the transparent sealing substrate 1923 of the nineteenth embodiment described above. The transparent sealing substrate 2023 is obtained by adding a recess TA to the transparent sealing substrate 1923 of the nineteenth embodiment described above. The recess TA is formed on the adhesive surface of the transparent resin layer 1403. The recess TA can be disposed in the peripheral region RA so as not to affect the optical characteristics of the pixel region RG. The transparent resin layer 1403 can enter the recess TA when the transparent sealing substrate 2023 is bonded to the semiconductor substrate 1921 via the transparent resin layer 1403. The other configurations of the sensor chip P101 are the same as those of the sensor chip P61 of the nineteenth embodiment described above.

[0400] As described above, in the 24th embodiment, the recess TA is provided on the bonding surface of the transparent sealing substrate 2023 of the sensor chip P101. This increases the bonding area of ​​the transparent sealing substrate 2023, and improves the bonding strength of the transparent sealing substrate 2023 without increasing the chip size of the sensor chip P101.

[0401] The configuration in which the recess TA is provided on the bonding surface of the transparent sealing substrate 2023 of the sensor chip P101 may be applied to any of the electronic devices according to the nineteenth to twenty-third embodiments described above.

[0402] 25. Twenty-fifth embodiment In the above-described nineteenth embodiment, the sensor chip P61 and the optical chip P62, each having a bonding surface with a plurality of surfaces, are bonded via a bonding layer 1951. In this twenty-fifth embodiment, a recess is provided in the support surface of the transparent support substrate of the optical chip.

[0403] FIG. 50 is a cross-sectional view showing a configuration example of an electronic device according to the twenty-fifth embodiment.

[0404] In the figure, an electronic device 2500 includes a laminated chip P25 instead of the laminated chip P19 of the above-described nineteenth embodiment. The laminated chip P25 includes an optical chip P112 instead of the optical chip P62 of the above-described nineteenth embodiment.

[0405] The optical chip P112 includes a transparent support substrate 2052 and a support member 2054 instead of the transparent support substrate 1952 and the support member 1954 of the above-described nineteenth embodiment. The transparent support substrate 2052 is obtained by adding a recess TB to the transparent support substrate 1952 of the above-described nineteenth embodiment. The recess TB is formed on the support surface of the transparent support substrate 2052. The recess TB can be arranged at a position where the protrusion TC of the support member 2054 can be inserted.

[0406] The support member 2054 has a convex portion TC added to the support member 1954 of the above-described nineteenth embodiment. The convex portion TC is formed on the bonding surface with the transparent support substrate 2052. The convex portion TC can be inserted into the concave portion TB. The other configurations of the optical chip P112 are the same as the configuration of the optical chip P62 of the above-described nineteenth embodiment.

[0407] As described above, in the 24th embodiment, a recess TB is provided on the support surface of the transparent support substrate 2052 of the optical chip P112, and a protrusion TC that can be inserted into the recess TB is provided on the support member 2054. This increases the bonding area of ​​the support surface of the transparent support substrate 2052, and improves the bonding strength of the support surface of the transparent support substrate 2052 without increasing the chip size of the optical chip P112.

[0408] The configuration in which the recess TB is provided on the support surface of the transparent support substrate 2052 of the optical chip P112 may be applied to any of the electronic devices according to the nineteenth to twenty-fourth embodiments described above.

[0409] 26. Twenty-sixth Embodiment In the above-described nineteenth embodiment, the chip size of the sensor chip P61 and the chip size of the optical chip P62 are equal. In this twenty-sixth embodiment, the chip size of the optical chip is made smaller than the chip size of the sensor chip P61.

[0410] FIG. 51 is a cross-sectional view showing a configuration example of an electronic device according to the twenty-sixth embodiment.

[0411] In the figure, an electronic device 2600 includes a laminated chip P26 instead of the laminated chip P19 of the above-described nineteenth embodiment. The laminated chip P26 includes an optical chip P122 instead of the optical chip P62 of the above-described nineteenth embodiment.

[0412] The chip size of the optical chip P122 is smaller than that of the sensor chip P61. In this case, the horizontal end positions of the sensor chip P61 can extend beyond the horizontal end positions of the optical chip P122. Other configurations of the optical chip P122 are similar to the configuration of the optical chip P62 of the above-described 19th embodiment.

[0413] In this way, in the twenty-sixth embodiment described above, the chip size of the optical chip P122 is made smaller than the chip size of the sensor chip P61. This allows dicing to cut out the sensor chip P61 and dicing to cut out the optical chip P122 to be performed separately. This allows the chip thickness restriction on the stacked chip P26 during dicing to be relaxed.

[0414] 27. Twenty-seventh embodiment In the twenty-sixth embodiment described above, the chip size of the optical chip P122 is made smaller than the chip size of the sensor chip P61. In this twenty-seventh embodiment, the chip size of the optical chip P122 is made smaller than the chip size of the sensor chip P61, and the bonding layer 1951 protrudes onto the side surface of the optical chip P122.

[0415] FIG. 52 is a cross-sectional view showing a configuration example of an electronic device according to the twenty-seventh embodiment.

[0416] In the same figure, the electronic device 2700 includes a stacked chip P27 instead of the stacked chip P19 of the above-described nineteenth embodiment. The stacked chip P27 includes a sensor chip P61 and an optical chip P122. The sensor chip P61 is bonded to the optical chip P122 via a bonding layer 1951. At this time, the bonding layer 1951 can protrude onto the side surface of the transparent support substrate 1952. For example, the bonding layer 1951 may creep up the side surface of the transparent support substrate 1952.

[0417] As described above, in the 27th embodiment, the chip size of the optical chip P122 is made smaller than the chip size of the sensor chip P61, and the bonding layer 1951 protrudes onto the side surface of the optical chip P122. This makes it possible to increase the bonding strength between the sensor chip P61 and the optical chip P122 while easing the constraints on the chip thickness of the stacked chip P27 during dicing.

[0418] 28. Twenty-eighth Embodiment In the above-described nineteenth embodiment, the sensor chip P61 and the optical chip P62, each having a bonding surface with a plurality of surfaces, are bonded via a bonding layer 1951. In this twenty-eighth embodiment, in the transparent substrate bonded to the sensor chip via the transparent resin layer 1403, the wettability of the opposing region facing the pixel region RG of the sensor chip is made higher than the wettability of the adjacent region adjacent to the opposing region.

[0419] 53 is a diagram showing a configuration example of an electronic device according to the 28th embodiment. In the figure, "a" is a cross-sectional view showing a configuration example obtained by cutting an electronic device 2800 in the vertical direction, and "b" is a plan view showing a configuration example of a transparent substrate 2801. "a" in the figure shows a configuration cut at the position of line A1-A2 in "b" in the figure.

[0420] In the figure, the electronic device 2800 includes a stacked chip P280. The stacked chip P280 includes a sensor chip SCP and a transparent substrate 2801. The transparent substrate 2801 is stacked on the sensor chip SCP via a transparent resin layer 1403. Here, the transparent substrate 2801 is diced to have the same size as the sensor chip SCP. At this time, the position of the horizontal edge of the transparent substrate 2801 can be aligned with the position of the horizontal edge of the sensor chip SCP. This allows the stacked chip P280 to form a WLCSP packaged at the wafer level.

[0421] The sensor chip SCP is the same as the sensor chip P61 of the above-described 19th embodiment except that the transparent sealing substrate 1923 has been removed. The other configurations of the electronic device 2800 are the same as the configurations of the sensor chip P61 of the above-described 19th embodiment.

[0422] The transparent substrate 2801 includes multiple surfaces with different wettability. The transparent substrate 2801 includes a facing region RK and an adjacent region RS. The facing region RK faces the pixel region RG of the sensor chip SCP. The adjacent region RS is adjacent to the facing region RK. The adjacent region RS may be disposed around the facing region RK. The wettability of the facing region RK is higher than that of the adjacent region RS. In order to make the wettability of the facing region RK higher than that of the adjacent region RS, a film layer 2802 may be formed in the facing region RK. In this case, the wettability of the surface of the film layer 2802 can be higher than that of the surface of the transparent substrate 2801. For example, if the transparent substrate 2801 is made of glass, the material of the film layer 2802 may be SiO ２ In this case, SiO ２ By controlling the film formation conditions and composition of SiN, ２ The wettability of SiN can be made higher than that of glass.

[0423] FIG. 54 is a diagram illustrating an example of a method for manufacturing an electronic device according to the twenty-eighth embodiment.

[0424] In the figure, a transparent substrate wafer 2801W is provided with partitioned regions 2801R. A transparent substrate 2801 is cut out from each partitioned region 2801R. Each partitioned region 2801R is partitioned along a scribe line 2801D.

[0425] In FIG. 2B, partitioned regions 2800R are provided on a semiconductor wafer 2800W. Sensor chips SCP are cut out from each partitioned region 2800R. Each partitioned region 2800R is partitioned along a scribe line 2800D. A solid-state imaging element is formed in each partitioned region 2800R.

[0426] A transparent substrate wafer 2801W is stacked on the semiconductor wafer 2800W. At this time, a transparent resin layer 1403 is formed on the entire surface of the semiconductor wafer 2800W. The transparent resin layer 1403 may be formed by coating, printing, spin coating, or potting. The transparent substrate wafer 2801W is then fixed onto the semiconductor wafer 2800W via the transparent resin layer 1403.

[0427] After the transparent substrate wafer 2801W is stacked on the semiconductor wafer 2800W, protruding electrodes 1916 can be formed on the back surface side of the semiconductor wafer 2800W. Thereafter, the stacked wafers of the semiconductor wafer 2800W and the transparent substrate wafer 2801W can be cut along the scribe lines 2800D and 2801D to cut out the stacked chips P280.

[0428] 55 is a diagram showing an example of a manufacturing method for an electronic device according to the twenty-eighth embodiment. In the figure, "a" is a plan view showing an example of a manufacturing method for an electronic device 2800, and "b" and "c" are cross-sectional views showing an example of a manufacturing method for an electronic device 2800. Note that the figure excerpts a bonding process between a semiconductor wafer 2800W and a transparent substrate wafer 2801W. Also, "a" in the figure shows a 2×2 partitioned region 2801R of the transparent substrate wafer 2801W, and "b" and "c" in the figure show two adjacent partitioned regions 2800R, 2801R.

[0429] In FIG. 28A, the film layer 2802 is formed for each divided region 2801R.

[0430] As shown in FIG. 1B, a light receiving layer 2803 is provided for each divided region 2800R on the semiconductor wafer 2800W. Each light receiving layer 2803 can be arranged in a pixel region RG. In this case, pixels are arranged in a matrix in the row and column directions on each light receiving layer 2803. A transparent substrate wafer 2801W is then stacked on the semiconductor wafer 2800W with a transparent resin layer 1403 interposed therebetween.

[0431] Here, as shown in c in the figure, the surface of the film deposition layer 2802 has higher wettability than the surface of the transparent substrate wafer 2801W, so the transparent resin layer 1403 spreads over the film deposition layer 2802. At this time, the void VOD is expelled from between the film deposition layer 2802 and the transparent resin layer 1403. Therefore, the void VOD can be moved between the film deposition layers 2802, and the void VOD on the light receiving layer 2803 can be eliminated.

[0432] FIG. 56 is a cross-sectional view showing an example of a method for manufacturing an electronic device according to the twenty-eighth embodiment.

[0433] In FIG. 28A, a film layer 2802 is formed on a transparent substrate wafer 2801W by coating, CVD, sputtering or other methods.

[0434] Next, as shown in b in the figure, a resist pattern RPA is formed based on lithography technology. The resist pattern RPA can be separated into each divided region 2800R so as to cover the opposing region RK.

[0435] Next, as shown in c in the figure, the film layer 2802 is etched using the resist pattern RPA as an etching mask to separate it into each divided region 2800 R. Then, the resist pattern RPA is removed by ashing or other method.

[0436] FIG. 57 is a cross-sectional view showing another example of the method for manufacturing an electronic device according to the twenty-eighth embodiment.

[0437] In the figure, a film layer 2802' is formed on a transparent substrate wafer 2801W by coating, CVD, sputtering, etc. A photosensitive material can be used for the film layer 2802'.

[0438] Next, as shown in b in the figure, the film layer 2802′ is exposed and developed to pattern the film layer 2802′. At this time, the film layer 2802′ can be separated into each divided region 2800R so that the opposing region RK is covered.

[0439] FIG. 58 is a cross-sectional view showing still another example of the method for manufacturing an electronic device according to the twenty-eighth embodiment.

[0440] In the same figure, a film forming material 2802Z is ​​ejected from a nozzle NZL by an inkjet method to form a film forming layer 2802" on a transparent substrate wafer 2801W. At this time, the film forming layer 2802" can be separated into each partitioned region 2800R so that the opposing region RK is covered.

[0441] 59 is a plan view showing another example of the configuration of an electronic device according to the twenty-eighth embodiment. In this figure, a 3×3 partitioned region 2801R is shown on a transparent substrate wafer 2801W.

[0442] In the figure, a film layer 2805 is formed on the transparent substrate wafer 2805W so as to cover the opposing region RK of each divided region 2801R. At this time, in the vertical direction of the transparent substrate wafer 2805W, the film layer 2805 is separated for every three divided regions 2801R. In the horizontal direction of the transparent substrate wafer 2805W, the film layer 2805 is separated for every one divided region 2801R.

[0443] In the figure, a film layer 2806 is formed on the transparent substrate wafer 2806W so as to cover the opposing regions RK of each divided region 2801R. At this time, in the horizontal direction of the transparent substrate wafer 2806W, the film layer 2806 is separated into three divided regions 2801R. In the vertical direction of the transparent substrate wafer 2806W, the film layer 2806 is separated into one divided region 2801R.

[0444] Note that Figure 59 shows an example in which the film formation layers are separated into three partition areas 2801R in the vertical or horizontal direction of each transparent substrate wafer 2805W, 2806W, but the film formation layers may also be separated into two or more partition areas 2801R in the vertical or horizontal direction of each transparent substrate wafer 2805W, 2806W.

[0445] FIG. 60 is a cross-sectional view showing still another configuration example of the electronic device according to the twenty-eighth embodiment.

[0446] In FIG. 53A, an electronic device 2810 includes a stacked chip P281. The stacked chip P281 includes a transparent substrate 2811 instead of the transparent substrate 2801 in FIG. 53. Other than that, the configuration of the stacked chip P281 is the same as the configuration of the stacked chip P280 in FIG.

[0447] The transparent substrate 2811 includes an ion implantation layer 2812 instead of the deposition layer 2802 in Fig. 53. Other configurations of the transparent substrate 2811 are the same as those of the transparent substrate 2801 in Fig. 53.

[0448] The ion implantation layer 2812 is formed at the position of the opposing region RK of the transparent substrate 2811. The wettability of the surface of the ion implantation layer 2812 is higher than the wettability of the surface of the adjacent region RS of the transparent substrate 2811. In this case, the surface of the ion implantation layer 2812 can be made more hydrophilic than the surface of the transparent substrate 2811.

[0449] In b of the figure, an electronic device 2820 includes a stacked chip P282. The stacked chip P282 includes a transparent substrate 2821 instead of the transparent substrate 2801 of Fig. 53. Other than that, the configuration of the stacked chip P282 is the same as the configuration of the stacked chip P280 of Fig. 53.

[0450] The transparent substrate 2821 includes a surface modification layer 2822 instead of the film formation layer 2802 in Fig. 53. Other configurations of the transparent substrate 2821 are the same as those of the transparent substrate 2801 in Fig. 53.

[0451] The surface modification layer 2822 is formed at the position of the opposing region RK of the transparent substrate 2821. The wettability of the surface of the surface modification layer 2822 is higher than the wettability of the surface of the adjacent region RS of the transparent substrate 2821. In this case, the surface of the surface modification layer 2822 can be made more hydrophilic than the surface of the transparent substrate 2821. The surface modification layer 2822 can, for example, bond hydrophilic elements to dangling bonds on the surface of the transparent substrate 2821.

[0452] As described above, in the 28th embodiment, the wettability of the facing region RK of the transparent substrate 2801 bonded to the sensor chip SCP via the transparent resin layer 1403 is made higher than the wettability of the adjacent region RS. This makes it possible to expel voids VOD that occur in the transparent resin layer 1403 when the sensor chip SCP and the transparent substrate 2801 are bonded together, from above the pixel region RG, thereby reducing pixel defects caused by the voids VOD.

[0453] 29. Twenty-ninth embodiment In the twenty-eighth embodiment described above, the wettability of the facing region RK of the transparent substrate 2801 bonded to the sensor chip SCP via the transparent resin layer 1403 is made higher than the wettability of the adjacent region RS. In this twenty-ninth embodiment, the wettability of the adjacent region RS of the transparent substrate 2801 bonded to the sensor chip SCP via the transparent resin layer 1403 is made lower than the wettability of the facing region RK.

[0454] 61 is a diagram showing a configuration example of an electronic device according to the 29th embodiment. In the figure, "a" is a cross-sectional view showing a configuration example obtained by cutting an electronic device 2900 vertically, and "b" is a plan view showing a configuration example of a transparent substrate 2901. "a" in the figure shows a configuration cut at the position of line A1-A2 in "b" in the figure.

[0455] In the figure, an electronic device 2900 includes a stacked chip P290 instead of the stacked chip P280 of the twenty-eighth embodiment. The stacked chip P290 includes a transparent substrate 2901 instead of the transparent substrate 2801 of the twenty-eighth embodiment. The rest of the configuration of the stacked chip P290 is the same as the configuration of the stacked chip P280 of the twenty-eighth embodiment.

[0456] The transparent substrate 2901 includes a film layer 2902 instead of the film layer 2802 of the twenty-eighth embodiment. The other configuration of the transparent substrate 2901 is the same as the configuration of the transparent substrate 2801 of the twenty-eighth embodiment.

[0457] The deposition layer 2902 is formed at the position of the adjacent region RS of the transparent substrate 2901. The wettability of the surface of the deposition layer 2902 is lower than the wettability of the surface of the opposing region RK of the transparent substrate 2901. In this case, the surface of the deposition layer 2902 can be made more hydrophobic than the surface of the transparent substrate 2901. The deposition layer 2902 may be formed by, for example, a fluorine coating.

[0458] FIG. 62 is a cross-sectional view showing another configuration example of the electronic device according to the twenty-ninth embodiment.

[0459] In FIG. 61A, an electronic device 2910 includes a stacked chip P291. The stacked chip P291 includes a transparent substrate 2911 instead of the transparent substrate 2901 in FIG. 61. Other than that, the configuration of the stacked chip P291 is the same as the configuration of the stacked chip P290 in FIG.

[0460] The transparent substrate 2911 includes an ion implantation layer 2912 instead of the film formation layer 2902 in Fig. 61. Other configurations of the transparent substrate 2911 are the same as those of the transparent substrate 2901 in Fig. 61.

[0461] The ion-implanted layer 2912 is formed at the position of the adjacent region RS of the transparent substrate 2911. The wettability of the surface of the ion-implanted layer 2912 is lower than the wettability of the surface of the opposing region RK of the transparent substrate 2911. In this case, the surface of the ion-implanted layer 2912 can be made more hydrophobic than the surface of the transparent substrate 2911. Ions such as N or C may be implanted to improve the hydrophobicity of the ion-implanted layer 2912.

[0462] 61. In FIG. 61B, an electronic device 2920 includes a stacked chip P292. The stacked chip P292 includes a transparent substrate 2921 instead of the transparent substrate 2801 in FIG. 61. Other than that, the configuration of the stacked chip P292 is the same as the configuration of the stacked chip P290 in FIG.

[0463] The transparent substrate 2921 includes a surface modification layer 2922 instead of the film formation layer 2902 in Fig. 61. Other configurations of the transparent substrate 2921 are the same as those of the transparent substrate 2901 in Fig. 61.

[0464] The surface modification layer 2922 is formed at the position of the adjacent region RS of the transparent substrate 2921. The wettability of the surface of the surface modification layer 2922 is lower than the wettability of the surface of the opposing region RK of the transparent substrate 2921. In this case, the surface of the surface modification layer 2922 can be made more hydrophobic than the surface of the transparent substrate 2921. The surface modification layer 2922 can bond a hydrophobic element such as H to the dangling bonds on the surface of the transparent substrate 2921, for example.

[0465] 61. In FIG. 61c, an electronic device 2930 includes a stacked chip P293. The stacked chip P293 includes a transparent substrate 2931 instead of the transparent substrate 2801 of FIG. 61. Other than that, the configuration of the stacked chip P293 is the same as the configuration of the stacked chip P290 of FIG.

[0466] The transparent substrate 2931 includes a rough surface layer 2932 instead of the deposition layer 2902 in Fig. 61. The other configuration of the transparent substrate 2931 is the same as the configuration of the transparent substrate 2901 in Fig. 61.

[0467] The rough surface layer 2932 is formed at the position of the adjacent region RS of the transparent substrate 2931. The wettability of the surface of the rough surface layer 2932 is lower than the wettability of the surface of the opposing region RK of the transparent substrate 2931. In this case, the surface of the rough surface layer 2932 can be made more hydrophobic than the surface of the transparent substrate 2931. The rough surface layer 2932 can be formed by a method such as sandblasting. In this case, the roughness of the rough surface layer 2932 can be adjusted by adjusting the particle size and kinetic energy of the particles used in the sandblasting.

[0468] 63 is a plan view showing yet another example of the configuration of the electronic device according to the twenty-ninth embodiment. In this figure, a 3×3 partitioned region 2801R of a transparent substrate wafer 2801W is shown.

[0469] In the figure, a film layer 2905 is formed on the transparent substrate wafer 2905W so as to cover the adjacent regions RS of each partitioned region 2801R. At this time, in the vertical direction of the transparent substrate wafer 2905W, the film layer 2905 is formed so that three partitioned regions 2801R are continuous. In the horizontal direction of the transparent substrate wafer 2805W, the film layer 2905 is formed so that each partitioned region 2801R is separated.

[0470] In the figure, a film layer 2906 is formed on the transparent substrate wafer 2906W so as to cover the adjacent regions RS of each divided region 2801R. At this time, in the horizontal direction of the transparent substrate wafer 2906W, the film layer 2906 is formed so that three divided regions 2801R are continuous. In the vertical direction of the transparent substrate wafer 2806W, the film layer 2906 is formed so that each divided region 2801R is separated.

[0471] In addition, Figure 59 shows an example in which a film layer is formed so that three partition areas 2801R are continuous in the vertical or horizontal direction of each transparent substrate wafer 2805W, 2806W, but a film layer may also be formed so that two or more partition areas 2801R are continuous in the vertical or horizontal direction of each transparent substrate wafer 2805W, 2806W.

[0472] As described above, in the twenty-ninth embodiment, the wettability of the adjacent region RS of the transparent substrate 2801 bonded to the sensor chip SCP via the transparent resin layer 1403 is made lower than the wettability of the opposing region RK. This makes it possible to expel voids VOD that occur in the transparent resin layer 1403 when the sensor chip SCP and the transparent substrate 2801 are bonded from above the pixel region RG without affecting the optical characteristics of the pixel region RG of the sensor chip SCP.

[0473] 30. Thirty-first embodiment In the twenty-eighth embodiment described above, the wettability of the opposing region RK of the transparent substrate 2801 bonded to the sensor chip SCP via the transparent resin layer 1403 is made higher than the wettability of the adjacent region RS. In this thirtieth embodiment, the wettability of the pixel region RG of the sensor chip SCP bonded to the transparent substrate 2801 via the transparent resin layer 1403 is made higher than the wettability of the adjacent region RA adjacent to the pixel region RG.

[0474] 64 is a diagram showing a configuration example of an electronic device according to the 30th embodiment. In the figure, "a" is a cross-sectional view showing a configuration example obtained by cutting the electronic device 3000 vertically, and "b" is a plan view showing a configuration example of the planarization layer 3001 of the sensor chip SCI. "a" in the figure shows a configuration cut at the position of line A1-A2 in "b" in the figure.

[0475] In the figure, the electronic device 3000 includes a stacked chip P30. The stacked chip P30 includes a sensor chip SCI instead of the sensor chip SCP of the twenty-eighth embodiment. The other configuration of the stacked chip P30 is the same as the configuration of the stacked chip P280 of the twenty-eighth embodiment.

[0476] The sensor chip SCI is obtained by adding a planarizing layer 3001 and a film deposition layer 3002 to the sensor chip SCP of the above-described twenty-eighth embodiment. The other configurations of the sensor chip SCI are the same as those of the sensor chip SCP of the above-described twenty-eighth embodiment.

[0477] The planarization layer 3001 flattens the rear surface of the sensor chip SCI. The planarization layer 3001 is formed on the semiconductor substrate 1921 so as to cover the on-chip lens 105. The refractive index of the planarization layer 3001 can be set so as not to impair the light-collecting effect of the on-chip lens 105. The material of the planarization layer 3001 is, for example, SiO ２ , SiN or SiCN can be used.

[0478] The film layer 3002 is formed at the position of the pixel region RG of the sensor chip SCI. The wettability of the surface of the film layer 3002 is higher than the wettability of the surface of the adjacent region RS of the planarization layer 3001. In this case, the surface of the film layer 3002 can be made more hydrophilic than the surface of the planarization layer 3001. The material of the film layer 3002 is SiO ２ The material may be an inorganic material such as silicon nitride or silicon nitride, or a transparent organic material.

[0479] In this way, in the above-described 30th embodiment, the wettability of the pixel region RG of the sensor chip SCI bonded to the transparent substrate 2801 via the transparent resin layer 1403 is made higher than the wettability of the adjacent region RA. This makes it possible to expel voids VOD that occur in the transparent resin layer 1403 when the sensor chip SCI and the transparent substrate 2801 are bonded together, from the pixel region RG.

[0480] In the above-described 30th embodiment, an example was shown in which the film formation layer 3002 is formed in the pixel region RG of the planarization layer 3001. As shown in the above-described 28th embodiment, an ion implantation layer or a surface modification layer may be formed in the pixel region RG of the planarization layer 3001. Alternatively, as shown in the above-described 29th embodiment, an ion implantation layer, a surface modification layer, or a roughened surface layer may be formed in the adjacent region RS of the planarization layer 3001.

[0481] 31. Thirty-first embodiment In the above-described thirtieth embodiment, the wettability of the pixel region RG of the sensor chip SCI bonded to the transparent substrate 2801 via the transparent resin layer 1403 is made higher than the wettability of the adjacent region RA. In this thirty-first embodiment, the pixel region RG of the sensor chip SCI in which the pixel region RG is sealed with the transparent resin layer is made higher than the wettability of the adjacent region RA.

[0482] FIG. 65 is a cross-sectional view showing a configuration example of an electronic device according to the thirty-first embodiment.

[0483] In the figure, the electronic device 3100 includes a transparent resin layer 3101 instead of the transparent resin layer 1403 of the 30th embodiment described above. Furthermore, the electronic device 3100 has the transparent substrate 2801 removed from the stacked chip P30 of the 30th embodiment described above. In this case, the electronic device 3100 can have a glass-less configuration in order to seal the back side of the sensor chip SCI. The other configurations of the electronic device 3100 are the same as those of the electronic device 3000 of the 30th embodiment described above.

[0484] The transparent resin layer 3101 seals the back surface side of the sensor chip SCI. The transparent resin layer 3101 may be made of a transparent resin such as a siloxane-based resin, an acrylic-based resin, or an epoxy-based resin. The transparent resin layer 3101 may contain an inorganic or organic filler to improve reliability.

[0485] In this way, in the above-described thirty-first embodiment, the wettability of the pixel region RG of the sensor chip SCI, in which the pixel region RG is sealed with the transparent resin layer 3101, is made higher than the wettability of the adjacent region RA. This makes it possible to seal the pixel region RG of the sensor chip SCI with the transparent resin layer 3101, while expelling voids VOD generated in the transparent resin layer 3101 from above the pixel region RG.

[0486] In the above-described 31st embodiment, an example was shown in which the film formation layer 3002 was formed in the pixel region RG of the planarization layer 3001. As shown in the above-described 28th embodiment, an ion implantation layer or a surface modification layer may be formed in the pixel region RG of the planarization layer 3001. Alternatively, as shown in the above-described 29th embodiment, an ion implantation layer, a surface modification layer, or a roughened surface layer may be formed in the adjacent region RS of the planarization layer 3001.

[0487] 32. Thirty-Second Embodiment In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this thirty-second embodiment, a film is formed on the inner surface of the recess 112 provided on the bonding surface of the transparent substrate 102 or the bonding surface of the chip 101 that are bonded via the adhesive layer 103.

[0488] 66 is a cross-sectional view showing a configuration example of a recess of an electronic device according to the thirty-second embodiment, which shows an enlarged view of a portion corresponding to region ER1 in FIG.

[0489] In the figure, this electronic device is the same as the electronic device 200 of the second embodiment described above, except that a film 3201 is added to the electronic device 200 of the second embodiment described above. The rest of the configuration of this electronic device is the same as the configuration of the electronic device 200 of the second embodiment described above.

[0490] The film 3201 is formed on the inner surface of the recess 112. The film 3201 may be an adsorption film having better adsorption properties than the transparent substrate 102. In this case, the specific surface area of ​​the film 3201 can be larger than the specific surface area of ​​the inner surface of the recess 112. For example, the film 3201 may be a porous film.

[0491] At this time, the film 3201 can adsorb outgassing from the adhesive layer 103. This makes it possible to suppress a decrease in the degree of vacuum in the recess 112 due to outgassing from the adhesive layer 103, and to suppress a decrease in the bonding strength between the chip 101 and the transparent substrate 102.

[0492] Alternatively, the film 3201 may be a thermally conductive film having better thermal conductivity than the transparent substrate 102. Alternatively, the film 3201 may be a stress relaxation film that relieves stress on the transparent substrate 102 or the chip 201. Alternatively, the film 3201 may be a light-absorbing film that absorbs light of a specific wavelength. For example, for blue light blocking, the film 3201 may absorb wavelengths around 450 nm. Note that the film 3201 may have multiple functions, or may have light-blocking properties.

[0493] The material of the membrane 3201 is, for example, zeolite, mesoporous silica, silica gel, Al ２ O ３ Examples of the material include metal oxide films such as silicon dioxide (SiO2), carbon black, tetraethyl orthosilicate (TEOS), and inorganic films such as SiN, and metals such as aluminum (Al), platinum (Pt), and copper (Cu). A plurality of these materials may be stacked. The aluminum or other easily oxidizable film 3201 reacts with gases released by heat generation from the chip 101, maintaining the degree of vacuum within the recess 112. Furthermore, by utilizing the stress of the film 3201, the stress applied to the transparent substrate 102 or the chip 201 can be adjusted, thereby improving the bonding strength via the recess 112.

[0494] FIG. 67 is a cross-sectional view showing an example of a method for manufacturing a recess in an electronic device according to the thirty-second embodiment.

[0495] In FIG. 10A, the transparent substrate wafer 102W is selectively etched to form a recess 112 in the bonding region R2 of the transparent substrate wafer 102W.

[0496] Next, as shown in FIG. 1B, a film 3201 is formed on the transparent substrate wafer 102W including the inner surface of the recess 112. The film 3201 can be formed by CVD, sputtering, vapor deposition, or the like.

[0497] Next, as shown in c in the figure, the surface of the transparent substrate wafer 102W is thinned by a method such as CMP, and the film 3201 on the transparent substrate wafer 102W is removed. At this time, the film 3201 can be left on the inner surface of the recess 112.

[0498] 68 is a cross-sectional view showing another example of the structure of the recess of the electronic device according to the thirty-second embodiment, which shows an enlarged view of the portion corresponding to the region ER1 in FIG.

[0499] In the figure, this electronic device is the same as the electronic device 200 of the second embodiment described above, except that a film 3202 is added to the electronic device 200 of the second embodiment described above. The rest of the configuration of this electronic device is the same as the configuration of the electronic device 200 of the second embodiment described above.

[0500] The film 3202 is formed on the side surface of the recess 112. At this time, it is possible to prevent the film 3202 from being formed on the bottom surface of the recess 112. Other configurations of the film 3202 are the same as those of the film 3201.

[0501] FIG. 69 is a cross-sectional view showing another example of the method for manufacturing a recess in an electronic device according to the thirty-second embodiment.

[0502] In FIG. 10A, the transparent substrate wafer 102W is selectively etched to form a recess 112 in the bonding region R2 of the transparent substrate wafer 102W.

[0503] Next, as shown in FIG. 1B, a film 3202 is formed on the transparent substrate wafer 102W including the inner surface of the recess 112.

[0504] Next, as shown in c in the figure, the film 3202 on the transparent substrate wafer 102W and on the bottom surface of the recess 112 is removed by a method such as etch-back. At this time, the film 3202 can be left on the side surface of the recess 112.

[0505] 70 is a cross-sectional view showing still another example of the structure of the recess of the electronic device according to the thirty-second embodiment, which shows an enlarged view of a portion corresponding to the region ER1 in FIG.

[0506] In the figure, this electronic device is the same as the electronic device 200 of the second embodiment described above, except that a film 3203 is added to the electronic device 200 of the second embodiment described above. The other configurations of this electronic device are the same as the configurations of the electronic device 200 of the second embodiment described above.

[0507] The film 3203 is formed on the inner surface of the recess 112. Concave and convex portions are formed on the surface of the film 3203. At this time, the specific surface area of ​​the film 3203 can be made larger than the specific surface area of ​​the film 3201. The concave and convex portions on the surface of the film 3203 may be formed by laser irradiation or plasma treatment. Concave and convex portions may also be formed at the interface between the film 3203 and the recess 112. At this time, the concave and convex portions can be formed on the inner surface of the recess 112 before the film 3203 is formed on the inner surface of the recess 112. Other configurations of the film 3203 are the same as those of the film 3201.

[0508] 71 is a cross-sectional view showing still another example of the structure of the recess of the electronic device according to the thirty-second embodiment, which shows an enlarged view of a portion corresponding to the region ER2 in FIG.

[0509] In the figure, this electronic device is the same as the electronic device 300 of the third embodiment described above, except that a film 3204 is added to the electronic device 300 of the third embodiment described above. The rest of the configuration of this electronic device is the same as the configuration of the electronic device 300 of the third embodiment described above.

[0510] The film 3204 is formed on the inner surface of the recess 111. The rest of the configuration of the film 3204 is the same as the configuration of the film 3201.

[0511] 72 is a cross-sectional view showing still another example of the structure of the recess of the electronic device according to the thirty-second embodiment, which shows an enlarged view of a portion corresponding to the region ER3 in FIG.

[0512] In the figure, this electronic device is the same as the electronic device 600 of the sixth embodiment described above, except that a film 3205 is added to the electronic device 600 of the sixth embodiment described above. The rest of the configuration of this electronic device is the same as the configuration of the electronic device 600 of the sixth embodiment described above.

[0513] The film 3205 is formed on the inner surface of the recess 111 and on the side surfaces of each of the through holes 113 and 612. At this time, the film 3205 is formed continuously from the recess 111 to the through hole 612. Other configurations of the film 3205 are the same as those of the film 3201.

[0514] In this way, in the above-described 32nd embodiment, the film 3201 is formed on the inner surface of the recess 112 provided on the bonding surface of the transparent substrate 102 or the bonding surface of the chip 101, which are bonded via the adhesive layer 103. This improves the bonding strength between the transparent substrate 102 and the chip 101, while imparting functions such as adsorption, thermal conductivity, wavelength selectivity, and stress relaxation to the recess 112.

[0515] 33. Thirty-Third Embodiment In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this thirty-third embodiment, projections and recesses are formed on the inner surface of the recess provided in the bonding region R2 of the transparent substrate 102.

[0516] FIG. 73 is a cross-sectional view showing a configuration example of a recess of an electronic device according to the thirty-third embodiment.

[0517] In the figure, this electronic device has a recess 3301 instead of the recess 112 of the second embodiment described above. The other configurations of this electronic device are the same as those of the electronic device 200 of the second embodiment described above.

[0518] The recess 3301 is provided in the bonding region R2 of the transparent substrate 102. An unevenness 3302 is formed on the inner surface of the recess 3301. In this case, the specific surface area of ​​the inner surface of the recess 3301 can be made larger than the specific surface area of ​​the inner surface of the recess 112. Furthermore, by forming the unevenness 3302 on the inner surface of the recess 3301, the inner surface of the recess 3301 can be made opaque, thereby preventing light from passing through. Laser irradiation or plasma treatment may be used to form the unevenness 3302 on the inner surface of the recess 3301. The rest of the configuration of the recess 3301 is the same as the configuration of the recess 112.

[0519] FIG. 74 is a cross-sectional view showing another example of the structure of the recess of the electronic device according to the thirty-third embodiment.

[0520] In this figure, this electronic device has a transparent substrate 3300 instead of the transparent substrate 102 in Fig. 73. Other configurations of this electronic device are the same as those of the electronic device in Fig. 73.

[0521] The transparent substrate 3300 includes a recess 3301. A concave-convex pattern 3302 is formed on the inner surface of the recess 3301. Furthermore, a concave-convex pattern 3303 is formed on the bonding surface of the transparent substrate 3300. The concave-convex pattern 3303 can be located at the boundary between the bonding surface of the transparent substrate 3300 and the adhesive layer 203. The concave-convex pattern 3303 is embedded in the adhesive layer 203. By forming the concave-convex pattern 3303 on the bonding surface of the transparent substrate 3300, the bonding area of ​​the bonding surface of the transparent substrate 3300 can be increased, thereby improving the bonding strength of the transparent substrate 3300. Furthermore, forming the concave-convex pattern 3302 on the inner surface of the recess 3301 makes the inner surface of the recess 3301 opaque, thereby preventing light from passing through. The concave-convex pattern 3303 on the bonding surface of the transparent substrate 3300 may be formed by laser irradiation or plasma treatment. The other configurations of the transparent substrate 3300 are the same as those of the transparent substrate 102.

[0522] As described above, in the thirty-third embodiment, the unevenness 3302 is formed on the inner surface of the recess 3301 provided in the bonding region R2 of the transparent substrate 102. This increases the specific surface area of ​​the inner surface of the recess 3301 provided in the bonding region R2 of the transparent substrate 102, thereby improving the adsorption properties of the inner surface of the recess 3301. This makes it possible to suppress a decrease in the degree of vacuum in the recess 3301 due to degassing from the adhesive layer 103, and to suppress a decrease in the bonding strength between the chip 201 and the transparent substrate 102.

[0523] 34. Thirty-fourth embodiment In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this thirty-fourth embodiment, the film formed on the inner surface of the recess 112 provided in the bonding region R2 of the transparent substrate 102 is extended to the outside of the bottom surface of the recess 112.

[0524] 75 is a diagram showing a configuration example of a recess of an electronic device according to the 34th embodiment. In the figure, "a" is a cross-sectional view showing the configuration example obtained by cutting the bonding region of the electronic device vertically, "b" is a plan view showing the configuration example of the electronic device, and "c" is a plan view showing another configuration example of the electronic device. "a" in the figure shows an enlarged view of a portion corresponding to region ER1 in FIG. 5.

[0525] In the figure, this electronic device is the same as the electronic device 200 of the second embodiment described above, except that a film 3401 is added to the electronic device 200. The other configurations of this electronic device are the same as those of the electronic device 200 of the second embodiment described above.

[0526] The film 3401 is formed on the inner surface of the recess 112 and extends outside the bottom surface of the recess 112. In this case, the position of the end of the film 3401 may coincide with the position of the end surface of the transparent substrate 102, or may be located inside the position of the end surface of the transparent substrate 102. As shown in b in the same figure, the film 3401 may be arranged discretely around the transparent substrate 102. Other configurations of the film 3401 are the same as those of the film 3201.

[0527] Alternatively, as shown in c in the same figure, a film 3401' may be provided instead of the film 3401. In this case, a recess 112' is provided in the transparent substrate 102 instead of the recess 112. The recess 112' is formed so as to surround the periphery of the transparent substrate 102. The film 3401' is formed on the inner surface of the recess 112' and extends outside the bottom surface of the recess 112'. In this case, as shown in c in the same figure, the film 3401' may extend in a fin-like shape outside the bottom surface of the recess 112'. Other configurations of the film 3401' are the same as those of the film 3401.

[0528] 76 to 78 are cross-sectional views showing an example of a method for manufacturing a recess in an electronic device according to the thirty-fourth embodiment.

[0529] 76 a, a resist pattern 3421 is formed on the transparent substrate wafer 102W based on lithography. An opening 3422 is formed in the resist pattern 3421 for each divided region 102R. The opening 3422 can be positioned at the position of the extending portion of the film 3401.

[0530] Next, as shown in FIG. 76b, the transparent substrate wafer 102W is etched in the depth direction using the resist pattern 3421 as an etching mask, to form steps 3423 in the transparent substrate wafer 102W for each partitioned region 102R.

[0531] 76c, a resist pattern 3424 is formed on the transparent substrate wafer 102W based on lithography. An opening 3425 is formed in the resist pattern 3424 for each partitioned region 102R. The opening 3425 can be formed at the position where the recess 112 is to be disposed.

[0532] 77 a, the transparent substrate wafer 102W is etched in the depth direction using the resist pattern 3424 as an etching mask, and through-holes 112A are formed in the transparent substrate wafer 102W for each partitioned region 102R. The through-holes 112A are formed at the positions of the recesses 112.

[0533] Next, as shown in FIG. 77b, a film 3401 is formed on the transparent substrate wafer 102W so as to cover the side surfaces of the through-holes 112A.

[0534] Next, as shown in Fig. 77c, the surface of the transparent substrate wafer 102W is thinned by a method such as CMP, and the film 3401 on the transparent substrate wafer 102W in the region inside the through-hole 112A is removed. Here, the height direction position of the surface of the transparent substrate wafer 102W in the region inside the through-hole 112A and the height direction position of the surface of the film 3401 in the region outside the through-hole 112A can be made to coincide with each other. At this time, the side surfaces of the through-hole 112A and the film 3401 on the transparent substrate wafer 102W in the region outside the through-hole 112A can be left.

[0535] 78 a, the transparent substrate wafer 102W′ is bonded onto the transparent substrate wafer 102W to form the recess 112. The transparent substrate wafers 102W and 102W′ may be bonded using an adhesive layer 3406. At this time, the transparent substrate wafer 102W′ can be used as a lid that closes the bottom of the recess 112.

[0536] 78B, a filter layer 604 may be formed on the transparent substrate wafer 102W to form the recess 112. In this case, the filter layer 604 can be used as a lid that closes the bottom of the recess 112.

[0537] As described above, in the thirty-fourth embodiment, the film 3401 formed on the inner surface of the recess 112 provided in the bonding region R2 of the transparent substrate 102 is extended to the outside of the bottom surface of the recess 112. This allows the film 3401 to be formed on the inner surface of the recess 112 while being disposed outside the recess 112. This makes it possible to improve the bonding strength between the transparent substrate 102 and the chip 201 while improving heat dissipation through the transparent substrate 102, and also to impart functions such as adsorption, thermal conductivity, wavelength selectivity, and stress relaxation to the recess 112.

[0538] 35. Thirty-fifth Embodiment In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this thirty-fifth embodiment, a film formed on the inner surface of the recess 112 provided in the bonding region R2 of the transparent substrate 102 is extended to the outside of the opening of the recess 112.

[0539] FIG. 79 is a cross-sectional view showing a configuration example of a recess of an electronic device according to the thirty-fifth embodiment.

[0540] In the figure, this electronic device is the same as the electronic device 200 of the second embodiment described above, except that a film 3501 is added to the electronic device 200 of the second embodiment described above. The rest of the configuration of this electronic device is the same as the configuration of the electronic device 200 of the second embodiment described above.

[0541] The film 3501 is formed on the inner surface of the recess 112 and extends outside the opening of the recess 112. In this case, the position of the end of the film 3501 may coincide with the position of the end face of the transparent substrate 102, or may be located inside the position of the end face of the transparent substrate 102. Other configurations of this electronic device are the same as those of the electronic device 200 of the second embodiment described above.

[0542] FIG. 80 is a cross-sectional view showing an example of a method for manufacturing a recess in an electronic device according to the thirty-fifth embodiment.

[0543] In FIG. 76A, after the step of FIG. 76, the transparent substrate wafer 102W is etched in the depth direction using the resist pattern 3424 as an etching mask, to form recesses 112 in the transparent substrate wafer 102W for each partitioned region 102R.

[0544] Next, as shown in FIG. 1B, a film 3501 is formed on the transparent substrate wafer 102W so as to cover the inner surface of the recess 112.

[0545] Next, as shown in c in the figure, the surface of the transparent substrate wafer 102W is thinned by a method such as CMP, and the film 3501 on the transparent substrate wafer 102W in the region inside the recess 112 is removed. Here, the height position of the surface of the transparent substrate wafer 102W in the region inside the recess 112 and the height position of the surface of the film 3501 in the region outside the recess 112 can be made to coincide with each other. At this time, the inner surface of the recess 112 and the film 3501 on the transparent substrate wafer 102W in the region outside the recess 112 can be left.

[0546] As described above, in the thirty-fifth embodiment, the film 3501 formed on the inner surface of the recess 112 provided in the bonding region R2 of the transparent substrate 102 is extended to the outside of the opening of the recess 112. This allows the film 3501 to be formed on the inner surface of the recess 112 while being disposed outside the recess 112. This makes it possible to improve the bonding strength between the transparent substrate 102 and the chip 201 while improving heat dissipation through the transparent substrate 102, and also to impart functions such as adsorption, thermal conductivity, wavelength selectivity, and stress relaxation to the recess 112.

[0547] 36. Thirty-sixth Embodiment In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this thirty-sixth embodiment, a recess 112′ is provided in the bonding region R2 of the transparent substrate 102, and the buried layer buried outside the recess 112′ is extended outside the bottom surface of the recess 112′.

[0548] 81 is a diagram showing a configuration example of a recess of an electronic device according to the 36th embodiment. In the figure, "a" is a cross-sectional view showing the configuration example obtained by cutting the bonding region of the electronic device vertically, "b" is a plan view showing the configuration example of the electronic device, and "c" is a plan view showing another configuration example of the electronic device. "a" in the figure shows an enlarged view of a portion corresponding to region ER1 in FIG. 5.

[0549] In the figure, this electronic device is the same as the electronic device 200 of the second embodiment described above, except that a buried layer 3601 is added to the electronic device 200 of the second embodiment described above. Other configurations of this electronic device are the same as the configuration of the electronic device 200 of the second embodiment described above.

[0550] The buried layer 3601 is formed outside the recess 112′ and extends outside the bottom surface of the recess 112′. In this case, the position of the end of the buried layer 3601 may coincide with the position of the end surface of the transparent substrate 102, or may be located inside the position of the end surface of the transparent substrate 102. As shown in FIG. 1B, the buried layer 3601 may be discretely disposed around the transparent substrate 102. Other configurations of the buried layer 3601 are the same as those of the film 3201.

[0551] Alternatively, as shown in FIG. 1C, a buried layer 3601′ may be provided instead of the buried layer 3601. The buried layer 3601′ is formed on the outer side of the recess 112′ and extends to the outside of the bottom surface of the recess 112′. In this case, the buried layer 3601′ may extend in a fin shape to the outside of the bottom surface of the recess 112′. Other configurations of the buried layer 3601′ are the same as those of the buried layer 3601.

[0552] As described above, in the 36th embodiment, the recess 112' is provided in the bonding region R2 of the transparent substrate 102, and the buried layer 3601 buried outside the recess 112' is extended outside the bottom surface of the recess 112'. This makes it possible to improve the bonding strength between the transparent substrate 102 and the chip 201 while improving the heat dissipation through the transparent substrate 102.

[0553] 37. Thirty-seventh Embodiment In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this thirty-seventh embodiment, a recess 112′ is provided in the bonding region R2 of the transparent substrate 102, and the buried layer buried outside the recess 112′ is extended outside the opening of the recess 112′.

[0554] FIG. 82 is a cross-sectional view showing a configuration example of a recess of an electronic device according to the thirty-seventh embodiment.

[0555] In the figure, this electronic device is the same as the electronic device 200 of the second embodiment described above, except that a buried layer 3701 is added to the electronic device 200 of the second embodiment described above. Other configurations of this electronic device are the same as the configuration of the electronic device 200 of the second embodiment described above.

[0556] The buried layer 3701 is formed on the outer side of the recess 112′ and extends to the outer side of the opening of the recess 112′. In this case, the position of the end of the buried layer 3701 may coincide with the position of the end face of the transparent substrate 102, or may be located inside the position of the end face of the transparent substrate 102. Other than that, the configuration of the buried layer 3701 is the same as the configuration of the film 3201.

[0557] 83 and 84 are cross-sectional views showing an example of a method for manufacturing a recess in an electronic device according to the thirty-seventh embodiment.

[0558] 83A, the transparent substrate wafer 102W is selectively etched in the depth direction to form recesses 3702 in the transparent substrate wafer 102W for each partitioned region 102R. The recesses 3702 are formed at the embedding positions of the embedding layer 3701.

[0559] 83 b, the transparent substrate wafer 102W on the outer side of the recess 3702 is selectively etched in the depth direction to thin the transparent substrate wafer 102W on the outer side of the recess 3702. At this time, the difference in height between the transparent substrate wafer 102W on the outer side of the recess 3702 and the transparent substrate wafer 102W on the inner side of the recess 3702 can be made to correspond to the thickness of the outer extending portion of the buried layer 3701.

[0560] Next, as shown in FIG. 83c, a buried layer 3701 is formed on the transparent substrate wafer 102W so as to fill the recessed portion 3702.

[0561] 84A, the surface of the buried layer 3701 is thinned by a method such as CMP, and the buried layer 3701 in the region inside the recess 3702 is removed. Here, the height position of the surface of the transparent substrate wafer 102W in the region inside the buried layer 3701 and the height position of the surface of the buried layer 3701 can be made to coincide with each other.

[0562] 84b, a resist pattern 3721 is formed on the transparent substrate wafer 102W based on lithography. An opening 3722 is formed in the resist pattern 3721 for each partitioned region 102R. The opening 3722 can be positioned at the position of the recess 112′.

[0563] Next, as shown in FIG. 84c, the transparent substrate wafer 102W is etched in the depth direction using the resist pattern 3721 as an etching mask, to form recesses 112' in the transparent substrate wafer 102W for each partitioned region 102R.

[0564] As described above, in the 37th embodiment, the recess 112' is provided in the bonding region R2 of the transparent substrate 102, and the buried layer 3701 buried outside the recess 112' extends outside the opening of the recess 112'. This makes it possible to improve the bonding strength between the transparent substrate 102 and the chip 201 while improving the heat dissipation through the transparent substrate 102.

[0565] 38. Thirty-eighth Embodiment In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this thirty-eighth embodiment, a lid that closes the bottom surface of the recess 112 is provided in the bonding region R2 of the transparent substrate 102.

[0566] 85 is a diagram showing a configuration example of a recess of an electronic device according to the 38th embodiment. In the figure, "a" is a cross-sectional view showing the configuration example obtained by cutting the bonding region of the electronic device vertically, and "b" is a plan view showing the configuration example of the electronic device. "a" in the figure shows an enlarged view of a portion corresponding to region ER1 in FIG. 5.

[0567] In the figure, this electronic device has a through-hole 3812 instead of the recess 112 of the above-described second embodiment. Also, this electronic device has a lid 3801 added to the electronic device 200 of the above-described second embodiment. Other configurations of this electronic device are similar to the configuration of the electronic device 200 of the above-described second embodiment.

[0568] The through-hole 3812 penetrates the transparent substrate 102 in the thickness direction in the bonding region R2 of the transparent substrate 102. The through-hole 3812 may be formed at the position of the recess 112 in the first embodiment described above, or may be formed at the position of the recess 112'. The side surface of the through-hole 3812 may be provided with the irregularities 3302 in the thirty-third embodiment described above.

[0569] The lid 3801 is formed on the transparent substrate 102 so as to close the through-hole 3812. By closing the through-hole 3812 with the lid 3801, a recess 112 can be formed in the transparent substrate 102. The lid 3801 may extend to the edge of the transparent substrate 102. The material of the lid 3801 may be the same as the material of the film 3201 in the thirty-second embodiment. In this case, the lid 3801 may have functions such as adsorption, thermal conductivity, wavelength selectivity, stress relaxation, and light blocking properties.

[0570] FIG. 86 is a cross-sectional view showing an example of a method for manufacturing a recess in an electronic device according to the thirty-eighth embodiment.

[0571] 86A, a resist pattern 3821 is formed on the transparent substrate wafer 102W by lithography. An opening 3822 is formed in the resist pattern 3821 for each partitioned region 102R. The opening 3822 can be disposed at the position of the through-hole 3812.

[0572] Next, as shown in FIG. 86b, the transparent substrate wafer 102W is etched in the depth direction using the resist pattern 3821 as an etching mask, to form through-holes 3812 in the transparent substrate wafer 102W for each partitioned region 102R.

[0573] Next, as shown in FIG. 86c, a lid 3801 is formed on the transparent substrate wafer 102W so as to close the through-hole 3812.

[0574] FIG. 87 is a cross-sectional view showing another example of the method for manufacturing a recess in an electronic device according to the thirty-eighth embodiment.

[0575] 87A, a lid material 3801' is laminated on the transparent substrate wafer 102W. The lid material 3801' may be laminated by using CVD or sputtering, or the lid material 3801' may be bonded onto the transparent substrate wafer 102W.

[0576] Next, as shown in FIG. 87b, the lid material 3801' is patterned to form the lid 3801 for each partitioned region 102R on the transparent substrate wafer 102W.

[0577] 87c, the transparent substrate wafer 102W is selectively etched in the thickness direction from the back surface side of the transparent substrate wafer 102W to form through-holes 3812 whose bottom surfaces are closed by the lids 3801. At this time, the lids 3801 can be used as an etch stopper when etching the transparent substrate wafer 102W.

[0578] In this way, in the above-described thirty-eighth embodiment, a lid 3801 that closes the bottom surface of the recess 112 is provided in the bonding region R2 of the transparent substrate 102. This makes it possible to improve the bonding strength between the transparent substrate 102 and the chip 201 while suppressing an increase in the number of processes, and also makes it possible to impart functions such as adsorption, thermal conductivity, wavelength selectivity, and stress relaxation to the recess 112 while improving heat dissipation through the transparent substrate 102.

[0579] 39. Thirty-ninth embodiment In the second embodiment described above, the rectangular recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this thirty-ninth embodiment, a tapered recess is provided in the bonding region R2 of the transparent substrate 102.

[0580] 88 is a diagram showing a configuration example of an electronic device according to the thirty-ninth embodiment. In the figure, "a" is a cross-sectional view showing the configuration example of an electronic device 3900 cut in the vertical direction, and "b" is a plan view showing the configuration example of the electronic device 3900. "a" in the figure is cut along the A1-A2 line in "b" in the figure.

[0581] In the figure, the electronic device 3900 includes a stacked chip P39 instead of the stacked chip P2 of the second embodiment described above. The other configuration of the electronic device 200 of the thirty-ninth embodiment is the same as the configuration of the electronic device 200 of the second embodiment described above.

[0582] The stacked chip P39 has a recess 3912 instead of the recess 112 of the second embodiment described above. The rest of the configuration of the stacked chip P39 is the same as the configuration of the stacked chip P2 of the second embodiment described above.

[0583] The recess 3912 is provided in the bonding region R2 of the transparent substrate 102. The cross-sectional shape of the recess 3912 may be tapered. The cross-sectional shape of the recess 3912 may also be wedge-shaped. In this case, the inner peripheral surface of the recess 3912 may include an inclined surface. The inclined surface may include a flat surface or a curved surface. The position of the inclined surface of the recess 3912 can be set so as to relieve stress applied to the transparent substrate 102. The position of the recess 3912 may be the same as the position of the recess 112 in the second embodiment described above.

[0584] 89 and 90 are cross-sectional views showing an example of a method for manufacturing an electronic device according to the thirty-ninth embodiment.

[0585] 89A, a resist pattern 3921 is formed on the transparent substrate wafer 102W by lithography. An opening 3922 is formed in the resist pattern 3921 for each partitioned region 102R. The openings 3922 can be provided at the positions where the recesses 3912 are to be disposed. At this time, the spacing between the openings 3922 can be varied along the formation positions of the inclined surfaces of the recesses 3912. For example, the spacing between the openings 3922 can be narrower at shallower positions of the recesses 3912 than at deeper positions. Here, narrowing the spacing between the openings 3922 can reduce the amount of etching in the depth direction of the transparent substrate wafer 102W.

[0586] Next, as shown in FIG. 89b, the transparent substrate wafer 102W is etched in the depth direction using the resist pattern 3921 as an etching mask, to form recesses 3912 in the transparent substrate wafer 102W for each partitioned region 102R.

[0587] 89c, an adhesive layer 203 is formed on the semiconductor wafer 201W. Then, the transparent substrate wafer 102W is positioned on the semiconductor wafer 201W so that the recess 3912 faces the adhesive layer 203.

[0588] Next, as shown in FIG. 90a, the transparent substrate wafer 102W and the semiconductor wafer 201W are bonded together with the adhesive layer 103 interposed between them so that the bonding regions R1 and R2 face each other.

[0589] Next, the transparent substrate wafer 102W is thinned from the front surface side as shown in Fig. 90B. The transparent substrate wafer 102W may be thinned by CMP or etch-back.

[0590] Next, the semiconductor wafer 201W is thinned from the front surface side as shown in Fig. 90. The semiconductor wafer 201W may be thinned by CMP or etch-back.

[0591] 88, protruding electrodes 106 are formed for each partitioned region 101R on the front surface of the semiconductor wafer 201W. Then, the laminated structure of the semiconductor wafer 201W and the transparent substrate wafer 102W is cut into each partitioned region 102R to cut out laminated chips P39.

[0592] FIG. 91 is a perspective view showing a configuration example of a recess of an electronic device according to the thirty-ninth embodiment, and FIG. 92 is a plan view showing a configuration example of an electronic device according to the thirty-ninth embodiment.

[0593] 91A, the recesses 3912 are arranged along the outer periphery of the transparent substrate 102. In this case, each recess 3912 has an inclined surface in one direction. The inclined surface of each recess 3912 may face outward.

[0594] 91b and 92, recesses 3912A and 3912B may be alternately arranged along the outer periphery of the transparent substrate 102. In this case, each of the recesses 3912A and 3912B has an inclined surface in one direction. The inclined surface of the recess 3912A may face inward. The inclined surface of the recess 3912B may face outward. This allows the stress acting on the transparent substrate 102 via the adhesive layer 203 to be dispersed, preventing stress concentration.

[0595] 91c, the recess 3912C is arranged along the outer periphery of the transparent substrate 102. In this case, the shape of the recess 3912C may be conical.

[0596] As described above, in the thirty-ninth embodiment, a tapered recess 3912 is provided in the bonding region R2 of the transparent substrate 102. This makes it possible to improve the bonding strength between the chip 101 and the transparent substrate 102 while alleviating the stress applied to the transparent substrate 102 via the adhesive layer 203.

[0597] 40. Fortieth Embodiment In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this fortieth embodiment, a recess is provided in the bonding region R2 of the transparent substrate 102, but is shifted from the bonding region R2.

[0598] 93 is a diagram showing a configuration example of an electronic device according to the fortieth embodiment. In the figure, "a" is a cross-sectional view showing the configuration example of the electronic device 4000A cut in the vertical direction, and "b" is a plan view showing the configuration example of the electronic device 4000A. "a" in the figure is cut along the A1-A2 line in "b" in the figure.

[0599] In the figure, the electronic device 4000A includes a stacked chip P40A instead of the stacked chip P2 of the second embodiment. The rest of the configuration of the electronic device 4000A of the fortieth embodiment is the same as the configuration of the electronic device 200 of the second embodiment.

[0600] The stacked chip P40A has a recess 4012A instead of the recess 112 of the second embodiment described above. The rest of the configuration of the stacked chip P40A is the same as the configuration of the stacked chip P2 of the second embodiment described above.

[0601] The recesses 4012A are provided in the bonding region R2 of the transparent substrate 102. The recesses 4012A are arranged in a staggered manner in the bonding region R2. For example, the recesses 4012A can be arranged in a staggered manner in the bonding region R2.

[0602] 94 is a diagram showing another example of the configuration of the electronic device according to the fortieth embodiment. In the figure, "a" is a cross-sectional view showing the example of the configuration of the electronic device 4000B cut in the vertical direction, and "b" is a plan view showing the example of the configuration of the electronic device 4000B. "a" in the figure is cut along the line A1-A2 in "b" in the figure.

[0603] In the figure, the electronic device 4000B includes a stacked chip P40B instead of the stacked chip P2 of the second embodiment. The rest of the configuration of the electronic device 4000B of the fortieth embodiment is the same as the configuration of the electronic device 200 of the second embodiment.

[0604] The stacked chip P40B has a recess 4012B instead of the recess 112 of the second embodiment described above. Other configurations of the stacked chip P40B are similar to those of the stacked chip P2 of the second embodiment described above.

[0605] The recesses 4012B are provided in the bonding region R2 of the transparent substrate 102. The recesses 4012B are arranged in a shifted manner in the bonding region R2. For example, the recesses 4012B can be arranged in a close-packed manner in the bonding region R2.

[0606] 95 is a diagram showing yet another example of the configuration of the electronic device according to the fortieth embodiment. In the figure, "a" is a cross-sectional view showing the example of the configuration of the electronic device 4000C cut vertically, and "b" is a plan view showing the example of the configuration of the electronic device 4000C. "a" in the figure is cut along the line A1-A2 in "b" in the figure.

[0607] In the figure, the electronic device 4000C includes a stacked chip P40C instead of the stacked chip P2 of the second embodiment. The rest of the configuration of the electronic device 4000C of the fortieth embodiment is the same as the configuration of the electronic device 200 of the second embodiment.

[0608] The stacked chip P40C has a recess 4012C instead of the recess 112 of the second embodiment described above. The rest of the configuration of the stacked chip P40C is the same as the configuration of the stacked chip P2 of the second embodiment described above.

[0609] The recesses 4012C are provided in the bonding region R2 of the transparent substrate 102. The recesses 4012C are arranged in a shifted manner in the bonding region R2. For example, the recesses 4012C can be arranged in a honeycomb pattern in the bonding region R2.

[0610] 96 and 97 are cross-sectional views showing an example of a method for manufacturing an electronic device according to the fortieth embodiment. Note that, although Fig. 96 and Fig. 97 show an example of a method for manufacturing the recess 4012C in Fig. 95, a similar method can also be applied to the recess 4012A in Fig. 93 and the recess 4012B in Fig. 94.

[0611] 96A, a resist pattern 4021 is formed on the transparent substrate wafer 102W by lithography. An opening 4022 is formed in the resist pattern 4021 for each partitioned region 102R. The opening 4022 can be provided at the position where the recess 4012C is to be disposed.

[0612] Next, as shown in FIG. 96b, the transparent substrate wafer 102W is etched in the depth direction using the resist pattern 4021 as an etching mask, to form recesses 4012C in the transparent substrate wafer 102W for each partitioned region 102R.

[0613] 96c, an adhesive layer 203 is formed on the semiconductor wafer 201W. Then, the transparent substrate wafer 102W is positioned on the semiconductor wafer 201W so that the recess 4012C faces the adhesive layer 203.

[0614] Next, as shown in FIG. 97a, the transparent substrate wafer 102W and the semiconductor wafer 201W are bonded together with the adhesive layer 203 interposed between them so that the bonding regions R1 and R2 face each other.

[0615] Next, as shown in FIG. 97b, the transparent substrate wafer 102W is thinned from the front surface side.

[0616] Next, as shown in FIG. 97c, the semiconductor wafer 201W is thinned from the front surface side.

[0617] 95, protruding electrodes 106 are formed for each partitioned region 101R on the front surface of the semiconductor wafer 201W. Then, the laminated structure of the semiconductor wafer 201W and the transparent substrate wafer 102W is cut into each partitioned region 102R to cut out laminated chips P40C.

[0618] In this way, in the above-described fortieth embodiment, the recesses 4012 are provided in a shifted arrangement in the bonding region R2 of the transparent substrate 102. This makes it possible to increase the arrangement density of the recesses 4012 and also improve the thermal insulation against external heat.

[0619] <41. Forty-first embodiment> In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this forty-first embodiment, the recesses provided in the bonding region R1 of the chip 101 and the bonding region R2 of the transparent substrate 102 are arranged so as not to overlap each other.

[0620] 98 is a diagram showing a configuration example of an electronic device according to the forty-first embodiment. In the figure, "a" is a cross-sectional view showing the configuration example of an electronic device 4100 cut in the vertical direction, and "b" is a plan view showing the configuration example of the electronic device 4100. "a" in the figure is cut along the A1-A2 line in "b" in the figure.

[0621] In the figure, the electronic device 4100 includes a stacked chip P41 instead of the stacked chip P4 of the fourth embodiment described above. The rest of the configuration of the electronic device 4100 of the forty-first embodiment is the same as the configuration of the electronic device 400 of the fourth embodiment described above.

[0622] The stacked chip P41 has recesses 4111 and 4112 instead of the recesses 111 and 112 of the fourth embodiment described above. The rest of the configuration of the stacked chip P41 is the same as the configuration of the stacked chip P4 of the fourth embodiment described above.

[0623] The recess 4111 is provided in the bonding region R1 of the chip 101. The recess 4112 is provided in the bonding region R2 of the transparent substrate 102. At this time, the recesses 4111 and 4112 are arranged so as not to overlap each other.

[0624] FIG. 99 is a cross-sectional view showing an example of a method for manufacturing an electronic device according to the forty-first embodiment.

[0625] 99 a, a resist pattern 4121 is formed on the semiconductor wafer 101W based on lithography. An opening 4122 is formed in the resist pattern 4121 for each divided region 102R. The opening 4122 can be provided at the arrangement position of the recess 4111. Here, the position coordinates of the opening 4122 can be determined by referring to the alignment marks of the color filters 104 formed on the semiconductor wafer 101W. Furthermore, a resist pattern 4123 is formed on the transparent substrate wafer 102W based on lithography. An opening 4124 is formed in the resist pattern 4123 for each divided region 102R. The opening 4124 can be provided at the arrangement position of the recess 4112.

[0626] 99 b, the semiconductor wafer 101W is etched in the depth direction using the resist pattern 4121 as an etching mask, and recesses 4111 are formed in the transparent substrate wafer 102W for each partitioned region 102R. Also, the transparent substrate wafer 102W is etched in the depth direction using the resist pattern 4123 as an etching mask, and recesses 4112 are formed in the transparent substrate wafer 102W for each partitioned region 102R.

[0627] Next, as shown in Fig. 99c, an adhesive layer 203 is formed on the semiconductor wafer 101W. Then, the transparent substrate wafer 102W is positioned on the semiconductor wafer 101W so that the recessed portion 4112 faces the adhesive layer 203. Here, the transparent substrate wafer 102W can be positioned on the semiconductor wafer 101W by referring to the alignment marks formed on the semiconductor wafer 101W and the alignment marks formed on the transparent substrate wafer 102W.

[0628] 98, the transparent substrate wafer 102W and the semiconductor wafer 101W are bonded together via the adhesive layer 103, with the bonding regions R1 and R2 facing each other. Then, protruding electrodes 106 are formed on the front surface of the semiconductor wafer 101W for each partitioned region 101R. Thereafter, the laminated structure of the semiconductor wafer 101W and the transparent substrate wafer 102W is cut into each partitioned region 102R to cut out laminated chips P41.

[0629] In this way, in the forty-first embodiment described above, the recesses 4111, 4112 provided in the bonding region R1 of the chip 101 and the bonding region R2 of the transparent substrate 102, respectively, are arranged so as not to overlap each other. This prevents the adhesive layer 103 from bending and breaking even when different negative pressures are applied to the top and bottom surfaces of the adhesive layer 103 via the recesses 4111, 4112.

[0630] 42. Forty-Second Embodiment In the second embodiment described above, the recesses 112 are provided in the bonding region R2 of the transparent substrate 102. In this forty-second embodiment, recesses and through holes are alternately provided in the bonding region R2 of the transparent substrate 102.

[0631] 100 is a diagram showing a configuration example of an electronic device according to the 42nd embodiment. In the figure, "a" is a cross-sectional view showing the configuration example of an electronic device 4200 cut in the vertical direction, and "b" is a plan view showing the configuration example of the electronic device 4200. "a" in the figure is cut along the A1-A2 line in "b" in the figure.

[0632] In the figure, the electronic device 4200 includes a stacked chip P42 instead of the stacked chip P2 of the second embodiment described above. The rest of the configuration of the electronic device 4200 of the 42nd embodiment is the same as the configuration of the electronic device 200 of the second embodiment described above.

[0633] The stacked chip P42 has a recess 4212 instead of the recess 112 of the second embodiment described above. Furthermore, the stacked chip P42 has a through hole 4213 added to the stacked chip P2 of the second embodiment described above. The rest of the configuration of the stacked chip P42 is the same as the configuration of the stacked chip P2 of the second embodiment described above.

[0634] The recesses 4212 and the through holes 4213 are provided in the bonding region R2 of the transparent substrate 102. The through holes 4213 penetrate the transparent substrate 102 in the thickness direction. At this time, the adhesive layer 103 can be exposed to the atmosphere through the through holes 4213. The recesses 4212 and the through holes 4213 may be alternately arranged in the bonding region R2 of the transparent substrate 102. The planar shapes of the recesses 4212 and the through holes 4213 may be different from each other.

[0635] 101 and 102 are cross-sectional views showing an example of a method for manufacturing an electronic device according to the forty-second embodiment.

[0636] 101A, a resist pattern 4221 is formed on the transparent substrate wafer 102W by lithography. In the resist pattern 4221, openings 4222 and through-holes 4223 are formed for each partitioned region 102R. The openings 4222 can be provided at the positions where the recesses 4212 are to be disposed. The through-holes 4223 can be provided at the positions where the through-holes 4213 are to be disposed.

[0637] Next, as shown in FIG. 101b, the transparent substrate wafer 102W is etched in the depth direction using the resist pattern 4221 as an etching mask to form recesses 4212 and through-holes 4213 in the transparent substrate wafer 102W for each partitioned region 102R.

[0638] 101c, an adhesive layer 203 is formed on the semiconductor wafer 201W. Then, the transparent substrate wafer 102W is positioned on the semiconductor wafer 201W so that the recess 4212 faces the adhesive layer 203.

[0639] Next, as shown in FIG. 102a, the transparent substrate wafer 102W and the semiconductor wafer 201W are bonded together with the adhesive layer 103 interposed between them so that the bonding regions R1 and R2 face each other.

[0640] Next, as shown in FIG. 102b, the transparent substrate wafer 102W is thinned from the front surface side.

[0641] Next, as shown in FIG. 102c, the semiconductor wafer 201W is thinned from the front surface side.

[0642] 100, protruding electrodes 106 are formed for each partitioned region 101R on the front surface of the semiconductor wafer 201W. Then, the laminated structure of the semiconductor wafer 201W and the transparent substrate wafer 102W is cut into each partitioned region 102R to cut out laminated chips P42.

[0643] In this way, in the above-described 42nd embodiment, the recesses 4212 and the through holes 4213 are alternately arranged in the bonding region R2 of the transparent substrate 102. This allows degassing from the adhesive layer 103 to escape through the through holes 4213, suppressing a decrease in the degree of vacuum in the recesses 4212 due to degassing from the adhesive layer 103, and suppressing a decrease in the bonding strength of the transparent substrate 102.

[0644] 43. Forty-Third Embodiment In the second embodiment described above, the recessed portion 112 is provided in the bonding region R2 of the transparent substrate 102. In this forty-third embodiment, recessed portions are arranged in a multiple-round pattern in the bonding region R2 of the transparent substrate 102.

[0645] 103 is a diagram showing a configuration example of an electronic device according to the 43rd embodiment. In the figure, "a" is a cross-sectional view showing the configuration example of an electronic device 4300 cut in the vertical direction, and "b" is a plan view showing the configuration example of the electronic device 4300. "a" in the figure is cut along the A1-A2 line in "b" in the figure.

[0646] In the figure, the electronic device 4300 includes a stacked chip P43 instead of the stacked chip P2 of the second embodiment described above. The rest of the configuration of the electronic device 4300 of the 43rd embodiment is the same as the configuration of the electronic device 200 of the second embodiment described above.

[0647] The stacked chip P43 has a recess 4312 instead of the recess 112 of the second embodiment described above. The rest of the configuration of the stacked chip P43 is the same as the configuration of the stacked chip P2 of the second embodiment described above.

[0648] The recess 4312 is provided in the bonding region R2 of the transparent substrate 102. The recess 4312 is arranged in multiple turns in the bonding region R2 of the transparent substrate 102. The number of turns of the recess 4312 may be two or more.

[0649] In this way, in the above-described 43rd embodiment, the recesses 4312 are arranged in multiple turns in the bonding region R2 of the transparent substrate 102. This increases the bonding area of ​​the recesses 4312, thereby improving the bonding strength of the transparent substrate 102 and increasing the heat insulating properties of the transparent substrate 102.

[0650] 44. Forty-fourth embodiment In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this forty-fourth embodiment, a recess is provided in the bonding region R2 of the transparent substrate 102, and a buried layer is buried outside the recess.

[0651] 104 is a diagram showing a configuration example of an electronic device according to the 44th embodiment. In addition, in the figure, "a" is a cross-sectional view showing the configuration example of an electronic device 4400 cut in the vertical direction, and "b" in the figure is a plan view showing the configuration example of the electronic device 4400. "a" in the figure is cut along the A1-A2 line in "b" in the figure.

[0652] In the figure, the electronic device 4400 includes a stacked chip P44 instead of the stacked chip P2 of the second embodiment described above. The rest of the configuration of the electronic device 4400 of the 44th embodiment is the same as the configuration of the electronic device 200 of the second embodiment described above.

[0653] The stacked chip P44 has a recess 4412 instead of the recess 112 of the second embodiment described above. Furthermore, the stacked chip P44 has an embedded layer 4413 added to the electronic device 200 of the second embodiment described above. Other configurations of the stacked chip P44 are the same as those of the stacked chip P2 of the second embodiment described above.

[0654] The recessed portion 4412 is provided in the bonding region R2 of the transparent substrate 102. The recessed portion 4412 may be arranged in multiple circles in the bonding region R2 of the transparent substrate 102.

[0655] The buried layer 4413 is formed on the outer side of the recess 4412. In this case, the outer periphery of the buried layer 4413 may extend in a fin shape. The position of the end of the buried layer 4413 may coincide with the position of the end face of the transparent substrate 102, or may be located inside the position of the end face of the transparent substrate 102. The material of the buried layer 4413 may have better thermal conductivity than the material of the transparent substrate 102. For example, the material of the buried layer 4413 may be a metal such as Cu or Al, a semiconductor such as Si, or an insulator such as SiC or AlN. The buried layer 4413 may have light-blocking properties.

[0656] 105 to 107 are cross-sectional views showing an example of a method for manufacturing an electronic device according to the forty-fourth embodiment.

[0657] 105A, a resist pattern 4421 is formed on the transparent substrate wafer 102W by lithography. Openings 4422 and 4423 are formed in the resist pattern 4421 for each partitioned region 102R. The openings 4422 can be provided at the positions where the recesses 4412 will be disposed. The openings 4423 can be provided at the positions where the buried layers 4413 will be disposed.

[0658] 105b, the transparent substrate wafer 102W is etched in the depth direction using the resist pattern 4421 as an etching mask to form recesses 4412 and 4414 in the transparent substrate wafer 102W for each partitioned region 102R. The recesses 4414 can be provided at positions where the buried layers 4413 are to be disposed.

[0659] Next, as shown in FIG. 105c, a filling material 4413' is formed on the transparent substrate wafer 102W so as to fill the recesses 4412 and 4414.

[0660] 106A, the filling material 4413' is thinned to expose the surface of the transparent substrate wafer 102W. At this time, a filling layer 4413 is formed in each of the recesses 4412 and 4414.

[0661] 106B, a resist pattern 4431 is formed on the transparent substrate wafer 102W based on lithography. An opening 4432 is formed in the resist pattern 4431 for each partitioned region 102R. The opening 4432 can be provided at the position where the recess 4412 is to be disposed.

[0662] 106c, the buried layer 4413 is selectively etched using the resist pattern 4431 as an etching mask to remove the buried layer 4413 in the recess 4412. At this time, the buried layer 4413 in the recess 4414 can be left.

[0663] Next, as shown in FIG. 107a, the resist pattern 4431 on the transparent substrate wafer 102W is removed by ashing or the like.

[0664] 107b, an adhesive layer 203 is formed on the semiconductor wafer 201W. Then, the transparent substrate wafer 102W and the semiconductor wafer 101W are bonded together with the adhesive layer 203 interposed between them so that the bonding regions R1 and R2 face each other.

[0665] Next, as shown in FIG. 107c, the semiconductor wafer 201W is thinned from the front surface side.

[0666] 104, protruding electrodes 106 are formed for each partitioned region 101R on the front surface of the semiconductor wafer 201W. Then, the laminated structure of the semiconductor wafer 201W and the transparent substrate wafer 102W is cut into each partitioned region 102R to cut out laminated chips P44.

[0667] As described above, in the 44th embodiment, the recess 4412 is provided in the bonding region R2 of the transparent substrate 102, and the buried layer 4413 is buried outside the recess 4412. This makes it possible to improve the bonding strength between the transparent substrate 102 and the chip 201 while improving the heat dissipation through the transparent substrate 102.

[0668] 45. Forty-fifth Embodiment In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this forty-fifth embodiment, a recess is provided in the bonding region R2 of the transparent substrate 102, and fine grooves are provided on both sides of the recess.

[0669] 108 is a cross-sectional view showing a configuration example of an electronic device according to the 45th embodiment. In the figure, "a" is a cross-sectional view showing the configuration example of an electronic device 4500 cut in the vertical direction, and "b" is a plan view showing the configuration example of the electronic device 4500. "a" in the figure is cut along the A1-A2 line in "b" in the figure.

[0670] In the figure, the electronic device 4500 includes a stacked chip P45 instead of the stacked chip P2 of the second embodiment described above. The rest of the configuration of the electronic device 4500 of the 45th embodiment is the same as the configuration of the electronic device 200 of the second embodiment described above.

[0671] The stacked chip P45 has a recess 4512 instead of the recess 112 of the second embodiment described above. Furthermore, the stacked chip P45 has a microgroove 4513 added to the electronic device 200 of the second embodiment described above. The rest of the configuration of the stacked chip P45 is the same as the configuration of the stacked chip P2 of the second embodiment described above.

[0672] The recess 4512 is provided in the bonding region R2 of the transparent substrate 102. The recess 4512 can surround the bonding region R2 of the transparent substrate 102. The microgrooves 4513 are provided on both sides of the recess 4512. The depth of the microgrooves 4513 can be shallower than the depth of the recess 4512. At this time, the adhesive layer 203 is embedded in the microgrooves 4513.

[0673] 109 and 110 are cross-sectional views showing an example of a method for manufacturing an electronic device according to the forty-fifth embodiment.

[0674] 109 a, a resist pattern 4521 is formed on the transparent substrate wafer 102W based on lithography. Openings 4522 and 4523 are formed in the resist pattern 4521 for each partitioned region 102R. The openings 4522 can be provided at the positions where the recesses 4512 are to be arranged. The openings 4523 can be provided at the positions where the fine grooves 4513 are to be arranged. The depth of the openings 4523 can be shallower than the depth of the openings 4522.

[0675] Next, as shown in FIG. 109b, the transparent substrate wafer 102W is etched in the depth direction using the resist pattern 4521 as an etching mask to form recesses 4512 and fine grooves 4513 in the transparent substrate wafer 102W for each partitioned region 102R.

[0676] 109c, an adhesive layer 203 is formed on the semiconductor wafer 201W. Then, the transparent substrate wafer 102W is positioned on the semiconductor wafer 201W so that the recesses 4512 and the fine grooves 4513 face the adhesive layer 203.

[0677] Next, as shown in FIG. 110a, the transparent substrate wafer 102W and the semiconductor wafer 201W are bonded together with the adhesive layer 103 interposed between them so that the bonding regions R1 and R2 face each other.

[0678] Next, as shown in FIG. 110b, the transparent substrate wafer 102W is thinned from the front surface side.

[0679] Next, as shown in FIG. 110c, the semiconductor wafer 201W is thinned from the front surface side.

[0680] 108, protruding electrodes 106 are formed for each partitioned region 101R on the front surface of the semiconductor wafer 201W. Then, the laminated structure of the semiconductor wafer 201W and the transparent substrate wafer 102W is cut into each partitioned region 102R to cut out laminated chips P45.

[0681] As described above, in the 45th embodiment, the recess 4512 is provided in the bonding region R2 of the transparent substrate 102, and the fine grooves 4513 are provided on both sides of the recess 4512. This makes it possible to lengthen the path to the recess 4512 via the interface between the transparent substrate 102 and the adhesive layer 203. Therefore, the path for air to enter the recess 4512 can be lengthened, and a decrease in the degree of vacuum in the recess 4512 can be suppressed.

[0682] 46. ​​Forty-Sixth Embodiment In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this forty-sixth embodiment, a recess with a widened tip is provided in the bonding region R2 of the transparent substrate 102.

[0683] 111 is a cross-sectional view showing a configuration example of an electronic device according to the 46th embodiment. In addition, a in the figure is a cross-sectional view showing the configuration example of an electronic device 4600 cut in the vertical direction, and b in the figure is a plan view showing the configuration example of the electronic device 4600. A in the figure is cut along the A1-A2 line in b in the figure.

[0684] In the figure, the electronic device 4600 includes a stacked chip P46 instead of the stacked chip P2 of the second embodiment described above. The rest of the configuration of the electronic device 4600 of the 46th embodiment is the same as the configuration of the electronic device 200 of the second embodiment described above.

[0685] The stacked chip P46 has a recess 4612 instead of the recess 112 of the second embodiment described above. The rest of the configuration of the stacked chip P46 is the same as the configuration of the stacked chip P2 of the second embodiment described above.

[0686] The recess 4612 is provided in the bonding region R2 of the transparent substrate 102. The tip of the recess 4612 is widened. In this case, a skirt portion 4613 may be provided at the tip of the recess 4612. The skirt portion 4613 may be shaped like a trumpet or a funnel. An adhesive layer 203 can be embedded in the skirt portion 4613.

[0687] 112 and 113 are cross-sectional views showing an example of a method for manufacturing an electronic device according to the forty-sixth embodiment.

[0688] 112 a, a resist pattern 4621 is formed on the transparent substrate wafer 102W based on lithography. An opening 4622 is formed in the resist pattern 4621 for each partitioned region 102R. The opening 4622 can be provided at the position where the recess 4612 is to be disposed. Furthermore, an opening 4623 is formed above the opening 4622. The width of the opening 4623 can be larger than the width of the opening 4622. The opening 4623 can be provided at the position where the skirt portion 4613 is to be disposed.

[0689] Next, as shown in FIG. 112b, the transparent substrate wafer 102W is etched in the depth direction using the resist pattern 4621 as an etching mask to form recesses 4612 and skirting portions 4613 in the transparent substrate wafer 102W for each partitioned region 102R.

[0690] 112c, an adhesive layer 203 is formed on the semiconductor wafer 201W. Then, the transparent substrate wafer 102W is positioned on the semiconductor wafer 201W so that the recess 4612 faces the adhesive layer 203.

[0691] Next, as shown in FIG. 113a, the transparent substrate wafer 102W and the semiconductor wafer 201W are bonded together with the adhesive layer 103 interposed between them so that the bonding regions R1 and R2 face each other.

[0692] Next, as shown in FIG. 113b, the transparent substrate wafer 102W is thinned from the front surface side.

[0693] Next, as shown in FIG. 113c, the semiconductor wafer 201W is thinned from the front surface side.

[0694] 111, protruding electrodes 106 are formed for each partitioned region 101R on the front surface of the semiconductor wafer 201W. Then, the laminated structure of the semiconductor wafer 201W and the transparent substrate wafer 102W is cut into each partitioned region 102R to cut out laminated chips P46.

[0695] In this way, in the above-described 46th embodiment, the recess 4612 with a widened tip is provided in the bonding region R2 of the transparent substrate 102. This allows for vacuum suction via the recess 4612, while increasing the bonding area between the transparent substrate 102 and the adhesive layer 203, thereby improving the bonding strength of the transparent substrate 102.

[0696] 47. Forty-seventh embodiment In the second embodiment described above, the recess 112 is provided in the bonding region R2 of the transparent substrate 102. In this forty-seventh embodiment, a recess is provided in the bonding region R2 of the transparent substrate 102, and jaggies are provided inside the inner surface of the recess.

[0697] 114 is a cross-sectional view showing a configuration example of an electronic device according to the 47th embodiment. In the figure, "a" is a cross-sectional view showing the configuration example of an electronic device 4700 cut vertically, "b" is a plan view showing the configuration example of the electronic device 4700, and "c" is a plan view showing the configuration example of an electronic device 4700'. "a" in the figure is cut along line A1-A2 in "b" and "c" in the figure.

[0698] In the figure, the electronic device 4700 includes a stacked chip P47 instead of the stacked chip P2 of the second embodiment described above. The rest of the configuration of the electronic device 4700 of the 47th embodiment is the same as the configuration of the electronic device 200 of the second embodiment described above.

[0699] The stacked chip P47 has a recess 4712 instead of the recess 112 of the second embodiment described above. The rest of the configuration of the stacked chip P47 is the same as the configuration of the stacked chip P2 of the second embodiment described above.

[0700] The recess 4712 is provided in the bonding region R2 of the transparent substrate 102. The recess 4712 has jaggies 4713 on the inside of its inner surface. The direction of the jaggies 4713 can be set in the thickness direction of the transparent substrate 102. The jaggies 4713 may have a jagged shape. In this case, as shown in b in the same figure, the recess 4712 may be discretely arranged around the periphery of the transparent substrate 102. Alternatively, as shown in c in the same figure, recesses 4712' may be provided instead of the recess 4712. In this case, the recess 4712...

Claims

1. An electronic device comprising: a first chip having a first bonding area and a first recess formed in part of the first bonding area; and a second chip bonded to the first chip via a second bonding area facing the first bonding area.

2. The electronic device according to claim 1, wherein the first recesses are arranged discretely around the periphery of the first chip.

3. The electronic device according to claim 1, wherein the first recess is a groove formed continuously around the periphery of the first chip.

4. The electronic device according to claim 1, further comprising: an adhesive layer interposed between the first chip and the second chip.

5. The electronic device according to claim 4, further comprising: a hard layer formed on the surface of said adhesive layer in a position corresponding to the opening position of said first recess.

6. The electronic device according to claim 1, wherein the first chip and the second chip are directly bonded to each other.

7. The electronic device according to claim 1, further comprising a light-shielding film formed on the inner surface of the first recess.

8. The electronic device according to claim 1, wherein the pressure in the first recess is lower than atmospheric pressure.

9. The electronic device of claim 1, further comprising: a gas sealed within said first recess.

10. The electronic device according to claim 1, wherein the first chip is formed on a transparent substrate, and the second chip is formed on a semiconductor substrate.

11. The electronic device of claim 10, further comprising: a filter layer formed on the first chip.

12. The electronic device of claim 1, further comprising a cavity formed inside the second bonding region.

13. The electronic device according to claim 1, wherein the second chip has a second recess formed in a portion of the second bonding region.

14. The electronic device of claim 1, wherein the second chip comprises a device region located inside the second junction region.

15. The electronic device described in claim 13, wherein the second chip comprises: a third chip having a first wiring layer formed on a first semiconductor substrate; a fourth chip having a second wiring layer formed on a second semiconductor substrate and stacked on the third chip so that the first wiring layer and the second wiring layer face each other; and a through electrode that penetrates the first semiconductor substrate and is connected to the first wiring layer.

16. The electronic device according to claim 15, wherein the second recess is formed in the first semiconductor substrate, penetrating the fourth chip and the first wiring layer.

17. The electronic device according to claim 16, wherein the through electrode is provided at a position different from a horizontal position of the second recess.

18. The electronic device of claim 1, wherein the second chip comprises: a third chip having a first wiring layer formed on a first semiconductor substrate; a fourth chip having a second wiring layer formed on a second semiconductor substrate and stacked on the third chip such that the first wiring layer and the second wiring layer face each other; and a through electrode that penetrates the first semiconductor substrate and is connected to the first wiring layer, the through electrode being formed to overlap at least a portion of the first recess.

19. An electronic device comprising: an optical chip having an optical system; and a sensor chip having a sensor element, the optical chip and the sensor chip being joined via a joining surface having a plurality of surfaces.

20. The electronic device described in claim 19, wherein the optical chip comprises a transparent substrate laminated on the sensor chip, and a groove is provided between the sensor chip and the transparent substrate, extending continuously from a first end to a second end of the laminated chip of the sensor chip and the transparent substrate.

21. The electronic device according to claim 20, wherein the groove is provided in the transparent substrate.

22. The electronic device according to claim 20, further comprising: a transparent resin layer that bonds the optical chip and the sensor chip; and an intermediate resin layer provided between the transparent substrate and the transparent resin layer or between the transparent resin layer and the sensor chip, the groove being provided in the intermediate resin layer.

23. The electronic device according to claim 22, wherein the refractive index of the transparent resin layer and the refractive index of the intermediate resin layer are equal to each other.

24. The electronic device according to claim 20, wherein the groove is disposed at a position that allows the laminated chip of the sensor chip and the transparent substrate to cross a wafer before it is solidified.

25. The electronic device according to claim 20, wherein one or more of the grooves are provided in a laminated chip of the sensor chip and the transparent substrate.

26. The electronic device according to claim 20, wherein the grooves are disposed on an effective pixel area, a peripheral area, or both on the effective pixel area and the peripheral area of ​​the sensor chip.

27. The electronic device according to claim 20, wherein the depth of the groove is equal to or less than the thickness of the transparent resin layer.

28. The electronic device according to claim 19, wherein the optical chip is packaged based on WLO (Wafer Level Optics), and the sensor chip is packaged based on WLCSP (Wafer Level Chip Size Package).

29. The electronic device of claim 19, wherein the optical system includes a lens.

30. The electronic device according to claim 19, wherein the optical system includes a stacked structure of multiple lens-equipped substrates.

31. The electronic device according to claim 30, wherein the plurality of lens-equipped substrates comprise a lens and a substrate on which the lens is formed, the lens and the substrate being made of the same or different materials.

32. The electronic device according to claim 19, wherein the optical system includes at least one of an aperture, a light-shielding film, a spacer, and an optical filter.

33. The electronic device according to claim 19, further comprising a bonding layer for bonding the optical chip and the sensor chip.

34. The electronic device of claim 33, wherein the bonding layer is composed of one or more materials.

35. The electronic device according to claim 19, wherein the joining surface includes at least one of a recess, a protrusion, and a rough surface.

36. The electronic device of claim 35, wherein at least one of the recesses, protrusions and roughened surfaces is located on a sensor surface of the sensor chip.

37. The electronic device according to claim 19, wherein the bonding surface having the plurality of surfaces is provided on at least one of the optical chip and the sensor chip.

38. The electronic device according to claim 19, wherein the sensor element is a photoelectric conversion element.

39. The electronic device according to claim 28, wherein the sensor chip comprises: a semiconductor substrate on which the sensor element is formed; and a transparent sealing substrate bonded to the semiconductor substrate.

40. The electronic device described in claim 39, wherein the optical chip comprises a transparent supporting substrate that supports the optical system, and the bonding surface having the multiple surfaces is provided on at least one of the transparent sealing substrate and the transparent supporting substrate.

41. The electronic device of claim 19, wherein the plurality of surfaces include surfaces having mutually different wettability.

42. The electronic device described in claim 41, wherein the optical chip comprises a transparent substrate laminated on the sensor chip via a transparent resin layer, the transparent substrate comprising an opposing region facing a sensor region of the sensor chip and an adjacent region adjacent to the opposing region, and the wettability of the opposing region is higher than the wettability of the adjacent region.

43. The electronic device according to claim 42, wherein the facing region is provided with a deposition layer, a surface modification layer, or an ion implantation layer having a higher wettability than the surface of the peripheral region.

44. The electronic device according to claim 42, wherein the adjacent region comprises a deposition layer, a surface modification layer, an ion-implanted layer, or a roughened surface layer having a lower wettability than the surface of the facing region.

45. The electronic device of claim 41, wherein the sensor chip comprises a sensor region and an adjacent region adjacent to the sensor region, the wettability of the sensor region being higher than the wettability of the adjacent region.

46. ​​The electronic device of claim 45, wherein the sensor region comprises a deposition layer, a surface modification layer, or an ion implantation layer that is more wettable than the surface of the adjacent region.

47. The electronic device of claim 45, wherein the adjacent region comprises a deposition layer, a surface modification layer, an ion implantation layer, or a roughened surface layer that has a lower wettability than the surface of the sensor region.

48. A method for manufacturing an electronic device comprising the steps of: forming a first recess in a first bonding area provided for each partitioned area of ​​a first wafer; bonding a second wafer to the first wafer via a second bonding area provided at a position opposite the first bonding area; and solidifying a laminated wafer in which the first wafer and the second wafer are bonded into each partitioned area.

49. The method of claim 48, wherein the second wafer is bonded to the first wafer under reduced pressure or in an atmospheric gas.

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