Electronic device for performing power control and operating method thereof

Abstract

According to an embodiment of the present disclosure, an electronic device (101) comprises: at least one of a graphic processing unit (GPU) (213) and a multimedia block (215); a processor (120, 200, 211); and a memory (130) for storing instructions, wherein the instructions, when executed by the processor, cause the electronic device to: detect a first stall ratio for a processor cycle of the processor; identify whether the first stall ratio exceeds a first threshold value; on the basis of identifying that the first stall ratio exceeds the first threshold value, identify whether a processor stall of the processor satisfies a condition related to a memory access delay for the memory; and on the basis of identifying that the condition is satisfied, adjust a quality of service (QoS)-related value applied to a transaction of the processor to be higher than a QoS-related value applied to a transaction of at least one of the GPU and the multimedia block. Various other embodiments are also possible.

Description

Electronic device performing power control and method of operation thereof

[0001] One embodiment of the present disclosure relates to an electronic device performing power control and a method of operating the same.

[0002] The performance and functionality of electronic devices (e.g., portable devices like smartphones) are constantly improving. Conversely, electronic devices are evolving to become smaller and lighter, enhancing user convenience. This miniaturization and weight reduction can limit the battery capacity of electronic devices, further increasing the importance of managing power consumption, which directly impacts the operating time of electronic devices.

[0003] Application processors (APs) used in electronic devices are configured with separate power domains for intellectual property (IP) blocks (e.g., central processing unit (CPU), graphic processing unit (GPU), neural processing unit (NPU), multimedia blocks, and / or memory controller) to control current consumption, and dynamic voltage and frequency scaling (DVFS) is applied to dynamically change the operating voltage and operating frequency of each power domain depending on the operating status of the electronic device. In order to control current consumption, APs also apply a core selection method that selects an appropriate CPU based on changes in CPU load (e.g., the sum of the load values ​​of runnable tasks) depending on the operating status of the electronic device, based on normalized CPU performance (e.g., DMIPS (Dhrystone Million Instructions Per Second)-based CPU performance).

[0004] The AP can be implemented in the form of a system on chip (SoC), and the SoC architecture is required to support quality of service (QoS) signaling. The interconnect block can determine the priority of each transaction based on the QoS value when routing transactions transmitted from IP blocks (e.g., CPU, GPU, and / or multimedia blocks), and can transfer the transaction to the memory controller based on the determined priority. The memory controller can also determine the scheduling priority based on the QoS value when accessing memory (e.g., dynamic random access memory (DRAM)) via read / write commands.

[0005] In the case of the CPU among IP blocks, although most of the CPU cycles are occupied by the CPU stall period, the existing DVFS method does not consider this CPU stall period, so the CPU may maintain an unnecessarily high operating frequency and consume relatively large current even during the CPU stall period.

[0006] The above information may be provided as background art to aid in understanding the present disclosure. No claim or determination is made as to whether any of the above is applicable as prior art related to the present disclosure.

[0007] According to one embodiment of the present disclosure, an electronic device (101) may include at least one of a graphic processing unit (GPU) (213) or a multimedia block (215), a processor (120; 200; 211) including processing circuitry, and a memory (130) for storing instructions.

[0008] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to detect a first stall ratio for processor cycles of the processor.

[0009] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to determine whether the first stall ratio exceeds a first threshold value.

[0010] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to determine whether a processor stall of the processor satisfies a condition related to a memory access delay to the memory, based on determining that the first stall ratio exceeds the first threshold value.

[0011] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to adjust a quality of service (QoS) related value applied to a transaction of the processor to be higher than a QoS related value applied to a transaction of at least one of the GPU or the multimedia block, based on determining that the condition is satisfied.

[0012] According to one embodiment of the present disclosure, the method may include an operation of detecting a first stall ratio for a processor cycle of a processor (120; 200; 211).

[0013] According to one embodiment of the present disclosure, the method may include an operation of determining whether the first stall ratio exceeds a first threshold value.

[0014] According to one embodiment of the present disclosure, the method may include an operation of determining whether a processor stall of the processor satisfies a condition related to a memory access delay to the memory (130) based on determining that the first stall ratio exceeds the first threshold value.

[0015] According to one embodiment of the present disclosure, the method may include an operation of adjusting a quality of service (QoS) related value applied to a transaction of the processor to be higher than a QoS related value applied to a transaction of at least one of a graphic processing unit (GPU) (213) or a multimedia block (215), based on verifying that the condition is satisfied.

[0016] According to one embodiment of the present disclosure, a storage medium storing at least one computer-readable command and data may be provided.

[0017] According to one embodiment of the present disclosure, the at least one command and data, when executed by the processor (120; 200; 211) of the electronic device (101), may cause the electronic device (101) to perform at least one operation.

[0018] According to one embodiment of the present disclosure, the at least one operation may include detecting a first stall ratio for a processor cycle of the processor.

[0019] According to one embodiment of the present disclosure, the at least one operation may include an operation of determining whether the first stall ratio exceeds a first threshold value.

[0020] According to one embodiment of the present disclosure, the at least one operation may include an operation of determining whether a processor stall of the processor satisfies a condition related to a memory access delay to the memory (130) based on determining that the first stall ratio exceeds the first threshold value.

[0021] According to one embodiment of the present disclosure, the at least one operation may include adjusting a quality of service (QoS) related value applied to a transaction of the processor to be higher than a QoS related value applied to a transaction of at least one of a graphic processing unit (GPU) (213) or a multimedia block (215), based on determining that the processor stall is caused by the memory access delay.

[0022] FIG. 1 is a block diagram schematically illustrating an electronic device within a network environment according to one embodiment.

[0023] FIG. 2 is a block diagram schematically illustrating an AP according to one embodiment.

[0024] Figure 3 is a block diagram schematically illustrating a CPU according to one embodiment.

[0025] FIG. 4 is a block diagram schematically illustrating the software architecture of an AP according to one embodiment.

[0026] FIG. 5 is a flowchart illustrating an operating method of an electronic device according to one embodiment.

[0027] FIG. 6 is a diagram illustrating a method for determining whether a processor stall is caused by a stall ratio of CPU cycles and a memory access delay according to one embodiment.

[0028] Figure 7 is a flowchart illustrating an operating method of an electronic device according to one embodiment.

[0029] FIG. 8 is a diagram for explaining an operation mode change based on a stall ratio of CPU cycles according to one embodiment.

[0030] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the attached drawings. In addition, when describing an embodiment of the present disclosure, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of an embodiment of the present disclosure, such detailed description will be omitted. In addition, the terms described below are terms defined in consideration of the functions in an embodiment of the present disclosure, and these may vary depending on the intention or custom of the user or operator. Therefore, the definitions should be made based on the contents throughout this specification.

[0031] It should be noted that the technical terms used in this specification are merely used to describe specific embodiments and are not intended to limit the embodiments of the present disclosure. Alternatively, unless specifically defined otherwise herein, the technical terms used in this specification should be interpreted as having a meaning generally understood by a person skilled in the art to which the present disclosure pertains, and should not be interpreted in an excessively broad or narrow sense. Alternatively, if a technical term used in this specification is an incorrect technical term that does not accurately express the spirit of the present disclosure, it should be replaced with a technical term that can be correctly understood by a person skilled in the art. Alternatively, general terms used in the embodiments of the present disclosure should be interpreted as defined in the dictionary or according to the context, and should not be interpreted in an excessively narrow sense.

[0032] Alternatively, the singular expressions used herein include plural expressions unless the context clearly dictates otherwise. In this application, terms such as "consist of" or "comprises" should not be construed to necessarily include all of the various components or various operations described in the specification, and should be construed to mean that some of the components or some of the operations may not be included, or that additional components or operations may be included.

[0033] Alternatively, terms including ordinal numbers, such as "first," "second," etc., used herein may be used to describe various components, but the components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present disclosure, a first component could be referred to as a "second component," and similarly, a second component could also be referred to as a "first component."

[0034] When a component is referred to as being "connected" or "connected" to another component, it may be directly connected or connected to that other component, but there may also be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0035] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or similar components will be given the same reference numbers and redundant descriptions thereof will be omitted. Alternatively, when describing an embodiment of the present disclosure, if a detailed description of a related known technology is determined to obscure the gist of the present disclosure, the detailed description thereof will be omitted. Alternatively, it should be noted that the attached drawings are only intended to facilitate easy understanding of the spirit of the present disclosure and should not be construed as limiting the spirit of the present disclosure by the attached drawings. The spirit of the present disclosure should be construed to extend to all modifications, equivalents, and substitutes other than the attached drawings.

[0036] Hereinafter, an embodiment of the present disclosure will be described using an electronic device as an example, but the electronic device may also be referred to as a terminal, a mobile station, mobile equipment (ME), user equipment (UE), user terminal (UT), subscriber station (SS), wireless device, handheld device, or access terminal (AT). Alternatively, in an embodiment of the present disclosure, the electronic device may be a device having a communication function, such as a mobile phone, a personal digital assistant (PDA), a smart phone, a wireless MODEM, or a laptop.

[0037] FIG. 1 is a block diagram schematically illustrating an electronic device (101) within a network environment (100) according to one embodiment.

[0038] Referring to FIG. 1, in a network environment (100), an electronic device (101) may communicate with an electronic device (102) via a first network (198) (e.g., a short-range wireless communication network), or may communicate with an electronic device (104) or a server (108) via a second network (199) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (101) may communicate with the electronic device (104) via the server (108). According to one embodiment, the electronic device (101) may include a processor (120), a memory (130), an input module (150), an audio output module (155), a display module (160), an audio module (170), a sensor module (176), an interface (177), a connection terminal (178), a haptic module (179), a camera module (180), a power management module (188), a battery (189), a communication module (190), a subscriber identification module (196), or an antenna module (197). In some embodiments, the electronic device (101) may omit at least one of these components (e.g., the connection terminal (178)), or may have one or more other components added. In some embodiments, some of these components (e.g., the sensor module (176), the camera module (180), or the antenna module (197)) may be integrated into one component (e.g., the display module (160)).

[0039] The processor (120) may control at least one other component (e.g., a hardware or software component) of the electronic device (101) connected to the processor (120) by executing, for example, software (e.g., a program (140)), and may perform various data processing or calculations. According to one embodiment, as at least a part of the data processing or calculation, the processor (120) may store a command or data received from another component (e.g., a sensor module (176) or a communication module (190)) in a volatile memory (132), process the command or data stored in the volatile memory (132), and store the resulting data in a non-volatile memory (134). According to one embodiment, the processor (120) may include a main processor (121) (e.g., a central processing unit or an application processor) or a secondary processor (123) (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) that can operate independently or together therewith. For example, if the electronic device (101) includes a main processor (121) and a secondary processor (123), the secondary processor (123) may be configured to use less power than the main processor (121) or to be specialized for a specified function. The secondary processor (123) may be implemented separately from the main processor (121) or as a part thereof.

[0040] The auxiliary processor (123) may control at least a part of functions or states associated with at least one component (e.g., a display module (160), a sensor module (176), or a communication module (190)) of the electronic device (101), for example, on behalf of the main processor (121) while the main processor (121) is in an inactive (e.g., sleep) state, or together with the main processor (121) while the main processor (121) is in an active (e.g., application execution) state. In one embodiment, the auxiliary processor (123) (e.g., an image signal processor or a communication processor) may be implemented as a part of another functionally related component (e.g., a camera module (180) or a communication module (190)). In one embodiment, the auxiliary processor (123) (e.g., a neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. The artificial intelligence models may be generated through machine learning. This learning can be performed, for example, in the electronic device (101) itself where artificial intelligence is performed, or can be performed through a separate server (e.g., server (108)). The learning algorithm can include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model can include multiple artificial neural network layers.The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to, or alternatively to, a hardware structure, an artificial intelligence model may include a software structure.

[0041] The memory (130) can store various data used by at least one component (e.g., processor (120) or sensor module (176)) of the electronic device (101). The data can include, for example, software (e.g., program (140)) and input data or output data for commands related thereto. The memory (130) can include volatile memory (132) or non-volatile memory (134).

[0042] The program (140) may be stored as software in memory (130) and may include, for example, an operating system (142), middleware (144), or an application (146).

[0043] The input module (150) can receive commands or data to be used in a component of the electronic device (101) (e.g., a processor (120)) from an external source (e.g., a user) of the electronic device (101). The input module (150) can include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0044] The audio output module (155) can output audio signals to the outside of the electronic device (101). The audio output module (155) can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. According to one embodiment, the receiver can be implemented separately from the speaker or as part of the speaker.

[0045] The display module (160) can visually provide information to an external party (e.g., a user) of the electronic device (101). The display module (160) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling the device. According to one embodiment, the display module (160) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of a force generated by the touch.

[0046] The audio module (170) can convert sound into an electrical signal, or vice versa, convert an electrical signal into sound. According to one embodiment, the audio module (170) can acquire sound through the input module (150), output sound through the sound output module (155), or an external electronic device (e.g., electronic device (102)) (e.g., speaker or headphone) directly or wirelessly connected to the electronic device (101).

[0047] The sensor module (176) can detect the operating status (e.g., power or temperature) of the electronic device (101) or the external environmental status (e.g., user status) and generate an electrical signal or data value corresponding to the detected status. According to one embodiment, the sensor module (176) can include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0048] The interface (177) may support one or more designated protocols that may be used to directly or wirelessly connect the electronic device (101) with an external electronic device (e.g., the electronic device (102)). In one embodiment, the interface (177) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0049] The connection terminal (178) may include a connector through which the electronic device (101) may be physically connected to an external electronic device (e.g., electronic device (102)). According to one embodiment, the connection terminal (178) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0050] A haptic module (179) can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that a user can perceive through tactile or kinesthetic sensations. According to one embodiment, the haptic module (179) can include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

[0051] The camera module (180) can capture still images and videos. According to one embodiment, the camera module (180) may include one or more lenses, image sensors, image signal processors, or flashes.

[0052] The power management module (188) can manage power supplied to the electronic device (101). According to one embodiment, the power management module (188) can be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

[0053] A battery (189) may power at least one component of the electronic device (101). In one embodiment, the battery (189) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0054] The communication module (190) may support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device (101) and an external electronic device (e.g., electronic device (102), electronic device (104), or server (108)), and the performance of communication through the established communication channel. The communication module (190) may operate independently from the processor (120) (e.g., application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (190) may include a wireless communication module (192) (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module (194) (e.g., a local area network (LAN) communication module, or a power line communication module). Among these communication modules, the corresponding communication module can communicate with an external electronic device (104) via a first network (198) (e.g., a short-range communication network such as Bluetooth, Wi-Fi (wireless fidelity) direct, or IrDA (infrared data association)) or a second network (199) (e.g., a long-range communication network such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules can be integrated into a single component (e.g., a single chip) or implemented as a plurality of separate components (e.g., multiple chips). The wireless communication module (192) can verify or authenticate the electronic device (101) within a communication network such as the first network (198) or the second network (199) by using subscriber information (e.g., an international mobile subscriber identity (IMSI)) stored in the subscriber identification module (196).

[0055] The wireless communication module (192) can support 5G networks and next-generation communication technologies following the 4G network, such as NR access technology (new radio access technology). The NR access technology can support high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimization of terminal power and connection of multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low-latency communications)). The wireless communication module (192) can support, for example, a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate. The wireless communication module (192) can support various technologies for securing performance in a high-frequency band, such as beamforming, massive multiple-input and multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module (192) can support various requirements specified in the electronic device (101), an external electronic device (e.g., the electronic device (104)), or a network system (e.g., the second network (199)). According to one embodiment, the wireless communication module (192) may support a peak data rate (e.g., 20 Gbps or more) for eMBB realization, a loss coverage (e.g., 164 dB or less) for mMTC realization, or a U-plane latency (e.g., 0.5 ms or less for downlink (DL) and uplink (UL), or 1 ms or less for round trip) for URLLC realization.

[0056] The antenna module (197) can transmit or receive signals or power to or from an external device (e.g., an external electronic device). According to one embodiment, the antenna module (197) may include an antenna including a radiator formed of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). According to one embodiment, the antenna module (197) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as the first network (198) or the second network (199), may be selected from the plurality of antennas, for example, by the communication module (190). A signal or power may be transmitted or received between the communication module (190) and an external electronic device via the selected at least one antenna. According to some embodiments, in addition to the radiator, another component (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as a part of the antenna module (197).

[0057] In one embodiment, the antenna module (197) may form a mmWave antenna module. In one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent a first side (e.g., a bottom side) of the printed circuit board and capable of supporting a designated high-frequency band (e.g., a mmWave band), and a plurality of antennas (e.g., an array antenna) disposed on or adjacent a second side (e.g., a top side or a side side) of the printed circuit board and capable of transmitting or receiving signals in the designated high-frequency band.

[0058] At least some of the above components can be interconnected and exchange signals (e.g., commands or data) with each other via a communication method between peripheral devices (e.g., a bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)).

[0059] According to one embodiment, commands or data may be transmitted or received between the electronic device (101) and an external electronic device (104) via a server (108) connected to a second network (199). Each of the external electronic devices (102 or 104) may be the same or a different type of device as the electronic device (101). According to one embodiment, all or part of the operations executed in the electronic device (101) may be executed in one or more of the external electronic devices (102, 104, or 108). For example, when the electronic device (101) is to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device (101) may, instead of or in addition to executing the function or service itself, request one or more external electronic devices to perform the function or at least a part of the service. One or more external electronic devices that receive the request may execute at least a portion of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device (101). The electronic device (101) may process the result as is or additionally and provide it as at least a portion of a response to the request. For this purpose, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device (101) may provide an ultra-low latency service by using distributed computing or mobile edge computing, for example. In one embodiment, the external electronic device (104) may include an Internet of Things (IoT) device. The server (108) may be an intelligent server utilizing machine learning and / or a neural network. According to one embodiment, the external electronic device (104) or the server (108) may be included in the second network (199).The electronic device (101) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0060] Electronic devices according to embodiments disclosed herein may take various forms. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. Electronic devices according to embodiments disclosed herein are not limited to the aforementioned devices.

[0061] The embodiments of this document and the terms used herein are not intended to limit the technical features described in this document to a specific embodiment, but should be understood to include various modifications, equivalents, or substitutes of the embodiment. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the items, unless the context clearly indicates otherwise. In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used merely to distinguish one component from another, and do not limit the components in any other respect (e.g., importance or order). When a component (e.g., a first component) is referred to as "coupled" or "connected" to another (e.g., a second component), with or without the terms "functionally" or "communicatively," it means that the component can be connected to the other component directly (e.g., wired), wirelessly, or through a third component.

[0062] The term "module" used in one embodiment of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A module may be an integral component, or a minimum unit or part of such a component that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0063] An embodiment of the present document may be implemented as software (e.g., a program (140)) including one or more instructions stored in a storage medium (e.g., an internal memory (136) or an external memory (138)) readable by a machine (e.g., an electronic device (101)). For example, a processor (e.g., a processor (120)) of the machine (e.g., an electronic device (101)) may call at least one instruction among the one or more instructions stored from the storage medium and execute it. This enables the machine to operate to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently or temporarily on the storage medium.

[0064] According to one embodiment, the method according to one embodiment disclosed in the present document may be provided as a computer program product. The computer program product may be traded between sellers and buyers as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)) or may be provided through an application store (e.g., Play Store). TM ) or directly between two user devices (e.g., smart phones), online distribution (e.g., downloading or uploading). In the case of online distribution, at least a portion of the computer program product may be at least temporarily stored or temporarily created in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0065] According to one embodiment, each component (e.g., a module or a program) of the above-described components may include one or more entities, and some of the entities may be separated and placed in other components. According to one embodiment, one or more components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., a module or a program) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to one embodiment, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

[0066] An application processor (AP) used in an electronic device may configure intellectual property (IP) blocks (e.g., a central processing unit (CPU), a graphic processing unit (GPU), a neural processing unit (NPU), a multimedia block, and / or a memory controller) into separate power domains in order to control current consumption, and may apply a dynamic voltage and frequency scaling (DVFS) method that dynamically changes the operating voltage and operating frequency of each power domain depending on the operating status of the electronic device. The AP may also apply a core selection method that selects an appropriate core depending on changes in CPU load (e.g., the sum of the load values ​​of runnable tasks) depending on the operating status of the electronic device, based on normalized CPU performance (e.g., DMIPS (Dhrystone Million Instructions Per Second)-based CPU performance) in order to control current consumption. For example, when a core selection method is used, the AP can select a core with relatively high performance to enable high-speed operation, even if this increases current consumption, to provide an optimal user experience (UX) for applications with relatively high loads, such as games. Conversely, for applications with relatively low loads, such as video sharing services, the AP can control current consumption by selecting a core that has an advantage in efficiency rather than performance by reducing the operating voltage and lowering the operating frequency.

[0067] In general, system on chip (SoC) architectures are required to support quality of service (QoS) signaling. An interconnect block can determine a priority for each transaction based on a QoS value (hereinafter, for convenience of explanation, the QoS value may also be referred to as a "QoS-related value") when routing transactions transmitted from IP blocks (e.g., CPU, GPU, and / or multimedia blocks), and can forward the transaction to a memory controller based on the determined priority. A transaction may represent a basic unit of read / write that each IP block transmits and receives to and from the interconnect. For example, a transaction may be forwarded to a memory controller based on a priority determined based on a QoS value. For example, a QoS value applied to a transaction may include a priority used to deliver the transaction to at least one additional circuit (e.g., an interconnect block, and / or a memory (e.g., DRAM, SRAM, Compute Express Link (CXL) memory, etc.) controller) associated with accessing memory. For example, transactions with the same QoS value may be delivered to the memory controller sequentially, or alternatively, a transaction with a larger QoS value (e.g., a higher priority) may be delivered to the memory controller with preference over a transaction with a smaller QoS value (e.g., a lower priority).

[0068] The memory controller can also determine scheduling priorities based on QoS values ​​for operations that access memory (e.g., dynamic random access memory (DRAM)) via read / write commands.

[0069] In real-world operating scenarios, front-end stalls or back-end stalls can occupy a majority of CPU cycles, drastically reducing the number of instructions per cycle (IPC) executed by the CPU. CPU stalls can indicate delays in CPU operation and can include CPU-bound stalls, memory-bound stalls, front-end stalls, and / or back-end stalls.

[0070] A CPU-bound stall can represent a stall that occurs in the CPU's internal execution engine that processes instructions.

[0071] Memory-bound stalls can refer to stalls that occur during memory access operations, including CPU internal caches and DRAM. Memory-bound stalls can include L1 instruction cache misses, which can result in front-end stalls, and L1 data cache misses, which can result in back-end stalls.

[0072] A front-end stall can refer to a stall that occurs while the CPU is fetching an instruction to be executed. A front-end stall can be caused by, but is not limited to, an L1 instruction cache miss. A front-end stall can also include a cache miss during an instruction fetch, or a delay caused by a CPU pipeline flush due to a branch misprediction.

[0073] A back-end stall can refer to a CPU stall that occurs while processing a read / write instruction. A back-end stall can be caused by, but is not limited to, an L1 data cache miss. A back-end stall can also include cases where a cache miss during a data read / write operation requires access to external resources such as DRAM. IPC, also known as instructions per clock, is the average number of instructions executed per clock cycle and can be an aspect of processor performance.

[0074] If the size of the translation lookaside buffer (TLB) is smaller than the working set size (WSS) of the application running on the AP, or if the cache / TLB miss rate is maintained above a threshold for a set amount of time due to inaccurate prediction by the prefetcher, when the CPU accesses DRAM, the CPU may be delayed in receiving the response it needs to receive due to contention between transactions by other IPs occurring in the interconnect block and transactions by the CPU, or due to insufficient bandwidth itself during operation. The prefetcher can perform a prefetching operation to prevent memory access delays. The prefetching operation monitors the memory access pattern of the running application, predicts what data the running application will access next, and fetches the predicted data in advance.

[0075] However, in the DVFS method that only considers the workload according to the operating situation based on the normalized CPU performance (e.g. DMIPS-based CPU performance) for current consumption control, the CPU stall (e.g. front end stall, back end stall) situation is not considered for dynamic control of the operating frequency and operating voltage, and therefore, the CPU may operate inefficiently by maintaining an unnecessarily high operating frequency and consuming unnecessarily large current during the CPU stall period when the CPU fetches data from DRAM through the interconnect block. To prevent such inefficient operation, one can try to apply a method to increase the operating frequency and operating voltage of the interconnect block and DRAM, but if the AP is already using the maximum power, it may be difficult to apply a method to increase the operating frequency and operating voltage of the interconnect block and DRAM, and therefore, it may be difficult to prevent unnecessary current consumption of the CPU.

[0076] One embodiment of the present disclosure can provide an electronic device performing power control and a method of operating the same.

[0077] One embodiment of the present disclosure can provide an electronic device and an operating method thereof that perform power control based on CPU stall information.

[0078] One embodiment of the present disclosure may provide an electronic device and a method of operating the same for adjusting QoS for a CPU transaction or controlling an operating frequency and an operating voltage.

[0079] FIG. 2 is a block diagram schematically illustrating an AP according to one embodiment.

[0080] Referring to FIG. 2, the AP (200) may include a CPU (211), a GPU (213), a multimedia block (215), an interconnect block (217), and / or a memory (e.g., DRAM, SRAM, CXL (Compute Express Link) memory, etc.) controller (219). The AP (200) may correspond to the processor (120) of FIG. 1. In FIG. 2, the AP (200) is illustrated as including a CPU (211), a GPU (213), a multimedia block (215), an interconnect block (217), and / or a memory controller (219), but is not limited thereto, and the AP (200) may include various additional IP blocks such as an NPU. In one embodiment, the CPU (211) may be a processor. According to one embodiment, the AP (200) may be implemented in the form of an SoC. According to one embodiment, the CPU (211) can collect and analyze information provided by a performance monitoring unit (PMU) (e.g., events provided by the PMU). The CPU (211) can collect and analyze information provided by the PMU at a set cycle (e.g., every second). The set cycle used to collect and analyze information provided by the PMU may vary depending on the situation. Since the information provided by the PMU will be described in detail in FIG. 3 below, a detailed description thereof will be omitted here.

[0081] In one embodiment, the CPU (211) can control the QoS value for transactions from the CPU (211) and / or other IP blocks (e.g., GPU (213) and / or multimedia block (215)). The CPU (211) can control DVFS operation. In one embodiment, the CPU (211) can control (or adjust) the operating voltage and / or operating frequency for other IP blocks (e.g., GPU (213), multimedia block (215), interconnect block (217), and / or memory controller (219)).

[0082] According to one embodiment, the CPU (211) can detect a stall ratio (stall_ratio) of a CPU cycle based on information provided by the PMU. In one embodiment, the stall ratio of a CPU cycle can indicate the ratio of a CPU cycle occupied by a CPU stall occurrence section. According to one embodiment, the stall ratio of a CPU cycle can be detected based on information provided by the PMU for a set time (e.g., 1 second). In one embodiment, the set time can indicate an optimal time required to detect an operating status of the CPU (211) and perform appropriate power control. In one embodiment, the set time can be a period corresponding to one CPU cycle or a time corresponding to a plurality of set CPU cycles, and the set time for detecting the stall ratio of a CPU cycle can vary depending on the situation.

[0083] In one embodiment, the CPU (211) can determine whether the stall ratio of CPU cycles exceeds a first threshold value (e.g., first threshold stall ratio (stall_ratio_rise)) that is preset. If the stall ratio of CPU cycles exceeds the first threshold value, the CPU (211) can determine whether the CPU stall is a memory-bound stall or a CPU-bound stall. In one embodiment, a memory-bound stall may be a stall caused by a memory access delay (e.g., a delay in accessing external memory of the CPU (211), such as a DRAM).

[0084] If the CPU stall is a CPU-bound stall, the CPU (211) may adjust (e.g., increase) the operating voltage and operating frequency of the CPU (211) based on the DVFS method when the power budget room is greater than or equal to a set threshold value (e.g., a third threshold value) to escape the CPU stall situation. If the CPU stall is a memory-bound stall, the CPU (211) may increase the QoS value applied to transactions of the CPU (211) by a set value (e.g., 1). In one embodiment, it will be described assuming that a larger QoS value for a transaction indicates a higher priority; however, alternatively, a smaller QoS value for a transaction may indicate a higher priority. Hereinafter, for convenience of explanation, the QoS value may also be referred to as a “QoS-related value.” For example, a transaction may be forwarded to the memory controller (219) based on a priority determined based on a QoS value. For example, a QoS value applied to a transaction may include a priority used to pass the transaction to at least one additional circuit associated with accessing memory (e.g., an interconnect block (217) and / or a memory (e.g., DRAM, SRAM, Compute Express Link (CXL) memory, etc.) controller (219)). For example, transactions with the same QoS value may be passed to the memory controller (219) sequentially, or alternatively, a transaction with a larger QoS value (e.g., higher priority) may be passed to the memory controller (219) with preference over a transaction with a smaller QoS value (e.g., lower priority). In one embodiment, the QoS value may include a priority used when the interconnect block (217) processes transactions requested by IP blocks (e.g., a CPU (211), a GPU (213), and / or a multimedia block (215)).Each of the IP blocks (e.g., CPU (211), GPU (213), and / or multimedia block (215)) can assign a QoS value to the transaction when the transaction is created, and the interconnect block (217) can differentiate the processing order based on the QoS value assigned to the transaction created in each of the IP blocks (e.g., CPU (211), GPU (213), and / or multimedia block (215)). For example, the interconnect block (217) can sequentially process transactions with the same QoS value, while prioritizing a transaction with a higher QoS value over a transaction with a lower QoS value. For example, the QoS value can be used as a priority indicator for the associated read / write transaction, and a higher value can indicate a higher priority transaction.

[0085] The CPU (211), which increases the QoS value applied to the transactions of the CPU (211) by a set value, can detect the stall ratio of the CPU cycle. The CPU (211) can check whether the stall ratio of the detected CPU cycle after increasing the QoS value by the set value is less than a preset second threshold value (e.g., second threshold stall ratio (stall_ratio_fall)). If the stall ratio of the CPU cycle is less than the second threshold value, the CPU (211) can restore the QoS value applied to the transactions of the CPU (211) to its original value (e.g., a value reduced by the set value). If the stall ratio of the detected CPU cycle after increasing the QoS value by the set value is equal to or greater than the second threshold value or the first threshold value, the CPU (211) can check whether the power budget room is equal to or greater than a third threshold value. In one embodiment, if the power budget room is equal to or greater than the third threshold value, it may indicate that the available power is relatively sufficient.

[0086] When the power budget room is equal to or greater than the third threshold, the CPU (211) can adjust the operating voltage and operating frequency of each of the interconnect block (217) and the memory controller (219). According to one embodiment, the CPU (211) can increase the operating voltage of each of the interconnect block (217) and the memory controller (219) by a set voltage, and can increase the operating frequency of each of the interconnect block (217) and the memory controller (219) by a set frequency. When the power budget room is equal to or greater than the third threshold, the CPU (211) can maintain the operating voltage and operating frequency of the CPU (211). In this way, the CPU (211) can detect the stall ratio of the CPU cycle after adjusting the operating voltage and operating frequency of each of the interconnect block (217) and the memory controller (219). The CPU (211) can check whether the stall ratio of the detected CPU cycle is less than the second threshold value or the first threshold value after adjusting the operating voltage and operating frequency of each of the interconnect block (217) and the memory controller (219). If the stall ratio of the detected CPU cycle is less than the second threshold value, which is preset, after adjusting the operating voltage and operating frequency of each of the interconnect block (217) and the memory controller (219), the CPU (211) can restore the QoS value applied to the transactions of the CPU (211) to its original value (e.g., a value reduced by the preset value). If the stall ratio of the detected CPU cycle is less than the second threshold value, which is preset, after adjusting the operating voltage and operating frequency of each of the interconnect block (217) and the memory controller (219), the CPU (211) can restore the operating voltage and operating frequency of each of the interconnect block (217) and the memory controller (219) to their original operating voltage and operating frequency.In one embodiment, when the stall ratio of the detected CPU cycle is less than a preset second threshold value after adjusting the operating voltage and operating frequency of each of the interconnect block (217) and the memory controller (219), the CPU (211) can lower the operating voltage of each of the interconnect block (217) and the memory controller (219) by the preset voltage, and lower the operating frequency of each of the interconnect block (217) and the memory controller (219) by the preset frequency.

[0087] When the power budget room is less than the third threshold value, the CPU (211) can adjust the operating voltage and operating frequency of each of the CPU (211), the interconnect block (217), and the memory controller (219). According to one embodiment, the CPU (211) can lower the operating voltage of the CPU (211) by a set voltage and lower the operating frequency of the CPU (211) by a set frequency, and at the same time, increase the operating voltage of each of the interconnect block (217) and the memory controller (219) by a set voltage and increase the operating frequency of each of the interconnect block (217) and the memory controller (219) by a set frequency. In this way, when the power budget room is below the third threshold (e.g., when the power budget is insufficient), the CPU (211) can escape from the CPU stall situation as quickly as possible by lowering the operating frequency and operating voltage of the CPU (211), which maintains a high operating frequency, even though it cannot process instructions quickly because most of the CPU cycles are occupied by CPU stall due to memory access, and using the saved power budget to increase the operating frequency and operating voltage of the interconnect block (217) and the memory controller (219).

[0088] In this way, the CPU (211) can detect the stall ratio of the CPU cycle after adjusting the operating voltage and operating frequency of each of the CPU (211), the interconnect block (217), and the memory controller (219). The CPU (211) can check whether the stall ratio of the CPU cycle detected after adjusting the operating voltage and operating frequency of each of the CPU (211), the interconnect block (217), and the memory controller (219) is less than a second threshold value. If the stall ratio of the CPU cycle detected after adjusting the operating voltage and operating frequency of each of the CPU (211), the interconnect block (217), and the memory controller (219) is less than a preset second threshold value, the QoS value applied to the transactions of the CPU (211) can be restored to its original value (e.g., a value reduced by the set value). When the stall ratio of the detected CPU cycle is less than a preset second threshold value after adjusting the operating voltage and operating frequency of each of the CPU (211), the interconnect block (217), and the memory controller (219), the CPU (211) can restore the operating voltage and operating frequency of each of the interconnect block (217) and the memory controller (219) to the original operating voltage and operating frequency. In one embodiment, when the stall ratio of the detected CPU cycle is less than the preset second threshold value after adjusting the operating voltage and operating frequency of each of the CPU (211), the interconnect block (217), and the memory controller (219), the CPU (211) can lower the operating voltage of each of the interconnect block (217) and the memory controller (219) by the preset voltage, and lower the operating frequency of each of the interconnect block (217) and the memory controller (219) by the preset frequency.After adjusting the operating voltage and operating frequency of each of the CPU (211), the interconnect block (217), and the memory controller (219), if the stall ratio of the detected CPU cycle is less than a preset second threshold value, the CPU (211) can restore the operating voltage and operating frequency of the CPU (211) to the original operating voltage and operating frequency. In one embodiment, the CPU (211) can increase the operating voltage of the CPU (211) by a set voltage, and can increase the operating frequency of the CPU (211) by a set frequency.

[0089] Figure 3 is a block diagram schematically illustrating a CPU according to one embodiment.

[0090] Referring to FIG. 3, a CPU (211) (e.g., CPU (211) of FIG. 2) may be included in an AP (e.g., processor (120) of FIG. 1 or AP (200) of FIG. 2). The CPU (211) may include a PMU monitor (311), a QoS governor (313), and / or a DVFS governor (315). In FIG. 3, a case where the PMU monitor (311), the QoS governor (313), and / or the DVFS governor (315) are implemented as separate blocks is described as an example, but at least two of the PMU monitor (311), the QoS governor (313), and / or the DVFS governor (315) may be integrated into one block.

[0091] According to one embodiment, the PMU monitor (311) can collect and analyze information provided by the PMU. According to one embodiment, the PMU monitor (311) can collect and analyze information provided by the PMU to determine (e.g., calculate) metrics as shown in Table 1 below.

[0092] Table 1

[0093]

[0094] In Table 1, IPC can represent the IPC of the CPU (211). For example, IPC can be determined as INST_RETIRED / CPU_CYCLES.

[0095] In Table 1, Stall Ratio may represent the stall ratio of the CPU (211), and may be determined as one of STALL / CPU_CYCLES, STALL_FRONTEND / CPU_CYCLES, and / or STALL_BACKED / CPU_CYCLES.

[0096] In Table 1, the Cache Miss Rate may represent the ratio of the number of cache accesses in which a miss occurred among the total number of cache accesses of the CPU (211), and may be determined as one of L1I_CACHE_REFILL / L1I_CACHE, L1D_CACHE_REFILL / L1D_CACHE, L2D_CACHE_REFILL / L2D_CACHE, and / or L3D_CACHE_REFILL / L3D_CACHE.

[0097] In Table 1, the TLB Miss Rate may represent the ratio of the number of TLB accesses in which a miss occurred among the total number of TLB accesses, and may be determined as any one of L1I_TLB_REFLL / L1I_TLB, L1D_TLB_REFILL / L1D_TLB, and / or L2D_TLB_REFILL / L2D_TLB.

[0098] In Table 1, the Branch Misprediction Rate may represent the ratio of branch instructions that were mispredicted and executed among all branch instructions executed by the CPU (211), and may be determined as BR_MIS_PRED_RETIRED / BR_RETIRED.

[0099] The QoS manager (313) can control QoS values ​​for transactions from the CPU (211), the GPU (213), and / or the multimedia block (215). The DVSF manager (313) can control DVFS operations. According to one embodiment, the DVSF manager (313) can control (or adjust) operating voltages and / or operating frequencies for the CPU (211) and other IP blocks (e.g., a GPU (e.g., GPU (213)), a multimedia block (e.g., multimedia block (215)), an interconnect block (e.g., interconnect block (217)), and / or a memory controller (e.g., memory controller (219)).

[0100] According to one embodiment, the PMU monitor (311) may detect a stall ratio of CPU cycles based on information collected from the PMU, and transmit a command to the QoS manager (313) to control a QoS value for a transaction from the CPU (211), the GPU (213), and / or the multimedia block (215). In one embodiment, the stall ratio of CPU cycles may indicate the proportion of CPU cycles occupied by a CPU stall period. In Table 1, Stall Ratio may correspond to the stall ratio of the cycles. According to one embodiment, the stall ratio of CPU cycles may be detected based on information provided from the PMU for a set time (e.g., 1 second). In one embodiment, the set time may indicate an optimal time required to detect a CPU operating situation and perform appropriate power control, and the set time for detecting the stall ratio of CPU cycles may vary depending on the situation.

[0101] According to one embodiment, the PMU monitor (311) can check whether the stall ratio of CPU cycles exceeds a first threshold value that is preset (e.g., first threshold stall ratio (stall_ratio_rise)). If the stall ratio of CPU cycles exceeds the first threshold value, the PMU monitor (311) can check whether the CPU stall is a CPU stall caused by a memory access delay (e.g., a DRAM access delay). According to one embodiment, the CPU stall caused by the memory access delay may be a memory bound stall. In one embodiment, the memory bound stall may be a stall caused by a memory access delay (e.g., a delay in accessing an external memory of the processor (e.g., the CPU), such as a DRAM). If the CPU stall is not a CPU stall caused by a DRAM access delay, the PMU monitor (311) can check whether the CPU stall is a CPU bound stall.

[0102] If the CPU stall is caused by a delay in accessing memory (e.g., DRAM, SRAM, CXL (Compute Express Link) memory, etc.), the PMU monitor (311) may send a command to the QoS manager (313) to increase the QoS value applied to transactions of the CPU (211) by a set value (e.g., 1). In one embodiment, it will be explained assuming that the higher the QoS value for a transaction, the higher the priority; however, conversely, the lower the QoS value for a transaction, the higher the priority.

[0103] After increasing the QoS value applied to the transactions of the CPU (211) by a set value, the PMU monitor (311) can detect the stall ratio of the CPU cycle and transmit a command to the QoS manager (313) and the DVFS manager (315) based on the detected stall ratio. The PMU monitor (311) can determine whether the stall ratio of the detected CPU cycle is less than a preset second threshold value (e.g., second threshold stall ratio (stall_ratio_fall)) after transmitting the command to the QoS manager (313) to increase the QoS value by the set value. If the stall ratio of the CPU cycle is less than the second threshold value, the PMU monitor (311) can transmit a command to the QoS manager (313) to restore the QoS value applied to the transactions of the CPU (211) to its original value (e.g., a value reduced by the set value). After increasing the QoS value by a set value, if the stall ratio of the detected CPU cycle is greater than or equal to the second threshold or the first threshold, the PMU monitor (311) can check whether the power budget room is greater than or equal to the third threshold. In one embodiment, if the power budget room is greater than or equal to the third threshold, it may indicate that the available power is relatively sufficient.

[0104] When the power budget room is equal to or greater than the third threshold, the PMU monitor (311) can transmit a command to the DVFS manager (315) to adjust the operating voltage and operating frequency of each of the interconnect block and the memory controller. According to one embodiment, the PMU monitor (311) can transmit a command to the DVFS manager (315) to increase the operating voltage of each of the interconnect block and the memory controller by a set voltage, and to increase the operating frequency of each of the interconnect block and the memory controller by a set frequency. When the power budget room is equal to or greater than the third threshold, the PMU monitor (311) can maintain the operating voltage and operating frequency of the CPU (211) without transmitting a separate command to the DVFS manager (315). In this way, the PMU monitor (311) transmits a command to the DVFS manager (315) to adjust the operating voltage and operating frequency of each of the interconnect block and the memory controller, and then the PMU monitor (311) detects the stall ratio of the CPU cycle and, based on this, transmits a command to the QoS manager (313) and the DVFS manager (315). The PMU monitor (311) transmits a command to the DVFS manager (315) to adjust the operating voltage and operating frequency of each of the interconnect block and the memory controller, and then determines whether the stall ratio of the detected CPU cycle is less than a second threshold value. The PMU monitor (311) transmits a command to the DVFS manager (315) to adjust the operating voltage and operating frequency of each interconnect block and memory controller, and when the stall ratio of the detected CPU cycle is less than a preset second threshold value, the PMU monitor (311) transmits a command to the QoS manager (313) to restore the QoS value applied to the transactions of the CPU (211) to the original value (e.g., a value reduced by the preset value).If the stall ratio of the CPU cycle detected after adjusting the operating voltage and operating frequency of each of the interconnect block and the memory controller is less than a preset second threshold value, the PMU monitor (311) may transmit a command to the DVFS manager (315) to restore the operating voltage and operating frequency of each of the interconnect block and the memory controller to the original operating voltage and operating frequency. In one embodiment, if the stall ratio of the CPU cycle detected after adjusting the operating voltage and operating frequency of each of the interconnect block and the memory controller is less than the preset second threshold value, the PMU monitor (311) may transmit a command to the DVFS manager (315) to lower the operating voltage of each of the interconnect block and the memory controller by the preset voltage, and to lower the operating frequency of each of the interconnect block and the memory controller by the preset frequency.

[0105] When the power budget room is less than the third threshold value, the PMU monitor (311) can transmit a command to the DVFS manager (315) to adjust the operating voltage and operating frequency of each of the CPU (211), the interconnect block, and the memory controller. According to one embodiment, the PMU monitor (311) can transmit a command to the DVFS manager (315) to lower the operating voltage of the CPU (211) by a set voltage and to lower the operating frequency of the CPU (211) by the set frequency, while simultaneously increasing the operating voltage of each of the interconnect block and the memory controller by the set voltage and increasing the operating frequency of each of the interconnect block and the memory controller by the set frequency.

[0106] In this way, after the DVFS manager (315) adjusts the operating voltage and operating frequency of each of the CPU (211), the interconnect block, and the memory controller, the PMU monitor (311) can detect the stall ratio of the CPU cycle and, based on this, transmit a command to the QoS manager (313) and the DVFS manager (315). The PMU monitor (311) can transmit a command to the DVFS manager (315) to adjust the operating voltage and operating frequency of each of the CPU (211), the interconnect block, and the memory controller, and then check whether the stall ratio of the detected CPU cycle is less than a second threshold value. The PMU monitor (311) transmits a command to the DVFS manager (315) to adjust the operating voltage and operating frequency of each of the CPU (211), the interconnect block, and the memory controller, and then, when the stall ratio of the detected CPU cycle is less than a preset second threshold value, transmits a command to the QoS manager (313) to restore the QoS value applied to the transactions of the CPU (211) to the original value (e.g., a value reduced by the preset value).

[0107] According to one embodiment, if the stall ratio of the CPU cycle detected after adjusting the operating voltage and operating frequency of each of the CPU (211), the interconnect block, and the memory controller is less than a preset second threshold value, the PMU monitor (311) may transmit a command to the DVFS manager (315) to restore the operating voltage and operating frequency of each of the interconnect block and the memory controller to the original operating voltage and operating frequency. In one embodiment, if the stall ratio of the CPU cycle detected after adjusting the operating voltage and operating frequency of each of the CPU (211), the interconnect block, and the memory controller is less than the preset second threshold value, the PMU monitor (311) may transmit a command to the DVFS manager (315) to lower the operating voltage of each of the CPU (211), the interconnect block, and the memory controller by the preset voltage, and to lower the operating frequency of each of the interconnect block and the memory controller by the preset frequency. After adjusting the operating voltage and operating frequency of each of the CPU (211), the interconnect block, and the memory controller, if the stall ratio of the detected CPU cycle is less than a preset second threshold value, the PMU monitor (311) can transmit a command to the DVFS manager (315) to restore the operating voltage and operating frequency of the CPU (211) to the original operating voltage and operating frequency. In one embodiment, the PMU monitor (311) can transmit a command to the DVFS manager (315) to increase the operating voltage of the CPU (211) by a set voltage and to increase the operating frequency of the CPU (211) by a set frequency.

[0108] FIG. 4 is a block diagram schematically illustrating the software architecture of an AP according to one embodiment.

[0109] Referring to FIG. 4, an AP (e.g., AP (200) of FIG. 2) may be implemented with a software architecture, and the software architecture (400) of the AP may include a user interface layer (411), a governor layer (413), a device driver layer (415), and / or an operating system (OS) layer (417).

[0110] According to one embodiment, the user interface layer (411) may include multiple applications.

[0111] According to one embodiment, the governor layer (413) may include a PMU monitor (e.g., the PMU monitor (311) of FIG. 3), a QoS manager (e.g., the QoS manager (313) of FIG. 3), and / or a DVFS manager (e.g., the DVFS manager (315) of FIG. 3). The PMU monitor, the QoS manager, and / or the DVFS manager may be implemented similarly or substantially identically to those described in FIG. 3, and thus, a detailed description thereof is omitted herein.

[0112] According to one embodiment, the device driver layer (415) may include a CPU frequency driver (CPUfreq) and / or a device frequency driver (Devfreq).

[0113] According to one embodiment, the OS layer (417) may include a kernel.

[0114] According to one embodiment of the present disclosure, an electronic device (101) may include at least one of a graphic processing unit (GPU) (213) or a multimedia block (215), a processor (120; 200; 211) including processing circuitry, and a memory (130) for storing instructions.

[0115] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to detect a first stall ratio for processor cycles of the processor.

[0116] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to determine whether the first stall ratio exceeds a first threshold value.

[0117] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to determine whether a processor stall of the processor satisfies a condition related to a memory access delay to the memory, based on determining that the first stall ratio exceeds the first threshold value.

[0118] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to adjust a quality of service (QoS) related value applied to a transaction of the processor to be higher than a QoS related value applied to a transaction of at least one of the GPU or the multimedia block, based on determining that the condition is satisfied.

[0119] According to one embodiment of the present disclosure, the condition may include at least one of a condition in which a cache miss occurs while the processor performs an operation of fetching an instruction from a cache, a condition in which access to the memory is required due to a cache miss that occurs while the processor performs a read / write operation for the cache, or a condition in which a miss rate of the cache exceeds a threshold miss rate.

[0120] According to one embodiment of the present disclosure, the electronic device may include at least one additional circuit (217; 219) associated with accessing the memory.

[0121] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to detect a second stall ratio for the processor cycle after adjusting a QoS related value applied to a transaction of the processor.

[0122] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to determine whether the second stall ratio is less than a second threshold value.

[0123] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to determine whether a power budget room is greater than or equal to a third threshold value based on determining that the second stall ratio is greater than or equal to the second threshold value.

[0124] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to increase an operating voltage and an operating frequency of the at least one additional circuit based on determining that the power budget room is greater than or equal to the third threshold value.

[0125] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to increase an operating voltage of the at least one additional circuit by a set voltage and to increase an operating frequency of the at least one additional circuit by a set frequency.

[0126] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to reduce an operating voltage and an operating frequency of the at least one processor based on determining that the power budget room is below the third threshold value.

[0127] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to increase an operating voltage and an operating frequency of the at least one additional circuit.

[0128] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to detect a third stall ratio for the processor cycle after increasing an operating voltage and an operating frequency of the at least one additional circuit.

[0129] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to determine whether the third stall ratio is less than the second threshold value.

[0130] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to perform at least one of a first operation of restoring a QoS-related value applied to a transaction of the adjusted processor to the QoS-related value prior to the adjustment, based on determining that the third stall ratio is less than the second threshold value, or a second operation of restoring an operating voltage and an operating frequency of the processor to the operating voltage and operating frequency prior to the reduction, or restoring an operating voltage and an operating frequency of the at least one additional circuit to the operating voltage and operating frequency prior to the increase.

[0131] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to operate based on a dynamic voltage and frequency scaling (DVFS) scheme after performing at least one of the first operation or the second operation.

[0132] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to operate based on a dynamic voltage and frequency scaling (DVFS) scheme based on determining that the first stall ratio is less than or equal to the first threshold value, or based on determining that the condition is not satisfied.

[0133] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, may cause the electronic device to perform the first operation based on determining that the third stall ratio is greater than or equal to the second threshold value.

[0134] According to one embodiment of the present disclosure, the QoS related values ​​applied to a transaction may include a priority used to forward the transaction to at least one additional circuit (217; 219) associated with accessing the memory and / or a priority used to process the transaction in the at least one additional circuit (217; 219).

[0135] According to one embodiment of the present disclosure, the instructions, when individually or collectively executed by the processor, cause the electronic device to transfer the transaction of the processor to at least one additional circuit (217; 219) associated with accessing the memory with priority over the transaction of the GPU or at least one of the multimedia blocks by adjusting a QoS-related value applied to the transaction of the processor to be higher than a QoS-related value applied to the transaction of the GPU or at least one of the multimedia blocks, or cause the transaction of the processor to be processed in the at least one additional circuit with priority over the transaction of the GPU or at least one of the multimedia blocks.

[0136] FIG. 5 is a flowchart illustrating an operating method of an electronic device according to one embodiment.

[0137] Referring to FIG. 5, an electronic device (e.g., an electronic device (101) of FIG. 1) (e.g., an AP (200) of FIG. 2 or a CPU (211) of FIG. 2 or FIG. 3) may detect a first stall ratio for a processor cycle of a processor (e.g., a CPU (211) of FIG. 2 or FIG. 3) in operation 511. The processor cycle may represent a CPU cycle, and a method of detecting the stall ratio may be implemented similarly or substantially identically to that described in FIG. 2 or FIG. 3, and thus, a detailed description thereof will be omitted herein.

[0138] The electronic device that detects the first stall ratio of the processor may, in operation 513, determine whether the first stall ratio exceeds a first threshold value. For example, the first threshold value may be a first threshold stall ratio. The first threshold value may be implemented similarly or substantially identically to that described in FIG. 2 or FIG. 3, and thus, a detailed description thereof will be omitted herein.

[0139] If the first stall ratio exceeds the first threshold value (operation 513 - Yes), the electronic device may determine in operation 515 whether the processor stall of the processor is due to a memory access delay to a memory (e.g., memory (130) of FIG. 1). In one embodiment, the processor stall may refer to a “CPU stall,” and it should be noted that the terms processor stall and CPU stall may be used interchangeably for the convenience of the following description. The CPU stall may be similar to that described with reference to FIGS. 2 to 4, and thus, a detailed description thereof will be omitted herein. In one embodiment, the processor stall caused by a memory access delay may be a memory-bound stall. In one embodiment, the memory-bound stall may be a stall caused by a memory access delay (e.g., a delay in accessing an external memory of the processor (e.g., CPU), such as a DRAM).

[0140] If the processor stall is due to a memory access delay (operation 515 - Yes), the electronic device may adjust the QoS value applied to the instruction transaction of the processor in operation 517. In one embodiment, the electronic device may adjust the QoS value applied to the instruction transaction of the processor to be higher than the QoS value applied to the instruction transaction of the GPU.

[0141] After adjusting the QoS value applied to the instruction transaction of the processor, the electronic device detects a second stall ratio for the processor cycle, determines whether the second stall ratio is less than a second threshold value, and if it is determined that the second stall ratio is greater than or equal to the second threshold value or the first threshold value, determines whether the power budget room is greater than or equal to a third threshold value, and based on determining that the power budget room is greater than or equal to the third threshold value, the electronic device can adjust the operating voltage and operating frequency of at least one IP block (or circuit) (e.g., the GPU (213) of FIG. 2 or FIG. 3, the multimedia block (215) of FIG. 2 or FIG. 3, the interconnect block (217) of FIG. 2 or FIG. 3, and / or the memory controller (219) of FIG. 2 or FIG. 3). In FIG. 5, the at least one IP block (or circuit) is described as including a CPU, a GPU, a multimedia block, an interconnect block, and / or a memory controller, but is not limited thereto, and may include additional various IP blocks such as an NPU. The electronic device may perform at least one of a first operation of detecting a third stall ratio of a processor cycle after adjusting an operating voltage and an operating frequency of at least one IP block, determining whether the third stall ratio is less than a second threshold, and restoring a QoS value applied to a transaction of the adjusted at least one processor to a QoS value before the adjustment based on determining that the third stall ratio is less than the second threshold, or a second operation of restoring an operating voltage and an operating frequency of the adjusted at least one processor or at least one IP block to the operating voltage and operating frequency before the adjustment.

[0142] If the first stall ratio is less than or equal to the first threshold (Action 513-No), the electronic device may, in operation 519, operate based on the DVFS scheme without QoS adjustment (e.g., maintain an operation mode in which it operates based on the existing DVFS scheme without QoS adjustment). If the processor stall is not a processor stall caused by a memory access delay (Action 515-No), the electronic device may, in operation 519, operate based on the DVFS scheme without QoS adjustment (e.g., maintain an operation mode in which it operates based on the existing DVFS scheme without QoS adjustment).

[0143] FIG. 6 is a diagram illustrating a method for determining a stall ratio of CPU cycles according to one embodiment.

[0144] Referring to FIG. 6, the AP (200) (e.g., the AP (200) of FIG. 2) may include a CPU (211) (e.g., the CPU (211) of FIG. 2 or FIG. 3), a GPU (213) (e.g., the GPU (213) of FIG. 2), a multimedia block (215) (e.g., the multimedia block (215) of FIG. 2), an interconnect block (217) (e.g., the interconnect block (217) of FIG. 2), and / or a memory controller (219) (e.g., the memory controller (219) of FIG. 2). The AP (200) may correspond to the processor (120) of FIG. 1. In one embodiment, the CPU (211) may be a processor. In FIG. 2, the memory controller (219) is described as an example, but the AP (200) may include an IP block capable of controlling not only DRAM but also memory. According to one embodiment, the AP (200) may be implemented in the form of a SoC.

[0145] According to one embodiment, the CPU (211) can collect and analyze information provided by the PMU. The CPU (211) can collect and analyze information provided by the PMU at a set cycle (e.g., every 1 second). The set cycle used to collect and analyze information provided by the PMU may vary depending on the situation. The information provided by the PMU can be implemented similarly or substantially identically to that described in FIG. 3, and therefore, a detailed description thereof will be omitted herein.

[0146] According to one embodiment, the CPU (211) can detect a stall ratio (stall_ratio) of a CPU cycle based on information provided by the PMU (e.g., an event provided by the PMU). In one embodiment, the stall ratio of a CPU cycle can indicate a ratio of a CPU cycle occupied by a CPU stall period. According to one embodiment, the stall ratio of a CPU cycle can be detected based on information provided by the PMU for a set time (e.g., 1 second). In one embodiment, the set time can indicate an optimal time required to detect a CPU operating situation and perform appropriate power control, and the set time for detecting the stall ratio of a CPU cycle can vary depending on the situation.

[0147] According to one embodiment, the CPU (211) can determine whether the stall ratio of CPU cycles exceeds a first threshold value that is preset (e.g., first threshold stall ratio (stall_ratio_rise)). If the stall ratio of CPU cycles exceeds the first threshold value, the CPU (211) can determine whether the CPU stall is a CPU stall (e.g., memory-bound stall) caused by a memory access delay (e.g., DRAM access delay). If the CPU stall is not a CPU stall caused by a DRAM access delay, the CPU (211) can determine whether the CPU stall is a CPU-bound stall. According to one embodiment, the CPU (211) can determine whether the CPU stall is a memory-bound stall or a CPU-bound stall based on information provided by the PMU.

[0148] In one embodiment, information provided by the PMU used to determine whether a CPU stall is a memory-bound stall may include STALL_FRONTEND_MEMBOUND and / or STALL_BACKEND_MEMBOUND. In one embodiment, STALL_FRONTEND_MEMBOUND may include a case where a cache miss occurs during an instruction fetch operation. In one embodiment, STALL_BACKEND_MEMBOUND may include a case where an access to external memory (e.g., DRAM) is required due to a cache miss occurring during a read / write operation.

[0149] In one embodiment, information provided by the PMU used to determine whether a CPU stall is a CPU-bound stall may include STALL_FRONTEND_CPUBOUND and / or STALL_BACKEND_CPUBOUND. In one embodiment, STALL_BACKEND_CPUBOUND may include a case where an instruction is delayed and cannot be executed due to a lack of resources in the CPU's internal execution engine.

[0150] In one embodiment, STALL_FRONTEND_CPUBOUND may include cases where a delay occurs due to a CPU pipeline flush operation caused by a branch misprediction.

[0151] According to one embodiment, the CPU (211) can determine whether the CPU stall is a memory bound stall or a CPU bound stall when it can obtain information such as STALL_FRONTEND_MEMBOUND, STALL_BACKEND_MEMBOUND, STALL_FRONTEND_CPUBOUND and / or STALL_BACKEND_CPUBOUND from the PMU.

[0152] If information such as STALL_FRONTEND_MEMBOUND, STALL_BACKEND_MEMBOUND, STALL_FRONTEND_CPUBOUND, and / or STALL_BACKEND_CPUBOUND is not provided from the PMU, the CPU (211) may use at least one of a cache miss rate (e.g., L1 I$ miss rate and / or L1 D$ miss rate), a branch misprediction rate, and / or a TLB miss rate to determine whether the CPU stall is a memory-bound stall or a CPU-bound stall.

[0153] As described in Table 1, the branch misprediction rate may represent the ratio of branch instructions that were mispredicted among all branch instructions executed by the CPU (211), and may be determined as BR_MIS_PRED_RETIRED / BR_RETIRED. As the branch misprediction rate increases, a CPU-bound stall may occur due to a pipeline flush operation caused by frequent misprediction. In one embodiment, the CPU (211) may determine that a CPU stall is a CPU-bound stall if the branch misprediction rate exceeds a fourth threshold value.

[0154] As described in Table 1, the cache miss rate may represent the ratio of the number of cache accesses in which a miss occurred among the total number of cache accesses of the CPU (211), and may be determined as any one of L1I_CACHE_REFILL / L1I_CACHE, L1D_CACHE_REFILL / L1D_CACHE, L2D_CACHE_REFILL / L2D_CACHE, and / or L3D_CACHE_REFILL / L3D_CACHE. As described in Table 1, the TLB miss rate may represent the ratio of the number of TLB accesses in which a miss occurred among the total number of TLB accesses, and may be determined as any one of L1I_TLB_REFLL / L1I_TLB, L1D_TLB_REFILL / L1D_TLB, and / or L2D_TLB_REFILL / L2D_TLB.

[0155] The cache miss rate and / or the TLB miss rate may be related to external memory (e.g., DRAM) accesses. In one embodiment, the CPU (211) may determine that the CPU stall is a memory-bound stall if the cache miss rate exceeds a fifth threshold value. In one embodiment, the CPU (211) may determine that the CPU stall is a memory-bound stall if the TLB miss rate exceeds a sixth threshold value.

[0156] In one embodiment, the CPU (211) can determine whether the CPU stall is a memory-bound stall based on a miss rate of a cache level connected to the interconnect block (217). In one embodiment, when a shared L2 cache is provided as the last level cache in a CPU cluster, the L2$ miss rate may be a miss rate of the cache level, and the CPU (211) can determine whether the CPU stall is a memory-bound stall based on the L2$ miss rate. The CPU (211) can determine that the CPU stall is a memory-bound stall if the L2$ miss rate exceeds a fifth threshold value. In one embodiment, when a shared L2 cache is used as the last level cache within a CPU cluster, the L3$ miss rate may be a miss rate of the cache level, and the CPU (211) may determine whether a CPU stall is a memory-bound stall based on the L3$ miss rate. The CPU (211) may determine that a CPU stall is a memory-bound stall if the L3$ miss rate exceeds a fifth threshold value.

[0157] As illustrated in FIG. 6, the CPU (211) may include a plurality of L1 instruction caches (I$) (611, 613, 615, 617), a plurality of L1 data caches (D$) (621, 623, 625, 627), a plurality of L2 caches (631, 633, 635, 637), and / or an L3 cache (641). In this case, the CPU (211) may determine whether a CPU stall is a memory-bound stall based on an L3$ miss rate for the L3 cache (641). In one embodiment, a fifth threshold value used to determine whether a CPU stall is a memory-bound stall may be changed based on various parameters, such as a cache size.

[0158] Figure 7 is a flowchart illustrating an operating method of an electronic device according to one embodiment.

[0159] Referring to FIG. 7, an electronic device (e.g., an electronic device (101) of FIG. 1) (e.g., an AP (200) of FIG. 2 or FIG. 6, or a CPU (211) of FIG. 2, FIG. 3, or FIG. 6) may detect a stall ratio of a CPU cycle based on information provided from a PMU (e.g., an event provided from the PMU) in operation 711. In one embodiment, the electronic device may detect the stall ratio of a CPU cycle by collecting and analyzing information provided from the PMU at a set cycle (e.g., 1 second). The set cycle used to collect and analyze the information provided from the PMU may vary depending on the situation. The information provided from the PMU may be implemented similarly or substantially identically to that described in FIG. 3, and thus a detailed description thereof will be omitted herein. An operation of determining a stall ratio of a CPU cycle may be implemented similarly or substantially identically to that described in FIG. 3, and thus a detailed description thereof will be omitted herein.

[0160] An electronic device that has detected a stall ratio of a CPU cycle can, in operation 713, determine whether the stall ratio of the detected CPU cycle exceeds a preset first threshold value (e.g., first threshold stall ratio (stall_ratio_rise)). The first threshold value may be implemented similarly or identically to that described in FIG. 2, FIG. 3, or FIG. 5, and thus, a detailed description thereof will be omitted herein.

[0161] If the stall ratio of CPU cycles exceeds the first threshold value (operation 713 - Yes), the electronic device can determine whether the CPU stall is caused by a memory access delay (e.g., a DRAM access delay) in operation 715. The operation of determining whether the CPU stall is caused by a memory access delay can be implemented similarly or substantially the same as that described in FIG. 3, and thus a detailed description thereof is omitted here.

[0162] If the CPU stall is caused by a memory access delay (operation 715 - Yes), the electronic device may increase the QoS value applied to the transactions of the CPU by a set value (e.g., 1) in operation 717. In one embodiment, it will be explained assuming that a larger QoS value for a transaction indicates a higher priority; however, alternatively, a smaller QoS value for a transaction may indicate a higher priority.

[0163] An electronic device that increases the QoS value applied to CPU transactions by a set value can detect a stall ratio of CPU cycles based on information provided from the PMU in operation 719. The operation of detecting the stall ratio of CPU cycles can be implemented similarly or substantially identically to operation 711, and therefore, a detailed description thereof is omitted here.

[0164] An electronic device that detects a stall ratio of a CPU cycle can, in operation 721, determine whether the stall ratio of the detected CPU cycle (e.g., the stall ratio of the detected CPU cycle after increasing a QoS value applied to transactions of the CPU by a set value) is less than a preset second threshold value (e.g., a second threshold stall ratio (stall_ratio_fall)). The second threshold value may be implemented similarly or identically to that described in FIG. 2, FIG. 3, or FIG. 5, and thus, a detailed description thereof will be omitted herein.

[0165] If the stall ratio of the CPU cycle is less than the second threshold value (operation 721 - Yes), the electronic device may perform a restoration operation in operation 733. According to one embodiment, the restoration operation may include an operation of restoring the QoS value applied to the transactions of the CPU to its original value (e.g., a value reduced by a set value). The electronic device, which has restored the QoS value applied to the transactions of the CPU to its original value, may operate in a second operation mode in operation 735 and return to operation 711. In one embodiment, the second operation mode may be an operation mode that operates based on a general DVFS scheme.

[0166] If the stall ratio of CPU cycles is greater than or equal to the second threshold or the first threshold (operation 721 - No), the electronic device may determine in operation 723 whether the power budget room is greater than or equal to a preset third threshold. In one embodiment, if the power budget room is greater than or equal to the third threshold, this may indicate that the available power is relatively sufficient. The third threshold may be implemented similarly or identically to that described in FIG. 2, FIG. 3, or FIG. 5, and thus, a detailed description thereof will be omitted herein.

[0167] If the power budget room is greater than or equal to the third threshold value (operation 723 - Yes), the electronic device may adjust the operating voltage and operating frequency of each of the interconnect block (e.g., the interconnect block (217) of FIG. 2 or FIG. 6) and the memory controller (e.g., the memory controller (219) of FIG. 2 or FIG. 6) in operation 727. Although FIG. 7 illustrates an example of adjusting the operating voltage and operating frequency of each of the interconnect block and the memory controller, operation 727 may be applicable to at least one of the IP blocks associated with the CPU as well as the interconnect block and the memory controller. According to one embodiment, the electronic device may adjust the operating voltage and operating frequency of each of the interconnect block and the memory controller by increasing the operating voltage of each of the interconnect block and the memory controller by a set voltage, and by increasing the operating frequency of each of the interconnect block and the memory controller by a set frequency. When the power budget room is greater than or equal to the third threshold, the electronic device can maintain the operating voltage and operating frequency of the CPU in operation 727.

[0168] If the power budget room is less than the third threshold (operation 723-No), the electronic device may adjust the operating voltage and operating frequency of the CPU in operation 725. In one embodiment, the electronic device may adjust the operating voltage and operating frequency of the CPU by lowering the operating voltage of the CPU by a set voltage and lowering the operating frequency of the CPU by a set frequency in operation 725. Having adjusted the operating voltage and operating frequency of the CPU, the electronic device may proceed to operation 727 to adjust the operating voltage and operating frequency of each of the interconnect block and the memory controller.

[0169] After adjusting the operating voltage and operating frequency of each of the interconnect block and the memory controller, the electronic device can detect the stall ratio of the CPU cycle based on the information provided from the PMU in operation 729. The operation of detecting the stall ratio of the CPU cycle can be implemented similarly or substantially identically to operation 711, and thus a detailed description thereof is omitted here.

[0170] The electronic device that has detected the stall ratio of the CPU cycle may, in operation 731, determine whether the stall ratio of the detected CPU cycle is less than a second threshold value. If the stall ratio of the detected CPU cycle is less than the second threshold value after adjusting the operating voltage and operating frequency of each of the interconnect block and the memory controller (operation 731 - Yes), the electronic device may proceed to operation 733 to perform a restoration operation. According to one embodiment, the restoration operation may include an operation of restoring a QoS value applied to transactions of the CPU to an original value (e.g., a value reduced by a set value), and restoring the operating voltage and operating frequency of each of the interconnect block and the memory controller, and the operating voltage and operating frequency of the CPU to the original operating voltage and operating frequency. In one embodiment, the electronic device may lower the operating voltage of each of the interconnect block and the memory controller by a set voltage, and lower the operating frequency of each of the interconnect block and the memory controller by the set frequency, thereby restoring the operating voltage and operating frequency of each of the interconnect block and the memory controller to their original operating voltage and operating frequency. According to one embodiment, the restoring operation may restore the QoS value applied to transactions of the CPU to its original value (e.g., a value reduced by the set value), restore the operating voltage and operating frequency of each of the interconnect block and the memory controller to its original operating voltage and operating frequency, and restore the operating voltage and operating frequency of the CPU to its original operating voltage and operating frequency. In one embodiment, the electronic device may increase the operating voltage of the CPU by a set voltage, and increase the operating frequency of the CPU by the set frequency, thereby restoring the operating voltage and operating frequency of the CPU to its original operating voltage and operating frequency.

[0171] If the stall ratio of the detected CPU cycles is greater than or equal to the second threshold value after adjusting the operating voltage and operating frequency of each of the interconnect block and the memory controller (operation 731-No), the electronic device may return to operation 729.

[0172] FIG. 8 is a diagram illustrating a method for determining threshold values ​​used to control power based on the stall ratio of CPU cycles according to one embodiment.

[0173] Referring to FIG. 8, threshold values ​​used to control (e.g., adjust) a QoS value for a CPU transaction and / or to control (e.g., adjust) operating voltages and operating frequencies for a CPU (e.g., CPU (211) of FIG. 2, FIG. 3, or FIG. 6) and IP blocks associated with the CPU may include a first threshold value (e.g., a first threshold stall ratio (stall_ratio_rise)) and / or a second threshold value (e.g., a second threshold stall ratio (stall_ratio_fall)). The first threshold value and the second threshold value may be implemented similarly or identically to those described in FIG. 2, FIG. 3, FIG. 5, or FIG. 7, and thus, a detailed description thereof will be omitted herein.

[0174] In Fig. 8, the vertical axis may represent an operation mode, and the horizontal axis may represent a stall ratio of CPU cycles. In Fig. 8, the first operation mode may be an operation mode that controls QoS, an operation voltage, and / or an operation frequency based on the stall ratio of CPU cycles proposed in one embodiment of the present disclosure, and the second operation mode may be an operation mode that operates based on a general DVFS method. The first threshold value and the second threshold value may be applied in the first operation mode, and the first threshold value, the second threshold value, and / or the first operation mode may be implemented similarly or identically to those described in Figs. 2 to 7, and thus, a detailed description thereof will be omitted herein.

[0175] According to one embodiment, when the CPU sets the first threshold value and / or the second threshold value, it can prevent (e.g., reduce or minimize) a ping-pong phenomenon from occurring when operating based on the first operating mode by applying hysteresis as illustrated in FIG. 8. In one embodiment, the first operating mode can be applied when the stall ratio of the CPU cycles exceeds the first threshold value, where the first threshold value can be set to a first value (e.g., 50%), for example. In one embodiment, the second operating mode can be applied (e.g., transition from the first operating mode to the second operating mode) when the stall ratio of the CPU cycles is less than the second threshold value, where the second threshold value can be set to a second value (e.g., 30%), for example. In this way, when the first threshold value is set to 50% and the second threshold value is set to 30%, the CPU can be guaranteed to stably operate in the first operation mode or the second operation mode while the stall ratio of the CPU cycle fluctuates within the range of 30% to 50%.

[0176] According to one embodiment of the present disclosure, when a CPU stall occurs, it is possible to control (e.g., adjust) the QoS of the CPU based on information provided by the PMU (e.g., various events provided by the PMU), or to control (e.g., adjust) the operating voltage and operating frequency of IP blocks related to the CPU (e.g., interconnect blocks and / or DRAM controllers), thereby enabling the CPU to escape from the stall situation more quickly. This can contribute to improving unnecessary current consumption and increasing (e.g., maximizing) the usage time of the electronic device.

[0177] According to one embodiment of the present disclosure, a method of an electronic device (101) may include an operation of detecting a first stall ratio for a processor cycle of a processor (120; 200; 211) including processing circuitry.

[0178] According to one embodiment of the present disclosure, the method may include an operation of determining whether the first stall ratio exceeds a first threshold value.

[0179] According to one embodiment of the present disclosure, the method may include an operation of determining whether a processor stall of the processor satisfies a condition related to a memory access delay to the memory (130) based on determining that the first stall ratio exceeds the first threshold value.

[0180] According to one embodiment of the present disclosure, the method may include an operation of adjusting a quality of service (QoS) related value applied to a transaction of the processor to be higher than a QoS related value applied to a transaction of at least one of a graphic processing unit (GPU) (213) or a multimedia block (215), based on verifying that the condition is satisfied.

[0181] According to one embodiment of the present disclosure, the condition may include at least one of a condition in which a cache miss occurs while the processor performs an operation of fetching an instruction from a cache, a condition in which access to the memory is required due to a cache miss that occurs while the processor performs a read / write operation for the cache, or a condition in which a miss rate of the cache exceeds a threshold miss rate.

[0182] According to one embodiment of the present disclosure, the method may include detecting a second stall ratio for the processor cycle after adjusting a QoS-related value applied to a transaction of the processor.

[0183] According to one embodiment of the present disclosure, the method may include an operation of determining whether the second stall ratio is less than a second threshold value.

[0184] According to one embodiment of the present disclosure, the method may include an operation of determining whether a power budget room is greater than or equal to a third threshold value based on determining that the second stall ratio is greater than or equal to the second threshold value.

[0185] According to one embodiment of the present disclosure, the method may include increasing an operating voltage and an operating frequency of at least one additional circuit (217; 219) based on determining that the power budget room is greater than or equal to the third threshold value.

[0186] According to one embodiment of the present disclosure, the operation of adjusting the operating voltage and operating frequency of the at least one additional circuit may include an operation of increasing the operating voltage of the at least one additional circuit by a set voltage and increasing the operating frequency of the at least one additional circuit by a set frequency.

[0187] According to one embodiment of the present disclosure, the method may include reducing an operating voltage and an operating frequency of the at least one processor based on determining that the power budget room is less than the third threshold value.

[0188] According to one embodiment of the present disclosure, the method may include an operation of increasing an operating voltage and an operating frequency of the at least one additional circuit.

[0189] According to one embodiment of the present disclosure, the method may include detecting a third stall ratio for the processor cycle after increasing an operating voltage and an operating frequency of the at least one additional circuit.

[0190] According to one embodiment of the present disclosure, the method may include an operation of determining whether the third stall ratio is less than the second threshold value.

[0191] According to one embodiment of the present disclosure, the method may include performing at least one of a first operation of restoring a QoS-related value applied to a transaction of the adjusted processor to the QoS-related value before the adjustment, based on determining that the third stall ratio is less than the second threshold value, or a second operation of restoring an operating voltage and an operating frequency of the processor to the operating voltage and operating frequency before the reduction, or restoring an operating voltage and an operating frequency of the at least one additional circuit to the operating voltage and operating frequency before the increase.

[0192] According to one embodiment of the present disclosure, the method may include an operation that operates based on a dynamic voltage and frequency scaling (DVFS) scheme after performing at least one of the first operation or the second operation.

[0193] According to one embodiment of the present disclosure, the method may include an operation that operates based on a dynamic voltage and frequency scaling (DVFS) scheme, based on determining that the first stall ratio is less than or equal to the first threshold value, or based on determining that the processor stall does not satisfy the condition.

[0194] According to one embodiment of the present disclosure, the method may include performing the first operation based on determining that the third stall ratio is greater than or equal to the second threshold value.

[0195] According to one embodiment of the present disclosure, the QoS related values ​​applied to a transaction may include a priority used to forward the transaction to at least one additional circuit (217; 219) associated with accessing the memory and / or a priority used to process the transaction in the at least one additional circuit (217; 219).

[0196] According to one embodiment of the present disclosure, by adjusting a QoS-related value applied to a transaction of the processor to be higher than a QoS-related value applied to a transaction of at least one of the GPU or the multimedia block, the transaction of the processor may be transferred to at least one additional circuit (217; 219) related to accessing the memory with priority over the transaction of at least one of the GPU or the multimedia block, or the transaction of the processor may be processed with priority over the transaction of at least one of the GPU or the multimedia block in the at least one additional circuit.

[0197] According to one embodiment of the present disclosure, a storage medium storing at least one computer-readable command and data may be provided.

[0198] According to one embodiment of the present disclosure, the at least one command and data, when executed by a processor (120; 200; 211) including processing circuitry of the electronic device (101), may cause the electronic device (101) to perform at least one operation.

[0199] According to one embodiment of the present disclosure, the at least one operation may include detecting a first stall ratio for a processor cycle of the processor.

[0200] According to one embodiment of the present disclosure, the at least one operation may include an operation of determining whether the first stall ratio exceeds a first threshold value.

[0201] According to one embodiment of the present disclosure, the at least one operation may include an operation of determining whether a processor stall of the processor satisfies a condition related to a memory access delay to the memory (130) based on determining that the first stall ratio exceeds the first threshold value.

[0202] According to one embodiment of the present disclosure, the at least one operation may include adjusting a quality of service (QoS) related value applied to a transaction of the processor to be higher than a QoS related value applied to a transaction of at least one of a graphic processing unit (GPU) (213) or a multimedia block (215), based on determining that the processor stall is caused by the memory access delay.

[0203] According to one embodiment of the present disclosure, the condition may include at least one of a condition in which a cache miss occurs while the processor performs an operation of fetching an instruction from a cache, a condition in which access to the memory is required due to a cache miss that occurs while the processor performs a read / write operation for the cache, or a condition in which a miss rate of the cache exceeds a threshold miss rate.

[0204] The technical tasks to be achieved in this document are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those with ordinary skill in the technical field to which this document pertains from the description below.

[0205] The effects that can be obtained from the present disclosure are not limited to the effects mentioned above, and other effects that are not mentioned can be clearly understood by a person having ordinary skill in the art to which the present disclosure belongs from the description below.

Claims

1. In an electronic device (101), At least one of a graphic processing unit (GPU) (213) or a multimedia block (215); a processor (120; 200; 211) comprising processing circuitry; and A memory (130) for storing instructions, wherein the instructions, when individually or collectively executed by the processor, cause the electronic device to: Detecting a first stall ratio for the processor cycles of the above processor, Check whether the first stall ratio exceeds the first threshold value, Based on determining that the first stall ratio exceeds the first threshold, determining whether the processor stall of the processor satisfies a condition related to a memory access delay to the memory, and An electronic device that causes a quality of service (QoS) related value applied to a transaction of the processor to be adjusted higher than a QoS related value applied to a transaction of at least one of the GPU or the multimedia block based on verification that the above condition is satisfied.

2. In paragraph 1, The electronic device includes at least one of the following conditions: a condition in which a cache miss occurs while the processor performs an operation of fetching an instruction from a cache, a condition in which access to the memory is required due to a cache miss that occurs while the processor performs a read / write operation for the cache, or a condition in which a miss rate of the cache exceeds a threshold miss rate.

3. In paragraph 1 or 2, comprising at least one additional circuit (217; 219) associated with accessing said memory; When said instructions are individually or collectively executed by said processor, said electronic device: After adjusting the QoS related values ​​applied to the transaction of the above processor, a second stall ratio for the processor cycle is detected, Check whether the second stall ratio is less than the second threshold value, Based on the confirmation that the second stall ratio is greater than or equal to the second threshold value, it is confirmed whether the power budget room is greater than or equal to the third threshold value, and The electronic device causing the operating voltage and operating frequency of the at least one additional circuit to increase based on determining that the power budget room is greater than or equal to the third threshold value.

4. In paragraph 3, When said instructions are individually or collectively executed by said processor, said electronic device: An electronic device that causes the operating voltage of said at least one additional circuit to increase by a set voltage and the operating frequency of said at least one additional circuit to increase by a set frequency.

5. In paragraph 3, When said instructions are individually or collectively executed by said processor, said electronic device: reducing the operating voltage and operating frequency of the at least one processor based on determining that the power budget room is less than the third threshold value, and An electronic device causing an operating voltage and an operating frequency of said at least one additional circuit to increase.

6. In any one of paragraphs 3 to 5, When said instructions are individually or collectively executed by said processor, said electronic device: After increasing the operating voltage and operating frequency of at least one additional circuit, detecting a third stall ratio for the processor cycle, Check whether the third stall ratio is less than the second threshold value, The electronic device causing the adjusted processor to perform at least one of a first operation for restoring a QoS-related value applied to a transaction of the adjusted processor to the QoS-related value before the adjustment, or a second operation for restoring an operating voltage and an operating frequency of the processor to the operating voltage and operating frequency before the reduction, or restoring an operating voltage and an operating frequency of the at least one additional circuit to the operating voltage and operating frequency before the increase, based on determining that the third stall ratio is less than the second threshold value.

7. In paragraph 6, When said instructions are individually or collectively executed by said processor, said electronic device: An electronic device that causes an operation based on a dynamic voltage and frequency scaling (DVFS) method after performing at least one of the first operation or the second operation.

8. In any one of paragraphs 1 to 7, When said instructions are individually or collectively executed by said processor, said electronic device: An electronic device that causes the first stall ratio to operate based on a dynamic voltage and frequency scaling (DVFS) scheme, based on determining that the first stall ratio is less than or equal to the first threshold value, or based on determining that the condition is not satisfied.

9. In paragraph 6, When said instructions are individually or collectively executed by said processor, said electronic device: The electronic device causing the first operation to be performed based on determining that the third stall ratio is greater than or equal to the second threshold value.

10. In paragraph 1, The QoS related values ​​applied to the transaction include a priority used to pass said transaction to at least one additional circuit (217; 219) associated with accessing said memory and / or a priority used to process said transaction in said at least one additional circuit (217; 219), and The instructions, when individually or collectively executed by the processor, cause the electronic device to cause the transaction of the processor to be transferred to at least one additional circuit (217; 219) associated with accessing the memory with priority over the transaction of the GPU or the at least one multimedia block by adjusting a QoS-related value applied to the transaction of the processor to be higher than a QoS-related value applied to the transaction of the at least one multimedia block, or cause the at least one additional circuit to process the transaction of the processor with priority over the transaction of the at least one GPU or the at least one multimedia block.

11. In the method of electronic device (101), An operation of detecting a first stall ratio for processor cycles of a processor (120; 200; 211) including processing circuitry; An operation for determining whether the first stall ratio exceeds a first threshold value; An operation of determining whether a processor stall of the processor satisfies a condition related to a memory access delay to a memory (130) based on determining that the first stall ratio exceeds the first threshold value; and A method including an operation of adjusting a quality of service (QoS) related value applied to a transaction of the processor to be higher than a QoS related value applied to a transaction of at least one of a graphic processing unit (GPU) (213) or a multimedia block (215), based on verifying that the above condition is satisfied.

12. In paragraph 11, The method includes at least one of the following conditions: a condition in which a cache miss occurs while the processor performs an operation of fetching an instruction from a cache, a condition in which access to the memory is required due to a cache miss that occurs while the processor performs a read / write operation for the cache, or a condition in which a miss rate of the cache exceeds a threshold miss rate.

13. In paragraph 11 or 12, An operation of detecting a second stall ratio for the processor cycle after adjusting a QoS related value applied to a transaction of the processor; An operation for determining whether the second stall ratio is less than a second threshold value; An operation of determining whether the power budget room is greater than or equal to a third threshold value based on determining that the second stall ratio is greater than or equal to the second threshold value; and The method further comprising the operation of increasing the operating voltage and operating frequency of at least one additional circuit (217; 219) based on determining that the power budget room is greater than or equal to the third threshold value.

14. In paragraph 11, The QoS related values ​​applied to the transaction include a priority used to pass said transaction to at least one additional circuit (217; 219) associated with accessing said memory and / or a priority used to process said transaction in said at least one additional circuit (217; 219), and The method of passing the transaction of the processor to at least one additional circuit (217; 219) related to accessing the memory with priority over the transaction of the processor of the GPU or the at least one multimedia block by adjusting the QoS related value applied to the transaction of the processor to be higher than the QoS related value applied to the transaction of the processor of the GPU or the at least one multimedia block, or processing the transaction of the processor with priority over the transaction of the processor of the GPU or the at least one multimedia block in the at least one additional circuit.

15. In a storage medium storing at least one computer-readable command and data, the at least one command and data, when executed by a processor (120; 200; 211) including processing circuitry of an electronic device (101), causes the electronic device (101) to perform at least one operation, At least one of the above actions: An operation of detecting a first stall ratio for processor cycles of said processor; An operation for determining whether the first stall ratio exceeds a first threshold value; An operation of determining whether a processor stall of the processor satisfies a condition related to a memory access delay to a memory (130) based on determining that the first stall ratio exceeds the first threshold value; and The storage medium including an operation of adjusting a quality of service (QoS) related value applied to a transaction of the processor to be higher than a QoS related value applied to a transaction of at least one of a graphic processing unit (GPU) (213) or a multimedia block (215), based on determining that the processor stall is caused by the memory access delay.

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