Liquid crystal display substrate and manufacturing method therefor, and display apparatus

Abstract

A liquid crystal display substrate and a manufacturing method therefor, and a display apparatus. A liquid crystal display substrate (100, 100', 200, 200', 300, 300', 400, 400', 500, 500') comprises: a base substrate (10); a first semiconductor layer (21), which comprises an active layer of a first thin-film transistor (T1); a first gate layer (31), which comprises a gate electrode (G1) of the first thin-film transistor (T1); a first electrically conductive layer (40) connected to the active layer of the first thin-film transistor (T1) by means of a first via hole (VH1), so as to form a first electrode of the first thin-film transistor (T1); a second electrically conductive layer (50) connected to the active layer of the first thin-film transistor (T1) by means of a second via hole (VH2), so as to form a second electrode of the first thin-film transistor (T1); a planarization layer (60), part of which fills the second via hole (VH2); a third electrically conductive layer (70) electrically connected to the second electrically conductive layer (50) by means of a third via hole (VH3), pixel electrodes (P1) of pixel units (PX) being located on the third electrically conductive layer (70); a passivation layer (PVX); a fourth electrically conductive layer (80), a common electrode (P2) of a plurality of pixel units (PX) being located on the fourth electrically conductive layer (80); a liquid crystal layer (90); and a black matrix layer (BM), which comprises a black matrix area (BM1) and a black matrix opening area (BM2), wherein the second electrically conductive layer (50), the third electrically conductive layer (70) and the fourth electrically conductive layer (80) each comprise a transparent electrically conductive material, and the orthographic projection of the second via hole (VH2) on the base substrate (10) is located within the orthographic projection of the black matrix opening area (BM2) on the base substrate (10).

Description

Liquid crystal display substrate, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a liquid crystal display substrate, a manufacturing method thereof, and a display device. Background Art

[0002] With the diversification of VR (virtual reality) and AR (augmented reality) applications, demand for VR and AR products is growing rapidly. Display panels are one of the core hardware components of VR and AR products, requiring more pixel viewpoints to restore real scenes. The PPI (Pixels Per Inch) density requirements are increasing, generally requiring resolutions above 1500 PPI. The higher the PPI requirement for a display panel, the smaller the area occupied by a single pixel. As pixel size decreases, the aperture ratio drops dramatically, and display brightness decreases, severely reducing the application of display panels in VR and AR.

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art.

[0004] Summary of the Invention

[0005] In one aspect, a liquid crystal display substrate is provided, having a plurality of pixel units arranged in a display area of ​​the liquid crystal display substrate, the pixel units including a first thin film transistor, wherein the liquid crystal display substrate includes: a base substrate; a first semiconductor layer arranged on one side of the base substrate, the active layer of the first thin film transistor being located in the first semiconductor layer; a first gate layer arranged on a side of the first semiconductor layer away from the base substrate, the gate of the first thin film transistor being located in the first gate layer; a first conductive layer arranged on a side of the first gate layer away from the base substrate, the first conductive layer being electrically connected to the active layer of the first thin film transistor through a first via hole to constitute a first electrode of the first thin film transistor; a second conductive layer arranged on a side of the first conductive layer away from the base substrate, the second conductive layer being electrically connected to the active layer of the first thin film transistor through a second via hole to constitute a second electrode of the first thin film transistor; a planar layer arranged on a side of the second conductive layer away from the base substrate On one side of the base substrate, a portion of the flat layer fills the second via hole; a third conductive layer is arranged on a side of the flat layer away from the base substrate, the third conductive layer is electrically connected to the second conductive layer through a third via hole, and the pixel electrode of the pixel unit is located in the third conductive layer; a passivation layer is arranged on a side of the third conductive layer away from the base substrate; a fourth conductive layer is arranged on a side of the passivation layer away from the base substrate, and the common electrode of the multiple pixel units is located in the fourth conductive layer; a liquid crystal layer is arranged on a side of the fourth conductive layer away from the base substrate, and the liquid crystal layer is located in the display area; a black matrix layer is arranged on a side of the liquid crystal layer away from the base substrate and is located in the display area, and the black matrix layer includes a black matrix area and a black matrix opening area; wherein the second conductive layer, the third conductive layer and the fourth conductive layer include transparent conductive materials, and the orthographic projection of the second via hole on the base substrate is located within the orthographic projection of the black matrix opening area on the base substrate.

[0006] In some exemplary embodiments of the present disclosure, the second via includes a first end away from the base substrate and a second end close to the base substrate, and the via opening area of ​​the second via parallel to the upper surface of the base substrate gradually decreases from the first end toward the second end.

[0007] In some exemplary embodiments of the present disclosure, the sidewall profile line of the second via has a first angle of θ1 with the upper surface of the substrate, 45°<θ1<90°, and the sidewall profile line of the second via is obtained based on the intersection of the sidewall of the second via and the cross-section passing through the axis of symmetry of the second via.

[0008] In some exemplary embodiments of the present disclosure, a slope change rate of the sidewall profile line near the first end is greater than a slope change rate of the sidewall profile line near the second end.

[0009] In some exemplary embodiments of the present disclosure, a via width of the first end of the second via is a, a via width of the second end of the second via is b, and 2.5um≤a≤4.5um, 1.5um≤b≤3.5um.

[0010] In some exemplary embodiments of the present disclosure, the planar layer includes a first planar area and a second planar area, wherein an orthographic projection of the first planar area on the base substrate is located within an orthographic projection of the second via hole on the base substrate, and the second planar area is an area outside the first planar area;

[0011] The first flat region includes a first flat surface away from the second conductive layer, the second flat region includes a second flat surface away from the second conductive layer, and a step difference between the first flat surface and the second flat surface is less than 0.2 um.

[0012] In some exemplary embodiments of the present disclosure, in a direction perpendicular to the upper surface of the base substrate, a depth H1 of the second via hole and a thickness H2 of the planar layer satisfy the following linear relationship:

[0013] H1=A×H2+0.2, where 0.4≤A≤0.6.

[0014] In some exemplary embodiments of the present disclosure, the liquid crystal display substrate further includes: a supporting material layer, arranged between the passivation layer and the black matrix layer, for dividing the pixel unit into a plurality of sub-pixels, and the orthographic projection of the supporting material layer on the base substrate is located within the orthographic projection of the black matrix area on the base substrate.

[0015] In some exemplary embodiments of the present disclosure, the liquid crystal display substrate further includes: a light-shielding layer, arranged between the supporting material layer and the passivation layer, and the orthographic projection of the light-shielding layer on the base substrate is located within the orthographic projection of the black matrix area on the base substrate.

[0016] In some exemplary embodiments of the present disclosure, an orthographic projection of the third via hole on the base substrate is located within an orthographic projection of the black matrix opening region on the base substrate.

[0017] In some exemplary embodiments of the present disclosure, an orthographic projection of the third via hole on the base substrate is located within an orthographic projection of the black matrix region on the base substrate.

[0018] In some exemplary embodiments of the present disclosure, the flat layer includes a first flat sub-portion and a second flat sub-portion, a portion of the second conductive layer and a portion of the first flat sub-portion fill the second via, a portion of the third conductive layer and the second flat sub-portion fill the third via, and the orthographic projection of the second flat sub-portion on the base substrate is located within the orthographic projection of the third via on the base substrate.

[0019] In some exemplary embodiments of the present disclosure, the planarizing layer includes a first planarizing layer close to the second conductive layer and a second planarizing layer away from the second conductive layer; the second via penetrates the first planarizing layer and exposes the active layer of the first thin film transistor, and a portion of the second conductive layer and a portion of the planarizing layer fill the second via; the third via penetrates the second planarizing layer and exposes the second conductive layer, and a portion of the passivation layer and a portion of the supporting material layer fill the third via.

[0020] In some exemplary embodiments of the present disclosure, the liquid crystal display substrate further includes: an interlayer insulating layer, arranged between the first semiconductor layer and the flat layer; wherein the second via includes a first sub-via and a second sub-via; the second conductive layer includes a first conductive sublayer close to the base substrate and a second conductive sublayer away from the base substrate; the first sub-via penetrates the interlayer insulating layer and exposes the active layer of the first thin film transistor, and a portion of the first conductive sublayer and a portion of the first flat layer fill the first sub-via; the second sub-via penetrates the first flat layer and exposes the first conductive sublayer, and a portion of the second conductive sublayer and a portion of the second flat layer fill the second sub-via.

[0021] In some exemplary embodiments of the present disclosure, the supporting material layer includes a first supporting material layer close to the passivation layer and a second supporting material layer away from the passivation layer, the orthographic projection of the third via on the base substrate is located within the orthographic projection of the first supporting material layer on the base substrate, and a portion of the first supporting material layer fills the third via.

[0022] In some exemplary embodiments of the present disclosure, the liquid crystal display substrate further comprises: a color filter layer, which is located on the same layer as the planar layer, and the orthographic projection of the color filter layer on the base substrate is located within the orthographic projection of the black matrix opening area on the base substrate. In some exemplary embodiments of the present disclosure, the thickness of the color filter layer is H3, the thickness of the first planar layer is H 21 The thickness of the second flat layer is H 22 The following relationship is satisfied: 21 +H 22 >H3.

[0023] In some exemplary embodiments of the present disclosure, the liquid crystal display substrate further includes: a color filter layer, which is arranged on the same layer as the black matrix layer, and the orthographic projection of the color filter layer on the base substrate is located within the orthographic projection of the black matrix opening area on the base substrate.

[0024] In some exemplary embodiments of the present disclosure, the orthographic projection of the first thin film transistor on the base substrate overlaps with the orthographic projection of the black matrix opening area on the base substrate; the first gate layer includes a first gate sublayer and a second gate sublayer; and at least one of the first gate sublayer and the second gate sublayer includes a transparent conductive material.

[0025] In some exemplary embodiments of the present disclosure, the third via hole has the same shape as the second via hole, and the planar layer includes an organic light-transmitting material.

[0026] In some exemplary embodiments of the present disclosure, the multiple pixel units include a first group of pixel units and a second group of pixel units extending in a first direction, the first group of pixel units and the second group of pixel units are adjacent in a second direction, and the first direction is perpendicular to the second direction; the sub-pixels of the first group of pixel units and the sub-pixels of the second group of pixel units are staggered in the second direction; or, the sub-pixels of the first group of pixel units and the sub-pixels of the second group of pixel units are aligned in the second direction.

[0027] Another aspect of the present disclosure provides a method for manufacturing a liquid crystal display substrate, wherein the liquid crystal display substrate has a plurality of pixel units arranged in a display area, the pixel units including first thin film transistors, and the method for manufacturing the liquid crystal display substrate includes:

[0028] providing a substrate;

[0029] forming a first semiconductor layer on one side of the base substrate, wherein the active layer of the first thin film transistor is located in the first semiconductor layer;

[0030] forming a first gate layer on a side of the first semiconductor layer away from the base substrate, wherein the gate of the first thin film transistor is located on the first gate layer;

[0031] forming a first conductive layer on a side of the first gate layer away from the base substrate, wherein the first conductive layer is electrically connected to the active layer of the first thin film transistor through a first via hole to constitute a first electrode of the first thin film transistor;

[0032] forming a second via hole to expose the active layer of the first thin film transistor;

[0033] forming a second conductive layer on a side of the first conductive layer away from the base substrate, wherein the second conductive layer is electrically connected to the active layer of the first thin film transistor through a second via hole to constitute a second electrode of the first thin film transistor;

[0034] forming a flat layer on a side of the second conductive layer away from the base substrate, wherein a portion of the flat layer fills the second via hole;

[0035] forming a third conductive layer on a side of the planar layer away from the base substrate, the third conductive layer being electrically connected to the second conductive layer through a third via hole, and the pixel electrode of the pixel unit being located on the third conductive layer;

[0036] forming a passivation layer on a side of the third conductive layer away from the substrate;

[0037] forming a fourth conductive layer on a side of the passivation layer away from the base substrate, wherein the common electrodes of the plurality of pixel units are located on the fourth conductive layer;

[0038] forming a liquid crystal layer on a side of the fourth conductive layer away from the base substrate, wherein the liquid crystal layer is located in the display area;

[0039] forming a black matrix layer on a side of the liquid crystal layer away from the base substrate, wherein the black matrix layer is located in the display area and includes a black matrix area and a black matrix opening area;

[0040] The second conductive layer, the third conductive layer and the fourth conductive layer include transparent conductive materials, and the orthographic projection of the second via hole on the base substrate is located within the orthographic projection of the black matrix opening area on the base substrate.

[0041] In some exemplary embodiments of the present disclosure, forming a second via hole to expose the active layer of the first thin film transistor includes:

[0042] The insulating layer on the side of the first conductive layer away from the substrate is etched to form a second via hole to expose the active layer of the first thin film transistor.

[0043] The second via hole includes a first end away from the base substrate and a second end close to the base substrate, and an opening area of ​​the second via hole parallel to the upper surface of the base substrate gradually decreases from the first end toward the second end;

[0044] The sidewall profile line of the second via hole and the upper surface of the substrate have a first angle of θ1, 45°<θ1<90°,

[0045] A sidewall section line of the second via hole is obtained by intersecting a section of the sidewall of the second via hole with a symmetry axis passing through the second via hole;

[0046] The slope change rate of the side wall profile line close to the first end is greater than the slope change rate of the side wall profile line close to the second end;

[0047] The via hole width at the first end of the second via hole is a, the via hole width at the second end of the second via hole is b, 2.5um≤a≤4.5um, 1.5um≤b≤3.5um.

[0048] In some exemplary embodiments of the present disclosure, a flat layer is formed on a side of the second conductive layer away from the base substrate, including drying and curing the flat layer, and the drying and curing temperature rise rate is in the range of 5°C / min to 15°C / min.

[0049] Another aspect of the embodiments of the present disclosure provides a display device, which includes the liquid crystal display substrate described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0051] FIG1A is a schematic plan view of a liquid crystal display substrate according to an exemplary embodiment of the present disclosure;

[0052] FIG1B is a schematic planar structural diagram of a liquid crystal display substrate according to another exemplary embodiment of the present disclosure;

[0053] FIG2A is a schematic plan view of a sub-pixel of the liquid crystal display substrate according to an exemplary embodiment of FIG1A ;

[0054] FIG2B is a schematic planar structural diagram of a sub-pixel of the liquid crystal display substrate according to another exemplary embodiment of FIG1A ;

[0055] FIG2C is a schematic planar structural diagram of a sub-pixel arrangement of a liquid crystal display substrate according to an exemplary embodiment of FIG1B ;

[0056] 3A is a schematic cross-sectional structural diagram of a liquid crystal display substrate along line AA' according to the exemplary embodiment of FIG. 2C ;

[0057] 3B is a schematic diagram of a cross-sectional structure of a liquid crystal display substrate at a second via hole according to an exemplary embodiment of the present disclosure;

[0058] 3C is a schematic diagram of a cross-sectional structure of a planar layer of a liquid crystal display substrate at a second via hole according to an exemplary embodiment of the present disclosure;

[0059] FIG3D is a topographic diagram of a cross-sectional structure of a planar layer of a liquid crystal display substrate at a second via hole according to an exemplary embodiment of the present disclosure;

[0060] FIG3E is a topographic diagram of a cross-sectional structure of a liquid crystal display substrate at a third via hole according to an exemplary embodiment of the present disclosure;

[0061] FIG3F is a topographic diagram of a cross-sectional structure of a liquid crystal display substrate at a third via hole according to another exemplary embodiment of the present disclosure;

[0062] 3G is a schematic cross-sectional structural diagram of the liquid crystal display substrate along line BB' according to the exemplary embodiment of FIG. 2C ;

[0063] FIG4A is a schematic cross-sectional view of a liquid crystal display substrate 200 according to another exemplary embodiment of the present disclosure;

[0064] FIG4B is a schematic cross-sectional view of a liquid crystal display substrate 200 ′ including a light shielding layer according to another exemplary embodiment of the present disclosure;

[0065] FIG4C is a schematic cross-sectional view of a liquid crystal display substrate 300 according to another exemplary embodiment of the present disclosure;

[0066] FIG4D is a schematic cross-sectional view of a liquid crystal display substrate 300' including a light shielding layer according to another exemplary embodiment of the present disclosure;

[0067] FIG5A is a schematic cross-sectional view of a liquid crystal display substrate 400 according to another exemplary embodiment of the present disclosure;

[0068] FIG5B is a schematic cross-sectional structural diagram of a liquid crystal display substrate 400 ′ including a light shielding layer according to another exemplary embodiment of the present disclosure;

[0069] FIG5C is a schematic cross-sectional view of a liquid crystal display substrate 500 according to another exemplary embodiment of the present disclosure;

[0070] FIG5D is a schematic cross-sectional view of a liquid crystal display substrate 500' including a light shielding layer according to another exemplary embodiment of the present disclosure;

[0071] 6A is a cross-sectional structural morphology diagram of a liquid crystal display substrate at a second via hole according to an exemplary embodiment of the present disclosure;

[0072] FIG6B is a cross-sectional structural morphology diagram of a liquid crystal display substrate at a second via hole according to another exemplary embodiment of the present disclosure;

[0073] 6C is a cross-sectional structural morphology diagram of the first supporting material layer of the liquid crystal display substrate at the third via hole according to an exemplary embodiment of the present disclosure;

[0074] 7A to 7F are flowcharts of a manufacturing process of a second via hole of a liquid crystal display substrate according to an exemplary embodiment of the present disclosure;

[0075] 8A to 8B are flowcharts of a planarization process of a second via hole of a liquid crystal display substrate according to an exemplary embodiment of the present disclosure;

[0076] 9A to 9C are flowcharts of a planarization process of a third via hole of a liquid crystal display substrate according to an exemplary embodiment of the present disclosure;

[0077] FIG10A is a schematic structural diagram of a display device according to an exemplary embodiment of the present disclosure;

[0078] FIG. 10B is a schematic structural diagram of a display device according to another exemplary embodiment of the present disclosure.

[0079] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0080] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0081] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0082] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0083] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0084] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0085] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0086] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0087] In this document, the directional expressions "first direction" and "second direction" are used to describe different directions along a pixel region, such as the longitudinal and transverse directions of a pixel region, or the row and column directions of a sub-pixel arrangement. It should be understood that such expressions are merely exemplary descriptions and are not intended to limit the present disclosure.

[0088] In existing liquid crystal display devices, the existing liquid crystal display substrate includes pixel electrodes, common electrodes, wiring areas, and via areas. The wiring areas and via areas are shielded by the black matrix layer to prevent problems such as light leakage. As pixel density increases and pixel size decreases, the pixel aperture ratio drops sharply, resulting in reduced display brightness and hindering the design of high-density pixel display panels. The via area of ​​the existing liquid crystal display substrate is shielded by the black matrix. To increase the pixel aperture ratio of the liquid crystal display substrate, the solution is generally to reduce the wiring size. However, the wiring size is limited by the process. In addition, when the wiring size is reduced, the resistance increases, and the voltage drop at different locations on the display substrate is larger, which leads to problems such as reduced display uniformity on the display substrate.

[0089] In order to solve the problem of low aperture ratio and low display brightness at high pixel density in liquid crystal display substrates in the prior art, the present disclosure provides a liquid crystal display substrate having a plurality of pixel units arranged in a display area of ​​the liquid crystal display substrate, wherein the pixel units include a first thin film transistor, wherein the liquid crystal display substrate includes but is not limited to: a base substrate; a first semiconductor layer arranged on one side of the base substrate, wherein the active layer of the first thin film transistor is located in the first semiconductor layer; a first gate layer arranged on a side of the first semiconductor layer away from the base substrate, wherein the gate of the first thin film transistor is located in the first gate layer; a first conductive layer arranged on a side of the first gate layer away from the base substrate, wherein the first conductive layer is electrically connected to the active layer of the first thin film transistor through a first via hole to constitute a first electrode of the first thin film transistor; a second conductive layer arranged on a side of the first conductive layer away from the base substrate, wherein the second conductive layer is electrically connected to the active layer of the first thin film transistor through a second via hole to constitute a second electrode of the first thin film transistor; a flat layer, arranged on a side of the second conductive layer away from the base substrate, with a portion of the flat layer filling the second via hole; a third conductive layer, arranged on a side of the flat layer away from the base substrate, the third conductive layer being electrically connected to the second conductive layer through a third via hole, and the pixel electrode of the pixel unit being located in the third conductive layer; a passivation layer, arranged on a side of the third conductive layer away from the base substrate; a fourth conductive layer, arranged on a side of the passivation layer away from the base substrate, and the common electrode of the plurality of pixel units being located in the fourth conductive layer; a liquid crystal layer, arranged on a side of the fourth conductive layer away from the base substrate, and the liquid crystal layer being located in the display area; a black matrix layer, arranged on a side of the liquid crystal layer away from the base substrate, and being located in the display area, the black matrix layer including a black matrix area and a black matrix opening area; wherein the second conductive layer, the third conductive layer and the fourth conductive layer comprise transparent conductive materials, and the orthographic projection of the second via hole on the base substrate is located within the orthographic projection of the black matrix opening area on the base substrate.

[0090] According to the liquid crystal display substrate of the embodiment of the present disclosure, by setting the second conductive layer, the third conductive layer and the fourth conductive layer to transparent conductive materials, and setting the orthographic projection of the second via on the base substrate to be located within the orthographic projection of the black matrix opening area on the base substrate, the second via connecting the first thin film transistor and the pixel electrode is located in the display area, and the second via is not blocked by the black matrix. Under the second process with the same wiring size, the pixel aperture ratio of the liquid crystal display substrate can be effectively improved to meet the demand for high pixel density without reducing the display effect of the liquid crystal display substrate.

[0091] Figure 1A is a schematic plan view of a liquid crystal display substrate according to an exemplary embodiment of the present disclosure. Figure 1B is a schematic plan view of a liquid crystal display substrate according to another exemplary embodiment of the present disclosure.

[0092] As shown in FIG. 1A and FIG. 1B , the display substrate 100 and the display substrate 100 ′ include a display area AA and a non-display area NA.

[0093] The display area AA may be an area where pixel cells PX that display an image are located. Each pixel cell PX will be described later. The non-display area NA is an area where pixel cells PX are not located, that is, an area where no image is displayed. The non-display area NA corresponds to the bezel in the final display device, and the width of the bezel is determined based on the width of the non-display area NA.

[0094] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes, such as a closed polygon (e.g., a rectangle) with straight sides, a circle or an ellipse with curved sides, or a semicircle or a semiellipse with both straight and curved sides. In the embodiment of the present disclosure, the display area AA is provided as a quadrilateral with straight sides. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0095] The non-display area NA may be provided on at least one side of the display area AA. In an embodiment of the present disclosure, the non-display area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the non-display area NA may include a transverse portion extending in a first direction X and a longitudinal portion extending in a second direction Y.

[0096] The pixel unit PX is arranged in the display area AA. The pixel unit PX is the smallest unit for displaying an image and can be arranged in multiple forms. For example, the pixel unit PX may include a light-emitting device that emits white light and / or colored light. The pixel unit PX is arranged in an array in the display area, for example, arranged in sequence in the first direction X and the second direction Y. The pixel unit PX can be arranged in multiple forms, arranged in a matrix form along rows extending in the first direction X and columns extending in the first direction Y. However, the embodiments of the present disclosure do not specifically limit the arrangement form of the pixel unit PX, and the pixel unit PX can be arranged in various forms. For example, the pixel unit PX can be arranged so that the direction inclined relative to the first direction X and the first direction Y becomes the column direction, and the direction intersecting the column direction becomes the row direction.

[0097] That is, the plurality of pixel units PX are arranged in an array along the first direction X and the second direction Y to form a plurality of rows of pixel units and a plurality of columns of pixel units.

[0098] A pixel unit PX may include multiple sub-pixels. For example, a pixel unit PX may include four sub-pixels, namely a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4. For example, the sub-pixels may be arranged in different colors or the same color. For example, the first sub-pixel SP1 and the second sub-pixel SP2 may be sub-pixels of the same color, such as a blue sub-pixel, the third sub-pixel SP3 may be a red sub-pixel, and the fourth sub-pixel SP4 may be a green sub-pixel. In some embodiments of the present disclosure, the four sub-pixels may be arranged in a first direction X and a second direction Y, respectively, so that the multiple sub-pixels within a pixel unit PX are arranged in an array.

[0099] It should be noted that in the embodiments of the present disclosure, the number of sub-pixels included in a pixel unit is not particularly limited and is not limited to the four described above. For example, the number may be greater than four. In this embodiment, the pixel unit in FIG1 is merely exemplary. The sizes of the pixel units and sub-pixels in the drawings used to describe the embodiments of the present disclosure may be exaggerated or reduced, that is, these drawings are not drawn to scale.

[0100] For example, in the exemplary embodiment shown in FIG1 , signal lines 101 and data lines 102 are schematically illustrated. Specifically, the liquid crystal display substrate may further include: a plurality of signal lines 101 and a plurality of data lines 102 disposed on the base substrate 10 . The plurality of signal lines 101 respectively supply, for example, scan control signals to multiple rows of pixel units, and the plurality of data lines 102 respectively supply data signals to multiple columns of pixel units. The signal lines 101 extend along a first direction X, and the plurality of signal lines 101 are arranged at intervals in a second direction Y. The data lines 102 extend along the second direction Y, and the plurality of data lines 102 are arranged at intervals in the first direction X.

[0101] For example, the signal line 101 may be a representative of a horizontal line, and the data line 102 may be a representative of a vertical line. It should be understood that the horizontal line may also include lines of other types or lines for supplying other signals, and the vertical line may also include lines of other types or lines for supplying other signals.

[0102] Each sub-pixel may include a liquid crystal layer and a drive circuit for driving the liquid crystal deflection within the liquid crystal layer. The drive circuit includes one or more thin-film transistors, and by controlling the on or off of one or more thin-film transistors, the sub-pixels within the pixel unit of the liquid crystal display substrate are controlled. The sub-pixels are arranged in a matrix on the base substrate 10 along rows extending in a first direction X and columns extending in a second direction Y.

[0103] The plurality of pixel units include a first group of pixel units C1 and a second group of pixel units C2 extending in a first direction X. The first group of pixel units C1 and the second group of pixel units C2 are adjacent to each other in a second direction, and the first direction is perpendicular to the second direction.

[0104] For example, as shown in FIG1A , the first group of pixel units includes, for example, a plurality of pixel units in a first direction X, and the second group of pixel units includes, for example, a plurality of pixel units in the first direction X. The first group of pixel units C1 and the second group of pixel units C2 are respectively spaced apart in the second direction Y, i.e., the second group of pixel units C2 is disposed between adjacent first group of pixel units C1. As shown in FIG1A , the sub-pixels of the first group of pixel units C1 and the sub-pixels of the second group of pixel units C2 are aligned in the second direction, i.e., the sub-pixels of adjacent rows are aligned in the second direction Y.

[0105] For another example, as shown in FIG1B , the sub-pixels of the first group of pixel units C1′ and the sub-pixels of the second group of pixel units C2′ are staggered in the second direction, that is, the sub-pixels of adjacent rows are staggered in the second direction Y, thereby satisfying different pixel density settings. For example, by staggering the sub-pixels of adjacent rows in the second direction Y, the pixel density of the display substrate can be improved.

[0106] Figure 2A is a schematic plan view of a sub-pixel of a liquid crystal display substrate according to an exemplary embodiment of Figure 1A. Figure 2B is a schematic plan view of a sub-pixel of a liquid crystal display substrate according to another exemplary embodiment of Figure 1A. Figure 2C is a schematic plan view of the sub-pixel arrangement of the liquid crystal display substrate according to an exemplary embodiment of Figure 1B. Figure 3A is a schematic cross-sectional view of the liquid crystal display substrate along line AA' according to an exemplary embodiment of Figure 2C.

[0107] The structure of the liquid crystal display substrate of the exemplary embodiment of the present disclosure will be described in detail below with reference to FIG. 2A , FIG. 2B , FIG. 2C and FIG. 3A .

[0108] As shown in FIG1A , FIG2A and FIG2B , the sub-pixels of the first group of pixel units C1 and the sub-pixels of the second group of pixel units C2 in the liquid crystal display substrate 100 are aligned in the second direction Y, that is, the sub-pixels P are aligned in both the first direction X and the second direction Y.

[0109] As shown in FIG1B and FIG2C , the sub-pixels of the first group of pixel units C1 and the sub-pixels of the second group of pixel units C2 in the liquid crystal display substrate 100 ′ are staggered in the second direction Y. For example, the sub-pixels P in the next row are arranged between two adjacent sub-pixels P in the previous row. This allows full use of the staggered space between the pixels for circuit arrangement, thereby improving the density of the circuit arrangement and meeting the setting requirements of high pixel density.

[0110] As shown in Figures 1B to 3A , a liquid crystal display substrate 100' includes a plurality of pixel units disposed in a display area AA of the liquid crystal display substrate. As shown in Figures 2C and 3A , the liquid crystal display substrate 100' includes a first thin-film transistor T1 located in the display area AA and a second thin-film transistor T2 located in the non-display area NA. Each pixel unit includes the first thin-film transistor T1, which controls the deflection of the liquid crystal material in the liquid crystal layer above a sub-pixel P, thereby turning the sub-pixel on or off.

[0111] In the embodiment of the present disclosure, the number of the first thin film transistor T1 and the second thin film transistor T2 can be adjusted according to the actual design requirements of the liquid crystal display substrate, and the present disclosure does not specifically limit the number of the first thin film transistor T1 and the second thin film transistor T2.

[0112] As shown in FIG3A , a liquid crystal display substrate 100 ′ includes a base substrate 10; a buffer layer 11 is provided on one side of the base substrate 10; a first semiconductor layer 21 is provided on a side of the buffer layer 11 away from the base substrate 10, and the active layer of the first thin film transistor T1 is located on the first semiconductor layer 21; a first gate layer 31 is provided on a side of the first semiconductor layer 21 away from the base substrate 10, and the gate G1 of the first thin film transistor T1 is located on the first gate layer 31; a first conductive layer 40 is provided on a side of the first gate layer 31 away from the base substrate 10, and the first conductive layer 40 is electrically connected to the active layer of the first thin film transistor T1 through a first via hole VH1 to constitute a first electrode of the first thin film transistor; a second conductive layer 50 is provided on a side of the first conductive layer 40 away from the base substrate 10, and the second conductive layer 50 is electrically connected to the active layer of the first thin film transistor T1 through a second via hole VH2 to constitute a second electrode of the first thin film transistor T1; and a planar layer 60 is provided on the first conductive layer 40. On the side of the second conductive layer 50 away from the base substrate 10, a portion of the planar layer 60 fills the second via hole VH2; a third conductive layer 70 is arranged on the side of the planar layer 60 away from the base substrate 10, the third conductive layer 70 is electrically connected to the second conductive layer 50 through the third via hole VH3, and the pixel electrode P1 of the pixel unit is located on the third conductive layer; a passivation layer PVX is arranged on the side of the third conductive layer 70 away from the base substrate 10; a fourth conductive layer 80 is arranged on the side of the passivation layer PVX away from the base substrate 10, and the common electrode P2 of the multiple pixel units is located on the fourth conductive layer 80; a liquid crystal layer 90 is arranged on the side of the fourth conductive layer 80 away from the base substrate 10, and the liquid crystal layer 90 is located in the display area AA; a black matrix layer BM is arranged on the side of the liquid crystal layer 90 away from the base substrate 10, and the black matrix layer BM is located in the display area AA, and the black matrix layer BM includes a black matrix area BM1 and a black matrix opening area RM2.

[0113] In some embodiments of the present disclosure, as shown in FIG2C , the orthographic projection of the third via hole on the base substrate is located within the orthographic projection of the black matrix area BM1 on the base substrate. That is, the third via hole VH3 can overlap with the orthographic projection of the data line 102 on the base substrate, and will not block light within the sub-pixel. The third via hole VH3 overlaps with the orthographic projections of the first supporting material layer 301 and the second supporting material layer 302 in the supporting material layer 30 on the base substrate.

[0114] In some embodiments of the present disclosure, the second conductive layer 50, the third conductive layer 70, and the fourth conductive layer 80 comprise transparent conductive materials, and the planar layer 60 comprises an organic light-transmitting material. This allows light emitted by the light-emitting element to pass through the second conductive layer 50, the planar layer 60, the third conductive layer 70, and the fourth conductive layer 80 and then be emitted from the light-emitting side of the liquid crystal display substrate, thereby ensuring the brightness of the liquid crystal display substrate. In an embodiment of the present disclosure, the orthographic projection of the second via hole VH2 on the base substrate 10 is located within the orthographic projection of the black matrix opening BM2 area on the base substrate. A liquid crystal layer 90 is provided on the side of the black matrix opening BM2 near the base substrate. When the liquid crystal in the liquid crystal layer 90 is controlled by the first thin-film transistor, it is deflected, allowing light to be emitted from the black matrix opening BM2. By providing the second via hole VH2 and configuring the second conductive layer 50 to be a transparent conductive material, the outgoing light is prevented from being blocked, thereby effectively improving the sub-pixel aperture ratio and meeting the design requirements of a high-pixel density liquid crystal display substrate.

[0115] As shown in FIG3A , the liquid crystal display substrate 100 ′ further includes a second semiconductor layer 22 and a second gate layer 32. The second semiconductor layer 22 is disposed on a side of the buffer layer 11 away from the substrate 10, and the second gate layer 32 is disposed on a side of the second semiconductor layer 22 away from the substrate 10. Insulating layers are also disposed between the various film layers, such as a first gate insulating layer 12 disposed between the buffer layer 11 and the second semiconductor layer 22, a first interlayer insulating layer 13 disposed between the second gate layer 32 and the first semiconductor layer 21, a second gate insulating layer 14 disposed between the first semiconductor layer 21 and the first gate layer 31, a second interlayer insulating layer 15 disposed between the first gate layer 31 and the first conductive layer 40, and a third interlayer insulating layer 16 disposed between the first conductive layer 40 and the second conductive layer 50.

[0116] The active layer of the second thin film transistor T2 is located in the second semiconductor layer 22 , the gate G2 of the second thin film transistor T2 is located in the second gate layer 32 , and the second semiconductor layer 22 is connected to the first conductive layer 40 through a via hole to form the source or drain of the second thin film transistor T2 .

[0117] As shown in Figure 3A, the orthographic projection of the first thin-film transistor T1 on the substrate 10 overlaps with the orthographic projection of the black matrix opening area BM2 on the substrate. That is, a portion of the first thin-film transistor T1 extends into the sub-pixel, and the orthographic projection of the first thin-film transistor T1 on the substrate 10 overlaps with the orthographic projection of the black matrix area BM1 on the substrate. According to the embodiments of the present disclosure, by disposing a portion of the first thin-film transistor T1 within the sub-pixel, the pixel aperture ratio of the sub-pixel can be effectively increased, while saving space for the drive circuit and meeting the design requirements of high pixel density.

[0118] The first gate layer includes a first gate sublayer and a second gate sublayer, and at least one of the first gate sublayer and the second gate sublayer includes a transparent conductive material.

[0119] For example, the first gate layer 31 includes a first gate sublayer 311 close to the base substrate and a second gate sublayer 312 away from the base substrate. The first gate sublayer 311 and the second gate sublayer 312 are in contact to achieve electrical connection. The first gate sublayer 311 is configured as a transparent conductive material, and the second gate sublayer 312 is configured as a non-transparent conductive material. In this embodiment, since the orthographic projection of the first thin film transistor T1 on the base substrate 10 overlaps with the orthographic projection of the black matrix opening area BM2 on the base substrate, the first gate sublayer 311 is configured as a transparent conductive material (such as indium tin oxide) to avoid blocking light. Compared with traditional metal materials as gates, although light can be prevented from being blocked, the resistance of transparent conductive materials is relatively large. As the distance increases, the voltage drop is more obvious, resulting in poor display uniformity of the liquid crystal display substrate. To solve this problem, this embodiment sets the first gate layer to a multilayer structure including a first gate sublayer and a second gate sublayer, and at least one of the first gate sublayer and the second gate sublayer includes a transparent conductive material. This can reduce the blocking of light by the first thin film transistor T1 and improve the display uniformity of the liquid crystal display substrate.

[0120] As shown in Figure 3A, the second via hole VH2 sequentially penetrates the second gate insulating layer 14, the second interlayer insulating layer 15, and the third interlayer insulating layer 16, exposing the active layer of the first thin-film transistor T1. The second via hole VH2 includes a first end away from the substrate tomb plate and a second end closer to the substrate. The opening area of ​​the second via hole parallel to the upper surface of the substrate gradually decreases from the first end toward the second end.

[0121] As shown in Figures 2C and 3A, the first semiconductor layer 21 is arranged at an angle relative to the first direction X and the second direction Y. The first gate layer 31 extends along the first direction X. The first conductive layer 40 is arranged around the sub-pixel P. The orthographic projection of the first via hole VH1 on the substrate is located within the orthographic projection of the black matrix area BM1 on the substrate. The orthographic projections of the second via hole VH2 and the third via hole VH3 on the substrate are located within the orthographic projection of the black matrix opening area BM2 on the substrate. The planarization layer 60 is used to planarize the second via hole VH2 and the third via hole VH3. In this embodiment, according to the above arrangement, wiring space can be effectively utilized to meet the requirements of high pixel density.

[0122] FIG. 3B is a schematic diagram of a cross-sectional structure of a liquid crystal display substrate at a second via hole according to an exemplary embodiment of the present disclosure.

[0123] As shown in FIG3A and FIG3B , a sidewall profile line of the second via hole VH2 forms a first angle θ1 with the upper surface of the substrate, where 45°<θ1<90°. The sidewall profile line of the second via hole is obtained by intersecting the sidewall of the second via hole with a cross section passing through an axis of symmetry of the second via hole. For example, the axis of symmetry of the second via hole is n, and the second via hole is truncated cone-shaped, with the axis of symmetry of the truncated cone being n. The sidewall profile line of the second via hole is axially symmetric with respect to the axis of symmetry n.

[0124] For example, 50°≤θ1≤89°. For example, θ1≥52° can ensure a good light leakage prevention effect. For example, θ1≥85° has an excellent light leakage prevention effect.

[0125] In some embodiments of the present disclosure, a slope change rate of the sidewall profile line near the first end is greater than a slope change rate of the sidewall profile line near the second end.

[0126] Exemplarily, the profile of the sidewall profile is an arc, and when close to the second end, the angle between the sidewall profile and the upper surface of the substrate is greater than the angle between the sidewall profile and the upper surface of the substrate at the first end.

[0127] As shown in FIG3B , the via hole width at the first end of the second via hole is a, and the via hole width at the second end of the second via hole is b, wherein 2.5 um≤a≤4.5 um, and 1.5 um≤b≤3.5 um.

[0128] For example, a = 4.2um, b = 3um. a = 2.8um, b = 2.5um.

[0129] Figure 3C is a schematic diagram of a cross-sectional structure of a planar layer of a liquid crystal display substrate at a second via hole according to an exemplary embodiment of the present disclosure. Figure 3D is a topographic diagram of a cross-sectional structure of a planar layer of a liquid crystal display substrate at a second via hole according to an exemplary embodiment of the present disclosure.

[0130] As shown in Figures 3C and 3D, the flat layer 60 includes a first flat area 601 and a second flat area 602. The orthographic projection of the first flat area 601 on the base substrate is located within the orthographic projection of the second via VH2 on the base substrate 10, and the second flat area 602 is an area outside the first flat area, that is, the first flat area 601 corresponds to the second via VH2, and the second flat area 602 is other areas outside the first flat area 601 on the flat layer 60.

[0131] The first flat region 601 includes a first flat surface 601A away from the second conductive layer. The second flat region 602 includes a second flat surface 602A away from the second conductive layer. The step m between the first flat surface 601A and the second flat surface 602A is less than 0.2 um.

[0132] According to an embodiment of the present disclosure, by associating the step difference between the first flat surface 601A and the second flat surface 602A with the shape of the second via hole VH2, and by setting the second via hole VH2 to the above-mentioned morphology, the step difference between the first flat surface 601A and the second flat surface 602A can be achieved within a range of less than 0.2 um, so that the surface of the flat layer away from the base substrate has good flatness, and a third conductive layer 70 is provided in the black matrix opening area BM2 and on the flat layer 60, so as to ensure that the black matrix opening area is completely flat, thereby realizing a high-brightness liquid crystal display substrate and a high pixel density, while effectively reducing light leakage.

[0133] As shown in FIG3A , the orthographic projection of the third via hole VH3 on the base substrate 10 is located within the orthographic projection of the black matrix opening area BM2 on the base substrate 10. The third via hole VH3 penetrates the planar layer 60 and exposes the second conductive layer 50. A portion of the third conductive layer 70 is filled in the third via hole VH3.

[0134] The flat layer 60 includes a first flat sub-portion 60A and a second flat sub-portion 60B. That is, the flat layer 60 is provided as a single layer. A portion of the second conductive layer 50 and a portion of the first flat sub-portion 60A fill the second via hole VH2. A portion of the third conductive layer 70 and the second flat sub-portion 60B fill the third via hole VH3, and the orthographic projection of the second flat sub-portion 60B on the base substrate 10 is located within the orthographic projection of the third via hole VH3 on the base substrate 10.

[0135] Figure 3E is a topographic diagram of a cross-sectional structure of a liquid crystal display substrate at a third via hole according to an exemplary embodiment of the present disclosure. Figure 3F is a topographic diagram of a cross-sectional structure of a liquid crystal display substrate at a third via hole according to another exemplary embodiment of the present disclosure.

[0136] As shown in FIG. 3E and FIG. 3F , the third via hole VH3 has the same shape as the second via hole VH2 .

[0137] For example, the third via includes a first end distal from the substrate and a second end proximal to the substrate. The area of ​​the via opening of the third via, parallel to the upper surface of the substrate, gradually decreases from the first end toward the second end. A sidewall profile of the third via forms a second angle θ2 with the upper surface of the substrate, where 45° < θ2 < 90°. The sidewall profile of the third via is determined by the intersection of the sidewall of the third via with a cross-section passing through the axis of symmetry of the third via. The slope of the sidewall profile near the first end of the third via is greater than the slope of the sidewall profile near the second end of the third via. The via width of the third via at the first end is c, and the via width of the third via at the second end is d, where 2.5 μm ≤ c ≤ 4.5 μm and 1.5 μm ≤ d ≤ 3.5 μm. For example, as shown in FIG. 3F , the via width c at the first end of the third via is 4.2 μm, and the via width d at the second end of the third via is 3 μm.

[0138] In some embodiments of the present disclosure, as shown in FIG3C , in a direction perpendicular to the upper surface of the base substrate, the depth H1 of the second via hole VH2 and the thickness H2 of the planar layer satisfy the following linear relationship: H1=A×H2+0.2, where 0.4≤A≤0.6.

[0139] According to an embodiment of the present disclosure, by setting the depth of the second via hole VH2 and the thickness of the flat layer to the above-mentioned linear relationship, when the flat layer is used to flatten the second via hole VH2, the flat layer can be better filled into the second via hole VH2, so that the step difference between the first flat surface 601A and the second flat surface 602A is less than 0.2um, ensuring better flatness.

[0140] As shown in FIG. 3A , the liquid crystal display substrate 100 ′ further includes a support material layer 30 and a light shielding layer CM.

[0141] The supporting material layer 30 is arranged between the passivation layer PVX and the black matrix layer BM, and is used to separate the pixel unit into multiple sub-pixels. The orthographic projection of the supporting material layer 30 on the base substrate 10 is located within the orthographic projection of the black matrix area BM1 on the base substrate 10.

[0142] The light shielding layer CM is disposed between the support material layer 30 and the passivation layer PVX. The orthographic projection of the light shielding layer CM on the base substrate is located within the orthographic projection of the black matrix area BM1 on the base substrate.

[0143] 3A , the liquid crystal display substrate 100 ′ further includes a color filter layer 110. The color filter layer 110 is provided on the same layer as the black matrix layer BM, and the orthographic projection of the color filter layer 110 on the base substrate is located within the orthographic projection of the black matrix opening area BM2 on the base substrate.

[0144] As shown in FIG3A , the color filter layer 110 adopts non-COA (CF On Array) technology. By placing the color filter layer 110 on the same layer as the black matrix BM, the thickness of the planar layer 60 can be effectively reduced. While ensuring the high pixel density and display uniformity of the liquid crystal display substrate, the overall thickness of the liquid crystal display substrate can be reduced to achieve a thin design.

[0145] In other embodiments of the present disclosure, the color filter layer adopts COA technology, that is, the color filter layer and the flat layer are located on the same layer, and the orthographic projection of the color filter layer on the base substrate is located within the orthographic projection of the black matrix opening area on the base substrate.

[0146] FIG. 3G is a schematic cross-sectional structural diagram of the liquid crystal display substrate along line BB′ according to the exemplary embodiment of FIG. 2C .

[0147] As shown in Figure 3G, the liquid crystal display substrate 100' includes a base substrate 10, a buffer layer 11, a first gate insulating layer 12, a first interlayer insulating layer 13, a second gate insulating layer 14, a second interlayer insulating layer 15, a first conductive layer 40, a third interlayer insulating layer 16, a planarization layer 60, a third conductive layer 70, a fourth conductive layer 80, a liquid crystal layer 90 and a black matrix layer BM in a cross section along the BB' line. The black matrix layer BM includes a black matrix area BM1 and a black matrix opening area BM2. In this cross section, the orthographic projection of the first conductive layer 40 on the base substrate is located within the orthographic projection of the black matrix area BM1 on the base substrate.

[0148] 4A is a schematic cross-sectional view of a liquid crystal display substrate 200 according to another exemplary embodiment of the present disclosure. FIG4B is a schematic cross-sectional view of a liquid crystal display substrate 200 ′ including a light shielding layer according to another exemplary embodiment of the present disclosure.

[0149] As shown in Figures 4A and 4B , in the liquid crystal display substrates 200 and 200', the orthographic projection of the third via hole VH3 on the base substrate 10 is located within the orthographic projection of the black matrix area BM1 on the base substrate. The orthographic projection of the second via hole VH2 on the base substrate 10 is located within the orthographic projection of the black matrix opening area BM2 on the base substrate. The third via hole VH3 does not block light, thereby further improving the display light transmission efficiency and display brightness of the liquid crystal display substrate.

[0150] The planar layer 60 includes a first planar layer 61 close to the second conductive layer 50 and a second planar layer 62 far from the second conductive layer.

[0151] The second via hole VH2 penetrates the first planar layer 61 and exposes the active layer of the first thin-film transistor T1. A portion of the second conductive layer 50 and a portion of the planar layer fill the second via hole VH2. For example, the second via hole VH2 sequentially penetrates the first planar layer 61, the third interlayer insulating layer 16, the second interlayer insulating layer 15, and the second gate insulating layer 14, thereby exposing the first semiconductor layer 21. A portion of the second planar layer 62 and a portion of the second conductive layer 50 fill the second via hole VH2.

[0152] The third via hole VH3 penetrates the second planar layer 62 and exposes the second conductive layer 50 . A portion of the passivation layer PVX and a portion of the support material layer 30 fill the third via hole.

[0153] As shown in Figures 4A and 4B, the supporting material layer 30 includes a first supporting material layer 301 close to the passivation layer PVX and a second supporting material layer 302 away from the passivation layer PVX. The orthographic projection of the third via VH3 on the base substrate 10 is located within the orthographic projection of the first supporting material layer 301 on the base substrate 10, and a portion of the first supporting material layer 301 fills the third via VH3.

[0154] For example, the first supporting material layer 301 can be Pillow, and the thickness can be thinned using the HalfTone Mask process. The second supporting material layer can be PS, and the PS and Pillow are aligned to support each other, thereby achieving self-alignment of the PS and Pillow on both sides, avoiding light leakage, and improving brightness and contrast.

[0155] As shown in FIG4B , the liquid crystal display substrate 200 ′ further includes a light shielding layer CM disposed between the support material layer 30 and the passivation layer PVX, wherein the orthographic projection of the light shielding layer CM on the base substrate is within the orthographic projection of the black matrix area BM1 on the base substrate.

[0156] For example, the light-shielding layer CM is arranged between the first supporting material 301 and the passivation layer PVX, and a portion of the light-shielding layer CM fills the third via hole VH3 along with the passivation layer PVX. By setting the light-shielding layer CM, the alignment error between the black matrix layer and the lower film layer can be reduced, and light leakage can be effectively reduced, thereby improving the display brightness and contrast of the liquid crystal display substrate.

[0157] Figure 4C is a schematic cross-sectional view of a liquid crystal display substrate 300 according to another exemplary embodiment of the present disclosure. Figure 4D is a schematic cross-sectional view of a liquid crystal display substrate 300' including a light shielding layer according to another exemplary embodiment of the present disclosure.

[0158] As shown in FIG4C and FIG4D , the liquid crystal display substrate 300 and the liquid crystal display substrate 300 ′ include an interlayer insulating layer disposed between the first semiconductor layer and the planar layer, including a second gate insulating layer 14 , a second interlayer insulating layer 15 , and a third interlayer insulating layer 16 .

[0159] The second via hole includes a first sub-via hole VH21 and a second sub-via hole VH22. The second conductive layer includes a first conductive sub-layer 51 close to the base substrate and a second conductive sub-layer 52 far from the base substrate.

[0160] The first sub-via hole VH21 penetrates the second gate insulating layer 14 , the second interlayer insulating layer 15 and the third interlayer insulating layer 16 and exposes the active layer of the first thin film transistor. A portion of the first conductive sublayer 51 and a portion of the first planar layer 61 fill the first sub-via hole VH21 .

[0161] The second sub-via hole VH22 penetrates the first planar layer 61 and exposes the first conductive sub-layer 51 , and a portion of the second conductive sub-layer 52 and a portion of the second planar layer 62 fill the second sub-via hole VH22 .

[0162] As shown in FIG4D , the liquid crystal display substrate 300 ′ further includes a light shielding layer CM disposed between the support material layer 30 and the passivation layer PVX, wherein the orthographic projection of the light shielding layer CM on the base substrate is within the orthographic projection of the black matrix area BM1 on the base substrate.

[0163] For example, the light-shielding layer CM is arranged between the first supporting material 301 and the passivation layer PVX, and a portion of the light-shielding layer CM fills the third via hole VH3 along with the passivation layer PVX. By setting the light-shielding layer CM, the alignment error between the black matrix layer and the lower film layer can be reduced, and light leakage can be effectively reduced, thereby improving the display brightness and contrast of the liquid crystal display substrate.

[0164] In some embodiments of the present disclosure, when the planar layer includes a first planar layer and a second planar layer, the total thickness of the planar layer can increase the vertical distance between the conductive layers, thereby effectively reducing parasitic capacitance, reducing crosstalk and noise, and improving the display effect of the liquid crystal display substrate.

[0165] In the embodiments of the present disclosure, the liquid crystal display substrates 100, 100', 200, 200', 300, 300' all adopt non-COA technology, that is, the color filter layer 110 and the black matrix layer BM are arranged on the same layer, and the orthographic projection of the color filter layer 110 on the base substrate is located within the orthographic projection of the black matrix opening area BM2 on the base substrate.

[0166] Figure 5A is a schematic cross-sectional view of a liquid crystal display substrate 400 according to another exemplary embodiment of the present disclosure. Figure 5B is a schematic cross-sectional view of a liquid crystal display substrate 400' including a light shielding layer according to another exemplary embodiment of the present disclosure. Figure 5C is a schematic cross-sectional view of a liquid crystal display substrate 500 according to another exemplary embodiment of the present disclosure. Figure 5D is a schematic cross-sectional view of a liquid crystal display substrate 500' including a light shielding layer according to another exemplary embodiment of the present disclosure.

[0167] As shown in Figures 5A, 5B, 5C, and 5D, the color filter layer 110 of the liquid crystal display substrate is located on the same layer as the planar layer 60. The orthographic projection of the color filter layer 110 on the base substrate 10 is located within the orthographic projection of the black matrix opening area BM2 on the base substrate 10. That is, the liquid crystal display substrates of Figures 5A to 5D all use COA technology, which incorporates a CF (color filter) on the array substrate. Because this technology does not involve alignment operations, it can achieve high pixel density. At the same time, the color filter layer is planarized by the first and second planar layers, which ensures that the side of the planar layer away from the base substrate has a higher degree of flatness, thereby improving display uniformity.

[0168] 5A corresponds to FIG. 4A , FIG. 5B corresponds to FIG. 4B , FIG. 5C corresponds to FIG. 4C , and FIG. 5D corresponds to FIG. 4D . The difference between these embodiments is that the color filter layer 110 is disposed at a different position, thereby achieving better flatness and display uniformity.

[0169] As shown in FIG5C and FIG5D , the thickness of the color filter layer 110 of the liquid crystal display substrate 500 and 500 ′ is H3, and the thickness of the first flat layer is H. 21 The thickness of the second flat layer is H 22 Satisfies the following relationship: H 21 +H 22 > H3.

[0170] After forming the color filter layer 110 on the side of the first conductive sublayer 51 facing away from the base substrate 10, the first sub-via VH21 and the color filter layer 110 are first flattened using a first flattening layer 61. For example, the thickness of the first flattening layer 61 can be 1.0 μm. A second flattening layer 62 is then formed on the side of the first flattening layer 61 facing away from the base substrate, performing a second flattening of the second sub-via VH22 and the color filter layer 110. For example, the thickness of the second flattening layer 62 can be 3 μm. For example, the thickness of the color filter layer 110 can be 2.1 μm. As a result, the sum of the thicknesses of the first flattening layer 61 and the second flattening layer 62 is greater than the thickness of the color filter layer 110. This double flattening process achieves a superior flattening effect, improving the display uniformity of the liquid crystal display substrate. Furthermore, the first and second flattening layers increase the distance between the multiple conductive layers, effectively reducing parasitic capacitance, crosstalk, and noise, further enhancing the display quality.

[0171] Figure 6A is a cross-sectional structural topography of a liquid crystal display substrate at a second via hole according to an exemplary embodiment of the present disclosure. Figure 6B is a cross-sectional structural topography of a liquid crystal display substrate at a second via hole according to another exemplary embodiment of the present disclosure. Figure 6C is a cross-sectional structural topography of a first supporting material layer of a liquid crystal display substrate at a third via hole according to an exemplary embodiment of the present disclosure.

[0172] As shown in Figures 6A and 6B, the liquid crystal display substrate is planarized on the side of the second via away from the base substrate using a first planarization layer 61 and a second planarization layer 62, respectively, to achieve excellent planarization. For example, in Figure 6A, the thickness of the first planarization layer 61 in a direction perpendicular to the upper surface of the base substrate is 1.5 μm, and the thickness of the second planarization layer 62 in a direction perpendicular to the upper surface of the base substrate is 2.5 μm. After planarization, the step difference between the first flat surface of the first flat area corresponding to the second via VH2 and the second flat surface of the second flat area is 0.05 μm, achieving excellent planarization. As shown in Figure 6B, the step difference between the first flat surface of the first flat area corresponding to the second via VH2 and the second flat surface of the second flat area after planarization is 0.04 μm, also achieving excellent planarization. The liquid crystal display substrates shown in Figures 6A and 6B both utilize COA technology, that is, the color filter layer is planarized using the first and second planarization layers, thereby ensuring excellent planarization.

[0173] As shown in FIG. 6C , the liquid crystal display substrate may be manufactured at the third via hole by a halftone mask process to form a first supporting material layer 301 in the supporting material layer.

[0174] Another aspect of the present disclosure provides a method for manufacturing a liquid crystal display substrate, wherein the liquid crystal display substrate has a plurality of pixel units disposed in a display area, the pixel units including a first thin film transistor, and the method for manufacturing the liquid crystal display substrate includes operations S1 to S12:

[0175] In operation S1 , a base substrate is provided.

[0176] In operation S2 , a first semiconductor layer is formed on one side of the base substrate, and the active layer of the first thin film transistor is located in the first semiconductor layer.

[0177] In operation S3 , a first gate layer is formed on a side of the first semiconductor layer away from the base substrate, and the gate of the first thin film transistor is located on the first gate layer.

[0178] In operation S4 , a first conductive layer is formed on a side of the first gate layer away from the base substrate, and the first conductive layer is electrically connected to the active layer of the first thin film transistor through a first via hole to form a first electrode of the first thin film transistor.

[0179] In operation S5 , a second via hole is formed to expose the active layer of the first thin film transistor.

[0180] In operation S6 , a second conductive layer is formed on a side of the first conductive layer away from the base substrate, and the second conductive layer is electrically connected to the active layer of the first thin film transistor through a second via hole to form a second electrode of the first thin film transistor.

[0181] In operation S7 , a planar layer is formed on a side of the second conductive layer away from the base substrate, and a portion of the planar layer fills the second via hole.

[0182] In operation S8 , a third conductive layer is formed on a side of the planar layer away from the base substrate. The third conductive layer is electrically connected to the second conductive layer through a third via hole. The pixel electrode of the pixel unit is located on the third conductive layer.

[0183] In operation S9 , a passivation layer is formed on a side of the third conductive layer away from the base substrate.

[0184] In operation S10 , a fourth conductive layer is formed on a side of the passivation layer away from the base substrate, and the common electrodes of the plurality of pixel units are located on the fourth conductive layer.

[0185] In operation S11 , a liquid crystal layer is formed on a side of the fourth conductive layer away from the base substrate, and the liquid crystal layer is located in the display area.

[0186] In operation S12, a black matrix layer is formed on a side of the liquid crystal layer away from the base substrate, the black matrix layer is located in the display area, and the black matrix layer includes a black matrix area and a black matrix opening area; the second conductive layer, the third conductive layer and the fourth conductive layer include transparent conductive materials, and the orthographic projection of the second via on the base substrate is located within the orthographic projection of the black matrix opening area on the base substrate.

[0187] Exemplarily, forming the second via hole to expose the active layer of the first thin-film transistor includes etching the insulating layer on a side of the first conductive layer away from the base substrate to form the second via hole to expose the active layer of the first thin-film transistor. The second via hole includes a first end away from the base substrate and a second end closer to the base substrate, and an opening area of ​​the second via hole parallel to the upper surface of the base substrate gradually decreases from the first end toward the second end.

[0188] A sidewall profile line of the second via forms a first angle θ1 with the upper surface of the substrate, where 45°<θ1<90°. The sidewall profile line of the second via is obtained by intersecting a cross section of the second via sidewall with an axis of symmetry passing through the second via. A slope change rate of the sidewall profile line near the first end is greater than a slope change rate of the sidewall profile line near the second end.

[0189] The via hole width at the first end of the second via hole is a, the via hole width at the second end of the second via hole is b, 2.5um≤a≤4.5um, 1.5um≤b≤3.5um.

[0190] In some embodiments of the present disclosure, a flat layer is formed on the side of the second conductive layer away from the base substrate, including drying and curing the flat layer, and the heating rate of the drying and curing is in the range of 5°C / min to 15°C / min, thereby ensuring that the via hole passing through the flat layer meets the first angle range, thereby achieving the effect of avoiding light leakage.

[0191] In some embodiments of the present disclosure, a method for manufacturing a liquid crystal display substrate may include, for example, the following formation steps: first, providing a base substrate; forming a buffer layer on the base substrate; forming a second semiconductor layer 22 on the buffer layer; forming a second gate layer 32 on a side of the second semiconductor layer 22 away from the base substrate; forming a first semiconductor layer 21; and forming a first gate layer 31 on a side of the first semiconductor layer 21 away from the base substrate. Next, forming vias connecting the second semiconductor layer 22 and the first semiconductor layer 21; and forming a first conductive layer 40 in each of the vias. The method further includes forming a first gate insulating layer 12, a first interlayer insulating layer 13, a second gate insulating layer 14, and a second interlayer insulating layer 15. After forming the first conductive layer 40, forming a third interlayer insulating layer 16 on a side of the first conductive layer 40 away from the base substrate. Next, forming a first sub-via hole VH21 on a side of the third interlayer insulating layer 16 away from the base substrate. The first sub-via hole VH21 penetrates the second gate insulating layer 14, the second interlayer insulating layer 15, and the third interlayer insulating layer 16, exposing the first semiconductor layer 21. Next, a first conductive sub-layer 51 is formed in the first sub-via hole VH21 Next, the first sub-via hole VH21 is planarized by a first planarization layer 61 , and then a second sub-via hole is formed on the first planarization layer 61 .

[0192] 7A to 7F are flowcharts of a manufacturing process of a second via hole of a liquid crystal display substrate according to an exemplary embodiment of the present disclosure.

[0193] The process of forming the second sub-via hole in the second via hole VH2 includes the following steps:

[0194] As shown in FIG. 7A , the first planarization layer 61 fills the first sub-via hole VH21 in the second via hole.

[0195] As shown in FIG. 7B , a hard mask HM (Hard Mask) is formed on a side of the first planar layer 61 away from the base substrate, and can be formed by, for example, CVD (Chemical Vapor Deposition).

[0196] As shown in FIG. 7C , a photoresist PR is further formed on the side of the hard mask HM away from the substrate, and is exposed to light, thereby developing the area corresponding to the second sub-via hole VH22 .

[0197] As shown in FIG. 7D , the hard mask and the first planar layer 61 in the region corresponding to the second sub-via hole VH22 are etched to expose the first conductive sub-layer.

[0198] As shown in FIG. 7E , the photoresist PR on the side of the hard mask HM away from the substrate is removed.

[0199] As shown in FIG. 7F , the hard mask HM on the side of the first planar layer 61 away from the base substrate is further removed, thereby generating a second sub-via hole VH22 in the second via hole.

[0200] In some embodiments of the present disclosure, the first planarization layer 61 can be made of, for example, a photosensitive organic material with a light transmittance greater than 59%. The process of planarizing the first sub-via hole using the first planarization layer 61 includes drying and curing the first planarization layer at a heating rate within a range of 5°C / min to 15°C / min, thereby ensuring good planarity of the planarization layer.

[0201] 8A to 8B are flowcharts of a planarization process of a second via hole of a liquid crystal display substrate according to an exemplary embodiment of the present disclosure.

[0202] As shown in FIG. 8A , after the second sub-via hole VH22 is formed, a second conductive sub-layer 52 is formed in the second sub-via hole VH22 .

[0203] As shown in FIG. 8B , a second planarization layer 62 is further formed on the second conductive sub-layer 52 , thereby effectively planarizing the second sub-via in the second via.

[0204] In some embodiments of the present disclosure, the second flat layer is flattened, and the second flat layer is dried and solidified at a heating rate of 5°C / min to 15°C / min, thereby ensuring that the flat layer has good flatness.

[0205] 9A to 9C are flowcharts of a planarization process of a third via hole of a liquid crystal display substrate according to an exemplary embodiment of the present disclosure.

[0206] The process flow for planarizing the third via hole includes the following steps:

[0207] As shown in FIG9A , a third conductive layer 70 is formed on a side of the planar layer 60 away from the base substrate and within the third via hole VH3. A planar layer 60P is then formed on a side of the third conductive layer 70 away from the base substrate to fill the third via hole VH3. The material of the planar layer 60P can be the same as or similar to that of the planar layer 60.

[0208] As shown in FIG. 9B , the planar layer 60P is thinned by a photolithography thinning process, thereby reducing the residual thickness after planarization, and at the same time reducing the time of subsequent processes and improving the yield.

[0209] As shown in FIG9C , an ashing process is further used to remove the planar layer material outside the third via hole VH3 region, so that the step difference between the upper surface corresponding to the third via hole region and the upper surface of the third conductive layer 70 meets the planarization requirement.

[0210] In some exemplary embodiments of the present disclosure, the planar layer material in the third via hole VH3 region may be thinned, for example, by a half-tone process, to obtain a structure as shown in FIG. 6C .

[0211] Fig. 10A is a schematic structural diagram of a display device according to an exemplary embodiment of the present disclosure. Fig. 10B is a schematic structural diagram of a display device according to another exemplary embodiment of the present disclosure.

[0212] In some embodiments of the present disclosure, as shown in Figure 10A, the embodiments of the present disclosure also provide a display device 1000, which may include the above-mentioned liquid crystal display substrates (100, 100', 200, 200', 300, 300', 400, 400', 500, 500') and may also include other liquid crystal display substrates.

[0213] In other embodiments of the present disclosure, as shown in FIG10B , a display device 2000 is further provided. The display device 2000 may be a head-mounted display device, such as a VR device or an MR device. The display device 2000 includes a housing 2100, the liquid crystal display substrate 100 described above, and an optical assembly 2200. The optical assembly 2200 is configured to refract an image generated within the liquid crystal display substrate 100 so that a user can view information displayed on the liquid crystal display substrate 100.

[0214] The beneficial effects that can be achieved by the display device in the above embodiment of the present disclosure are the same as the beneficial effects that can be achieved by the above display substrate, and will not be described in detail here.

[0215] The display device can be any device that displays an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or graphic. More specifically, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like.

[0216] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0217] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A liquid crystal display substrate having a plurality of pixel units disposed in a display area of the liquid crystal display substrate, the pixel unit including a first thin film transistor, wherein, the liquid crystal display substrate includes: a substrate; a first semiconductor layer disposed on one side of the substrate, and an active layer of the first thin film transistor is located in the first semiconductor layer; a first gate layer disposed on a side of the first semiconductor layer away from the substrate, and a gate of the first thin film transistor is located in the first gate layer; a first conductive layer disposed on a side of the first gate layer away from the substrate, and the first conductive layer is electrically connected to the active layer of the first thin film transistor through a first via hole to form a first pole of the first thin film transistor; a second conductive layer disposed on a side of the first conductive layer away from the substrate, and the second conductive layer is electrically connected to the active layer of the first thin film transistor through a second via hole to form a second pole of the first thin film transistor; a planarization layer disposed on a side of the second conductive layer away from the substrate, and a part of the planarization layer fills the second via hole; a third conductive layer disposed on a side of the planarization layer away from the substrate, and the third conductive layer is electrically connected to the second conductive layer through a third via hole, and a pixel electrode of the pixel unit is located in the third conductive layer; a passivation layer disposed on a side of the third conductive layer away from the substrate; a fourth conductive layer disposed on a side of the passivation layer away from the substrate, and a common electrode of the plurality of pixel units is located in the fourth conductive layer; a liquid crystal layer disposed on a side of the fourth conductive layer away from the substrate, and the liquid crystal layer is located in the display area; a black matrix layer disposed on a side of the liquid crystal layer away from the substrate, located in the display area, and the black matrix layer includes a black matrix area and a black matrix opening area; wherein, the second conductive layer, the third conductive layer, and the fourth conductive layer include a transparent conductive material, and a positive projection of the second via hole on the substrate is located within a positive projection of the black matrix opening area on the substrate.

2. The liquid crystal display substrate according to claim 1, wherein, the second via hole includes a first end away from the substrate and a second end close to the substrate, and a via hole opening area of the second via hole parallel to the upper surface of the substrate gradually decreases from the first end to the second end.

3. The liquid crystal display substrate according to claim 2, wherein, The sidewall profile line of the second via hole has a first included angle θ with the upper surface of the substrate 1 , 45° < θ 1 < 90°, a side wall profile line of the second via hole is obtained by intersecting a side wall of the second via hole with a section passing through a symmetry axis of the second via hole.

4. The liquid crystal display substrate according to claim 3, wherein, a slope change rate of the side wall profile line near the first end is greater than a slope change rate of the side wall profile line near the second end.

5. The liquid crystal display substrate according to claim 4, wherein, a via hole width at the first end of the second via hole is a, and a via hole width at the second end of the second via hole is b, 2.5um ≤ a ≤ 4.5um, 1.5um ≤ b ≤ 3.5um.

6. The liquid crystal display substrate according to claim 5, wherein, the planarization layer includes a first planar region and a second planar region, a positive projection of the first planar region on the substrate substrate is located within a positive projection of the second via hole on the substrate substrate, and the second planar region is a region outside the first planar region; the first planar region includes a first planar surface away from the second conductive layer, the second planar region includes a second planar surface away from the second conductive layer, and a step difference between the first planar surface and the second planar surface is less than 0.2 um.

7. The liquid crystal display substrate according to any one of claims 1 to 6, wherein, In a direction perpendicular to the upper surface of the substrate, the depth H of the second via hole 1 and the thickness H of the planarization layer 2 satisfy the following linear relationship: H 1 = A × H 2 + 0.2, where 0.4 ≤ A ≤ 0.

6.

8. The liquid crystal display substrate according to claim 7, wherein, further comprising: a support material layer disposed between the passivation layer and the black matrix layer for separating the pixel unit into a plurality of sub-pixels, a positive projection of the support material layer on the substrate substrate is located within a positive projection of the black matrix region on the substrate substrate.

9. The liquid crystal display substrate according to claim 8, wherein, further comprising: a light-shielding layer disposed between the support material layer and the passivation layer, a positive projection of the light-shielding layer on the substrate substrate is located within a positive projection of the black matrix region on the substrate substrate.

10. The liquid crystal display substrate according to claim 9, wherein, a positive projection of the third via hole on the substrate substrate is located within a positive projection of the black matrix opening region on the substrate substrate.

11. The liquid crystal display substrate according to claim 9, wherein, a positive projection of the third via hole on the substrate substrate is located within a positive projection of the black matrix region on the substrate substrate.

12. The liquid crystal display substrate according to claim 10, wherein, the planarization layer includes a first planar sub-region and a second planar sub-region, a part of the second conductive layer and a part of the first planar sub-region fill the second via hole, a part of the third conductive layer and the second planar sub-region fill the third via hole, and a positive projection of the second planar sub-region on the substrate substrate is located within a positive projection of the third via hole on the substrate substrate.

13. The liquid crystal display substrate according to claim 11, wherein, the planarization layer includes a first planarization layer close to the second conductive layer and a second planarization layer away from the second conductive layer; the second via hole penetrates through the first planarization layer and exposes the active layer of the first thin film transistor, and a part of the second conductive layer and a part of the planarization layer fill the second via hole; the third via hole penetrates through the second planarization layer and exposes the second conductive layer, and a part of the passivation layer and a part of the support material layer fill the third via hole.

14. The liquid crystal display substrate according to claim 13, further comprising: an interlayer insulating layer disposed between the first semiconductor layer and the planarization layer; wherein, the second via hole includes a first sub-via hole and a second sub-via hole; the second conductive layer includes a first conductive sub-layer close to the substrate substrate and a second conductive sub-layer away from the substrate substrate; The first sub-via penetrates through the interlayer insulating layer and exposes the active layer of the first thin film transistor, and a part of the first electron conducting layer and a part of the first planar layer fill the first sub-via; The second sub-via penetrates through the first planar layer and exposes the first electron conducting layer, and a part of the second electron conducting layer and a part of the second planar layer fill the second sub-via.

15. The liquid crystal display substrate according to claim 13 or 14, wherein, the support material layer includes a first support material layer close to the passivation layer and a second support material layer far from the passivation layer, the orthographic projection of the third via on the substrate is located within the orthographic projection of the first support material layer on the substrate, and a part of the first support material layer fills the third via.

16. The liquid crystal display substrate according to claim 15, wherein, the liquid crystal display substrate further includes: a color filter layer, which is on the same layer as the planar layer, and the orthographic projection of the color filter layer on the substrate is located within the orthographic projection of the black matrix opening area on the substrate.

17. The liquid crystal display substrate according to claim 16, wherein, The thickness H of the color film layer 3 and the thickness of the first flat layer is H 21 and the thickness of the second flat layer is H 22 satisfy the following relationship: H 21 +H 22 >H 3 .

18. The liquid crystal display substrate according to claim 15, wherein, further includes: a color filter layer, which is on the same layer as the black matrix layer, and the orthographic projection of the color filter layer on the substrate is located within the orthographic projection of the black matrix opening area on the substrate.

19. The liquid crystal display substrate according to claim 7, wherein, the orthographic projection of the first thin film transistor on the substrate overlaps with the orthographic projection of the black matrix opening area on the substrate; the first gate layer includes a first gate sub-layer and a second gate sub-layer; at least one of the first gate sub-layer and the second gate sub-layer includes a transparent conductive material.

20. The liquid crystal display substrate according to claim 7, wherein, the third via has the same shape as the second via, and the planar layer includes an organic light-transmitting material.

21. The liquid crystal display substrate according to claim 1, wherein, the plurality of pixel units include a first group of pixel units and a second group of pixel units arranged in an extending manner in a first direction, the first group of pixel units and the second group of pixel units are adjacent in a second direction, and the first direction is perpendicular to the second direction; the sub-pixels of the first group of pixel units and the sub-pixels of the second group of pixel units are arranged in a staggered manner in the second direction; or, the sub-pixels of the first group of pixel units and the sub-pixels of the second group of pixel units are arranged in an aligned manner in the second direction.

22. A manufacturing method of a liquid crystal display substrate, wherein, the liquid crystal display substrate has a plurality of pixel units provided in a display area, the pixel units include a first thin film transistor, and the manufacturing method of the liquid crystal display substrate includes: providing a substrate; forming a first semiconductor layer on one side of the substrate, and the active layer of the first thin film transistor is located in the first semiconductor layer; forming a first gate layer on the side of the first semiconductor layer far from the substrate, and the gate of the first thin film transistor is located in the first gate layer; A first conductive layer is formed on a side of the first gate layer away from the substrate, and the first conductive layer is electrically connected to the active layer of the first thin film transistor through a first via hole to form a first pole of the first thin film transistor; A second via hole is formed to expose the active layer of the first thin film transistor; A second conductive layer is formed on a side of the first conductive layer away from the substrate, and the second conductive layer is electrically connected to the active layer of the first thin film transistor through a second via hole to form a second pole of the first thin film transistor; A planarization layer is formed on a side of the second conductive layer away from the substrate, and a part of the planarization layer fills the second via hole; A third conductive layer is formed on a side of the planarization layer away from the substrate, and the third conductive layer is electrically connected to the second conductive layer through a third via hole, and a pixel electrode of the pixel unit is located on the third conductive layer; A passivation layer is formed on a side of the third conductive layer away from the substrate; A fourth conductive layer is formed on a side of the passivation layer away from the substrate, and a common electrode of the plurality of pixel units is located on the fourth conductive layer; A liquid crystal layer is formed on a side of the fourth conductive layer away from the substrate, and the liquid crystal layer is located in the display area; A black matrix layer is formed on a side of the liquid crystal layer away from the substrate, the black matrix layer is located in the display area, and the black matrix layer includes a black matrix area and a black matrix opening area; Wherein, the second conductive layer, the third conductive layer, and the fourth conductive layer include a transparent conductive material, and a positive projection of the second via hole on the substrate is located within a positive projection of the black matrix opening area on the substrate.

23. The method according to claim 22, Wherein, The forming the second via hole to expose the active layer of the first thin film transistor includes: Etching an insulating layer on a side of the first conductive layer away from the substrate to form a second via hole to expose the active layer of the first thin film transistor, Wherein, the second via hole includes a first end away from the substrate and a second end close to the substrate, and an opening area of the second via hole parallel to the upper surface of the substrate gradually decreases from the first end towards The second end; The sidewall profile line of the second via hole has a first included angle θ with the upper surface of the substrate 1 , 45° < θ 1 < 90°, A sidewall profile line of the second via hole is obtained by intersecting a sidewall of the second via hole with a section passing through a symmetry axis of the second via hole; A slope change rate of the sidewall profile line near the first end is greater than a slope change rate of the sidewall profile line near the second end; A via hole width of the first end of the second via hole is a, and a via hole width of the second end of the second via hole is b, 2.5um ≤ a ≤ 4.5um, 1.5um ≤ b ≤ 3.5um.

24. The method according to claim 23, Wherein, Forming the planarization layer on a side of the second conductive layer away from the substrate includes drying and curing the planarization layer, and a heating rate of the drying and curing is in a range of 5°C / min to 15°C / min.

25. A display device, Wherein, It includes a liquid crystal display substrate according to any one of claims 1 to 21.

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