Qubit mapping method and apparatus, device, and storage medium

Abstract

A qubit mapping method and apparatus, a device, and a storage medium, relating to the technical field of quanta. The method comprises: acquiring a coupling graph corresponding to a quantum device, wherein each vertex in the coupling graph represents a qubit in the quantum device, and an edge between two vertices indicates that a two-qubit gate is allowed to directly act on qubits corresponding to the two vertices (110); generating at least two connected subgraphs on the basis of the coupling graph, wherein the number of vertices of each connected subgraph is greater than or equal to 2 and less than or equal to the number of routings of the coupling graph, and the sum of the number of vertices of the at least two connected subgraphs is equal to a constant multiple of the number of vertices of the coupling graph (120); and on the basis of the at least two connected subgraphs, performing qubit mapping on a logic circuit to obtain a hardware-compilable circuit equivalent to the logic circuit (130). The method solves the problem of excessive depth brought about by qubit permutation under the limitation of a coupling graph, thereby achieving the technical effect of effectively reducing the time complexity of qubit mapping.

Description

Quantum bit mapping method, device, equipment and storage medium

[0001] This application claims priority to Chinese patent application number 202311200317.5, filed on September 15, 2023, entitled “Quantum Bit Mapping Method, Apparatus, Device and Storage Medium,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of quantum technology, and in particular to a quantum bit mapping method, apparatus, device and storage medium. Background Art

[0003] Research on quantum bit mapping methods is crucial for implementing quantum algorithms and improving the performance of quantum computers. It is also one of the key issues in current quantum computing research.

[0004] When studying qubit mapping methods, an optimization-based approach involves reducing the qubit mapping problem to an equivalent mathematical optimization problem, which is then solved using existing optimization solvers. Specifically, a mathematical model must first be established to transform the various constraints and objective functions in the qubit mapping problem into constraints and objective functions in the optimization problem. When developing the model, it is important to ensure that the original problem and the transformed optimization problem are equivalent, ensuring that the solution to the optimization problem is also a feasible solution to the original mapping problem. Next, depending on the type of optimization problem, an existing solver algorithm and package is selected, such as a linear programming, quadratic programming, or semidefinite programming solver. The established mathematical model is input into the solver, and after iterative calculations, a solution that satisfies the constraints and optimizes the objective function is obtained. Finally, the optimized solution generated by the solver is mapped back into the solution space of the qubit mapping problem, resulting in a feasible solution to the original mapping problem.

[0005] In related technologies, using optimization-based methods for quantum bit mapping results in high time complexity.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a quantum bit mapping method, apparatus, device, and storage medium. The technical solutions provided by the embodiments of the present application are as follows:

[0008] According to one aspect of an embodiment of the present application, a quantum bit mapping method is provided, the method being executed by a computer device, the method comprising:

[0009] Obtaining a coupling graph corresponding to the quantum device, where each vertex in the coupling graph represents a quantum bit in the quantum device, and an edge between two vertices indicates that a two-qubit gate is allowed to directly act on the quantum bits corresponding to the two vertices;

[0010] Generating at least two connected subgraphs based on the coupling graph, wherein the number of vertices of each connected subgraph is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph, and the sum of the number of vertices of the at least two connected subgraphs is equal to a constant multiple of the number of vertices of the coupling graph; wherein the number of routes of the coupling graph is the maximum number of permutation rounds of all permutations on the coupling graph;

[0011] Based on the at least two connected subgraphs, quantum bit mapping is performed on the logic circuit to obtain a hardware compilable circuit equivalent to the logic circuit.

[0012] According to one aspect of an embodiment of the present application, a quantum bit mapping device is provided, the device comprising:

[0013] an acquisition module, configured to acquire a coupling graph corresponding to a quantum device, wherein each vertex in the coupling graph represents a quantum bit in the quantum device, and an edge between two vertices indicates that a two-qubit gate is allowed to directly act on the quantum bits corresponding to the two vertices;

[0014] a generating module, configured to generate at least two connected subgraphs based on the coupling graph, wherein the number of vertices of each connected subgraph is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph, and the sum of the number of vertices of the at least two connected subgraphs is equal to a constant multiple of the number of vertices of the coupling graph; wherein the number of routes of the coupling graph is the maximum number of permutation rounds of all permutations on the coupling graph;

[0015] A mapping module is used to perform quantum bit mapping on the logic circuit based on the at least two connected subgraphs to obtain a hardware compilable circuit equivalent to the logic circuit.

[0016] According to one aspect of an embodiment of the present application, a computer device is provided, comprising a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to implement the above-mentioned quantum bit mapping method.

[0017] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the above-mentioned quantum bit mapping method.

[0018] According to one aspect of an embodiment of the present application, a computer program product is provided, which includes a computer program, and the computer program is loaded and executed by a processor to implement the above-mentioned quantum bit mapping method.

[0019] The technical solutions provided by the embodiments of the present application have at least the following beneficial effects:

[0020] By dividing the coupling graph into at least two connected subgraphs, the quantum bit replacement originally performed under the restriction of the entire coupling graph is transformed into quantum bit replacement on multiple connected subgraphs, which solves the problem of excessive depth caused by quantum bit replacement under the restriction of the coupling graph, thereby controlling the circuit depth of the hardware-compilable circuit and achieving the technical effect of effectively reducing the time complexity of quantum bit mapping. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] FIG1 is a flowchart of a quantum bit mapping method provided by one embodiment of the present application;

[0023] FIG2 is a schematic diagram of two coupling diagrams corresponding to a superconducting quantum device provided in one embodiment of the present application;

[0024] FIG3 is a schematic diagram of calculating the number of common connectivity graph routes provided by one embodiment of the present application;

[0025] FIG4 is a schematic diagram of a pseudo code of a graph algorithm provided by an embodiment of the present application;

[0026] FIG5 is a schematic diagram of a graph algorithm example provided by one embodiment of the present application;

[0027] FIG6 is a schematic diagram of the number of quantum circuit layers provided by one embodiment of the present application;

[0028] FIG7 is a schematic diagram of a hardware compilable circuit structure provided by one embodiment of the present application;

[0029] FIG8 is a block diagram of a quantum bit mapping device provided by one embodiment of the present application;

[0030] FIG9 is a structural block diagram of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0032] Before introducing and explaining the technical solution of this application, some concepts involved in this application are first defined and explained.

[0033] 1. Quantum circuit: A quantum computing model consisting of a series of quantum gates and measurement sequences, with calculations performed by quantum gates.

[0034] 2. Qubit: The basic unit of quantum computing. Traditional computers use 0 and 1 as the basic units of binary. However, quantum computing can process both 0 and 1 simultaneously, allowing the system to be in a linear superposition of 0 and 1: |ψ>=α|0>+β|1>, where α and β represent the complex probability amplitude of the system at 0 and 1. Their squared modulus |α| 2 ,|β| 2 represent the probabilities of being 0 and 1 respectively.

[0035] 3. Coupling Graph: This graph, with qubits as vertices and the coupling relationships between qubits as edges, forms a graphical model for representing the coupling relationships between qubits. If an edge connects the vertices corresponding to two qubits in the coupling graph, this pair of qubits can directly perform a two-qubit gate operation. Indirectly connected qubit pairs require a swap gate to swap the states of the two qubits before performing a two-qubit gate operation.

[0036] 4. Quantum bit mapping: For any coupled graph G = (V, E), the vertex set V represents the set of qubits. A quantum circuit is hardware compilable if any two-qubit gate acting on qubits u, w ∈ V satisfies (u, w) ∈ E.

[0037] 5. Quantum bit mapping problem: Given an arbitrary coupling graph G and an arbitrary logic circuit C, a hardware-compilable circuit C′ equivalent to the above logic circuit C can be obtained simply by inserting swap gates.

[0038] 6. Routing on graphs: Given a coupled graph G = (V, E), with an element at each vertex, in the following example, the element is a stone. Routing on a graph is the following process: for any permutation π∈S V , then move the stone on each vertex v∈V to π(v). In the i-th round, there is a matching If (u,v)∈M i, then the two stones at vertices u and v are allowed to be exchanged. rt(G,π) represents the minimum number of rounds required to move all the stones from their initial position v to the target position π(v). The routing number of the graph G is defined as:

[0039] That is, the number of routes of a graph is equal to the maximum number of permutation rounds considering all permutations of the graph. The number of rounds is the number of permutation rounds required to move the stone at each vertex v∈V to π(v).

[0040] 7. Basic symbols: [n] represents the set of integers {1,2,…,n}. For sets V1 and V2, the set The symbol \ represents the difference set, and the set V1\V2 represents the set of vertices that belong to the set V1 but not to the set V2. For a graph G = (V, E), V and E represent the vertex set and edge set of the graph G respectively. For a graph G = (V, E) and the set Define edge sets Then the graph G′=(V′,E′) is called the subgraph of G generated by V′. For any set V of size n, S V Represents the set of all permutations defined on V. For a set S, |S| represents the size of the set.

[0041] 8. Worst depth overhead: Let G = (V, E) denote a coupled graph with n vertices, K n represents a complete graph containing n vertices, C n represents an n-qubit logic circuit, that is, a qubit logic circuit containing n vertices in the graph G. The worst excess depth on the coupled graph G is defined as:

[0042] Among them, d(C n ,G) represents C n The minimum depth of the hardware compilable circuit corresponding to the coupling graph G is d(C n ,K n ) represents the logic circuit C n circuit depth.

[0043] In the quantum bit mapping method provided in the embodiments of the present application, the execution subject of each step can be a computer device, which can be any electronic device with computing and storage capabilities, such as a PC (Personal Computer), a server, or other electronic device.

[0044] Please refer to Figure 1, which shows a flowchart of a quantum bit mapping method provided by one embodiment of the present application. The execution subject of each step of the method can be a computer device. The method can include at least one of the following steps 110 to 130.

[0045] Step 110: Obtain a coupling graph corresponding to the quantum device. Each vertex in the coupling graph represents a quantum bit in the quantum device. The edge between two vertices indicates that a two-qubit gate is allowed to directly act on the quantum bits corresponding to the two vertices.

[0046] Quantum devices are devices that exploit quantum physics effects to achieve functions such as accelerated computing, communication, and detection. Qubits are the fundamental unit of quantum devices. The coupling relationships between multiple qubits in a quantum device can be represented by a graph, called a coupling graph. In other words, a coupling graph abstractly depicts the physical interactions between qubits in a quantum device.

[0047] In some embodiments, the coupling graph of the present application is a connected graph. Because the connectivity of the coupling graph corresponding to a quantum device depends on the design goals and physical implementation of the quantum device, the coupling graph corresponding to the quantum device may be disconnected. This connectivity refers to whether there is a path connecting any two vertices. Since this application studies the problem of quantum bit mapping of arbitrary logic circuits, it includes the application of two-qubit gates on arbitrary quantum bit pairs. This requires that the coupling graph is at least connected. Therefore, in this application, the coupling graph is a connected graph by default.

[0048] In a coupling graph, vertices represent qubits in a quantum device, and edges represent two-qubit gates that can be performed on the two qubits connected by the edge. A two-qubit gate is a quantum gate that acts on two qubits, used to implement logical operations and interactions between the qubits. Examples of two-qubit gates include, but are not limited to, controlled NOT (CNOT), SWAP (swap gate), SQSWAP (square root of SWAP), CZ (controlled Z gate), CR (controlled rotation gate), and ISWAP (interaction SWAP).

[0049] In one possible implementation, the coupling diagram corresponding to any quantum device is obtained through a design drawing or document, or the coupling diagram corresponding to any quantum device is obtained by experimentally measuring the interaction relationship between different quantum bits, which is not limited in this application.

[0050] Please refer to Figure 2, which shows a schematic diagram of two coupling graphs corresponding to a superconducting quantum device provided in an embodiment of the present application, wherein subgraph (a) is a path graph and subgraph (b) is a brick wall graph. The vertices represent the quantum bits in the quantum device. If there is an edge connecting two vertices, it means that the two-qubit gate can directly act on the quantum bits corresponding to the two vertices. In a logic circuit, the two logic bits corresponding to any two-qubit gate may not have an edge between the coupling graphs, that is, they cannot be directly implemented on the quantum device. For example, please refer to subgraph (b) of Figure 2. If a two-qubit gate, such as CNOT, is to be implemented between two quantum bits 0 and 18, it cannot be directly implemented because the two quantum bits 0 and 18 are not directly connected. For example, please refer to subgraph (b) of Figure 2. If a two-qubit gate, such as CNOT, is to be implemented between two quantum bits 0 and 1, it cannot be directly implemented because the two quantum bits 0 and 1 are directly connected.

[0051] Step 120: Generate at least two connected subgraphs based on the coupling graph, where the number of vertices of each connected subgraph is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph, and the sum of the number of vertices of the at least two connected subgraphs is equal to a constant multiple of the number of vertices of the coupling graph; wherein the number of routes of the coupling graph is the maximum number of permutation rounds of all permutations on the coupling graph.

[0052] The permutation refers to the movement of an element on a vertex of the coupling graph from an initial vertex position to a target vertex position. There is an element on each vertex of the coupling graph, where the initial vertex position refers to the vertex position where the element is currently located, and the target vertex position refers to the vertex position where the element wants to reach. The initial vertex position and the target vertex position are not at the same vertex position, and this application does not limit the notation of the element. For example, permutation 1→2 refers to the exchange of positions of the element on vertex 1 with the element on vertex 2. For the element on vertex 1, its initial vertex position is the position of vertex 1, and the target vertex position is the position of vertex 2. A permutation may include the movement of some or all elements from the initial vertex position to the target vertex position, and this application does not limit this.

[0053] For a coupled graph G = (V, E), if a subgraph H of G satisfies: the node set of H is a subset of V, the edge set is a subset of E; H is connected, that is, any two vertices in H are always connected by a path. Then this subgraph H is called a connected subgraph of the graph G.

[0054] The number of routes in the coupling graph G is expressed as Here, rt(G,π) represents the number of routes that undergo a permutation π in graph G, and rt(G) represents the maximum number of routes among all permutations in graph G. For details, see the definition of route number above. A specific example is given below.

[0055] Please refer to Figure 3, which shows a schematic diagram of calculating the number of routes in a common connected graph provided by an embodiment of the present application. For example, as shown in subgraph (a), a permutation π1 is performed on a complete graph K4 with 4 vertices: 1→2, 2→3, 3→4, 4→1. The permutation steps are as follows: in the first round, 1, 2 and 3, 4 are swapped, and in the second round, 2, 4 are swapped. A total of two rounds are required, so rt(K4,π1)=2.

[0056] For example, as shown in subgraph (b), permutations π2 are performed on the path graph P4: 1→2, 2→3, 3→4, 4→1. The permutation steps are as follows: the first round swaps 1, 2, the second round swaps 1, 3, and the third round swaps 1, 4, requiring three rounds in total, so rt(P4,π2) = 3. For any rt(G,π), there is actually a permutation algorithm for π. For example, the permutation steps 1, 2 and 3, 4 for permutation π1 in the complete graph K4 are implemented by the permutation algorithm. More details about the permutation algorithm are described later.

[0057] In some embodiments, the number of routes in different connected graphs may be different. n , the number of routes is rt(K n )=2. For a path P of length n n , the number of routes is rt(P n )=O(n). Where O(n) describes rt(P n ) has an asymptotic upper bound, which means that there exists a positive number c such that all rt(P n )≤cn, the O symbol has a similar meaning below. For a two-dimensional grid of size n1×n2 The number of routes is For a tree T with n vertices n , whose routing number is rt(T n )=O(n).

[0058] In some embodiments, for a connected graph G = (V, E), the upper bound of its routing number is O(|V|). This is because the above description of the tree T with n vertices has been made. n , whose routing number is rt(T n ) = O(n). For any connected graph G, there is a corresponding spanning tree. Since the spanning tree contains all the vertices of graph G, rt(G) = O(|V|). This means that the number of routes in a connected graph is at most a constant multiple of its number of vertices.

[0059] In some embodiments, the lower bound of the number of routes of a graph is Ω(|V1| / |V2|), which means that there exists a positive number c such that all rt(G) ≥ c(|V1| / |V2|), which reflects the asymptotic relationship between rt(G) and the point set size ratio |V1| / |V2|. The lower bound of the number of routes is Ω(|V1| / |V2|). The proof process is as follows: For a connected graph G = (V, E), suppose there are two vertex sets satisfy: For any u∈V1, in That is, N(u) represents the set of vertices in the graph G that are directly connected to the vertices in the set V1. We mark the stones on the vertex set V1 as 1, 2, ..., |V1|. Definition And permutationπ:=(1,1+s)(2,2+s)...(s,2s). Implement permutationπ on graph G, that is, move stone i to the vertex where stone i+s is. Because for any u∈V1, Stone i must pass through the vertices in set V2 to reach the vertex where stone i+s is located. In one round, at most |V2| stones in V1 can pass through V2, so it takes at least wheel, of which It means that the ratio of s / |V2| is rounded up to an integer. So

[0060] In some embodiments, the number of vertices in each connected subgraph is restricted to 2 or greater and less than or equal to the number of routes in the coupled graph. This is to ensure that each connected subgraph has at least two qubits and that the mapping complexity of each connected subgraph is controlled. Furthermore, the number of vertices in all connected subgraphs covers a constant multiple of the set of vertices in the coupled graph. The constant here is a positive number that can be pre-set based on practical circumstances, for example, 2. This generates multiple connected subgraphs that meet certain scale constraints while also covering most or even all of the vertices in the coupled graph, providing favorable conditions for subsequent qubit mapping.

[0061] Step 130: Based on at least two connected subgraphs, perform quantum bit mapping on the logic circuit to obtain a hardware compilable circuit equivalent to the logic circuit.

[0062] The term "logic circuit" here refers to the quantum circuit corresponding to the quantum algorithm the user wishes to implement. Quantum algorithms implement their algorithmic tasks by designing quantum gates within the quantum circuit. When implemented on a quantum device, the quantum circuit corresponding to any logic circuit is constrained by the device's coupling graph. If a quantum circuit contains a two-qubit gate acting on two qubits, and these two qubits are not directly connected in the coupling graph, then the quantum circuit is not hardware-compilable.

[0063] However, in practice, the quantum circuit corresponding to the quantum algorithm a user wants to implement is often not a hardware-compilable circuit. To implement arbitrary logic circuits, we can insert commutation gates. These gates swap the quantum states of the two qubits they act on, thereby changing the order of interaction between the qubits and obtaining a hardware-compilable circuit equivalent to the logic circuit. Therefore, we study how to perform qubit mapping on arbitrary logic circuits by inserting commutation gates to obtain an equivalent hardware-compilable circuit. This is the so-called qubit mapping problem.

[0064] Refer to Figure 2. To implement a two-qubit gate between qubits 0 and 18, since the two-qubit gate cannot be directly applied to qubits 0 and 18, we introduce a swap gate, resulting in a hardware-compilable circuit equivalent to this logic circuit. In one possible implementation, the quantum states of qubits 0 and 14 are first swapped using a swap gate. Now that qubits 0 and 18 are adjacent, the desired two-qubit gate can be implemented between them. For example, to implement a CNOT, qubit 0 can be used as the control bit and qubit 18 as the target bit. In this case, the hardware-compilable circuit requires one swap gate and one CNOT, executed sequentially, resulting in a circuit depth of two.

[0065] In some embodiments, the equivalent hardware-compilable circuit for any logic circuit is not unique, and the corresponding circuit depths may vary. Referring to Figure 2, to implement a two-qubit gate between qubits 0 and 18, another possible implementation involves first swapping the quantum states of qubits 0 and 1 using a swap gate. Now, qubits 0 and 2 are adjacent. Then, the quantum states of qubits 0 and 2 are swapped, bringing qubits 0 and 3 adjacent. Then, the quantum states of qubits 0 and 3 are swapped, bringing qubits 0 and 4 adjacent. Continued swap gates are applied, successively swapping qubit 0 to the vertex corresponding to qubits 4, 15, 22, 21, 20, and 19. Now, qubits 0 and qubit 18 are adjacent. The desired two-qubit gate can then be implemented between them. For example, to implement a CNOT, qubit 0 can be used as the control bit and qubit 18 as the target bit. In this case, the hardware-compilable circuit uses nine swap gates and one CNOT, executed sequentially. This results in a circuit depth of 10.

[0066] When studying qubit mapping problems, circuit depth reflects the time complexity of quantum algorithms—that is, the number of quantum gate operations performed. Therefore, when designing hardware-compilable circuits equivalent to logic circuits, optimizing circuit depth can reduce the time complexity of quantum algorithms and improve the speed and efficiency of quantum computing.

[0067] In some embodiments, based on at least two connected subgraphs, if the quantum bit pairs acted upon by a two-qubit gate in a logic circuit are within the same connected subgraph, then permutations between quantum bits can be performed within the connected subgraph to complete the quantum bit mapping of the logic circuit. If the quantum bit pairs acted upon by a two-qubit gate in the logic circuit are not within the same connected subgraph, partial permutations within the connected subgraph can be used to help reduce the distance between the quantum bit pairs, and then global adjustments can be performed to complete the quantum bit mapping of the logic circuit, thereby obtaining a hardware-compilable circuit equivalent to the logic circuit.

[0068] In this process, the connected subgraph ensures that the distance between all the quantum bit pairs affected by the two-qubit gate will not be too far after a constant number of permutations. The circuit depth corresponding to each quantum bit pair permutation process is equal to the number of routes of the graph after a certain permutation.

[0069] The technical solution provided in the embodiments of the present application, by dividing the coupling graph into at least two connected subgraphs, converts the original quantum bit replacement under the restriction of the entire coupling graph into quantum bit replacement on multiple connected subgraphs, thereby solving the problem of excessive depth caused by quantum bit replacement under the restriction of the coupling graph, thereby controlling the circuit depth of the hardware compilable circuit and achieving the technical effect of effectively reducing the time complexity of quantum bit mapping.

[0070] The following describes a process of generating at least two connected subgraphs based on a coupling graph.

[0071] In some embodiments, a first vertex set family and a second vertex set family are generated based on the coupling graph, the first vertex set family includes at least one vertex set, the second vertex set family includes at least one vertex set, and each vertex set includes at least two vertices in the coupling graph; after obtaining the first vertex set family and the second vertex set family, a connected subgraph corresponding to each vertex set in the first vertex set family and the second vertex set family is generated to obtain at least two connected subgraphs.

[0072] Among them, the first vertex set family and the second vertex set family satisfy the following conditions: the subgraph corresponding to each vertex set in the first vertex set family and the second vertex set family is a connected graph; there are no identical vertices in any two vertex sets in the first vertex set family, and there are no identical vertices in any two vertex sets in the second vertex set family; the number of vertices contained in each vertex set in the first vertex set family and the second vertex set family is greater than or equal to 2 and less than or equal to the number of routes in the coupled graph; the total number of vertices in the first vertex set family and the second vertex set family is equal to a constant multiple of the number of vertices in the coupled graph.

[0073] A cluster is a set whose elements are part of the vertex set of the coupled graph. We restrict the cluster to a set of vertices. Since a two-qubit gate describes the interaction or correlation between two qubits, if the subgraph is not connected, then the two-qubit gate defined between them is meaningless. Therefore, the subgraph corresponding to each vertex set is a connected graph. To enable parallel mapping of subgraphs without mapping conflicts and improve concurrency, no two vertex sets in each cluster have the same vertex.

[0074] The above method first generates a set of subgraph vertices that meet certain restrictions, and then constructs the corresponding connected subgraph, providing a basis for the subsequent quantum bit mapping of the logic circuit.

[0075] In some embodiments, the steps of generating a first vertex cluster and a second vertex cluster according to a coupling graph are as follows: first, construct a maximum matching of the coupling graph, where the maximum matching includes at least one edge in the coupling graph; then, based on the maximum matching, generate a first vertex cluster, where each vertex set in the first vertex cluster corresponds to two vertices connected by an edge included in the maximum matching; the first vertex cluster is denoted as Let the vertex set be W i , where i is an integer not greater than the maximum number of matching edges; then, based on the first vertex set, a second vertex set is generated.

[0076] A graph matching is a subset of edges in a graph where no two edges share a common vertex. A maximum matching of a graph is a matching that contains the largest number of edges. Algorithms for constructing maximum matchings of graphs include, but are not limited to, the Hungarian algorithm, the Kuhn-Munkres (Hungarian matrix matching) algorithm, the Edmonds algorithm, and the Stream algorithm. In one possible implementation, the Hungarian algorithm is used to solve the maximum matching problem for a qubit coupling graph. First, qubits are represented as vertices in the graph, and the two-qubit gate operations between them are represented as edges. A quantum coupling graph G = (V, E) is constructed, assuming the number of vertices is n. An n×n distance weight matrix is ​​then initialized with all zeros. Next, an unmatched node is found in the residual graph. A breadth-first search is performed from this node to obtain the shortest path length from it to each unmatched node, and the values ​​in the weight matrix are updated accordingly. Next, the element with the smallest weight in the weight matrix is ​​found, representing the shortest augmenting path, and the matching relationship is updated based on this element. After matching, the residual graph needs to be updated. This process is repeated, each time finding the minimum weight augmenting path and expanding the matching until all nodes are matched. The final matching result is the maximum matching.

[0077] After obtaining the maximum matching of the graph, the pair of qubits connected by each matching edge is added as a vertex set to the first vertex set. Then, other vertices in the coupling graph that are directly connected to the vertices included in the first vertex set and do not belong to the first vertex set are added to the second vertex set.

[0078] By constructing the maximum matching of the coupling graph and generating the first vertex set family based on the maximum matching, each vertex set includes at least two vertices in the coupling graph, thereby generating a connected subgraph corresponding to each vertex set, providing a basis for the subsequent quantum bit mapping of the logic circuit.

[0079] In some embodiments, according to the first vertex cluster Generate the second vertex cluster The steps are as follows:

[0080] According to the first vertex set, determine the initialized set T p, the initialized set T p The vertices that belong to the coupled graph and do not belong to the first vertex cluster are included in , and p is a positive integer with an initial value of 1;

[0081] According to the initialized set T p , determine the initialized set S p , the initialized set S p The first vertex set and the initialized set T are included p The vertices in the connected vertices;

[0082] Determine the initialized collection is an empty set, and determines the initialized set A 0,p is an empty set, i is a positive integer with an initial value of 1;

[0083] The set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p In which, \ represents the difference of two sets, and the adjacent vertices of the i-th vertex refer to the vertices connected to the i-th vertex;

[0084] will be collected With set A i,p The union of is determined as the set

[0085] If i is less than k1, let i=i+1 and again select the set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p The steps in are executed; where k1 is the number of vertices in set S1;

[0086] If i is equal to k1, then Greater than or equal to |T p | / 2, a second vertex set is generated; wherein the vertex set included in the second vertex set is a set and set S p The union of the i-th vertex in , represent The number of vertices in |T p | represents the set T p The number of vertices in ;

[0087] will be collected Determine the set T p+1 ;

[0088] Based on the set T p and k p Determine the set S p+1 ;

[0089] |S p+1 |Determined to be k p+1 ; Among them, |S p+1 | represents the set S p+1 The number of vertices in ;

[0090] If p is less than |T1|, then set p=p+1 and again set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p The steps in the start execution;

[0091] If p is equal to |T1|, the process ends and the final generated second vertex cluster is obtained.

[0092] In the description of the above steps, the symbols used are only used to illustrate the ideas and processes of the algorithm. The specific symbol marking method is not limited in the embodiments of this application.

[0093] In some embodiments, in order to ensure that the number of vertices contained in each vertex set in the generated second vertex set family is greater than or equal to 2 and does not exceed the number of routes in the coupling graph, the set S is implemented. p The i-th vertex in the set The adjacent vertices in are put into set A i,p In the case of set S p The i-th vertex in the set At most adjacent vertices, then select the i-th vertex in the set All adjacent vertices in are put into set A i,p In; if the set S p The i-th vertex in the set More than adjacent vertices, then select the i-th vertex in the set Most hits adjacent vertices into set A i,p Among them, Represents the pair |T p | / k p Round up.

[0094] In a possible implementation, the present application designs a graph algorithm according to the above steps, and the following describes the generated first vertex set: and the second vertex cluster Please refer to FIG4 , which shows a schematic diagram of a pseudo code of a graph algorithm provided by an embodiment of the present application.

[0095] For any input graph G = (V, E), there exist integers s and t, and the algorithm outputs two vertex sets and The following conditions are met:

[0096] Condition 1: For any i∈[s] and j∈[t], W i and W′ j The resulting subgraph is a connected graph.

[0097] Condition 2: For any i1≠i2∈[s] and j1≠j2∈[t], and

[0098] Condition 3: For any i∈[s] and j∈[t], 2≤|W i |=O(rt(G)) and 2≤|W′ j |=O(rt(G)). To ensure that the number of vertices in the connected subgraph is greater than or equal to 2 and does not exceed O(rt(G)).

[0099] Condition 4: |∪ i∈[s] W i |+|∪ j∈[t] W′ j |=Ω(|V|), in order to ensure that all vertices of the subgraph can cover a constant multiple of the vertex set of the coupled graph.

[0100] Conditions 1 to 4 correspond to the conditions satisfied by the first vertex cluster and the second vertex cluster respectively.

[0101] Please refer to Figure 5, which shows a schematic diagram of a graph algorithm example provided by an embodiment of the present application. For example, the running process of the graph algorithm pseudocode shown in Figure 4 is specifically described below with reference to the example.

[0102] Step 1: Select the maximum matching (double solid line) in the graph, and its corresponding white vertex set can be used to construct a set family

[0103] Step 2: Select the black vertices (vertices other than the white vertices in step 1) as the set T1: = {7, 8, 9, 10, 11, 12}, and select the vertices adjacent to the vertices in T1 (white vertices) as S1: = {1, 2, 3, 4, 5, 6}.

[0104] Step 3: Since (where k1 = |S1|), for vertex 1, select one of its neighbors {7} in T1; for vertex 2, select one of its neighbors {8} in T1\{7}:={8,9,10,11,12}; since vertices 3, 4, 5, and 6 have no neighbors in T1\{7,8}:={9,10,11,12}, they are not selected. Then for the vertices in S1, their corresponding sets are defined as:

[0105] because So onto the next step.

[0106] Step 4: Since (where k1 = |S1|), then select S2 = {1,2} and T2: = T1\{7,8} = {9,10,11,12}.

[0107] Step 5: Since (where k2 = |S2|). For vertex 1, select one of its neighbors {9,10} in T2. ​​Since vertices 2, 3, 4, 5, and 6 have no neighbors in T2\{9,10}:={11,12}, they are not selected. Then, for the vertices in S1, their corresponding set is defined as:

[0108] because The algorithm output is:

[0109] The final connected subgraph includes and The connected subgraph formed by the set of vertices contained in it.

[0110] In some embodiments, the present application proves the correctness of the graph algorithm shown in FIG4 as follows:

[0111] Condition 1: Group clan The set W in i ={w 2i-1 ,w 2i}Satisfy(w 2i-1 ,w 2i )∈M, where M is the maximum matching of the graph; The collection in middle Each vertex and w j Adjacent. Therefore W i and W′ j The resulting subgraph is a connected graph.

[0112] Condition 2: By the group and From the construction, we can see that for any i1≠i2∈[s] and j1≠j2∈[t], and

[0113] Condition 3: (1) Group clan The number of routes of the graph algorithm shown in Figure 4, line 2, and the complete graph described above is 2, and the set family Each element W in i Satisfy 2=|W i |=rt(K n )≤rt(G). (2) Set family In line 13 of the graph algorithm shown in Figure 4, the set Each element W′ in j Satisfy |W j ′|≥2. Assume that the algorithm stops at step l of the outer loop. We will set S l Rewrite For any Due to the definition of line 17 of the graph algorithm shown in Figure 4, and Therefore, we can know that:

[0114] Define S l The union of the sets corresponding to the vertices in is This can be obtained from the above equation:

[0115] Since the graph algorithm has not stopped at step l-1,

[0116] Therefore, we get |T l |≥|T1| / 2>|C|. By T l and S l From the structure of , we can see that And for all u∈T l All neighbors of u are included in S l In, that is From the above description, we can know that rt(G)=Ω(|T l | / k l ). In summary, rt(G) satisfies:

[0117] Therefore, for Any set in The size of its set satisfies:

[0118] so The size of any set in is O(rt(G)).

[0119] Condition 4: Assume that the algorithm ends at step 1 of the outer loop. From the graph algorithm shown in Figure 4, lines 3 and 12, we can see that the set family The elements satisfy |∪ i∈[s] W i |=|V|-|T1| and the set The elements satisfy Therefore, we can get |∪ i∈[s] W i |+|∪ j∈[t] W′ j |=Ω(|V|).

[0120] The above method designs a graph algorithm that can output a set of vertices that meet specific conditions for any coupled graph, thereby constructing a connected subgraph. Verification of the algorithm demonstrates that it works as expected. This ensures that the designed qubit mapping method can be practically implemented and that the corresponding graph algorithm can correctly and efficiently generate the required connected subgraph. Furthermore, verification of the graph algorithm confirms the feasibility of the theoretical implementation and algorithmic feasibility of this application.

[0121] The technical solution provided in the embodiments of this application utilizes maximum matching of a coupling graph to construct a first vertex cluster containing the quantum bit pairs corresponding to the maximum matching. Based on this first vertex cluster, neighbors are found to form a second vertex cluster. The generation of these two clusters takes into account conditions such as set size limits and connectivity requirements. By constructing these convenient vertex clusters, this solution provides a simple and efficient preprocessing method for converting arbitrary logic circuits into equivalent hardware-compilable circuits.

[0122] The following describes the process of performing quantum bit mapping on a logic circuit based on at least two connected subgraphs to obtain a hardware-compilable circuit equivalent to the logic circuit.

[0123] In some embodiments, a first number of logic bit pairs in a logic circuit are permuted based on at least two connected subgraphs; wherein the first number is the number of edges included in the maximum matching of the coupling graph, and each logic bit pair corresponds to two quantum bits acted on by a two-qubit gate in the logic circuit; a first portion of hardware compilable circuits corresponding to the first number of logic bit pairs is generated; according to at least two connected subgraphs, the remaining logic bit pairs in the logic circuit are permuted; a second portion of hardware compilable circuits corresponding to the remaining logic bit pairs are generated; and according to the first portion of the hardware compilable circuits and the second portion of the hardware compilable circuits, a hardware compilable circuit equivalent to the logic circuit is obtained.

[0124] Permutation here refers to graph permutation: for a graph G = (V, E), the graph structure is reconstructed by changing the positions of nodes in V. Common algorithms for implementing graph permutations include matching-based permutation algorithms, such as the swap algorithm and the permutation tree algorithm, sorting-based permutation algorithms, such as bubble sort, insertion sort, and merge sort, and search-based permutation algorithms, such as DFS (Depth First Search) and BFS (Breadth First Search).

[0125] In one possible implementation, a permutation algorithm is used to permute the coupled qubit graph. The process is as follows: Analyze the internal structure of each connected subgraph to determine the qubits that need to be permuted within the connected subgraph. Within each subgraph, a permutation algorithm is used to perform a local permutation of the qubits. Specifically, an augmenting path is found within the subgraph's matching and a permutation operation is performed. The permutation operation is repeated until the permutation within each subgraph is complete. Based on the requirements of the global permutation, the connectivity between connected subgraphs is adjusted, and the local permutations of the connected subgraphs are combined into a global permutation. The global permutation result is checked and any necessary corrections or adjustments are made. Repeat these steps, gradually improving the permutation accuracy until it meets the requirements of the logic circuit. Finally, a global permutation of the entire coupled graph is achieved. Finally, the permutation results are verified and the new graph structure is saved.

[0126] The number of base quantum gate layers in a quantum circuit corresponds to the parallel running time of a quantum algorithm. The number of base quantum gate layers in a quantum circuit refers to the number of layers into which the quantum circuit is decomposed and contains only basic quantum gates (basic quantum gates are the basic operating units of quantum computing, such as CNOT gates, Hadamard gates, etc.). Each layer contains only basic gates that can be run in parallel. There is no dependency within the same layer, but there is dependency across layers, which determines the parallel execution capability of the quantum circuit and the time complexity of the quantum algorithm. In other words, if a quantum circuit consists of L layers of base quantum gates, the time complexity of this quantum algorithm running in parallel on a quantum computer is O(L). For example, please refer to Figure 6, which shows a schematic diagram of the number of quantum circuit layers provided by an embodiment of the present application. The figure represents a four-layer quantum circuit diagram, so the time complexity of the quantum algorithm running on a quantum computer is O(4).

[0127] The maximum matching number reflects the upper limit of the number of quantum gates that can be implemented in parallel in a quantum circuit. That is, if the size of the maximum matching of a graph G is m, then in the quantum circuit, at most m two-qubit gates can be implemented in one layer. In one possible implementation, m two-qubit gates can be implemented by permuting π1. Suppose we want to implement a logical quantum circuit with a depth of 1 and a layer with Since m two-qubit gates have been realized by replacing π1, the remaining The two-qubit gates are then permuted based on the connected subgraph obtained above.

[0128] For example, please refer to FIG7 , which shows a schematic diagram of a hardware compilable circuit structure provided by an embodiment of the present application. First, two clusters of connected graphs G are constructed by a graph algorithm. and The construction process follows the flow of the graph algorithm described above and will not be elaborated on here. A hardware-compilable circuit is constructed with the input circuit shown in the figure. The two-bit quantum gates in the circuit are denoted as (1,8), (2,9), (3,6), (4,7), and (5,10). A two-qubit gate (i,j) acts on qubits i and j. For example, (1,8) represents a two-qubit gate acting on qubits 1 and 8. The construction process is as follows: First, use the permutation algorithm (π1) to permute qubits 6, 7, 8, and 9 to 8, 9, 6, and 7. This way, qubit pairs (1,8), (2,9), (3,6), and (4,7) are adjacent on the graph, allowing their corresponding two-bit quantum gates to be directly acted upon. The depth of this step is O(rt(G))+1=O(rt(G)), and its depth is O(rt(G)), as can be seen in the description below; secondly, the permutation algorithm (π2) is used to permute the quantum bits 7,10 to 10,7, so that the quantum bit pair (5,10) is adjacent in the graph, so the corresponding two-qubit gate can be directly acted on. The depth of this step is O(rt(G))+1=O(rt(G)).

[0129] Therefore, only a depth of O(rt(G)) is needed to complete the construction of the hardware compilable circuit of the logic circuit.

[0130] In some embodiments, for any input logic circuit, the algorithm outputs a hardware compilable circuit with an additional circuit depth of at most O(rt(G)), where the additional circuit depth is the ratio of the output circuit depth to the input circuit depth.

[0131] The proof process is as follows: According to |∪ i∈[s] W i |+|∪ j∈[t] W′ j |=Ω(|V|), then there exists a constant c>0, satisfying |∪ i∈[s] W i |≥c|V| or |∪ j∈[t] W′ j |≥c|V|. Without loss of generality, assume |∪ i∈[s] W i |≥c|V|. For some integer

[0132] represents the set of two-qubit gates consisting of one layer of any |V|-qubit logic circuit, q i ,q i+1 Represents the logical bit in Gate. The following constructs its corresponding hardware compilable quantum circuit:

[0133] Will Replace the logical bits in Gate to the vertex set ∪ i∈[s] W i , for each set W i , which can be assigned to For logical bits. This process is equivalent to routing on the graph G, so the circuit depth is rt(G). i Generated subgraph G i In , since the distance between any two logical bits is at most 2, a two-qubit gate (a pair of logical bits) can be realized by inserting at most one exchange gate. i |=O(rt(G)), so in W i Existence Two-qubit gates. Implement G i (W i ) requires a quantum circuit of depth O(rt(G)). Since all G i The vertices do not intersect, so each G i The two-qubit gates on can be implemented in parallel. The circuit depth of this step is O(rt(G))+O(rt(G))=O(rt(G)).

[0134] Because |W i |≥2, so Repeat the above steps times, that is, all two-qubit gates in Gate can be realized with a constant number of times.

[0135] According to the above method, for one layer of logic circuit, the present application obtains a logic circuit with a depth of 2·O(rt(G))=O(rt(G)). Therefore, for any coupled graph G, its worst additional depth is

[0136] In some embodiments, after obtaining a hardware-compilable circuit equivalent to the logic circuit based on the first and second hardware-compilable circuits, the process further includes: permuting each logic bit in the logic circuit back to its original position. This permutation facilitates the subsequent implementation of the quantum algorithm. For example, in Figure 7 , the permutation algorithm (π3) is used to restore the quantum bits to their original positions. The depth of this step is O(rt(G)).

[0137] The technical solution provided by the embodiments of the present application completes the permutation of qubits based on connected subgraphs, and this permutation process has high concurrency. We can complete the permutation of logical quanta within the subgraph, thereby reducing the number of inserted exchange gates and effectively controlling the additional depth of the total mapping circuit. Even when mapping between subgraphs, the mapping within the subgraph can be used to help reduce the distance between qubits. This mapping method based on graph partitioning can globally optimize the distance between qubits and comprehensively control the additional circuit depth of the mapping. That is, for any input logic circuit, the additional circuit depth of the algorithm output hardware-compilable circuit is at most O(rt(G)), where the additional circuit depth is the ratio of the output circuit depth to the input circuit depth.

[0138] The following are device embodiments of the present application, which can be used to implement the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

[0139] Please refer to Figure 8, which shows a block diagram of a qubit mapping device provided by one embodiment of the present application. This device has the function of implementing the above-mentioned qubit mapping method. The function can be implemented by hardware or by hardware executing corresponding software. The device can be a computer device or can be installed in a computer device. The device 800 may include: an acquisition module 810, a generation module 820, and a mapping module 830.

[0140] An acquisition module 810 is configured to acquire a coupling graph corresponding to a quantum device, where each vertex in the coupling graph represents a quantum bit in the quantum device, and an edge between two vertices indicates that a two-qubit gate is allowed to directly act on the quantum bits corresponding to the two vertices.

[0141] A generation module 820 is used to generate at least two connected subgraphs based on the coupling graph, where the number of vertices of each connected subgraph is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph, and the sum of the number of vertices of the at least two connected subgraphs is equal to a constant multiple of the number of vertices of the coupling graph; wherein the number of routes of the coupling graph is the maximum number of permutation rounds of all permutations on the coupling graph.

[0142] The mapping module 830 is configured to perform quantum bit mapping on the logic circuit based on the at least two connected subgraphs to obtain a hardware compilable circuit equivalent to the logic circuit.

[0143] In some embodiments, the generation module 820 includes: a first generation unit and a second generation unit (not shown in FIG. 8 ).

[0144] The first generating unit is used to generate a first vertex set family and a second vertex set family according to the coupling graph, wherein the first vertex set family includes at least one vertex set, the second vertex set family includes at least one vertex set, and each vertex set includes at least two vertices in the coupling graph.

[0145] The second generating unit is configured to generate a connected subgraph corresponding to each vertex set in the first vertex set family and the second vertex set family, to obtain the at least two connected subgraphs.

[0146] The first vertex cluster and the second vertex cluster meet the following conditions:

[0147] The subgraph corresponding to each vertex set in the first vertex set family and the second vertex set family is a connected graph;

[0148] There are no identical vertices in any two vertex sets in the first vertex set, and no identical vertices in any two vertex sets in the second vertex set;

[0149] The number of vertices contained in each vertex set in the first vertex set family and the second vertex set family is greater than or equal to 2 and less than or equal to the number of routes in the coupling graph;

[0150] The total number of vertices in the first vertex group and the second vertex group is equal to a constant multiple of the number of vertices in the coupling graph.

[0151] In some embodiments, the first generation unit includes: a construction subunit, a first generation subunit and a second generation subunit (not shown in FIG8 ).

[0152] The construction subunit is used to construct a maximum matching of the coupling graph, where the maximum matching includes at least one edge in the coupling graph.

[0153] The first generating subunit is configured to generate the first vertex set family according to the maximum matching, wherein each vertex set in the first vertex set family corresponds to two vertices connected by an edge included in the maximum matching.

[0154] The second generating subunit is configured to generate the second vertex set based on the first vertex set.

[0155] In some embodiments, the second generating subunit is configured to:

[0156] According to the first vertex set, determine the initialized set T p , the initialized set T p includes vertices belonging to the coupled graph and not belonging to the first vertex set, and p is a positive integer with an initial value of 1;

[0157] According to the initialized set T p , determine the initialized set S p , the initialized set S p The first vertex set and the initialized set T are included in p The vertices in the connected vertices;

[0158] Determine the initialized collection is an empty set, and determines the initialized set A 0,p is an empty set, i is a positive integer with an initial value of 1;

[0159] The set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p In which, \ represents the difference of two sets, and the adjacent vertices of the i-th vertex refer to the vertices connected to the i-th vertex;

[0160] will be collected With set A i,p The union of is determined as the set

[0161] If i is less than k1, let i=i+1, and again from the set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p The steps in are executed; wherein k1 is the number of vertices in the set S1;

[0162] If i is equal to k1, then Greater than or equal to |T p | / 2, generate the second vertex set; wherein the vertex set included in the second vertex set is the set and the set S p The union of the i-th vertex in , represent The number of vertices in |T p | represents the set T p The number of vertices in ;

[0163] will be collected Determine the set T p+1 ;

[0164] Based on the set T p and k p Determine the set S p+1 ;

[0165] |S p+1 |Determined to be k p+1 ; Among them, |S p+1 | represents the set S p+1 The number of vertices in ;

[0166] If p is less than |T1|, let p=p+1, and again set the set S from the p The i-th vertex in the set The adjacent vertices in are put into set A i,p The steps in the start execution;

[0167] If p is equal to |T1|, the process ends and the second vertex cluster is finally generated.

[0168] In some embodiments, the second generating subunit is configured to:

[0169] If the set S p The i-th vertex in the set At most adjacent vertices, then select the i-th vertex in the set All adjacent vertices are put into the set A i,p middle;

[0170] If the set S p The i-th vertex in the set More than adjacent vertices, then select the i-th vertex in the set Most hits adjacent vertices into the set A i,p middle;

[0171] in, Represents the pair |T p | / k p Round up.

[0172] In some embodiments, the mapping module 830 includes: a first replacement unit, a third generation unit, a second replacement unit, a fourth generation unit, and an acquisition unit (not shown in FIG. 8 ).

[0173] A first permutation unit is configured to permute a first number of logic bit pairs in the logic circuit according to the at least two connected subgraphs; wherein the first number is the number of edges included in the maximum matching of the coupling graph, and each logic bit pair corresponds to two quantum bits acted upon by a two-qubit gate in the logic circuit.

[0174] The third generating unit is configured to generate a first portion of hardware compilable circuits corresponding to the first number of logic bit pairs.

[0175] The second replacement unit is configured to replace the remaining logic bit pairs in the logic circuit according to the at least two connected subgraphs.

[0176] The fourth generating unit is configured to generate a second portion of hardware compilable circuits corresponding to the remaining logic bit pairs.

[0177] An acquiring unit is configured to acquire a hardware compilable circuit equivalent to the logic circuit according to the first portion of the hardware compilable circuit and the second portion of the hardware compilable circuit.

[0178] In some embodiments, the mapping module 830 further includes a third replacement unit (not shown in FIG. 8 ).

[0179] The third replacement unit is used to replace each of the logic bits in the logic circuit to an original position.

[0180] It should be noted that the apparatus provided in the above embodiments, when implementing its functions, is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0181] Please refer to FIG9 , which shows a structural block diagram of a computer device 900 provided in one embodiment of the present application.

[0182] Typically, the computer device 900 includes a processor 910 and a memory 920 .

[0183] The processor 910 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 910 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), or PLA (Programmable Logic Array). The processor 910 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 910 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 910 may also include an AI processor for processing computing operations related to machine learning.

[0184] The memory 920 may include one or more computer-readable storage media, which may be non-transitory. The memory 920 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 920 is used to store a computer program, which is configured to be executed by one or more processors to implement the above-mentioned quantum bit mapping method.

[0185] Those skilled in the art will appreciate that the structure shown in FIG. 9 does not limit the computer device 900 , and may include more or fewer components than shown, or combine certain components, or adopt a different component arrangement.

[0186] In some embodiments, a computer-readable storage medium is also provided, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the above-mentioned quantum bit mapping method.

[0187] Optionally, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random-Access Memory), SSD (Solid State Drives), or an optical disk, etc. Among them, the random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0188] In some embodiments, a computer program product is also provided, which includes a computer program stored in a computer-readable storage medium, and a processor reads and executes the computer program from the computer-readable storage medium to implement the above-mentioned quantum bit mapping method.

[0189] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application do not limit this.

[0190] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A quantum bit mapping method, the method being performed by a computer device, the method comprising: Obtaining a coupling graph corresponding to a quantum device, wherein each vertex in the coupling graph represents a quantum bit in the quantum device, and an edge between two vertices indicates that a two-qubit gate is allowed to directly act on the quantum bits corresponding to the two vertices; At least two connected subgraphs are generated according to the coupling graph, the number of vertices of each connected subgraph is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph, and the sum of the number of vertices of the at least two connected subgraphs is equal to a constant multiple of the number of vertices of the coupling graph; wherein the number of routes of the coupling graph is the maximum number of permutation rounds of all permutations on the coupling graph; Based on the at least two connected subgraphs, quantum bit mapping is performed on the logic circuit to obtain a hardware compilable circuit equivalent to the logic circuit.

2. The method according to claim 1, wherein: Generating at least two connected subgraphs according to the coupling graph includes: Generate a first vertex set family and a second vertex set family according to the coupling graph, wherein the first vertex set family includes at least one vertex set, the second vertex set family includes at least one vertex set, and each vertex set includes at least two vertices in the coupling graph; Generate a connected subgraph corresponding to each vertex set in the first vertex set family and the second vertex set family to obtain the at least two connected subgraphs; The first vertex group and the second vertex group satisfy the following conditions: The subgraph corresponding to each vertex set in the first vertex set family and the second vertex set family is a connected graph; There are no identical vertices in any two vertex sets in the first vertex set family, and there are no identical vertices in any two vertex sets in the second vertex set family; The number of vertices contained in each vertex set in the first vertex set family and the second vertex set family is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph; The total number of vertices in the first vertex group and the second vertex group is equal to a constant multiple of the number of vertices in the coupling graph.

3. The method according to claim 2, wherein: Generating the first vertex cluster and the second vertex cluster according to the coupling graph comprises: Constructing a maximum matching of the coupling graph, wherein the maximum matching includes at least one edge in the coupling graph; Generate the first vertex set family according to the maximum matching, each vertex set in the first vertex set family corresponds to two vertices connected by an edge included in the maximum matching; The second vertex set is generated according to the first vertex set.

4. The method according to claim 3, wherein: The step of generating the second vertex set according to the first vertex set includes: According to the first vertex set, determine the initialized set T p , the initialized set T p includes vertices belonging to the coupling graph and not belonging to the first vertex set, and p is a positive integer with an initial value of 1; According to the set T initialized p , determine the initialized set S p , the initialized set S p The first vertex set and the initialized set T are included in p The vertices in are connected to each other; Determine the initialized collection is an empty set, and determines the initialized set A 0,p is an empty set, i is a positive integer with an initial value of 1; The set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p Among them, \ table represents the difference of two sets, and the adjacent vertices of the i-th vertex refer to the vertices connected to the i-th vertex; Will gather With set A i,p The union of is determined as the set If i is less than k1, let i=i+1, and again from the set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p The steps in are executed; wherein k1 is the number of vertices in the set S1; If i is equal to k1, then Greater than or equal to |T p | / 2, the second vertex set cluster is generated; wherein the vertex set included in the second vertex set cluster is the set and the set S p The union of the i-th vertex in , represent The number of vertices in |T p | represents the set T p The number of vertices in ; Will gather Determine the set T p+1 ; Based on the set T p and k p Determine the set S p+1 ; |S p+1 |Determined as k p+1 ; Among them, |S p+1 | represents the set S p+1 The number of vertices in ; If p is less than |T1|, then set p=p+1, and again set the set S from p The i-th vertex in the set The adjacent vertices in are put into set A i,p The steps in start to execute; If p is equal to |T1|, the process ends and the second vertex cluster is finally generated.

5. The method according to claim 4, wherein: The set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p Including: If the set S p The i-th vertex in the set At most adjacent vertices, then select the i-th vertex in the set All adjacent vertices in are put into the set A i,p middle; If the set S p The i-th vertex in the set More than adjacent vertices, then select the i-th vertex in the set Most The adjacent vertices are put into the set A i,p middle; in, Represents |T p | / k p Round up.

6. The method according to any one of claims 1 to 5, wherein: The step of performing quantum bit mapping on the logic circuit based on the at least two connected subgraphs to obtain a hardware compilable circuit equivalent to the logic circuit comprises: According to the at least two connected subgraphs, a first number of logic bit pairs in the logic circuit are permuted; wherein the first number is the number of edges included in the maximum matching of the coupling graph, and each logic bit pair corresponds to two qubits acted on by a two-qubit gate in the logic circuit, generating a first portion of hardware compilable circuits corresponding to the first number of logic bit pairs; According to the at least two connected subgraphs, permuting remaining logic bit pairs in the logic circuit; Generating a second portion of hardware compilable circuits corresponding to the remaining logic bit pairs; A hardware compilable circuit equivalent to the logic circuit is obtained according to the first part of the hardware compilable circuit and the second part of the hardware compilable circuit.

7. The method according to claim 6, wherein: After obtaining a hardware compilable circuit equivalent to the logic circuit according to the first part of the hardware compilable circuit and the second part of the hardware compilable circuit, the method further includes: Each of the logic bits in the logic circuit is replaced to an original position.

8. A quantum bit mapping device, comprising: An acquisition module is used to acquire a coupling graph corresponding to a quantum device, wherein each vertex in the coupling graph represents a quantum bit in the quantum device, and an edge between two vertices indicates that a two-qubit gate is allowed to directly act on the quantum bits corresponding to the two vertices; A generating module, configured to generate at least two connected subgraphs according to the coupling graph, wherein the number of vertices of each connected subgraph is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph, and the sum of the number of vertices of the at least two connected subgraphs is equal to the number of routes of the coupling graph A constant multiple of the number of vertices of ; wherein the number of routes of the coupling graph is the maximum number of permutation rounds of all permutations on the coupling graph; A mapping module is used to perform quantum bit mapping on the logic circuit based on the at least two connected subgraphs to obtain a hardware compilable circuit equivalent to the logic circuit.

9. A computer device, comprising a processor and a memory, wherein the memory stores a computer program, and the computer program is loaded and executed by the processor to implement the quantum bit mapping method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and the computer program is loaded and executed by a processor to implement the quantum bit mapping method according to any one of claims 1 to 7.

11. A computer program product, comprising a computer program, wherein the computer program is loaded and executed by a processor to implement the quantum bit mapping method according to any one of claims 1 to 7.

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