Circuit board, circuit board assembly and electronic device

Abstract

Provided in the embodiments of the present application are a circuit board, a circuit board assembly and an electronic device, which are applied to the technical field of electronics. The circuit board is configured to bear a target storage chip, which is any type of at least two types of storage chips, and the circuit board comprises a first bonding pad group, which is configured to connect to the target storage chip and comprises a plurality of first bonding pads, wherein each first bonding pad is connected to at least two traces; each trace connected to at least some of the first bonding pads comprises a first jump connection region, and is disconnected at the first jump connection region; and in a case where the circuit board is configured to bear the target storage chip, the first jump connection regions comprised by target traces connected to the at least some of the first bonding pads are configured such that jump connection elements are assembled therein, and each target trace is the trace of at least two traces connected to each first bonding pad that corresponds to the target storage chip. In this way, different types of storage chips can be compatible on the same circuit board.

Description

Circuit boards, circuit board assemblies, and electronic devices

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on September 12, 2023, with application number 202311170956.1 and application name “Circuit Board, Circuit Board Assembly and Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a circuit board, a circuit board assembly, and an electronic device. Background Art

[0003] With the continuous development of electronic technology, electronic devices such as mobile phones and tablet computers have gradually become common tools in people's daily life and work. In order to meet users' diverse needs for electronic devices, electronic devices can be equipped with various types of chips, such as processor chips and memory chips.

[0004] For example, memory chips installed in electronic devices can be mounted on circuit boards within the electronic device. Currently, there are many different types of memory chips. When different types of memory chips are installed on circuit boards, different circuit boards are required. This reduces the utilization rate of circuit boards of the same type and increases circuit board design costs.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a circuit board, a circuit board assembly, and an electronic device, which can be compatible with different types of memory chips on the same circuit board, thereby improving the utilization rate of the same type of circuit boards and reducing the design cost of the circuit boards.

[0007] In a first aspect, an embodiment of the present application proposes a circuit board, which is used to carry a target memory chip. The target memory chip includes any one of at least two types of memory chips, the number of pins of each type of memory chip in the at least two types of memory chips is equal, and the pin arrangement of each type of memory chip in the at least two types of memory chips is the same. The circuit board includes a first pad group, which is used to connect to the target memory chip; the first pad group includes a plurality of first pads, each first pad is connected to at least two traces, and each trace connected to at least some of the first pads includes a first jumper area, and the traces at the first jumper area are disconnected. In the case where the circuit board is used to carry the target memory chip, the target traces connected to at least some of the first pads include a first jumper area for assembling a jumper element, and the target trace is one of the at least two traces connected to the first pad that corresponds to the target memory chip.

[0008] In this way, by configuring each first pad on the circuit board to connect to at least two traces, the pin connections of different types of memory chips are compatible. Furthermore, each trace connected to at least some of the first pads includes a first jumper region. When different types of memory chips are mounted on the circuit board, a jumper element can be installed at the first jumper region included in a corresponding trace of the at least two traces connected to the first pads to enable selection. This allows compatibility of different types of memory chips on the same circuit board, thereby increasing the utilization rate of the same type of circuit board and reducing circuit board design costs.

[0009] In one possible implementation, the target memory chip includes a first memory chip or a second memory chip. Each first pad is connected to two traces, and at least some of the two traces connected to the first pads include a first jumper region. When the circuit board is used to carry the first memory chip, the first traces connected to at least some of the first pads include a first jumper region for assembling a jumper component; the first trace is one of the two traces connected to the first pads that corresponds to the first memory chip; when the circuit board is used to carry the second memory chip, the second traces connected to at least some of the first pads include a first jumper region for assembling a jumper component; the second trace is one of the two traces connected to the first pads that corresponds to the second memory chip. In this way, compatibility between the first memory chip and the second memory chip can be achieved on the same circuit board.

[0010] In one possible implementation, the plurality of first pads include first-type pads, the first-type pads being used to connect to power pins of a first memory chip and / or power pins of a second memory chip, and the first-type pads not being used to connect to unused pins of the first memory chip or unused pins of the second memory chip; the circuit board is further used to carry a first power module. When the first-type pads are used to connect to power pins of the first memory chip, the first power module is used to connect to the first-type pads via a first trace; and / or, when the first-type pads are used to connect to power pins of a second memory chip, the first power module is used to connect to the first-type pads via a second trace. In this way, a specific connection relationship of the first-type pads in the circuit board is provided.

[0011] In one possible implementation, the first routing line and the second routing line connected by the first type of pad both include a first jumper area. When the circuit board is used to carry a first memory chip, the first jumper area included in the first routing line connected by the first type of pad is used to assemble a jumper component, and the first jumper area included in the second routing line connected by the first type of pad is not used to assemble a jumper component; when the circuit board is used to carry a second memory chip, the first jumper area included in the second routing line connected by the first type of pad is used to assemble a jumper component, and the first jumper area included in the first routing line connected by the first type of pad is not used to assemble a jumper component. In this way, by jumping the first jumper area included in the first routing line and the second routing line connected by the first type of pad, the first type of pad on the same circuit board can be compatible with some pins in the first memory chip and the second memory chip.

[0012] In one possible implementation, the first trace and / or the second trace connected to the first power module does not include the first jumper area, and the first trace or the second trace not connected to the first power module includes the first jumper area. When the circuit board is used to carry the first memory chip and the first type of pad is used to connect to the power pin of the first memory chip, the first power module is used to power on the first trace connected to the first type of pad; and / or, when the circuit board is used to carry the second memory chip and the first type of pad is used to connect to the power pin of the second memory chip, the first power module is used to power on the second trace connected to the first type of pad. In this way, by powering on the first power module, the first type of pad on the same circuit board can be compatible with some pins in the first memory chip and the second memory chip, which can reduce the jumper components that need to be assembled at the first jumper area, thereby reducing the cost of the circuit board assembly and simplifying the manufacturing steps of the circuit board assembly.

[0013] In one possible implementation, neither the first trace nor the second trace connected to the first power module includes a first jumper region. When the circuit board is used to carry a first memory chip and the first type of pad is used to connect to the power pin of the first memory chip, the first power module is used to power on the first trace connected to the first type of pad, and the first power module is used not to power on the second trace connected to the first type of pad; and when the circuit board is used to carry a second memory chip and the first type of pad is used to connect to the power pin of the second memory chip, the first power module is used to power on the second trace connected to the first type of pad, and the first power module is used not to power on the first trace connected to the first type of pad.

[0014] In one possible implementation, a first trace connected to a first power module does not include a first jumper region, and a second trace not connected to the first power module includes a first jumper region. When the circuit board is used to carry a first memory chip and the first-type pad is used to connect to a power pin of the first memory chip, the first power module is used to power on the first trace connected to the first-type pad, and the first jumper region included in the second trace connected to the first-type pad is not used to assemble a jumper component; and when the circuit board is used to carry a second memory chip and the first-type pad is used to connect to a signal pin or a ground pin of the second memory chip, the first jumper region included in the second trace connected to the first-type pad is used to assemble a jumper component, and the first power module is used to not power on the first trace connected to the first-type pad.

[0015] In one possible implementation, the second trace connected to the first power module does not include a first jumper region, and the first trace not connected to the first power module includes a first jumper region. When the circuit board is used to carry a first memory chip, and the first type of pad is used to connect to a signal pin or a ground pin of the first memory chip, the first jumper region included in the first trace connected to the first type of pad is used to assemble a jumper component, and the first power module is used to not power on the second trace connected to the first type of pad; and when the circuit board is used to carry a second memory chip, and the first type of pad is used to connect to a power pin of the second memory chip, the first power module is used to power on the second trace connected to the first type of pad, and the first jumper region included in the first trace connected to the first type of pad is not used to assemble a jumper component.

[0016] In one possible implementation, the plurality of first pads include second-type pads, and the second-type pads are used to connect to the signal pins of the first memory chip and the signal pins of the second memory chip, or to connect to the signal pins of the first memory chip and the ground pins of the second memory chip, or to connect to the ground pins of the first memory chip and the signal pins of the second memory chip. The first traces and the second traces connected to the second-type pads both include a first jumper region; when the circuit board is used to carry the first memory chip, the first jumper region included in at least some of the first traces connected to the second-type pads is used to mount a jumper component; when the circuit board is used to carry the second memory chip, the first jumper region included in the second traces connected to the second-type pads is used to mount a jumper component. In this way, by jumpering the first jumper region included in the first traces and the second traces connected to the second-type pads, the second-type pads on the same circuit board can be compatible with some pins in the first memory chip and the second memory chip.

[0017] In one possible implementation, the first pad group further includes multiple second pads, each of which is connected to a trace, with the trace connected by the second pads being a third trace. Some of the third traces connected to the second pads include a second jumper region, with the third trace disconnected at the second jumper region; another portion of the third traces connected to the second pads do not include a second jumper region. When the circuit board is used to support the first or second memory chip, at least some of the third traces connected to the second pads include a second jumper region for mounting a jumper component. This provides a specific connection relationship for the second pads on the circuit board.

[0018] In one possible implementation, the plurality of second pads include third-type pads, where the third-type pads are configured to connect to a power pin of the first memory chip and an unused pin of the second memory chip, or to connect to an unused pin of the first memory chip and a power pin of the second memory chip. The circuit board is further configured to carry a second power module, which is configured to connect to the third-type pads via a third trace.

[0019] In one possible implementation, the third trace connected to the third-type pad includes a second jumper region. When the circuit board is used to support a first memory chip and the third-type pad is used to connect to a power pin of the first memory chip, the second jumper region included in the third trace connected to the third-type pad is used to mount a jumper component. When the circuit board is used to support a second memory chip and the third-type pad is used to connect to an unused pin of the second memory chip, the second jumper region included in the third trace connected to the third-type pad is not used to mount a jumper component. When the circuit board is used to support a first memory chip and the third-type pad is used to connect to an unused pin of the first memory chip, the second jumper region included in the third trace connected to the third-type pad is not used to mount a jumper component. When the circuit board is used to support a second memory chip and the third-type pad is used to connect to a power pin of the second memory chip, the second jumper region included in the third trace connected to the third-type pad is used to mount a jumper component. In this way, by determining whether the second jumper region included in the third trace connected to the third-type pad is mounted with a jumper component, the third-type pads on the same circuit board can be compatible with some pins of the first and second memory chips.

[0020] In one possible implementation, the third trace connected to the third type of pad does not include the second jumper area. When the circuit board is used to carry the first memory chip, and the third type of pad is used to connect to the power pin of the first memory chip, the second power module is used to power on the third trace connected to the third type of pad; when the circuit board is used to carry the second memory chip, and the third type of pad is used to connect to the unused pin of the second memory chip, the second power module is used not to power on the third trace connected to the third type of pad. When the circuit board is used to carry the first memory chip, and the third type of pad is used to connect to the unused pin of the first memory chip, the second power module is used not to power on the third trace connected to the third type of pad; when the circuit board is used to carry the second memory chip, and the third type of pad is used to connect to the power pin of the second memory chip, the second power module is used to power on the third trace connected to the third type of pad. In this way, by powering on or off the second power supply module, the third type of pads on the same circuit board can be compatible with some pins in the first memory chip and the second memory chip, which can reduce the jump selection components that need to be assembled in the second jump selection area, thereby reducing the cost of the circuit board assembly and simplifying the production steps of the circuit board assembly.

[0021] In one possible implementation, the plurality of second pads include a fourth type of pad, which is used to connect to unused pins of the first storage chip and / or unused pins of the second storage chip, and the fourth type of pad is not used to connect to the power pins of the first storage chip or the power pins of the second storage chip.

[0022] In one possible implementation, the third trace connected to the fourth-category pad includes a second jumper region. When the circuit board is used to carry a first memory chip and the fourth-category pad is used to connect to an unused pin of the first memory chip, the second jumper region included in the third trace connected to the fourth-category pad is not used to mount a jumper component; when the circuit board is used to carry a second memory chip and the fourth-category pad is used to connect to a ground pin or a signal pin of the second memory chip, the second jumper region included in the third trace connected to the fourth-category pad is used to mount a jumper component. When the circuit board is used to carry a first memory chip and the fourth-category pad is used to connect to a ground pin or a signal pin of the first memory chip, the second jumper region included in the third trace connected to the fourth-category pad is used to mount a jumper component or is not used to mount a jumper component; when the circuit board is used to carry a second memory chip and the fourth-category pad is used to connect to an unused pin of the second memory chip, the second jumper region included in the third trace connected to the fourth-category pad is not used to mount a jumper component. In this way, whether the second jumper area included in the third trace connected by the fourth type pad is equipped with a jumper element makes the fourth type pad on the same circuit board compatible with some pins in the first memory chip and the second memory chip.

[0023] In one possible implementation, the third trace connected to the fourth type of pad does not include the second jumper region. Thus, when assembling the first memory chip or the second memory chip on the circuit board, fewer jumper components need to be mounted in the second jumper region, thereby reducing the cost of the circuit board assembly and simplifying the production steps of the circuit board assembly.

[0024] In one possible implementation, the plurality of second pads include a fifth type of pad, which is used to connect to the ground pin of the first memory chip and the ground pin of the second memory chip. The third trace connected to the fifth type of pad includes a second jumper region; when the circuit board is used to carry the first memory chip, the second jumper region included in the third trace connected to the fifth type of pad is used to mount a jumper component; when the circuit board is used to carry the second memory chip, the second jumper region included in the third trace connected to the fifth type of pad is used to mount a jumper component or is not used to mount a jumper component; or, the third trace connected to the fifth type of pad does not include a second jumper region. In this way, a specific connection relationship between the fifth type of pads in the circuit board is provided, so that the fifth type of pads on the same circuit board can be compatible with some pins in the first memory chip and the second memory chip.

[0025] In one possible implementation, the circuit board further includes a second solder pad group configured to connect to the processor chip, and the circuit board further supports a third power module. The plurality of second solder pads include a sixth type of solder pad, configured to connect to power pins of a first memory chip and a second memory chip. When the circuit board supports the first memory chip, the power pin of the first memory chip is sequentially connected to the first power pin of the processor chip via the sixth type of solder pad, a third trace, and the third power module. When the circuit board supports the second memory chip, the power pin of the second memory chip is sequentially connected to the second power pin of the processor chip via the sixth type of solder pad, a third trace, and the third power module. The first power pin and the second power pin are the same power pin. The third trace connected to the sixth type of solder pad includes a second jumper region. When the circuit board supports the first or second memory chip, the third trace connected to the sixth type of solder pad includes a second jumper region for mounting a jumper component. Alternatively, the third trace connected to the sixth type of solder pad does not include a second jumper region. When the circuit board supports the first or second memory chip, the third power module is configured to power on the third trace connected to the sixth type of solder pad. In this way, when the same power pin in the processor chip is connected to the power pins at the same position in the first memory chip and the second memory chip respectively, the two traces can be merged into one trace to simplify the structure of the circuit board.

[0026] In a possible implementation, the jump element includes any one of a resistor, a capacitor, a diode, and a transistor.

[0027] In a possible implementation, the sizes of the memory chips in the at least two types of memory chips are the same, so as to facilitate reserving mounting positions for the memory chips in the circuit board.

[0028] In one possible implementation, the at least two storage chips include at least two of a first universal flash storage (UFS) storage chip, a second UFS storage chip, and an embedded multi media card (EMMC) storage chip; an interface version of the first UFS storage chip is different from an interface version of the second UFS storage chip.

[0029] In a second aspect, an embodiment of the present application provides a circuit board assembly, comprising a target memory chip and the above-mentioned circuit board, wherein the target memory chip is connected to the circuit board.

[0030] In a third aspect, an embodiment of the present application provides an electronic device, comprising a housing and the above-mentioned circuit board assembly, wherein the circuit board assembly is disposed inside the housing.

[0031] The possible implementation methods of the second and third aspects have effects similar to those of the first aspect and the possible designs of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1 is a schematic diagram of the three-dimensional structure of an electronic device provided in an embodiment of the present application;

[0033] FIG2 is a schematic diagram of the exploded structure of an electronic device provided in an embodiment of the present application;

[0034] FIG3 is a schematic structural diagram of a circuit board assembly provided in an embodiment of the present application;

[0035] FIG4 is a schematic diagram of the layout of pins of the first memory chip or the second memory chip after packaging according to an embodiment of the present application;

[0036] FIG5 is a schematic diagram of an exemplary structure of a circuit board provided in an embodiment of the present application;

[0037] FIG6 is a schematic diagram of a connection relationship between a first type of pin-shared pad and a first trace and a second trace provided in an embodiment of the present application;

[0038] FIG7 is a schematic diagram of another connection relationship between the first type of pin-shared pad and the first trace and the second trace provided in an embodiment of the present application;

[0039] FIG8 is a schematic diagram of a connection relationship between the second type of pin-shared pad and the first trace and the second trace provided in an embodiment of the present application;

[0040] FIG9 is a schematic diagram of another connection relationship between the second type of pin-shared pad and the first trace and the second trace provided in an embodiment of the present application;

[0041] FIG10 is a schematic diagram of a connection relationship between a third type of pin-shared pad and a first trace and a second trace provided in an embodiment of the present application;

[0042] FIG11 is a schematic diagram of another connection relationship between the third type of pin-shared pad and the first trace and the second trace provided in an embodiment of the present application;

[0043] FIG12 is a schematic diagram of a connection relationship between the fourth type of pin-shared pad and the first trace and the second trace provided in an embodiment of the present application;

[0044] FIG13 is a schematic diagram of another connection relationship between the fourth type of pin-shared pad and the first trace and the second trace provided in an embodiment of the present application;

[0045] FIG14 is a schematic diagram of a connection relationship between the fifth type of pin-shared pad and the first trace and the second trace provided in an embodiment of the present application;

[0046] FIG15 is a schematic diagram of another connection relationship between the fifth type of pin-shared pad and the first trace and the second trace provided in an embodiment of the present application;

[0047] FIG16 is a schematic diagram of a connection relationship between a sixth type of pin-shared pad and a first trace and a second trace provided in an embodiment of the present application;

[0048] FIG17 is a schematic diagram of a connection relationship between a seventh type of pin-shared pad and a first trace and a second trace provided by an embodiment of the present application;

[0049] FIG18 is a schematic diagram of a connection relationship between the eighth type of pin-shared pad and the first trace and the second trace provided in an embodiment of the present application;

[0050] FIG19 is a schematic diagram of a connection relationship between the ninth type of pin-shared pad and the third trace provided in an embodiment of the present application;

[0051] FIG20 is a schematic diagram of another connection relationship between the ninth type of pin-shared pad and the third trace provided in an embodiment of the present application;

[0052] FIG21 is a schematic diagram of a connection relationship between the tenth type of pin-shared pad and the third trace provided in an embodiment of the present application;

[0053] FIG22 is a schematic diagram of another connection relationship between the tenth type of pin-shared pad and the third trace provided by an embodiment of the present application;

[0054] FIG23 is a schematic diagram of a connection relationship between the eleventh type of pin-shared pad and the third trace provided in an embodiment of the present application;

[0055] FIG24 is a schematic diagram of a connection relationship between the twelfth type of pin-shared pad and the third trace provided in an embodiment of the present application;

[0056] FIG25 is a schematic diagram of a connection relationship between the thirteenth category pin-shared pad and the third trace provided in an embodiment of the present application;

[0057] FIG26 is a schematic diagram of a connection relationship between the fourteenth type of pin-shared pad and the third trace provided in an embodiment of the present application;

[0058] FIG27 is a schematic diagram of a connection relationship between the fifteenth type of pin-shared pad and the third trace provided by an embodiment of the present application;

[0059] FIG28 is a schematic diagram of a connection relationship between the sixteenth type of pin-shared pad and the third trace provided by an embodiment of the present application;

[0060] FIG29 is a schematic diagram of an exemplary structure of a first memory chip mounted on a circuit board according to an embodiment of the present application;

[0061] FIG30 is a schematic diagram of an exemplary structure of a second memory chip mounted on a circuit board according to an embodiment of the present application;

[0062] FIG31 is a schematic diagram of a connection relationship between the sixth type of pad and the third trace provided in an embodiment of the present application;

[0063] FIG32 is a schematic diagram of another connection relationship between the sixth type of pad and the third trace provided in an embodiment of the present application. DETAILED DESCRIPTION

[0064] To facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. For example, the first chip and the second chip are merely used to distinguish different chips and do not limit their order. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean that they are different.

[0065] It should be noted that in the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0066] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0067] Some electronic devices feature circuit boards that can be mounted with memory chips. Currently, there are many different types of memory chips, each with its own unique protocol. Consequently, mounting different types of memory chips on a circuit board requires a different circuit board. This means that each type of memory chip requires a separate circuit board, which reduces the utilization of the same type of circuit board and increases circuit board design costs.

[0068] Based on this, an embodiment of the present application provides a circuit board, a circuit board assembly and an electronic device, wherein the circuit board is used to carry a target memory chip, the target memory chip includes any one of at least two memory chips, the number of pins of various memory chips in the at least two memory chips are equal, and the pin arrangement of various memory chips in the at least two memory chips is the same; the circuit board includes a first pad group, the first pad group is used to connect to the target memory chip, the first pad group includes multiple first pads, each first pad is connected to at least two routing lines, each routing line connected to at least some of the first pads includes a first jump selection area, and the routing at the first jump selection area is disconnected; when the circuit board is used to carry the target memory chip, the target routing lines connected to at least some of the first pads include a first jump selection area for assembling a jump selection element, and the target routing line is one routing line corresponding to the target memory chip among the at least two routing lines connected to the first pads.

[0069] Therefore, by configuring each first pad on the circuit board to connect to at least two traces, the pin connections of different types of memory chips are compatible. Furthermore, each trace connected to at least some of the first pads includes a first jumper region. When different types of memory chips are mounted on the circuit board, a jumper element can be installed at the first jumper region included in a corresponding trace of the at least two traces connected to the first pads to enable selection. This allows compatibility of different types of memory chips on the same circuit board, thereby increasing the utilization rate of the same type of circuit board and reducing circuit board design costs.

[0070] It is understood that the electronic devices in the embodiments of the present application may be mobile phones, tablet computers (Pads), laptop computers, smart TVs, wearable devices (such as smart watches, smart bracelets, etc.), e-book readers, personal computers (PCs), personal digital assistants (PDAs), vehicle-mounted devices, financial devices, virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and other electronic products including memory chips. The embodiments of the present application do not limit the specific technology and specific device form used by the electronic devices.

[0071] Figure 1 is a schematic diagram of the three-dimensional structure of an electronic device provided in an embodiment of the present application, and Figure 2 is a schematic diagram of the exploded structure of the electronic device shown in Figure 1. Referring to Figures 1 and 2, taking a mobile phone as an example, the electronic device may include a display module 10, a housing 20, and a circuit board assembly 30. The housing 20 includes a middle frame 21 and a back cover 22, with the middle frame 21 positioned between the display module 10 and the back cover 22.

[0072] The display module 10 is used to implement a display function. The display module 10 may include a display panel, which may be a liquid crystal display (LCD) panel, an organic light-emitting diode (OLED) display panel, an active-matrix organic light-emitting diode (AMOLED) display panel, a flexible light-emitting diode (FLED) display panel, a MiniLED display panel, a MicroLED display panel, a Micro-OLED display panel, a quantum dot light-emitting diode (QLED) display panel, etc.

[0073] In some embodiments, the middle frame 21 and back cover 22 can be integrally formed to enhance the compactness of the electronic device and reduce the possibility of damage to the electronic components within the electronic device due to the detachment of the back cover 22 when the electronic device is dropped. In other embodiments, the middle frame 21 and back cover 22 can also be detachably connected to facilitate the repair or replacement of electronic components such as batteries and circuit boards within the electronic device, thereby increasing the flexibility of the electronic device.

[0074] The display module 10, the middle frame 21, and the back cover 22 can enclose a housing space for the electronic device, in which components such as the circuit board assembly 30, a battery, and a camera module can be placed, so that the circuit board assembly 30 can be disposed inside the housing 20. For example, as shown in FIG2 , the circuit board assembly 30 can be located on the surface of the middle frame 21 facing the back cover 22.

[0075] For example, FIG3 is a schematic diagram of the structure of a circuit board assembly provided in an embodiment of the present application. Referring to FIG3 , the circuit board assembly 30 includes a circuit board 31, a target memory chip 32, a processor chip 33, and a power management chip 34. The target memory chip 32, the processor chip 33, and the power management chip 34 can be connected to the circuit board 31. Specifically, the target memory chip 32, the processor chip 33, and the power management chip 34 can be connected to the circuit board 31 by soldering.

[0076] The circuit board 31 may be a mainboard of an electronic device, and serves to carry electronic components such as a target memory chip 32, a processor chip 33, and a power management chip 34, and to electrically connect the target memory chip 32, the processor chip 33, and the power management chip 34. Furthermore, the circuit board 31 may include, but is not limited to, a printed circuit board (PCB), a flexible printed circuit board (FPC), and a rigid-flexible circuit board.

[0077] In electronic devices, the core components of the storage system include the target memory chip 32, the processor chip 33, interfaces, and buses. The interface of the target memory chip 32 includes the pins of the packaged target memory chip 32, and the interface of the processor chip 33 includes the pins of the packaged processor chip 33. The bus refers to the wiring on the circuit board 31 that enables communication between the target memory chip 32 and the processor chip 33 when the target memory chip 32 and the processor chip 33 are connected to the circuit board 31.

[0078] In the electronic device's storage system, the power management chip 34 powers on and, under the constraints of the protocol, enables data exchange between the target storage chip 32 and the processor chip 33. The bus, interface, and power management chip 34 provide the necessary hardware environment for the electronic device's storage system. The protocol regulates hardware behavior, reduces data errors during high-speed transmission, and maintains the normal operation of the storage system.

[0079] The processor chip 33 includes but is not limited to a central processing unit (CPU) chip, and the processor chip 33 may also be referred to as a host chip. Some processor chips 33 may support multiple different types of memory chips.

[0080] The power management chip 34 may be a power management integrated circuit (PMIC) chip, which is mainly used to convert the voltage provided by the processor chip 33 into the voltage required for the target memory chip 32 to operate.

[0081] The target memory chip 32 may include any one of at least two memory chips, wherein the protocols (protocol modes or protocol specifications) of the at least two memory chips are different. Furthermore, the number of pins of the at least two memory chips is equal, and the pin arrangements of the at least two memory chips are the same.

[0082] It should be noted that the pin arrangements of various memory chips in at least two memory chips are the same, which specifically means that the number of pins of various memory chips in at least two memory chips arranged in any direction and the spacing between two adjacent pins arranged in any direction are equal.

[0083] Currently, memory chips used in electronic devices are rapidly developing in terms of protocols and interfaces. Currently, existing mobile embedded memory chips primarily fall into two categories: UFS memory chips and EMMC memory chips. UFS memory chips offer numerous advantages over EMMC memory chips, particularly in performance; however, EMMC memory chips have certain advantages in cost and supply. While UFS and EMMC memory chips are independent in terms of protocol, they share the same pinout: UFS and EMMC memory chips have the same number of pins, and their pinout layout is identical.

[0084] The UFS storage chip may include a first UFS storage chip and a second UFS storage chip, the interface version of the first UFS storage chip is different from the interface version of the second UFS storage chip. In addition, the number of pins of the first UFS storage chip, the number of pins of the second UFS storage chip, and the number of pins of the EMMC storage chip are all equal, and the pin arrangement of the first UFS storage chip, the pin arrangement of the second UFS storage chip, and the pin arrangement of the EMMC storage chip are all the same.

[0085] The first UFS storage chip can be a UFS storage chip that supports UFS3.0 and above, and the second UFS storage chip can be a UFS storage chip that supports UFS3.0 and below. The first UFS storage chip is backward compatible with the protocol of the second UFS storage chip. For example, the first UFS storage chip can be a UFS3.1 storage chip, and the second UFS storage chip can be a UFS2.2 storage chip. The EMMC storage chip can be an EMMC5.1 storage chip.

[0086] In some embodiments, the processor chip 33 supports not only UFS storage chips but also EMMC storage chips. For example, the processor chip 33 supports a first UFS storage chip and an EMMC storage chip, or the processor chip 33 supports a second UFS storage chip and an EMMC storage chip.

[0087] In this way, by setting each first pad on the circuit board 31 to be connected to two routing lines, a compatible design is implemented for the connection relationship between the processor chip 33 and the UFS storage chip, and the connection relationship between the processor chip 33 and the EMMC storage chip. When a UFS storage chip or an EMMC storage chip is assembled on the circuit board 31, a jump select element can be assembled at the first jump select area included in the corresponding one of the two routing lines connected to the first pad to achieve gating, thereby achieving compatibility between UFS storage chips and EMMC storage chips on the same circuit board 31. Therefore, the embodiment of the present application can implement access and control of UFS storage chips or EMMC storage chips on the same circuit board 31.

[0088] In some other embodiments, the processor chip 33 may also support a first UFS storage chip and a second UFS storage chip. Accordingly, the same circuit board 31 may be compatible with both the first UFS storage chip and the second UFS storage chip.

[0089] In some further embodiments, the processor chip 33 may further support a first UFS storage chip, a second UFS storage chip, and an EMMC storage chip.

[0090] In this way, by setting each first solder pad on the circuit board 31 to be connected to at least two routing lines, a compatible design is implemented for the connection relationship between the processor chip 33 and the first UFS storage chip, the connection relationship between the processor chip 33 and the second UFS storage chip, and the connection relationship between the processor chip 33 and the EMMC storage chip. When any one of the first UFS storage chip, the second UFS storage chip and the EMMC storage chip is assembled on the circuit board 31, a jump selection element can be assembled at the first jump selection area included in the corresponding one of the at least two routing lines connected to the first solder pad to achieve selection, thereby achieving compatibility of the three types of storage chips, namely the first UFS storage chip, the second UFS storage chip and the EMMC storage chip, on the same circuit board 31.

[0091] In summary, the at least two memory chips include at least two of a first UFS memory chip, a second UFS memory chip, and an EMMC memory chip. Thus, the embodiment of the present application performs a differential analysis of the interfaces and external circuit designs of memory chips with different protocols. On the premise that the processor chip 33 can simultaneously support memory chips with multiple different protocols, this allows compatibility of memory chips with different protocols on the same circuit board 31, thereby improving the flexibility of the storage system.

[0092] It is understood that some target storage chips 32 may include a storage medium and a control module. The storage medium includes multiple storage areas, each of which is used to store business data. The control module is used to control writing data to the storage area or reading data from the storage area.

[0093] The following takes the example where the target storage chip includes a first storage chip or a second storage chip, the first storage chip includes a first UFS storage chip or a second UFS storage chip, and the second storage chip includes an EMMC storage chip to illustrate the specific structure of the circuit board in the embodiment of the present application.

[0094] For example, FIG4 is a schematic diagram of the layout of the pins of the first memory chip or the second memory chip after packaging provided in an embodiment of the present application. Referring to FIG4, the pins 321 in the first memory chip or the second memory chip are arranged in an array, and each row of pins is marked from top to bottom as row A, row B, row C, row D, row E, row F, row G, row H, row J, row K, row L, row M, row N, and row P, and each column of pins is marked from left to right as column 1, column 2, column 3, column 4, column 5, column 6, column 7, column 8, column 9, column 10, column 11, column 12, column 13, and column 14. In addition, the first memory chip or the second memory chip includes 153 pins.

[0095] Each row of the first memory chip or the second memory chip includes a plurality of pins 321, and the number of pins in different rows may be equal or unequal. Each column of the first memory chip or the second memory chip includes a plurality of pins 321, and the number of pins in different columns may be equal or unequal.

[0096] According to the functions of the pins in the first memory chip or the second memory chip, the pins in the first memory chip or the second memory chip can be divided into signal pins, power pins, ground pins and unused (NU) pins, that is, the first memory chip includes signal pins, power pins, ground pins and unused pins, and the second memory chip also includes signal pins, power pins, ground pins and unused pins.

[0097] Taking the first memory chip as an example, the signal pins of the first memory chip include pins for accessing and controlling the first memory chip, the power pins of the first memory chip provide power to the first memory chip, the ground pins of the first memory chip refer to pins that are directly or indirectly connected to ground, and the unused pins of the first memory chip refer to pins of the first memory chip that are generally not externally connected and are left floating. Unused pins include internal redundant (not connect, NC) pins and reserved for furture use (RFU) pins. Unused pins indicate that no components are connected.

[0098] It should be noted that different memory chip manufacturers have different names for the pins of the first memory chip or the second memory chip, and the embodiments of the present application are described based on the actual functions of the pins.

[0099] For example, Figure 5 is a schematic diagram of an exemplary structure of a circuit board provided in an embodiment of the present application. Referring to Figure 5 , a circuit board 31 is used to carry a target memory chip 32 (not shown in Figure 5 ). The target memory chip 32 includes a first memory chip or a second memory chip. The number of pins on the first memory chip is equal to the number of pins on the second memory chip, and the pin arrangement of the first memory chip is the same as the pin arrangement of the second memory chip.

[0100] It should be noted that the pin arrangement of the first memory chip is the same as the pin arrangement of the second memory chip, which specifically means that the number of pins arranged in any direction of the first memory chip and the second memory chip, and the spacing between two adjacent pins arranged in any direction are equal.

[0101] The circuit board 31 includes a first pad group for connecting to the first memory chip or the second memory chip. The first pad group includes multiple first pads, each of which is connected to two traces. At least some of the two traces connected to the first pads include a first jumper region 316, and the traces at the first jumper region 316 are disconnected.

[0102] It should be noted that the first jumper region 316 may be composed of two pads at a certain interval, so that the traces in the first jumper region 316 are not connected.

[0103] When the circuit board 31 is used to carry a first memory chip, the first jumper area 316 included in the first routing line connected to at least part of the first pad is used to mount a jumper component; the first routing line is one of the two routing lines connected to the first pad that corresponds to the first memory chip; when the circuit board 31 is used to carry a second memory chip, the first jumper area 316 included in the second routing line connected to at least part of the first pad is used to mount a jumper component; the second routing line is one of the two routing lines connected to the first pad that corresponds to the second memory chip.

[0104] In this way, by setting each first solder pad on the circuit board 31 to be connected to two traces, when the first memory chip is assembled on the circuit board 31, a jump selection element can be assembled at the first jump selection area 316 included in the first trace of the two traces connected to the first solder pad to achieve selection, and when the second memory chip is assembled on the circuit board 31, a jump selection element can be assembled at the first jump selection area 316 included in the second trace of the two traces connected to the first solder pad to achieve selection, thereby achieving compatibility between the first memory chip and the second memory chip on the same circuit board 31.

[0105] In some embodiments, the pads included in the first pad group are arranged in an array. Furthermore, the pads included in the first pad group correspond one-to-one to the pins included in the first memory chip, and the pads included in the first pad group correspond one-to-one to the pins included in the second memory chip. The corresponding pads and pins are used to electrically connect to achieve signal transmission.

[0106] Specifically, the arrangement array of the pads (including the first pad and the second pad) included in the first pad group is the same as the arrangement array of the pins included in the first memory chip, and the number of pads included in the first pad group is equal to the number of pins included in the first memory chip. Correspondingly, the arrangement array of the pads included in the first pad group is the same as the arrangement array of the pins included in the second memory chip, and the number of pads included in the first pad group is equal to the number of pins included in the second memory chip.

[0107] Since the embodiment of the present application can be compatible with the first memory chip and the second memory chip on the same circuit board 31, for the pads at the same position in the first pad group, the function of the pins when connecting to the first memory chip may be different from the function of the pins when connecting to the second memory chip.

[0108] Therefore, when the first memory chip and the second memory chip are compatible on the circuit board 31 , the specific connection relationship between the pads in the first pad group on the circuit board 31 may be the following sixteen situations.

[0109] In the first case, the pads at the same position on the circuit board 31 are connected to the power pin of the first memory chip when the first memory chip is assembled on the circuit board 31, and are connected to the power pin of the second memory chip when the second memory chip is assembled on the circuit board 31. Such pads can be referred to as first-class pin-shared pads. For example, the first-class pin-shared pads can be pads at the UFS power pin / EMMC power pin shown in FIG5 , which indicate that they are connected to the power pin of the UFS memory chip when the UFS memory chip is assembled on the circuit board 31, and are connected to the power pin of the EMMC memory chip when the EMMC memory chip is assembled on the circuit board 31.

[0110] In the second case, the pad at the same position on the circuit board 31 is connected to the power pin of the first memory chip when the first memory chip is assembled on the circuit board 31, and is connected to the signal pin of the second memory chip when the second memory chip is assembled on the circuit board 31. This pad can be called a second-type pin-shared pad. For example, the second-type pin-shared pad can be the pad at the UFS power pin / EMMC signal pin shown in Figure 5, which indicates that it is connected to the power pin of the UFS memory chip when the UFS memory chip is assembled on the circuit board 31, and is connected to the signal pin of the EMMC memory chip when the EMMC memory chip is assembled on the circuit board 31.

[0111] In the third case, the pad at the same position on the circuit board 31 is connected to the power pin of the first memory chip when the first memory chip is assembled on the circuit board 31, and is connected to the ground pin of the second memory chip when the second memory chip is assembled on the circuit board 31. This pad can be called a third-type pin-shared pad. For example, the third-type pin-shared pad can be the pad at the UFS power pin / EMMC ground pin shown in Figure 5, which indicates that it is connected to the power pin of the UFS memory chip when the UFS memory chip is assembled on the circuit board 31, and is connected to the ground pin of the EMMC memory chip when the EMMC memory chip is assembled on the circuit board 31.

[0112] In the fourth case, the pad at the same position on the circuit board 31 is connected to the signal pin of the first memory chip when the first memory chip is assembled on the circuit board 31, and is connected to the power pin of the second memory chip when the second memory chip is assembled on the circuit board 31. This pad can be called a fourth type of pin-shared pad. Taking the first memory chip as a UFS memory chip and the second memory chip as an EMMC memory chip as an example, there may be no fourth type of pin-shared pad on the circuit board 31. Therefore, the fourth type of pin-shared pad is not shown in Figure 5. Of course, it is understandable that when the first memory chip and / or the second memory chip are other types of memory chips, there may also be a fourth type of pin-shared pad on the circuit board 31.

[0113] In the fifth case, the pad at the same position on the circuit board 31 is connected to the ground pin of the first memory chip when the first memory chip is assembled on the circuit board 31, and is connected to the power pin of the second memory chip when the second memory chip is assembled on the circuit board 31. This pad can be called a fifth type of pin-shared pad. For example, the fifth type of pin-shared pad can be the pad at the UFS ground pin / EMMC power pin shown in Figure 5, which indicates that it is connected to the ground pin of the UFS memory chip when the UFS memory chip is assembled on the circuit board 31, and is connected to the power pin of the EMMC memory chip when the EMMC memory chip is assembled on the circuit board 31.

[0114] In the sixth case, the pads at the same position on the circuit board 31 are connected to the signal pins of the first memory chip when the first memory chip is assembled on the circuit board 31, and are connected to the signal pins of the second memory chip when the second memory chip is assembled on the circuit board 31. Such pads can be referred to as the sixth type of pin-shared pads. Taking the first memory chip as a UFS memory chip and the second memory chip as an EMMC memory chip as an example, there may be no sixth type of pin-shared pads on the circuit board 31. Therefore, the sixth type of pin-shared pads are not shown in FIG5 . Of course, it is understandable that when the first memory chip and / or the second memory chip are other types of memory chips, there may also be sixth type of pin-shared pads on the circuit board 31.

[0115] In the seventh case, the pad at the same position on the circuit board 31 is connected to the ground pin of the first memory chip when the first memory chip is assembled on the circuit board 31, and is connected to the signal pin of the second memory chip when the second memory chip is assembled on the circuit board 31. This pad can be called a seventh type of pin-shared pad. For example, the seventh type of pin-shared pad can be the pad at the UFS ground pin / EMMC signal pin shown in Figure 5, which indicates that it is connected to the ground pin of the UFS memory chip when the UFS memory chip is assembled on the circuit board 31, and is connected to the signal pin of the EMMC memory chip when the EMMC memory chip is assembled on the circuit board 31.

[0116] In the eighth case, the pad at the same position on the circuit board 31 is connected to the signal pin of the first memory chip when the first memory chip is assembled on the circuit board 31, and is connected to the ground pin of the second memory chip when the second memory chip is assembled on the circuit board 31. This pad can be called the eighth type of pin-shared pad. Taking the first memory chip as a UFS memory chip and the second memory chip as an EMMC memory chip as an example, there may be no eighth type of pin-shared pad on the circuit board 31. Therefore, the eighth type of pin-shared pad is not shown in Figure 5. Of course, it is understandable that when the first memory chip and / or the second memory chip are other types of memory chips, there may also be an eighth type of pin-shared pad on the circuit board 31.

[0117] In the ninth case, the pads at the same position on the circuit board 31 are connected to the unused pins of the first memory chip when the first memory chip is assembled on the circuit board 31, and are connected to the power pins of the second memory chip when the second memory chip is assembled on the circuit board 31. Such pads can be referred to as the ninth type of pin-shared pads. For example, the ninth type of pin-shared pads can be the pads at the UFS unused pins / / EMMC power pins shown in FIG5 , which indicate that they are connected to the unused pins of the UFS memory chip when the UFS memory chip is assembled on the circuit board 31, and are connected to the power pins of the EMMC memory chip when the EMMC memory chip is assembled on the circuit board 31.

[0118] In the tenth case, the pad at the same position on the circuit board 31 is connected to the power pin of the first memory chip when the first memory chip is assembled on the circuit board 31, and is connected to the unused pin of the second memory chip when the second memory chip is assembled on the circuit board 31. This pad can be called the tenth type of pin-shared pad. For example, the tenth type of pin-shared pad can be the pad at the UFS power pin / EMMC unused pin shown in Figure 5, which indicates that it is connected to the power pin of the UFS memory chip when the UFS memory chip is assembled on the circuit board 31, and is connected to the unused pin of the EMMC memory chip when the EMMC memory chip is assembled on the circuit board 31.

[0119] In the eleventh case, the pad at the same position on the circuit board 31 is connected to the ground pin of the first memory chip when the first memory chip is assembled on the circuit board 31, and is connected to the unused pin of the second memory chip when the second memory chip is assembled on the circuit board 31. This pad can be called the eleventh type of pin-shared pad. For example, the eleventh type of pin-shared pad can be the pad at the UFS ground pin / EMMC unused pin shown in Figure 5, which indicates that it is connected to the ground pin of the UFS memory chip when the UFS memory chip is assembled on the circuit board 31, and is connected to the unused pin of the EMMC memory chip when the EMMC memory chip is assembled on the circuit board 31.

[0120] In the twelfth case, the pad at the same position on the circuit board 31 is connected to the unused pin of the first memory chip when the first memory chip is assembled on the circuit board 31, and is connected to the ground pin of the second memory chip when the second memory chip is assembled on the circuit board 31. This pad can be called a twelfth-category pin-shared pad. For example, the twelfth-category pin-shared pad can be the pad at the UFS unused pin / EMMC ground pin shown in Figure 5, which indicates that it is connected to the unused pin of the UFS memory chip when the UFS memory chip is assembled on the circuit board 31, and is connected to the ground pin of the EMMC memory chip when the EMMC memory chip is assembled on the circuit board 31.

[0121] In the thirteenth case, the pad at the same position on the circuit board 31 is connected to the signal pin of the first memory chip when the first memory chip is assembled on the circuit board 31, and is connected to the unused pin of the second memory chip when the second memory chip is assembled on the circuit board 31. This pad can be called a thirteenth type of pin-shared pad. For example, the thirteenth type of pin-shared pad can be the pad at the UFS signal pin / EMMC unused pin shown in Figure 5, which indicates that it is connected to the signal pin of the UFS memory chip when the UFS memory chip is assembled on the circuit board 31, and is connected to the unused pin of the EMMC memory chip when the EMMC memory chip is assembled on the circuit board 31.

[0122] In the fourteenth case, the pad at the same position on the circuit board 31 is connected to the unused pin of the first memory chip when the first memory chip is assembled on the circuit board 31, and is connected to the signal pin of the second memory chip when the second memory chip is assembled on the circuit board 31. This pad can be called a fourteenth-category pin-shared pad. For example, the fourteenth-category pin-shared pad can be the pad at the UFS unused pin / EMMC signal pin shown in Figure 5, which indicates that it is connected to the unused pin of the UFS memory chip when the UFS memory chip is assembled on the circuit board 31, and is connected to the signal pin of the EMMC memory chip when the EMMC memory chip is assembled on the circuit board 31.

[0123] In the fifteenth case, the pads at the same position on the circuit board 31 are connected to the unused pins of the first memory chip when the first memory chip is assembled on the circuit board 31, and are connected to the unused pins of the second memory chip when the second memory chip is assembled on the circuit board 31. Such pads can be referred to as the fifteenth type of pin-shared pads. For example, the fifteenth type of pin-shared pads can be the pads at the UFS unused pins / EMMC unused pins shown in FIG5 , which indicate that they are connected to the unused pins of the UFS memory chip when the UFS memory chip is assembled on the circuit board 31, and are connected to the unused pins of the EMMC memory chip when the EMMC memory chip is assembled on the circuit board 31.

[0124] In the sixteenth case, the pad at the same position on the circuit board 31 is connected to the ground pin of the first memory chip when the first memory chip is assembled on the circuit board 31, and is connected to the ground pin of the second memory chip when the second memory chip is assembled on the circuit board 31. This pad can be called a sixteenth-category pin-shared pad. For example, the sixteenth-category pin-shared pad can be the pad at the UFS ground pin / EMMC ground pin shown in FIG5 , which indicates that it is connected to the ground pin of the UFS memory chip when the UFS memory chip is assembled on the circuit board 31, and is connected to the ground pin of the EMMC memory chip when the EMMC memory chip is assembled on the circuit board 31.

[0125] In order to facilitate the distinction between the above sixteen situations, the pads in the first pad group used for connecting to two routing lines can be referred to as first pads, and the pads in the first pad group used for connecting to one routing line can be referred to as second pads. In addition, the first pads in the plurality of first pads used for connecting to the power pins of the first storage chip and / or the power pins of the second storage chip can be referred to as first-type pads 311, and the first pads in the plurality of first pads not used for connecting to the power pins of the first storage chip or the power pins of the second storage chip can be referred to as second-type pads 312. In addition, the second pads in the plurality of second pads used for connecting to the power pins of the first storage chip or the power pins of the second storage chip can be referred to as third-type pads 313, the second pads in the plurality of second pads connected to the ground pins of the first storage chip and the ground pins of the second storage chip can be referred to as fifth-type pads 315, and the remaining second pads in the plurality of second pads can be referred to as fourth-type pads 314.

[0126] Therefore, the plurality of first pads are divided into first-class pads 311 and second-class pads 312; the first-class pads 311 may include the aforementioned first-class pin-shared pads, second-class pin-shared pads, third-class pin-shared pads, fourth-class pin-shared pads, and fifth-class pin-shared pads; the second-class pads 312 include the aforementioned sixth-class pin-shared pads, seventh-class pin-shared pads, and eighth-class pin-shared pads. The plurality of second pads are divided into third-class pads 313, fourth-class pads 314, and fifth-class pads 315; the third-class pads 313 include the aforementioned ninth-class pin-shared pads and tenth-class pin-shared pads; the fourth-class pads 314 include the aforementioned eleventh-class pin-shared pads, twelfth-class pin-shared pads, thirteenth-class pin-shared pads, fourteenth-class pin-shared pads, and fifteenth-class pin-shared pads; and the fifth-class pads 315 include the aforementioned sixteenth-class pin-shared pads.

[0127] For the multiple first pads in the first pad group, the pin to which each first pad is connected when connected to the first storage chip and the pin to which it is connected when connected to the second storage chip both correspond to certain functions. Therefore, the routing of each first pad connection can be designed by jump selection.

[0128] In some embodiments, the plurality of first pads include a first type pad 311, which is used to connect to the power pin of the first memory chip and / or the power pin of the second memory chip, and the first type pad is not used to connect to the unused pin of the first memory chip or the unused pin of the second memory chip.

[0129] Since the first memory chip and the second memory chip both include four types of pins, namely, signal pins, power pins, ground pins and unused pins, the first type of pad 311 is used to connect to the power pin of the first memory chip and the power pin of the second memory chip, or to connect to the power pin of the first memory chip and the signal pin of the second memory chip, or to connect to the power pin of the first memory chip and the ground pin of the second memory chip, or to connect to the signal pin of the first memory chip and the power pin of the second memory chip, or to connect to the ground pin of the first memory chip and the power pin of the second memory chip.

[0130] Furthermore, the circuit board 31 is further configured to carry a first power module. When the first-type solder pads 311 are configured to connect to power pins of a first memory chip, the first power module is configured to connect to the first-type solder pads 311 via a first trace; and / or when the first-type solder pads 311 are configured to connect to power pins of a second memory chip, the first power module is configured to connect to the first-type solder pads 311 via a second trace.

[0131] FIG6 is a schematic diagram of a connection relationship between the first type of pin-shared pad and the first and second traces provided in an embodiment of the present application, and FIG7 is a schematic diagram of another connection relationship between the first type of pin-shared pad and the first and second traces provided in an embodiment of the present application. Referring to FIG6 and FIG7, for the first type of pin-shared pad 3111 in the first type of pad 311, it can be a pad at the UFS power pin / EMMC power pin, that is, the first type of pin-shared pad 3111 is used to connect to the power pin of the first memory chip and the power pin of the second memory chip. The first type of pin-shared pad 3111 is connected to two traces, and the two traces connected to the first type of pin-shared pad 3111 are respectively the first trace 41 corresponding to the UFS memory chip and the second trace 42 corresponding to the EMMC memory chip. The first power module 341 may include a first power supply unit and a second power supply unit, the first power supply unit is connected to the first type of pin-shared pad 3111 through the first trace 41, and the second power supply unit is connected to the first type of pin-shared pad 3111 through the second trace 42. In addition, the first power supply unit in the first power supply module 341 is connected to one power supply pin of the processor chip 33 , and the second power supply unit in the first power supply module 341 is also connected to another power supply pin of the processor chip 33 .

[0132] In one embodiment, as shown in FIG. 6 , the first trace 41 and the second trace 42 connected to the first-type pin-shared pad 3111 both include a first jumper region 316 .

[0133] When a first memory chip is mounted on the circuit board 31, a jumper element is installed at the first jumper region 316 of the first trace 41 connected to the first pin-shared pad 3111, so that the first trace 41 connected to the first pin-shared pad 3111 is conductive. In this way, the power pin corresponding to the first memory chip in the processor chip 33 outputs a corresponding voltage to the first power module 341. After the first power supply unit in the first power module 341 converts this voltage into the voltage required for operation of the first memory chip, the converted voltage can be transmitted to the power pin of the first memory chip via the first trace 41 and the first pin-shared pad 3111. Furthermore, no jumper element is installed at the first jumper region 316 of the second trace 42 connected to the first pin-shared pad 3111, so that the second trace 42 connected to the first pin-shared pad 3111 is disconnected.

[0134] For example, the voltage output by the power pin corresponding to the first storage chip in the processor chip 33 may be 3.0V, and the voltage required for the first storage chip to operate may be 2.5V. The first power supply unit in the first power supply module 341 may convert the 3.0V voltage into 2.5V, and transmit it to the power pin of the first storage chip through the first trace 41 and the first type pin shared pad 3111.

[0135] Accordingly, when a second memory chip is mounted on the circuit board 31, a jumper element is installed at the first jumper region 316 included in the second trace 42 connected to the first-class pin-shared pad 3111, so that the second trace 42 connected to the first-class pin-shared pad 3111 is conductive. In this way, the power pin corresponding to the second memory chip in the processor chip 33 outputs a corresponding voltage to the first power module 341. After the second power supply unit in the first power module 341 converts this voltage into the voltage required for operation of the second memory chip, the converted voltage can be transmitted to the power pin of the second memory chip via the second trace 42 and the first-class pin-shared pad 3111. Furthermore, no jumper element is installed at the first jumper region 316 included in the first trace 41 connected to the first-class pin-shared pad 3111, so that the first trace 41 connected to the first-class pin-shared pad 3111 is disconnected.

[0136] Taking the case where the first storage chip is a first UFS storage chip and the second storage chip is an EMMC storage chip as an example, the pin at position F5 in the first UFS storage chip is a VCCQ pin (i.e., a power pin), and the pin at position F5 in the EMMC storage chip is a VCC pin (i.e., a power pin), therefore, the first type of pin-shared pad 3111 includes a first pad connected to the pins at position F5 in the first UFS storage chip and the EMMC storage chip. In this way, when the first UFS storage chip is assembled on the circuit board 31, the first-class pin-shared pad 3111 is connected to the pin located at the F5 position in the first UFS storage chip, and a resistor, a diode, or a transistor and other jump elements are assembled at the first jump area 316 included in the first routing line 41 connected to the first-class pin-shared pad 3111; when the EMMC storage chip is assembled on the circuit board 31, the first-class pin-shared pad 3111 is connected to the pin located at the F5 position in the EMMC storage chip, and a resistor, a diode, or a transistor and other jump elements are assembled at the first jump area 316 included in the second routing line 42 connected to the first-class pin-shared pad 3111.

[0137] It should be understood that the pin located at the F5 position in the first UFS storage chip represents the pin located at the 5th column and row F in the first UFS storage chip, and the pin located at the F5 position in the EMMC storage chip represents the pin located at the 5th column and row F in the EMMC storage chip. The following description of the pin position can refer to the F5 position.

[0138] Taking the case where the first storage chip is a second UFS storage chip and the second storage chip is an EMMC storage chip as an example, the pin at position C6 in the second UFS storage chip is a VCCQ2 pin (i.e., a power pin), and the pin at position C6 in the EMMC storage chip is a VCCQ pin (i.e., a power pin). Therefore, the first type of pin-shared pad 3111 includes the first pad connected to the pin at position C6 in the second UFS storage chip and the EMMC storage chip. In this way, when the second UFS storage chip is assembled on the circuit board 31, the first-class pin-shared pad 3111 is connected to the pin located at the C6 position in the second UFS storage chip, and a resistor, a diode, or a transistor and other jump elements are assembled at the first jump area 316 included in the first routing line 41 connected to the first-class pin-shared pad 3111; when the EMMC storage chip is assembled on the circuit board 31, the first-class pin-shared pad 3111 is connected to the pin located at the C6 position in the EMMC storage chip, and a resistor, a diode, or a transistor and other jump elements are assembled at the first jump area 316 included in the second routing line 42 connected to the first-class pin-shared pad 3111.

[0139] In another embodiment, as shown in FIG. 7 , the first trace 41 and the second trace 42 connected to the first-type pin-shared pad 3111 do not include the first jumper region 316 .

[0140] When the first memory chip is mounted on the circuit board 31, the first power supply unit in the first power supply module 341 powers the first trace 41 connected to the first-class pin-shared pad 3111. That is, the first power supply unit converts the voltage provided by the processor chip 33 into the voltage required for the operation of the first memory chip, and outputs it to the first trace 41 connected to the first-class pin-shared pad 3111. This allows the voltage converted by the first power supply unit to be transmitted to the power pin of the first memory chip via the first trace 41 and the first-class pin-shared pad 3111. Furthermore, the second power supply unit in the first power supply module 341 does not power the second trace 42 connected to the first-class pin-shared pad 3111. That is, the second power supply unit does not convert the voltage provided by the processor chip 33 into the voltage required for the operation of the second memory chip, nor does it output the voltage required for the operation of the second memory chip to the second trace 42 connected to the first-class pin-shared pad 3111.

[0141] Accordingly, when a second memory chip is mounted on the circuit board 31, the second power supply unit in the first power supply module 341 powers the second trace 42 connected to the first-class pin-shared pad 3111. Specifically, the second power supply unit converts the voltage provided by the processor chip 33 into the voltage required for the operation of the second memory chip and outputs it to the second trace 42 connected to the first-class pin-shared pad 3111. This allows the converted voltage from the second power supply unit to be transmitted to the power pin of the second memory chip via the second trace 42 and the first-class pin-shared pad 3111. Furthermore, the first power supply unit in the first power supply module 341 does not power the first trace 41 connected to the first-class pin-shared pad 3111. Specifically, the first power supply unit does not convert the voltage provided by the processor chip 33 into the voltage required for the operation of the first memory chip, nor does it output the voltage required for the operation of the first memory chip to the first trace 41 connected to the first-class pin-shared pad 3111.

[0142] Therefore, for the first-type pin-shared pads 3111 in the first-type pads 311 shown in FIG7 , the first traces 41 and the second traces 42 connected to the first power module 341 do not include the first jumper region 316. When the circuit board 31 is used to carry a first memory chip and the first-type pads 311 are used to connect to the power pins of the first memory chip, the first power module 341 is used to power the first traces 41 connected to the first-type pads 311, and the first power module 341 is used to not power the second traces 42 connected to the first-type pads 311. Furthermore, when the circuit board 31 is used to carry a second memory chip and the first-type pads 311 are used to connect to the power pins of the second memory chip, the first power module 341 is used to power the second traces 42 connected to the first-type pads 311, and the first power module 341 is used to not power the first traces 41 connected to the first-type pads 311.

[0143] FIG8 is a schematic diagram of a connection relationship between the second type of pin-sharing pad and the first and second lines provided in an embodiment of the present application; FIG9 is a schematic diagram of another connection relationship between the second type of pin-sharing pad and the first and second lines provided in an embodiment of the present application. Referring to FIG8 and FIG9 , for the second type of pin-sharing pad 3112 in the first type of pad 311, it can be a pad at the UFS power pin / EMMC signal pin, that is, the second type of pin-sharing pad 3112 is used to connect to the power pin of the first memory chip and the signal pin of the second memory chip. The second type of pin-sharing pad 3112 is connected to two lines, and the two lines connected to the second type of pin-sharing pad 3112 are respectively the first line 41 corresponding to the UFS memory chip and the second line 42 corresponding to the EMMC memory chip. The first power module 341 may further include a third power supply unit, and the third power supply unit is connected to the second type of pin-sharing pad 3112 through the first line 41. In addition, the third power supply unit in the first power supply module 341 is also connected to a power pin of the processor chip 33 , and a signal pin of the processor chip 33 is also connected to the second-category pin-shared pad 3112 through the second trace 42 .

[0144] In one embodiment, as shown in FIG. 8 , the first trace 41 and the second trace 42 connected to the second-type pin-shared pad 3112 both include a first jumper region 316 .

[0145] When the first memory chip is mounted on the circuit board 31, a jumper element is installed at the first jumper region 316 of the first trace 41 connected to the second pin-shared pad 3112, so that the first trace 41 connected to the second pin-shared pad 3112 is conductive. In this way, the power pin in the processor chip 33 outputs a corresponding voltage to the first power module 341. After the third power supply unit in the first power module 341 converts this voltage into the voltage required for operation of the first memory chip, the converted voltage is transmitted to the power pin of the first memory chip via the first trace 41 and the second pin-shared pad 3112. Furthermore, no jumper element is installed at the first jumper region 316 of the second trace 42 connected to the second pin-shared pad 3112, so that the second trace 42 connected to the second pin-shared pad 3112 is disconnected.

[0146] Accordingly, when a second memory chip is mounted on the circuit board 31, a jumper element is installed at the first jumper region 316 of the second trace 42 connected to the second-type pin-shared pad 3112, so that the second trace 42 connected to the second-type pin-shared pad 3112 is conductive. In this way, the signal output by the signal pin of the processor chip 33 can be transmitted to the signal pin of the second memory chip via the second trace 42 and the second-type pin-shared pad 3112. Furthermore, no jumper element is installed at the first jumper region 316 of the first trace 41 connected to the second-type pin-shared pad 3112, so that the first trace 41 connected to the second-type pin-shared pad 3112 is disconnected.

[0147] Take the first storage chip as a first UFS storage chip and the second storage chip as an EMMC storage chip as an example. The pins at positions A4, A5, B4, and B5 in the first UFS storage chip are VCCQ pins (i.e., power pins), and the pin at position A4 in the EMMC storage chip is a DAT1 pin (i.e., a signal pin), the pin at position A5 in the EMMC storage chip is a DAT2 pin (i.e., a signal pin), the pin at position B4 in the EMMC storage chip is a DAT5 pin (i.e., a signal pin), and the pin at position B5 in the EMMC storage chip is a DAT6 pin (i.e., a signal pin). Therefore, the second type of pin-shared pad 3112 may include: a first pad connected to the pins at positions A4, A5, B4, and B5 in the first UFS storage chip and the EMMC storage chip.

[0148] In this way, when the first UFS storage chip is assembled on the circuit board 31, the multiple first pads included in the second-type pin-shared pad 3112 are respectively connected to the pins located at the A4 position, A5 position, B4 position and B5 position in the first UFS storage chip, and a resistor, a diode or a transistor and other jump elements are assembled at the first jump area 316 included in the first routing line 41 connected to the second-type pin-shared pad 3112; when the EMMC storage chip is assembled on the circuit board 31, the multiple first pads included in the second-type pin-shared pad 3112 are respectively connected to the pins located at the A4 position, A5 position, B4 position and B5 position in the EMMC storage chip, and a resistor, a diode or a transistor and other jump elements are assembled at the first jump area 316 included in the second routing line 42 connected to the second-type pin-shared pad 3112.

[0149] Take the case where the first memory chip is a second UFS memory chip and the second memory chip is an EMMC memory chip as an example. The pin at position B6 in the second UFS memory chip is the VCCQ2 pin (i.e., the power pin), and the pin at position B6 in the EMMC memory chip is the DAT7 pin (i.e., the signal pin). Therefore, the second type of pin-shared pad 3112 includes the first pad connected to the pin at position B6 in the second UFS memory chip and the EMMC memory chip.

[0150] In this way, when the second UFS storage chip is assembled on the circuit board 31, the second-class pin-shared pad 3112 is connected to the pin located at the B6 position in the second UFS storage chip, and a resistor, a diode, or a transistor and other jump elements are assembled at the first jump area 316 included in the first routing line 41 connected to the second-class pin-shared pad 3112; when the EMMC storage chip is assembled on the circuit board 31, the second-class pin-shared pad 3112 is connected to the pin located at the B6 position in the EMMC storage chip, and a resistor, a diode, or a transistor and other jump elements are assembled at the first jump area 316 included in the second routing line 42 connected to the second-class pin-shared pad 3112.

[0151] In another embodiment, as shown in FIG. 9 , the first trace 41 connected to the second-type pin-shared pad 3112 does not include the first jumper region 316 , and the second trace 42 connected to the second-type pin-shared pad 3112 includes the first jumper region 316 .

[0152] When the first memory chip is mounted on the circuit board 31, the third power supply unit in the first power supply module 341 powers the first trace 41 connected to the second pin-shared pad 3112. Specifically, the third power supply unit converts the voltage provided by the processor chip 33 into the voltage required for operation of the first memory chip and outputs it to the first trace 41 connected to the second pin-shared pad 3112. This voltage, after conversion by the third power supply unit, is transmitted to the power pins of the first memory chip via the first trace 41 and the second pin-shared pad 3112. Furthermore, no jumper element is mounted on the first jumper region 316 of the second trace 42 connected to the second pin-shared pad 3112, thereby disconnecting the second trace 42 connected to the second pin-shared pad 3112.

[0153] Accordingly, when a second memory chip is mounted on the circuit board 31, a jumper element is mounted at the first jumper region 316 included in the second trace 42 connected to the second-type pin-shared pad 3112, so that the second trace 42 connected to the second-type pin-shared pad 3112 is conductive. Then, the signal output by the signal pin of the processor chip 33 can be transmitted to the signal pin of the second memory chip via the second trace 42 and the second-type pin-shared pad 3112. Furthermore, the third power supply unit in the first power supply module 341 does not power the first trace 41 connected to the second-type pin-shared pad 3112. In other words, the third power supply unit does not convert the voltage provided by the processor chip 33 into the voltage required for the operation of the first memory chip, nor does it output the voltage required for the operation of the first memory chip to the first trace 41 connected to the second-type pin-shared pad 3112.

[0154] Figure 10 is a schematic diagram of a connection relationship between the third type of pin-sharing pad provided in an embodiment of the present application and the first and second lines, and Figure 11 is a schematic diagram of another connection relationship between the third type of pin-sharing pad provided in an embodiment of the present application and the first and second lines. Referring to Figures 10 and 11, for the third type of pin-sharing pad 3113 in the first type of pad 311, it can be a pad at the UFS power pin / EMMC ground pin, that is, the third type of pin-sharing pad 3113 is used to connect to the power pin of the first memory chip and the ground pin of the second memory chip. The third type of pin-sharing pad 3113 is connected to two lines, and the two lines connected to the third type of pin-sharing pad 3113 are respectively the first line 41 corresponding to the UFS memory chip and the second line 42 corresponding to the EMMC memory chip. The first power module 341 may also include a fourth power supply unit, and the fourth power supply unit is connected to the third type of pin-sharing pad 3113 through the first line 41. In addition, the fourth power supply unit in the first power supply module 341 is also connected to a power pin of the processor chip 33 , and the second trace 42 connected to the third type pin common pad 3113 is also connected to the ground terminal GND in the circuit board 31 .

[0155] In one embodiment, as shown in FIG. 10 , the first trace 41 and the second trace 42 connected to the third-type pin-shared pad 3113 both include a first jumper region 316 .

[0156] When the first memory chip is mounted on the circuit board 31, a jumper component is installed at the first jumper region 316 of the first trace 41 connected to the third-type pin-shared pad 3113, so that the first trace 41 connected to the third-type pin-shared pad 3113 is conductive. In this way, the power pin in the processor chip 33 outputs a corresponding voltage to the first power module 341. After the fourth power supply unit in the first power module 341 converts this voltage into the voltage required for operation of the first memory chip, the converted voltage can be transmitted to the power pin of the first memory chip via the first trace 41 and the third-type pin-shared pad 3113. Furthermore, no jumper component is installed at the first jumper region 316 of the second trace 42 connected to the third-type pin-shared pad 3113, so that the second trace 42 connected to the third-type pin-shared pad 3113 is disconnected.

[0157] Accordingly, when a second memory chip is mounted on the circuit board 31, a jumper component is mounted at the first jumper region 316 of the second trace 42 connected to the third-type pin-shared pad 3113, thereby conducting the second trace 42 connected to the third-type pin-shared pad 3113. This allows the ground pin of the second memory chip to be electrically connected to the ground terminal GND via the third-type pin-shared pad 3113 and the second trace 42. Furthermore, no jumper component is mounted at the first jumper region 316 of the first trace 41 connected to the third-type pin-shared pad 3113, thereby disconnecting the first trace 41 connected to the third-type pin-shared pad 3113.

[0158] Take the case where the first storage chip is a first UFS storage chip and the second storage chip is an EMMC storage chip as an example. The pin at position C4 in the first UFS storage chip is a VCCQ pin (i.e., a power pin), the pin at position K8 in the first UFS storage chip is a VCC pin (i.e., a power pin), and the pins at positions C4 and K8 in the EMMC storage chip are both VSS pins (i.e., ground pins). Therefore, the third type of pin-shared pad 3113 may include a first pad connected to the pins at positions C4 and K8 in the first UFS storage chip and the EMMC storage chip.

[0159] In this way, when the first UFS storage chip is assembled on the circuit board 31, the multiple first pads included in the third-type pin-shared pad 3113 are respectively connected to the pins located at the C4 position and the K8 position in the first UFS storage chip, and the first jump selection area 316 included in the first routing line 41 connected to the third-type pin-shared pad 3113 is assembled with resistors, diodes or transistors and other jump selection elements; when the EMMC storage chip is assembled on the circuit board 31, the multiple first pads included in the third-type pin-shared pad 3113 are respectively connected to the pins located at the C4 position and the K8 position in the EMMC storage chip, and the first jump selection area 316 included in the second routing line 42 connected to the third-type pin-shared pad 3113 is assembled with resistors, diodes or transistors and other jump selection elements.

[0160] Take the case where the first memory chip is a second UFS memory chip and the second memory chip is an EMMC memory chip as an example. The pin at position A6 in the second UFS memory chip is a VCCQ2 pin (i.e., a power pin), the pin at position K8 in the second UFS memory chip is a VCC pin (i.e., a power pin), and the pins at positions A6 and K8 in the EMMC memory chip are both VSS pins (i.e., ground pins). Therefore, the third type of pin-shared pad 3113 may include a first pad connected to the pins at positions A6 and K8 in the second UFS memory chip and the EMMC memory chip.

[0161] In this way, when the second UFS storage chip is assembled on the circuit board 31, the multiple first pads included in the third-type pin-shared pad 3113 are respectively connected to the pins located at the A6 position and the K8 position in the second UFS storage chip, and the first jump selection area 316 included in the first routing line 41 connected to the third-type pin-shared pad 3113 is assembled with resistors, diodes or transistors and other jump selection elements; when the EMMC storage chip is assembled on the circuit board 31, the multiple first pads included in the third-type pin-shared pad 3113 are respectively connected to the pins located at the A6 position and the K8 position in the EMMC storage chip, and the first jump selection area 316 included in the second routing line 42 connected to the third-type pin-shared pad 3113 is assembled with resistors, diodes or transistors and other jump selection elements.

[0162] In another embodiment, as shown in FIG. 11 , the first trace 41 connected to the third-type pin-shared pad 3113 does not include the first jumper region 316 , and the second trace 42 connected to the third-type pin-shared pad 3113 includes the first jumper region 316 .

[0163] When the first memory chip is mounted on the circuit board 31, the fourth power supply unit in the first power supply module 341 powers the first trace 41 connected to the third-type pin-shared pad 3113. Specifically, the fourth power supply unit converts the voltage provided by the processor chip 33 into the voltage required for operation of the first memory chip and outputs it to the first trace 41 connected to the third-type pin-shared pad 3113. This allows the voltage converted by the fourth power supply unit to be transmitted to the power pins of the first memory chip via the first trace 41 and the third-type pin-shared pad 3113. Furthermore, no jumper element is mounted at the first jumper region 316 of the second trace 42 connected to the third-type pin-shared pad 3113, thereby disconnecting the second trace 42 connected to the third-type pin-shared pad 3113.

[0164] Accordingly, when a second memory chip is mounted on the circuit board 31, a jumper element is mounted at the first jumper region 316 included in the second trace 42 connected to the third-type pin-shared pad 3113, so that the second trace 42 connected to the third-type pin-shared pad 3113 is conductive. Thus, the ground pin of the second memory chip can be electrically connected to the ground terminal GND via the third-type pin-shared pad 3113 and the second trace 42. Furthermore, the fourth power supply unit in the first power supply module 341 does not power the first trace 41 connected to the third-type pin-shared pad 3113. In other words, the fourth power supply unit does not convert the voltage provided by the processor chip 33 into the voltage required for the operation of the first memory chip, nor does it output the voltage required for the operation of the first memory chip to the first trace 41 connected to the third-type pin-shared pad 3113.

[0165] Therefore, in conjunction with Figures 9 and 11 , it can be seen that the first trace 41 connected to the first power module 341 does not include the first jumper region 316, while the second trace 42 not connected to the first power module 341 does include the first jumper region 316. When the circuit board 31 is used to carry a first memory chip and the first-type pads 311 are used to connect to the power pins of the first memory chip, the first power module 341 is used to power the first trace 41 connected to the first-type pads 311, and the first jumper region 316 included in the second trace 42 connected to the first-type pads 311 is not used to mount a jumper component. Furthermore, when the circuit board 31 is used to carry a second memory chip and the first-type pads 311 are used to connect to the signal pins or ground pins of the second memory chip, the first jumper region 316 included in the second trace 42 connected to the first-type pads 311 is used to mount a jumper component, and the first power module 341 is used to not power the first trace 41 connected to the first-type pads 311.

[0166] FIG12 is a schematic diagram of a connection relationship between the fourth type of pin-sharing pad and the first and second lines provided in an embodiment of the present application, and FIG13 is a schematic diagram of another connection relationship between the fourth type of pin-sharing pad and the first and second lines provided in an embodiment of the present application. Referring to FIG12 and FIG13 , for the fourth type of pin-sharing pad 3114 in the first type of pad 311, it can be a pad at the UFS signal pin / EMMC power pin, that is, the fourth type of pin-sharing pad 3114 is used to connect to the signal pin of the first memory chip and the power pin of the second memory chip. The fourth type of pin-sharing pad 3114 is connected to two lines, and the two lines connected to the fourth type of pin-sharing pad 3114 are respectively the first line 41 corresponding to the UFS memory chip and the second line 42 corresponding to the EMMC memory chip. The first power supply module 341 also includes a fifth power supply unit, and the fifth power supply unit is connected to the fourth type of pin-sharing pad 3114 through the second line 42. In addition, the fifth power supply unit in the first power supply module 341 is also connected to a power pin of the processor chip 33 , and a signal pin of the processor chip 33 is also connected to the fourth-category pin-shared pad 3114 through the first trace 41 .

[0167] In one embodiment, as shown in FIG. 12 , the first trace 41 and the second trace 42 connected to the fourth-category pin-shared pad 3114 both include a first jumper region 316 .

[0168] When the first memory chip is mounted on the circuit board 31, a jump element such as a resistor, diode, or transistor is installed at the first jump region 316 of the first trace 41 connected to the fourth-category pin-shared pad 3114, so that the first trace 41 connected to the fourth-category pin-shared pad 3114 is conductive. In this way, the signal output by the signal pin of the processor chip 33 can be transmitted to the signal pin of the second memory chip via the first trace 41 and the fourth-category pin-shared pad 3114. Furthermore, no jump element is installed at the first jump region 316 of the second trace 42 connected to the fourth-category pin-shared pad 3114, so that the second trace 42 connected to the fourth-category pin-shared pad 3114 is disconnected.

[0169] Accordingly, when a second memory chip is mounted on the circuit board 31, a jump element such as a resistor, diode, or transistor is mounted at the first jump region 316 of the second trace 42 connected to the fourth-type pin-shared pad 3114, thereby conducting the second trace 42 connected to the fourth-type pin-shared pad 3114. This allows the power pin in the processor chip 33 to output a corresponding voltage to the first power module 341. After the fifth power supply unit in the first power module 341 converts this voltage into the voltage required for operation of the second memory chip, the converted voltage can be transmitted to the power pin of the second memory chip via the second trace 42 and the fourth-type pin-shared pad 3114. Furthermore, no jump element is mounted at the first jump region 316 of the first trace 41 connected to the fourth-type pin-shared pad 3114, thereby disconnecting the first trace 41 connected to the fourth-type pin-shared pad 3114.

[0170] Taking the case where the first storage chip is a first UFS storage chip and the second storage chip is an EMMC storage chip as an example, there is no pin at the same position in the first UFS storage chip and the EMMC storage chip that is connected to the fourth type of pin shared pad 3114, that is, the fourth type of pin shared pad 3114 may not exist on the circuit board 31. Alternatively, taking the case where the first storage chip is a second UFS storage chip and the second storage chip is an EMMC storage chip as an example, there is no pin at the same position in the second UFS storage chip and the EMMC storage chip that is connected to the fourth type of pin shared pad 3114.

[0171] In another embodiment, as shown in FIG. 13 , the first trace 41 connected to the fourth type pin-shared pad 3114 includes the first jumper region 316 , and the second trace 42 connected to the fourth type pin-shared pad 3114 does not include the first jumper region 316 .

[0172] When the first memory chip is mounted on the circuit board 31, a jumper element is installed at the first jumper region 316 of the first trace 41 connected to the fourth-category pin-shared pad 3114, so that the first trace 41 connected to the fourth-category pin-shared pad 3114 is conductive. The signal output by the signal pin of the processor chip 33 can then be transmitted to the signal pin of the first memory chip via the first trace 41 and the fourth-category pin-shared pad 3114. Furthermore, the fifth power supply unit in the first power supply module 341 does not power the second trace 42 connected to the fourth-category pin-shared pad 3114. In other words, the fifth power supply unit does not convert the voltage provided by the processor chip 33 into the voltage required for the operation of the second memory chip, nor does it output the voltage required for the operation of the second memory chip to the second trace 42 connected to the fourth-category pin-shared pad 3114.

[0173] Accordingly, when a second memory chip is mounted on the circuit board 31, the fifth power supply unit in the first power supply module 341 powers the second trace 42 connected to the fourth-category pin-shared pad 3114. Specifically, the fifth power supply unit converts the voltage provided by the processor chip 33 into the voltage required for operation of the second memory chip and outputs it to the second trace 42 connected to the fourth-category pin-shared pad 3114. This allows the converted voltage from the fifth power supply unit to be transmitted to the power pin of the second memory chip via the second trace 42 and the fourth-category pin-shared pad 3114. Furthermore, no jumper element is mounted at the first jumper region 316 of the first trace 41 connected to the fourth-category pin-shared pad 3114, thereby disconnecting the first trace 41 connected to the fourth-category pin-shared pad 3114.

[0174] FIG14 is a schematic diagram of a connection relationship between the fifth type of pin-sharing pad and the first and second lines provided in an embodiment of the present application, and FIG15 is a schematic diagram of another connection relationship between the fifth type of pin-sharing pad and the first and second lines provided in an embodiment of the present application. Referring to FIG14 and FIG15 , for the fifth type of pin-sharing pad 3115 in the first type of pad 311, it can be a pad at the UFS ground pin / EMMC power pin, that is, the fifth type of pin-sharing pad 3115 is used to connect to the ground pin of the first storage chip and the power pin of the second storage chip. The fifth type of pin-sharing pad 3115 is connected to two lines, and the two lines connected to the fifth type of pin-sharing pad 3115 are respectively the first line 41 corresponding to the UFS storage chip and the second line 42 corresponding to the EMMC storage chip. The first power supply module 341 may also include a sixth power supply unit, and the sixth power supply unit is connected to the fifth type of pin-sharing pad 3115 through the second line 42. In addition, the sixth power supply unit in the first power supply module 341 is also connected to a power pin of the processor chip 33 , and the first trace 41 connected to the fifth type pin common pad 3115 is also connected to the ground terminal GND in the circuit board 31 .

[0175] In one embodiment, as shown in FIG. 14 , the first trace 41 and the second trace 42 connected to the fifth type pin shared pad 3115 both include a first jumper region 316 .

[0176] When the first memory chip is mounted on the circuit board 31, a jumper component is installed at the first jumper region 316 of the first trace 41 connected to the fifth-category pin-shared pad 3115, so that the first trace 41 connected to the fifth-category pin-shared pad 3115 is conductive. In this way, the ground pin of the first memory chip can be electrically connected to the ground terminal GND via the fifth-category pin-shared pad 3115 and the first trace 41. Furthermore, no jumper component is installed at the first jumper region 316 of the second trace 42 connected to the fifth-category pin-shared pad 3115, so that the second trace 42 connected to the fifth-category pin-shared pad 3115 is disconnected.

[0177] Accordingly, when a second memory chip is mounted on the circuit board 31, a jumper element is installed at the first jumper region 316 of the second trace 42 connected to the fifth pin-shared pad 3115, thereby conducting the second trace 42 connected to the fifth pin-shared pad 3115. This allows the power pins in the processor chip 33 to output a corresponding voltage to the first power module 341. After the sixth power supply unit in the first power module 341 converts this voltage into the voltage required for operation of the second memory chip, the converted voltage can be transmitted to the power pins of the second memory chip via the second trace 42 and the fifth pin-shared pad 3115. Furthermore, no jumper element is installed at the first jumper region 316 of the first trace 41 connected to the fifth pin-shared pad 3115, thereby disconnecting the first trace 41 connected to the fifth pin-shared pad 3115.

[0178] Take the first memory chip as a first UFS memory chip and the second memory chip as an EMMC memory chip as an example. The pins at the M4 position, N4 position, and P5 position in the first UFS memory chip are all VSS pins (i.e., ground pins), and the pins at the M4 position, N4 position, and P5 position in the EMMC memory chip are all VCCQ pins (i.e., power pins). Therefore, the fifth type of pin-shared pad 3115 may include the first pad connected to the pins at the M4 position, N4 position, and P5 position in the first UFS memory chip and the EMMC memory chip.

[0179] In this way, when the first UFS storage chip is assembled on the circuit board 31, the multiple first pads included in the fifth type of pin-shared pad 3115 are respectively connected to the pins located at the M4 position, the N4 position and the P5 position in the first UFS storage chip, and the first jump selection area 316 included in the first routing line 41 connected to the fifth type of pin-shared pad 3115 is assembled with resistors, diodes or transistors and other jump selection elements; when the EMMC storage chip is assembled on the circuit board 31, the multiple first pads included in the fifth type of pin-shared pad 3115 are respectively connected to the pins located at the M4 position, the N4 position and the P5 position in the EMMC storage chip, and the first jump selection area 316 included in the second routing line 42 connected to the fifth type of pin-shared pad 3115 is assembled with resistors, diodes or transistors and other jump selection elements.

[0180] Take the case where the first memory chip is a second UFS memory chip and the second memory chip is an EMMC memory chip as an example. The pins at the M4 position, N4 position, and P5 position in the second UFS memory chip are all VSS pins (i.e., ground pins), and the pins at the M4 position, N4 position, and P5 position in the EMMC memory chip are all VCCQ pins (i.e., power pins). Therefore, the fifth type of pin-shared pad 3115 may include a first pad connected to the pins at the M4 position, N4 position, and P5 position in the second UFS memory chip and the EMMC memory chip.

[0181] In this way, when the second UFS storage chip is assembled on the circuit board 31, the multiple first pads included in the fifth type of pin-shared pad 3115 are respectively connected to the pins located at the M4 position, N4 position and P5 position in the second UFS storage chip, and the first jump selection area 316 included in the first routing line 41 connected to the fifth type of pin-shared pad 3115 is assembled with resistors, diodes or transistors and other jump selection elements; when the EMMC storage chip is assembled on the circuit board 31, the multiple first pads included in the fifth type of pin-shared pad 3115 are respectively connected to the pins located at the M4 position, N4 position and P5 position in the EMMC storage chip, and the first jump selection area 316 included in the second routing line 42 connected to the fifth type of pin-shared pad 3115 is assembled with resistors, diodes or transistors and other jump selection elements.

[0182] In another embodiment, as shown in FIG. 15 , the first trace 41 connected to the fifth type pin-shared pad 3115 includes a first jumper region 316 , and the second trace 42 connected to the fifth type pin-shared pad 3115 does not include the first jumper region 316 .

[0183] When the first memory chip is mounted on the circuit board 31, a jumper element is mounted at the first jumper region 316 of the first trace 41 connected to the fifth-category pin-shared pad 3115, thereby conducting the first trace 41 connected to the fifth-category pin-shared pad 3115. This allows the ground pin of the first memory chip to be electrically connected to the ground terminal GND via the fifth-category pin-shared pad 3115 and the first trace 41. Furthermore, the sixth power supply unit in the first power module 341 does not power the second trace 42 connected to the fifth-category pin-shared pad 3115. Specifically, the sixth power supply unit does not convert the voltage provided by the processor chip 33 into the voltage required for the operation of the second memory chip, nor does it output the voltage required for the operation of the second memory chip to the second trace 42 connected to the fifth-category pin-shared pad 3115.

[0184] Accordingly, when a second memory chip is mounted on the circuit board 31, the sixth power supply unit in the first power supply module 341 powers the second trace 42 connected to the fifth-category pin-shared pad 3115. Specifically, the sixth power supply unit converts the voltage provided by the processor chip 33 into the voltage required for operation of the second memory chip and outputs it to the second trace 42 connected to the fifth-category pin-shared pad 3115. This allows the converted voltage from the sixth power supply unit to be transmitted sequentially through the second trace 42 and the fifth-category pin-shared pad 3115 to the power pins of the second memory chip. Furthermore, no jumper element is mounted at the first jumper region 316 of the first trace 41 connected to the fifth-category pin-shared pad 3115, thereby disconnecting the first trace 41 connected to the fifth-category pin-shared pad 3115.

[0185] Therefore, in conjunction with Figures 13 and 15 , it can be seen that the second trace 42 connected to the first power module 341 does not include the first jumper region 316, while the first trace 41 not connected to the first power module 341 does include the first jumper region 316. When the circuit board 31 is used to carry a first memory chip and the first-type pads 311 are used to connect to signal pins or ground pins of the first memory chip, the first jumper region 316 included in the first trace 41 connected to the first-type pads 311 is used to mount a jumper component, and the first power module 341 is used to not power the second trace 42 connected to the first-type pads 311. Furthermore, when the circuit board 31 is used to carry a second memory chip and the first-type pads 311 are used to connect to power pins of the second memory chip, the first power module 341 is used to power the second trace 42 connected to the first-type pads 311, and the first jumper region 316 included in the first trace 41 connected to the first-type pads 311 is not used to mount a jumper component.

[0186] In summary, in conjunction with Figures 6, 8, 10, 12, and 14, the first trace 41 and the second trace 42 connected to the first-type pad 311 both include a first jumper region 316. When the circuit board 31 is used to carry a first memory chip, the first jumper region 316 included in the first trace 41 connected to the first-type pad 311 is used to mount a jumper component, and the first jumper region 316 included in the second trace 42 connected to the first-type pad 311 is not used to mount a jumper component. When the circuit board 31 is used to carry a second memory chip, the first jumper region 316 included in the second trace 42 connected to the first-type pad 311 is used to mount a jumper component, and the first jumper region 316 included in the first trace 41 connected to the first-type pad 311 is not used to mount a jumper component.

[0187] In summary, in combination with Figures 7, 9, 11, 13, and 15, the first trace 41 and / or the second trace 42 connected to the first power module 341 do not include the first jumper region 316, and the first trace 41 or the second trace 42 not connected to the first power module 341 includes the first jumper region 316. When the circuit board 31 is used to carry a first memory chip and the first-type pads 311 are used to connect to the power pins of the first memory chip, the first power module 341 is used to power the first trace 41 connected to the first-type pads 311; and / or when the circuit board 31 is used to carry a second memory chip and the first-type pads 311 are used to connect to the power pins of the second memory chip, the first power module 341 is used to power the second trace 42 connected to the first-type pads 311.

[0188] It should be noted that the first power supply unit, the second power supply unit, the third power supply unit, the fourth power supply unit, the fifth power supply unit, and the sixth power supply unit mentioned above can be the same functional unit for voltage conversion in the first power supply module 341, or can be multiple different functional units for voltage conversion in the first power supply module 341. In addition, the first power supply unit, the second power supply unit, the third power supply unit, the fourth power supply unit, the fifth power supply unit, and the sixth power supply unit mentioned above can be integrated into the same device, such as all integrated into the power management chip 34, or the first power supply unit, the second power supply unit, the third power supply unit, the fourth power supply unit, the fifth power supply unit, and the sixth power supply unit mentioned above can also be independently provided, which is not limited in the embodiments of the present application.

[0189] In some embodiments, the plurality of first pads include second-type pads 312, which are used to connect to a signal pin of the first memory chip and a signal pin of the second memory chip, or to connect to a signal pin of the first memory chip and a ground pin of the second memory chip, or to connect to a ground pin of the first memory chip and a signal pin of the second memory chip. Furthermore, the first traces 41 and the second traces 42 connected to the second-type pads 312 both include a first jumper region 316. When the circuit board 31 is used to support the first memory chip, the first jumper region 316 included in the first traces 41 connected to at least some of the second-type pads 312 is used to mount a jumper component. When the circuit board 31 is used to support the second memory chip, the first jumper region 316 included in the second traces 42 connected to the second-type pads 312 is used to mount a jumper component.

[0190] Figure 16 is a schematic diagram of a connection relationship between the sixth type of pin-sharing pad and the first and second traces provided in an embodiment of the present application. Referring to Figure 16, for the sixth type of pin-sharing pad 3121 in the second type of pad 312, it can be a pad at the UFS signal pin / EMMC signal pin, that is, the sixth type of pin-sharing pad 3121 is used to connect to the signal pin of the first storage chip and the signal pin of the second storage chip. The sixth type of pin-sharing pad 3121 is connected to two traces, and the two traces connected to the sixth type of pin-sharing pad 3121 are the first trace 41 corresponding to the UFS storage chip and the second trace 42 corresponding to the EMMC storage chip. In addition, a signal pin of the processor chip 33 is connected to the sixth type of pin-sharing pad 3121 through the first trace 41, and another signal pin of the processor chip 33 is also connected to the sixth type of pin-sharing pad 3121 through the second trace 42.

[0191] The first trace 41 and the second trace 42 connected to the sixth type pin shared pad 3121 both include a first jumper region 316 .

[0192] When the first memory chip is mounted on the circuit board 31, a jumper element such as a resistor, diode, or transistor is installed at the first jumper region 316 of the first trace 41 connected to the sixth-category pin-shared pad 3121, thereby conducting the first trace 41 connected to the sixth-category pin-shared pad 3121. In this way, the signal output from the signal pin corresponding to the first memory chip in the processor chip 33 can be sequentially transmitted to the signal pin of the first memory chip via the first trace 41 and the sixth-category pin-shared pad 3121. Furthermore, no jumper element is installed at the first jumper region 316 of the second trace 42 connected to the sixth-category pin-shared pad 3121, thereby disconnecting the second trace 42 connected to the sixth-category pin-shared pad 3121.

[0193] Accordingly, when a second memory chip is mounted on the circuit board 31, a jumper element such as a resistor, diode, or transistor is mounted at the first jumper region 316 of the second trace 42 connected to the sixth-category pin-shared pad 3121, thereby conducting the second trace 42 connected to the sixth-category pin-shared pad 3121. In this way, the signal output from the signal pin corresponding to the second memory chip in the processor chip 33 can be sequentially transmitted to the signal pin of the second memory chip via the second trace 42 and the sixth-category pin-shared pad 3121. Furthermore, no jumper element is mounted at the first jumper region 316 of the first trace 41 connected to the sixth-category pin-shared pad 3121, thereby disconnecting the first trace 41 connected to the sixth-category pin-shared pad 3121.

[0194] Taking the case where the first storage chip is a first UFS storage chip and the second storage chip is an EMMC storage chip as an example, there is no pin at the same position in the first UFS storage chip and the EMMC storage chip that is connected to the sixth type of pin shared pad 3121, that is, the sixth type of pin shared pad 3121 may not exist on the circuit board 31. Alternatively, taking the case where the first storage chip is a second UFS storage chip and the second storage chip is an EMMC storage chip as an example, there is also no pin at the same position in the second UFS storage chip and the EMMC storage chip that is connected to the sixth type of pin shared pad 3121.

[0195] Figure 17 is a schematic diagram of a connection relationship between the seventh type of pin-sharing pad and the first and second traces provided in an embodiment of the present application. Referring to Figure 17, for the seventh type of pin-sharing pad 3122 in the second type of pad 312, it can be a pad at the UFS ground pin / EMMC signal pin, that is, the seventh type of pin-sharing pad 3122 is used to connect to the ground pin of the first storage chip and the signal pin of the second storage chip. The seventh type of pin-sharing pad 3122 is connected to two traces, and the two traces connected to the seventh type of pin-sharing pad 3122 are the first trace 41 corresponding to the UFS storage chip and the second trace 42 corresponding to the EMMC storage chip. In addition, the first trace 41 connected to the seventh type of pin-sharing pad 3122 is also connected to the ground terminal GND in the circuit board 31, and a signal pin of the processor chip 33 is connected to the seventh type of pin-sharing pad 3122 through the second trace 42.

[0196] The first trace 41 and the second trace 42 connected to the seventh type pin shared pad 3122 both include a first jumper region 316 .

[0197] When the first memory chip is mounted on the circuit board 31, a jump element or no jump element is mounted in the first jump region 316 of the first trace 41 connected to the seventh-category pin-shared pad 3122. Furthermore, no jump element is mounted in the first jump region 316 of the second trace 42 connected to the seventh-category pin-shared pad 3122.

[0198] Accordingly, when a second memory chip is mounted on the circuit board 31, a jumper element is installed at the first jumper region 316 of the second trace 42 connected to the seventh-category pin-shared pad 3122, thereby conducting the second trace 42 connected to the seventh-category pin-shared pad 3122. In this way, the signal output by the signal pin of the processor chip 33 can be transmitted to the signal pin of the second memory chip via the second trace 42 and the seventh-category pin-shared pad 3122. Furthermore, no jumper element is installed at the first jumper region 316 of the first trace 41 connected to the seventh-category pin-shared pad 3122, thereby disconnecting the first trace 41 connected to the seventh-category pin-shared pad 3122.

[0199] Take the first storage chip as the first UFS storage chip and the second storage chip as the EMMC storage chip as an example. The pin at the A3 position in the first UFS storage chip is the VDDiQ pin (i.e., the ground pin), and the pin at the A3 position in the EMMC storage chip is the DAT0 pin (i.e., the signal pin); the pins at the B2 position, H5 position, K5 position, and M5 position in the first UFS storage chip are all VSS pins (i.e., the ground pin), and the pin at the B2 position in the EMMC storage chip is the DAT3 pin (i.e., the signal pin), the pin at the H5 position in the EMMC storage chip is the DS pin (i.e., the signal pin), the pin at the K5 position in the EMMC storage chip is the RST_n pin (i.e., the signal pin), and the pin at the M5 position in the EMMC storage chip is the CMD pin (i.e., the signal pin). Therefore, the seventh type of pin-shared pad 3122 may include the first pad connected to the pins at the A3 position, B2 position, H5 position, K5 position, and M5 position in the first UFS storage chip and the EMMC storage chip.

[0200] In this way, for the seventh type of pin-shared pad 3122, the first pad connected to the pin at the A3 position in the first UFS storage chip and the EMMC storage chip. When the first UFS storage chip is assembled on the circuit board 31, a capacitor is assembled at the first jump selection area 316 included in the first routing line 41 corresponding to the pin at the A3 position in the first UFS storage chip, or no jump selection element is assembled. If no jump selection element is assembled at the first jump selection area 316 included in the first routing line 41 corresponding to the pin at the A3 position in the first UFS storage chip, the first routing line 41 corresponding to the pin at the A3 position in the first UFS storage chip can be placed in an open circuit state. When the EMMC storage chip is assembled on the circuit board 31, a resistor, a diode, or a transistor is assembled at the first jump selection area 316 included in the second routing line 42 corresponding to the pin at the A3 position in the EMMC storage chip.

[0201] Furthermore, for the first pads connected to the pins at positions B2, H5, K5, and M5 of the first UFS memory chip and the EMMC memory chip in the seventh category of pin-shared pads 3122, when the first UFS memory chip is assembled on the circuit board 31, a resistor, a diode, or a transistor, etc., is assembled at the first jump region 316 included in the first trace 41 corresponding to the pins at positions B2, H5, K5, and M5 of the first UFS memory chip; when the EMMC memory chip is assembled on the circuit board 31, a resistor, a diode, or a transistor, etc., is assembled at the first jump region 316 included in the second trace 42 corresponding to the pins at positions B2, H5, K5, and M5 of the EMMC memory chip.

[0202] It should be noted that, when the first storage chip is the second UFS storage chip, the positions of the multiple first pads included in the seventh category of pin-shared pads 3122, the functions of the connected pins, whether a jump element is assembled at each first jump selection area 316, and the type of jump element when the jump element is assembled at the first jump selection area 316 are the same as the positions of the multiple first pads included in the seventh category of pin-shared pads 3122 when the first storage chip is the first UFS storage chip, the functions of the connected pins, whether a jump element is assembled at each first jump selection area 316, and the type of jump element when the jump element is assembled at the first jump selection area 316, and are not described in detail here.

[0203] Figure 18 is a schematic diagram of a connection relationship between the eighth type of pin-sharing pad and the first and second traces provided in an embodiment of the present application. Referring to Figure 18, for the eighth type of pin-sharing pad 3123 in the second type of pad 312, it can be a pad at the UFS signal pin / EMMC ground pin, that is, the eighth type of pin-sharing pad 3123 is used to connect to the signal pin of the first storage chip and the ground pin of the second storage chip. The eighth type of pin-sharing pad 3123 is connected to two traces, and the two traces connected to the eighth type of pin-sharing pad 3123 are the first trace 41 corresponding to the UFS storage chip and the second trace 42 corresponding to the EMMC storage chip. In addition, a signal pin of the processor chip 33 is connected to the eighth type of pin-sharing pad 3123 through the first trace 41, and the second trace 42 connected to the eighth type of pin-sharing pad 3123 is also connected to the ground terminal GND in the circuit board 31.

[0204] The first trace 41 and the second trace 42 connected to the eighth-category pin-shared pad 3123 both include a first jumper region 316 .

[0205] When the first memory chip is mounted on the circuit board 31, a jump element such as a resistor, capacitor, diode, or transistor is installed at the first jump region 316 of the first trace 41 connected to the eighth-category pin-shared pad 3123, so that the first trace 41 connected to the eighth-category pin-shared pad 3123 is conductive. In this way, the signal output by the signal pin of the processor chip 33 can be transmitted to the signal pin of the first memory chip via the first trace 41 and the eighth-category pin-shared pad 3123. Furthermore, no jump element is installed at the first jump region 316 of the second trace 42 connected to the eighth-category pin-shared pad 3123, so that the second trace 42 connected to the eighth-category pin-shared pad 3123 is disconnected.

[0206] Accordingly, when a second memory chip is mounted on the circuit board 31, a jump element such as a resistor, capacitor, diode, or transistor is mounted at the first jump region 316 of the second trace 42 connected to the eighth-category pin-shared pad 3123, thereby conducting the second trace 42 connected to the eighth-category pin-shared pad 3123. In this way, the ground pin of the second memory chip can be electrically connected to the ground terminal GND via the eighth-category pin-shared pad 3123 and the second trace 42. Furthermore, no jump element is mounted at the first jump region 316 of the first trace 41 connected to the eighth-category pin-shared pad 3123, thereby disconnecting the first trace 41 connected to the eighth-category pin-shared pad 3123.

[0207] Taking the case where the first storage chip is a first UFS storage chip and the second storage chip is an EMMC storage chip as an example, there is no pin at the same position in the first UFS storage chip and the EMMC storage chip that is connected to the eighth category pin shared pad 3123, that is, the eighth category pin shared pad 3123 may not exist on the circuit board 31. Alternatively, taking the case where the first storage chip is a second UFS storage chip and the second storage chip is an EMMC storage chip as an example, there is also no pin at the same position in the second UFS storage chip and the EMMC storage chip that is connected to the eighth category pin shared pad 3123.

[0208] In some embodiments, as shown in FIG5 , the first pad group further includes a plurality of second pads, each of which is connected to a trace, with the trace connected to the second pad being a third trace. Some of the third traces connected to the second pads include a second jumper region 317, with the third trace at the second jumper region 317 disconnected. Other third traces connected to the second pads do not include the second jumper region 317. When the circuit board 31 is used to carry the first memory chip or the second memory chip, at least some of the third traces connected to the second pads include the second jumper region 317 for mounting jumper components.

[0209] It should be noted that the second jumper region 317 may be composed of two pads at a certain interval, so that the traces in the second jumper region 317 are not connected.

[0210] The plurality of second pads include third-type pads 313, which are configured to connect to a power pin of the first memory chip and an unused pin of the second memory chip, or to connect to an unused pin of the first memory chip and a power pin of the second memory chip. Furthermore, the circuit board 31 is further configured to carry a second power module, which is configured to connect to the third-type pads 313 via a third trace.

[0211] FIG19 is a schematic diagram of a connection relationship between the ninth type of pin-sharing pad and the third routing provided in an embodiment of the present application, and FIG20 is a schematic diagram of another connection relationship between the ninth type of pin-sharing pad and the third routing provided in an embodiment of the present application. Referring to FIG19 and FIG20 , for the ninth type of pin-sharing pad 3131 in the third type of pad 313, it can be a pad at the unused pin / EMMC power pin of the UFS, that is, the ninth type of pin-sharing pad 3131 is used to connect to the unused pin of the first memory chip and the power pin of the second memory chip. The ninth type of pin-sharing pad 3131 is connected to a routing line, and the routing line connected to the ninth type of pin-sharing pad 3131 is the third routing line 43 corresponding to the UFS memory chip and the EMMC memory chip. The second power supply module 342 may include a seventh power supply unit, which is connected to the ninth type of pin-sharing pad 3131 through the third routing line 43, and the seventh power supply unit is also connected to a power pin of the processor chip 33.

[0212] In one embodiment, as shown in FIG. 19 , the third trace 43 connected to the ninth type pin-shared pad 3131 includes a second jumper region 317 .

[0213] When a first memory chip is mounted on the circuit board 31, no jumper component is mounted at the second jumper region 317 of the third trace 43 connected to the ninth pin-shared pad 3131, leaving the third trace 43 connected to the ninth pin-shared pad 3131 in an open state. When a second memory chip is mounted on the circuit board 31, a jumper component is mounted at the second jumper region 317 of the third trace 43 connected to the ninth pin-shared pad 3131, leaving the third trace 43 connected to the ninth pin-shared pad 3131 conductive. In this way, the power pins in the processor chip 33 output a corresponding voltage to the second power module 342. After the seventh power supply unit in the second power module 342 converts this voltage into the voltage required for the operation of the second memory chip, the converted voltage can be transmitted to the power pins of the second memory chip via the third trace 43 and the ninth pin-shared pad 3131.

[0214] 20 , the third trace 43 connected to the ninth type pin shared pad 3131 does not include the second jumper region 317. That is, the third trace 43 in the circuit board 31 is directly connected during fabrication, and the second jumper region 317 does not exist.

[0215] When a first memory chip is mounted on the circuit board 31, the seventh power supply unit in the second power supply module 342 does not power the third trace 43 connected to the ninth type pin-shared pad 3131. When a second memory chip is mounted on the circuit board 31, the seventh power supply unit in the second power supply module 342 powers the third trace 43 connected to the ninth type pin-shared pad 3131. That is, the seventh power supply unit converts the voltage provided by the processor chip 33 into the voltage required for the operation of the second memory chip and outputs it to the third trace 43 connected to the ninth type pin-shared pad 3131. This allows the converted voltage from the seventh power supply unit to be transmitted to the power pin of the second memory chip via the third trace 43 and the ninth type pin-shared pad 3131 in sequence.

[0216] Take the case where the first storage chip is a first UFS storage chip and the second storage chip is an EMMC storage chip as an example. The pin at position C6 in the first UFS storage chip is the NU pin (i.e., unused pin), and the pin at position C6 in the EMMC storage chip is the VCCQ pin (i.e., power pin); the pin at position E6 in the first UFS storage chip is the VSF pin (debugging pin, also an unused pin), and the pin at position E6 in the EMMC storage chip is the VCC pin (i.e., power pin); the pin at position J10 in the first UFS storage chip is the VSF pin (i.e., unused pin), and the pin at position J10 in the EMMC storage chip is the VCC pin (i.e., power pin); the pin at position K9 in the first UFS storage chip is the NU pin (i.e., unused pin), and the pin at position K9 in the EMMC storage chip is the VCC pin (i.e., power pin); the pin at position P3 in the first UFS storage chip is the NU pin (i.e., unused pin), and the pin at position P3 in the EMMC storage chip is the VCCQ pin (i.e., power pin). Therefore, the ninth type of pin-shared pads 3131 include second pads connected to the pins located at positions C6, E6, J10, K9, and P3 in the first UFS memory chip and the EMMC memory chip.

[0217] In this way, for the second solder pad in the ninth category of pin-shared solder pads 3131, which are respectively connected to the pins at the C6 position, K9 position and P3 position in the first UFS storage chip and the EMMC storage chip, the third trace 43 connected thereto does not include the second jump selection area 317, so that when the first UFS storage chip or the EMMC storage chip is assembled on the circuit board 31, the third traces 43 corresponding to the pins at the C6 position, K9 position and P3 position are all in a short-circuit state.

[0218] Alternatively, for the plurality of second pads in the ninth category of pin-shared pads 3131 that are respectively connected to the pins at positions C6, K9, and P3 in the first UFS storage chip and the EMMC storage chip, the third traces 43 connected thereto include a second jumper region 317. When the first UFS storage chip is assembled on the circuit board 31, no jumper components are assembled at the second jumper region 317 included in the third traces 43 corresponding to the pins at positions C6, K9, and P3, so that these third traces 43 are in an open circuit state; and when the EMMC storage chip is assembled on the circuit board 31, jumper components such as resistors, diodes, or transistors are assembled at the second jumper region 317 included in the third traces 43 corresponding to the pins at positions C6, K9, and P3.

[0219] Furthermore, for the second pads in the ninth category of pin-shared pads 3131 that are respectively connected to the pins at positions E6 and J10 in the first UFS storage chip and the EMMC storage chip, the third trace 43 connected thereto includes a second jumper region 317. When the first UFS storage chip is assembled on the circuit board 31, no jumper components are assembled in the second jumper region 317 included in the third traces 43 corresponding to the pins at positions E6 and J10, rendering these third traces 43 in an open circuit state. When the EMMC storage chip is assembled on the circuit board 31, jumper components such as resistors, diodes, or transistors are assembled in the second jumper region 317 included in the third traces 43 corresponding to the pins at positions E6 and J10.

[0220] Take the case where the first storage chip is a second UFS storage chip and the second storage chip is an EMMC storage chip as an example. The pin at position E6 in the second UFS storage chip is a VSF pin (i.e., an unused pin), and the pin at position E6 in the EMMC storage chip is a VCC pin (i.e., a power pin); the pin at position F5 in the second UFS storage chip is a NU pin (i.e., an unused pin), and the pin at position F5 in the EMMC storage chip is a VCC pin (i.e., a power pin); the pin at position J10 in the second UFS storage chip is a VSF pin (i.e., an unused pin), and the pin at position J10 in the EMMC storage chip is a VCC pin (i.e., a power pin); the pin at position K9 in the second UFS storage chip is a NU pin (i.e., an unused pin), and the pin at position K9 in the EMMC storage chip is a VCC pin (i.e., a power pin); the pin at position P3 in the second UFS storage chip is a NU pin (i.e., an unused pin), and the pin at position P3 in the EMMC storage chip is a VCCQ pin (i.e., a power pin). Therefore, the ninth type of pin-shared pads 3131 include second pads connected to the pins located at positions E6, F5, J10, K9, and P3 in the second UFS memory chip and the EMMC memory chip.

[0221] In this way, for the ninth category of pin-shared pads 3131, the multiple second pads are respectively connected to the pins at the F5 position, K9 position and P3 position in the second UFS storage chip and the EMMC storage chip, and the third traces 43 connected thereto do not include the second jump selection area 317, so that when the second UFS storage chip or the EMMC storage chip is assembled on the circuit board 31, the third traces 43 corresponding to the pins at the F5 position, K9 position and P3 position are all in a short-circuit state.

[0222] Alternatively, for the plurality of second pads in the ninth category of pin-shared pads 3131 that are respectively connected to the pins at the F5 position, the K9 position, and the P3 position in the second UFS storage chip and the EMMC storage chip, the third traces 43 connected thereto include a second jumper region 317. When the second UFS storage chip is assembled on the circuit board 31, no jumper components are assembled at the second jumper region 317 included in the third traces 43 corresponding to the pins at the F5 position, the K9 position, and the P3 position, so that these third traces 43 are in an open circuit state; and when the EMMC storage chip is assembled on the circuit board 31, jumper components such as resistors, diodes, or transistors are assembled at the second jumper region 317 included in the third traces 43 corresponding to the pins at the F5 position, the K9 position, and the P3 position.

[0223] Furthermore, for the second pads in the ninth category of pin-shared pads 3131 that are respectively connected to the pins at positions E6 and J10 of the second UFS storage chip, the third trace 43 connected thereto includes a second jumper region 317. When the second UFS storage chip is assembled on the circuit board 31, no jumper components are assembled in the second jumper region 317 included in the third traces 43 corresponding to the pins at positions E6 and J10, rendering these third traces 43 in an open circuit state. When the EMMC storage chip is assembled on the circuit board 31, jumper components such as resistors, diodes, or transistors are assembled in the second jumper region 317 included in the third traces 43 corresponding to the pins at positions E6 and J10.

[0224] Figure 21 is a schematic diagram of a connection relationship between the tenth type of pin-shared pad and the third routing provided in an embodiment of the present application, and Figure 22 is a schematic diagram of another connection relationship between the tenth type of pin-shared pad and the third routing provided in an embodiment of the present application. Referring to Figures 21 and 22, for the tenth type of pin-shared pad 3132 in the third type of pad 313, it can be a pad at the UFS power pin / EMMC unused pin, that is, the tenth type of pin-shared pad 3132 is used to connect to the power pin of the first memory chip and the unused pin of the second memory chip. The tenth type of pin-shared pad 3132 is connected to a routing line, and the routing line connected to the tenth type of pin-shared pad 3132 is the third routing line 43 corresponding to the UFS memory chip and the EMMC memory chip. The second power supply module 342 may include an eighth power supply unit, which is connected to the tenth type of pin-shared pad 3132 through the third routing line 43, and the eighth power supply unit is also connected to a power pin of the processor chip 33.

[0225] In one embodiment, as shown in FIG. 21 , the third trace 43 connected to the tenth type pin shared pad 3132 includes a second jumper region 317 .

[0226] When a first memory chip is mounted on the circuit board 31, a jumper component is installed at the second jumper region 317 of the third trace 43 connected to the tenth-category pin-shared pad 3132, rendering the third trace 43 connected to the tenth-category pin-shared pad 3132 conductive. This allows the power pins in the processor chip 33 to output a corresponding voltage to the second power module 342. After the eighth power supply unit in the second power module 342 converts this voltage into the voltage required for operation of the first memory chip, the converted voltage is transmitted to the power pins of the first memory chip via the third trace 43 and the tenth-category pin-shared pad 3132. When a second memory chip is mounted on the circuit board 31, no jumper component is installed at the second jumper region 317 of the third trace 43 connected to the tenth-category pin-shared pad 3132, rendering the third trace 43 connected to the tenth-category pin-shared pad 3132 open.

[0227] In another manner, as shown in FIG. 22 , the third trace 43 connected to the tenth type pin shared pad 3132 does not include the second jumper area 317 .

[0228] When the first memory chip is mounted on the circuit board 31, the eighth power supply unit in the second power supply module 342 powers the third trace 43 connected to the tenth-category pin-shared pad 3132. Specifically, the eighth power supply unit converts the voltage provided by the processor chip 33 into the voltage required for operation of the first memory chip and outputs it to the third trace 43 connected to the tenth-category pin-shared pad 3132. This allows the converted voltage from the eighth power supply unit to be transmitted to the power pins of the first memory chip via the third trace 43 and the tenth-category pin-shared pad 3132, in sequence. When the second memory chip is mounted on the circuit board 31, the eighth power supply unit in the second power supply module 342 does not power the third trace 43 connected to the tenth-category pin-shared pad 3132.

[0229] Taking the first storage chip as a first UFS storage chip and the second storage chip as an EMMC storage chip as an example, the pins at positions A9, C5, and E5 in the first UFS storage chip are all VCCQ pins (i.e., power pins), the pins at positions B8, B9, C8, C9, E8, N8, N9, P8, and P9 in the first UFS storage chip are all VCC pins (i.e., power pins), and the pins at positions A9, B8, B9, C5, C8, C9, E5, E8, N8, N9, P8, and P9 in the EMMC storage chip are all NU pins (i.e., unused pins). Therefore, the tenth category of pin-shared pads 3132 include the second pads connected to the pins located at A9 position, B8 position, B9 position, C5 position, C8 position, C9 position, E5 position, E8 position, N8 position, N9 position, P8 position and P9 position in the first UFS storage chip and the EMMC storage chip.

[0230] In this way, the third trace 43 connected to the tenth type pin shared pad 3132 may not include the second jump selection area 317, so that when the first UFS storage chip or EMMC storage chip is assembled on the circuit board 31, the third trace 43 corresponding to the pins at position A9, position B8, position B9, position C5, position C8, position C9, position E5, position E8, position N8, position N9, position P8 and position P9 are all in a short-circuit state.

[0231] Alternatively, the third trace 43 connected to the tenth type pin-shared pad 3132 may include a second jump region 317. When the first UFS memory chip is assembled on the circuit board 31, a resistor, a diode, or a transistor is assembled at the second jump region 317 included in the third trace 43 corresponding to the pins at positions A9, B8, B9, C5, C8, C9, E5, E8, N8, N9, P8, and P9; and when the EMMC memory chip is assembled on the circuit board 31, no jump region 317 included in the third trace 43 corresponding to the pins at positions A9, B8, B9, C5, C8, C9, E5, E8, N8, N9, P8, and P9 is assembled, so that these third traces 43 are in an open state.

[0232] Taking the first memory chip as the second UFS memory chip and the second memory chip as an EMMC memory chip as an example, the pins at positions A7, B7, C7, K6, and K7 in the second UFS memory chip are all VCCQ2 pins (i.e., power pins), the pins at positions B8, B9, C8, C9, E8, N8, N9, P8, and P9 in the second UFS memory chip are all VCC pins (i.e., power pins), and the pins at positions A7, B7, B8, B9, C7, C8, C9, E8, K6, K7, N8, N9, P8, and P9 in the EMMC memory chip are all NU pins (i.e., unused pins). Therefore, the tenth category of pin-shared pads 3132 include the second pads connected to the pins located at A7 position, B7 position, B8 position, B9 position, C7 position, C8 position, C9 position, E8 position, K6 position, K7 position, N8 position, N9 position, P8 position and P9 position in the second UFS storage chip and the EMMC storage chip.

[0233] In this way, the third trace 43 connected to the tenth type pin shared pad 3132 may not include the second jump selection area 317, so that when the second UFS storage chip or EMMC storage chip is assembled on the circuit board 31, the third trace 43 corresponding to the pins at position A7, position B7, position B8, position B9, position C7, position C8, position C9, position E8, position K6, position K7, position N8, position N9, position P8 and position P9 are all in a short-circuit state.

[0234] Alternatively, the third trace 43 connected to the tenth type pin-shared pad 3132 may include a second jump region 317. When a second UFS memory chip is mounted on the circuit board 31, a resistor, a diode, or a transistor is mounted at the second jump region 317 of the third trace 43 corresponding to the pins at positions A7, B7, B8, B9, C7, C8, C9, E8, K6, K7, N8, N9, P8, and P9; and when an EMMC memory chip is mounted on the circuit board 31, no jump region 317 of the third trace 43 corresponding to the pins at positions A7, B7, B8, B9, C7, C8, C9, E8, K6, K7, N8, N9, P8, and P9 is mounted, so that these third traces 43 are in an open state.

[0235] Therefore, in conjunction with Figures 19 and 21 above, the third trace 43 connected to the third-type pad 313 includes a second jumper region 317. As shown in Figure 21, when the circuit board 31 is used to support a first memory chip and the third-type pad 313 is used to connect to the power pin of the first memory chip, the second jumper region 317 included in the third trace 43 connected to the third-type pad 313 is used to mount a jumper component. When the circuit board 31 is used to support a second memory chip and the third-type pad 313 is used to connect to the unused pin of the second memory chip, the second jumper region 317 included in the third trace 43 connected to the third-type pad 313 is not used to mount a jumper component. As shown in Figure 19, when the circuit board 31 is used to carry the first memory chip and the third type of pad 313 is used to connect to the unused pins of the first memory chip, the second jump selection area 317 included in the third routing 43 connected to the third type of pad 313 is not used to assemble the jump selection component; when the circuit board 31 is used to carry the second memory chip and the third type of pad 313 is used to connect to the power pin of the second memory chip, the second jump selection area 317 included in the third routing 43 connected to the third type of pad 313 is used to assemble the jump selection component.

[0236] Therefore, in conjunction with Figures 20 and 22 above, the third trace 43 connected to the third-type pad 313 does not include the second jumper region 317. As shown in Figure 22, when the circuit board 31 is used to carry a first memory chip and the third-type pad 313 is used to connect to the power pin of the first memory chip, the second power module 342 is used to power on the third trace 43 connected to the third-type pad 313; when the circuit board 31 is used to carry a second memory chip and the third-type pad 313 is used to connect to the unused pin of the second memory chip, the second power module 342 is used to not power on the third trace 43 connected to the third-type pad 313. As shown in Figure 20, when the circuit board 31 is used to carry the first storage chip and the third type of pad 313 is used to connect to the unused pins of the first storage chip, the second power supply module 342 is used to not power on the third trace 43 connected to the third type of pad 313; when the circuit board 31 is used to carry the second storage chip and the third type of pad 313 is used to connect to the power pin of the second storage chip, the second power supply module 342 is used to power on the third trace 43 connected to the third type of pad 313.

[0237] It should be noted that the seventh power supply unit and the eighth power supply unit may be two different functional units for voltage conversion in the second power supply module 342. Furthermore, the seventh power supply unit and the eighth power supply unit may be integrated into the same device, such as both integrated into the power management chip 34, or the seventh power supply unit and the eighth power supply unit may be independently provided, which is not limited in the embodiment of the present application.

[0238] In some embodiments, the first power module 341 and the second power module 342 may be integrated into the power management chip 34. Of course, the first power module 341 and the second power module 342 may also be independently provided.

[0239] In some embodiments, as shown in Figure 5, the plurality of second pads include a fourth type of pad 314, which is used to connect to unused pins of the first memory chip and / or unused pins of the second memory chip, and the fourth type of pad 314 is not used to connect to the power pins of the first memory chip or the power pins of the second memory chip.

[0240] Since the first memory chip and the second memory chip both include four types of pins, namely, signal pins, power pins, ground pins and unused pins, the fourth type of pad 314 is used to connect to the ground pin of the first memory chip and the unused pin of the second memory chip, to connect to the unused pin of the first memory chip and the ground pin of the second memory chip, to connect to the signal pin of the first memory chip and the unused pin of the second memory chip, to connect to the unused pin of the first memory chip and the signal pin of the second memory chip, and to connect to the unused pin of the first memory chip and the unused pin of the second memory chip.

[0241] Figure 23 is a schematic diagram of a connection relationship between the eleventh type of pin-shared pad and the third routing provided in an embodiment of the present application. Referring to Figure 23, for the eleventh type of pin-shared pad 3141 in the fourth type of pad 314, it can be a pad at the UFS ground pin / EMMC unused pin, that is, the eleventh type of pin-shared pad 3141 is used to connect to the ground pin of the first storage chip and the unused pin of the second storage chip. The eleventh type of pin-shared pad 3141 is connected to a routing line, and the routing line connected to the eleventh type of pin-shared pad 3141 is the third routing line 43 corresponding to the UFS storage chip and the EMMC storage chip. In addition, the third routing line 43 connected to the eleventh type of pin-shared pad 3141 is also connected to the ground terminal GND in the circuit board 31.

[0242] In one embodiment, as shown in FIG. 23 , the third trace 43 connected to the eleventh type pin shared pad 3141 includes a second jumper region 317 .

[0243] When a first memory chip is mounted on the circuit board 31, a jump element is mounted or not mounted at the second jump region 317 of the third trace 43 connected to the eleventh-category pin-shared pad 3141. When a second memory chip is mounted on the circuit board 31, no jump element is mounted at the second jump region 317 of the third trace 43 connected to the eleventh-category pin-shared pad 3141, leaving the third trace 43 connected to the eleventh-category pin-shared pad 3141 in an open circuit state.

[0244] Alternatively, the third trace 43 connected to the eleventh type pin-shared pad 3141 does not include the second jumper region 317. Thus, when the first memory chip or the second memory chip is mounted on the circuit board 31, the third trace 43 connected to the eleventh type pin-shared pad 3141 is in a short-circuit state.

[0245] Take the first memory chip as the first UFS memory chip and the second memory chip as the EMMC memory chip as an example. The pin at position A8 in the first UFS memory chip is the VDDiQ2 pin (i.e., the ground pin), and the pin at position A8 in the EMMC memory chip is the NU pin (i.e., the unused pin); the pins at positions B11, B12, C1, C3, C11, C12, D3, D12, D13, D14, E1, E2, E3, F3, F12, F13 in the first UFS memory chip are VDDiQ2 pins (i.e., the ground pin). The pins at the positions of F1, F14, G1, G2, G3, G10, G12, H3, H12, H13, H14, J1, J2, J3, J12, K3, K12, K13, K14, L1, L2, L3, L12, M3, M12, M13, M14, N3, N11, N12, P11, and P12 are all VSS pins (i.e., ground pins), and the pins at the positions of B11, B12, C1, C3, C11, C12, and D3 in the EMMC storage chip are all VSS pins (i.e., ground pins). The pins at 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 11, 12, 13, 14, 12, 13, 14, 13, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80Therefore, the eleventh type of pin-shared pads 3141 include the first UFS memory chip and the EMMC memory chip, located at A8 position, B11 position, B12 position, C1 position, C3 position, C11 position, C12 position, D3 position, D12 position, D13 position, D14 position, E1 position, E2 position, E3 position, F3 position, F12 position, F13 position, F14 position, G1 position, G2 position, G3 position, G10 position The second solder pad connected to the pins at position 1, G12, H3, H12, H13, H14, J1, J2, J3, J12, K3, K12, K13, K14, L1, L2, L3, L12, M3, M12, M13, M14, N3, N11, N12, P11, and P12.

[0246] Thus, for the second pad in the eleventh type of pin-shared pad 3141 , which is respectively connected to the pin at position A8 in the first UFS memory chip and the EMMC memory chip, the third trace 43 connected thereto may include a second jump selection area 317 . When the first UFS memory chip is mounted on the circuit board 31, a jump element such as a capacitor is mounted at the second jump region 317 of the third routing line 43 connected to the pin at the A8 position, or no jump element is mounted. If no jump element is mounted at the second jump region 317 of the third routing line 43 connected to the pin at the A8 position, the third routing line 43 connected to the pin at the A8 position can be placed in an open circuit state. When the EMMC memory chip is mounted on the circuit board 31, no jump element is mounted at the second jump region 317 of the third routing line 43 connected to the pin at the A8 position, so that the third routing line 43 connected to the pin at the A8 position is placed in an open circuit state. Alternatively, a jump element may be mounted at the second jump region 317 of the third routing line 43 connected to the pin at the A8 position, so that the third routing line 43 connected to the pin at the A8 position is placed in a short circuit state.

[0247] Moreover, for the eleventh type of pin-shared pads 3141, except for the second pad connected to the pin at the A8 position, the third trace 43 connected thereto includes a second jumper area 317. When the first UFS memory chip is assembled on the circuit board 31, at positions B11, B12, C1, C3, C11, C12, D3, D12, D13, D14, E1, E2, E3, F3, F12, F13, F14, G1, G2, G3, G10, G12, H3, H12, H13, and H14, , J1 position, J2 position, J3 position, J12 position, K3 position, K12 position, K13 position, K14 position, L1 position, L2 position, L3 position, L12 position, M3 position, M12 position, M13 position, M14 position, N3 position, N11 position, N12 position, P11 position and P12 position pins corresponding to the second jump area 317 of the third trace 43 included in the installation resistor, diode or transistor jump components; on the circuit board When assembling EMMC memory chip on 31, at B11 position, B12 position, C1 position, C3 position, C11 position, C12 position, D3 position, D12 position, D13 position, D14 position, E1 position, E2 position, E3 position, F3 position, F12 position, F13 position, F14 position, G1 position, G2 position, G3 position, G10 position, G12 position, H3 position, H12 position, H13 position, H14 position, J1 position , J2 position, J3 position, J12 position, K3 position, K12 position, K13 position, K14 position, L1 position, L2 position, L3 position, L12 position, M3 position, M12 position, M13 position, M14 position, N3 position, N11 position, N12 position, P11 position and P12 position, the second jump selection area 317 of the third routing lines 43 connected to the pins corresponding to the pins is not equipped with any jump selection elements, so that these third routing lines 43 are in an open state.

[0248] Alternatively, for the eleventh type of pin-shared pads 3141, except for the second pad connected to the pin at the A8 position, the third trace 43 connected thereto does not include the second jumper area 317. When the first UFS memory chip or EMMC memory chip is assembled on the circuit board 31, the pins at B11, B12, C1, C3, C11, C12, D3, D12, D13, D14, E1, E2, E3, F3, F12, F13, F14, G1, G2, G3, G10, G12, H3, The third traces 43 corresponding to the pins at H12 position, H13 position, H14 position, J1 position, J2 position, J3 position, J12 position, K3 position, K12 position, K13 position, K14 position, L1 position, L2 position, L3 position, L12 position, M3 position, M12 position, M13 position, M14 position, N3 position, N11 position, N12 position, P11 position and P12 position are all in a short-circuit state.

[0249] Taking the first memory chip as the second UFS memory chip and the second memory chip as the EMMC memory chip as an example, the eleventh type of pin-shared pad 3141 includes the second UFS memory chip and the EMMC memory chip, located at A8 position, A9 position, B11 position, B12 position, C1 position, C3 position, C11 position, C12 position, D3 position, D12 position, D13 position, D14 position, E1 position, E2 position, E3 position, F3 position, F12 position, F13 position, F14 position, The second solder pads connected to the pins at G1 position, G2 position, G3 position, G10 position, G12 position, H3 position, H12 position, H13 position, H14 position, J1 position, J2 position, J3 position, J12 position, K3 position, K12 position, K13 position, K14 position, L1 position, L2 position, L3 position, L12 position, M3 position, M12 position, M13 position, M14 position, N3 position, N11 position, N12 position, P11 position and P12 position.

[0250] The pin at position A9 in the second UFS storage chip is a VDDi pin (i.e., a ground pin), and the pin at position A9 in the EMMC storage chip is a NU pin (i.e., an unused pin). Thus, for the second pad in the eleventh category of pin-shared pads 3141 that is connected to the pins at position A9 in the second UFS storage chip and the EMMC storage chip, respectively, the third trace 43 connected thereto may include a second jumper region 317. When a second UFS memory chip is assembled on the circuit board 31, a jump element such as a capacitor is assembled at the second jump area 317 included in the third routing line 43 corresponding to the pin located at the A9 position, or no jump element is assembled; and when an EMMC memory chip is assembled on the circuit board 31, no jump element is assembled at the second jump area 317 included in the third routing line 43 corresponding to the pin located at the A9 position, so that the third routing line 43 corresponding to the pin located at the A9 position is in an open circuit state. Alternatively, a jump element may be assembled at the second jump area 317 included in the third routing line 43 corresponding to the pin located at the A9 position, so that the third routing line 43 corresponding to the pin located at the A9 position is in a short circuit state.

[0251] In the second UFS memory chip, the positions of the pins connected to the eleventh-category pin-sharing pad 3141, except for the A9 position, the functions of the connected pins, whether a jump element is installed in each second jump selection area 317, and the type of jump element when the jump element is installed in the second jump selection area 317 are the same as the positions of the pins connected to the eleventh-category pin-sharing pad 3141, the functions of the connected pins, whether a jump element is installed in each second jump selection area 317, and the type of jump element when the jump element is installed in the second jump selection area 317 in the first UFS memory chip, and will not be described in detail here.

[0252] Figure 24 is a schematic diagram of a connection relationship between the twelfth type pin-shared pad and the third routing provided in an embodiment of the present application. Referring to Figure 24, for the twelfth type pin-shared pad 3142 in the fourth type pad 314, it can be a pad at the unused pin / EMMC ground pin of the UFS, that is, the twelfth type pin-shared pad 3142 is used to connect to the unused pin of the first storage chip and the ground pin of the second storage chip. The twelfth type pin-shared pad 3142 is connected to a routing line, and the routing line connected to the twelfth type pin-shared pad 3142 is the third routing line 43 corresponding to the UFS storage chip and the EMMC storage chip. In addition, the third routing line 43 connected to the twelfth type pin-shared pad 3142 is also connected to the ground terminal GND in the circuit board 31.

[0253] In one embodiment, as shown in FIG. 24 , the third trace 43 connected to the twelfth type pin shared pad 3142 includes a second jumper region 317 .

[0254] When the first memory chip is mounted on the circuit board 31, no jumper component is mounted in the second jumper region 317 of the third trace 43 connected to the twelfth-category pin-shared pad 3142, leaving the third trace 43 connected to the twelfth-category pin-shared pad 3142 in an open circuit state. When the second memory chip is mounted on the circuit board 31, a jumper component is mounted in the second jumper region 317 of the third trace 43 connected to the twelfth-category pin-shared pad 3142.

[0255] Alternatively, the third trace 43 connected to the twelfth pin-shared pad 3142 does not include the second jumper region 317. Thus, when the first memory chip or the second memory chip is mounted on the circuit board 31, the third trace 43 connected to the twelfth pin-shared pad 3142 is in a short-circuit state.

[0256] Take the first memory chip as the first UFS memory chip and the second memory chip as the EMMC memory chip as an example. The pins at the G5 position and the E7 position in the first UFS memory chip are all VSF pins (i.e., unused pins), the pins at the A6 position and the P6 position in the first UFS memory chip are all NU pins (i.e., unused pins), and the pins at the G5 position, E7 position, A6 position, and P6 position in the EMMC memory chip are all VSS pins (i.e., ground pins). Therefore, the twelfth type of pin-shared pad 3142 includes the second pad connected to the pins at the G5 position, E7 position, A6 position, and P6 position in the first UFS memory chip and the EMMC memory chip.

[0257] In this way, for the second pads in the twelfth category of pin-shared pads 3142 that are respectively connected to the pins at the G5 position and the E7 position in the first UFS storage chip and the EMMC storage chip, the third trace 43 connected thereto may include a second jump region 317. When the first UFS storage chip is assembled on the circuit board 31, no jump element is assembled at the second jump region 317 included in the third trace 43 corresponding to the pins at the G5 position and the E7 position, so that the third trace 43 corresponding to the pins at the G5 position and the E7 position is in an open circuit state; and when the EMMC storage chip is assembled on the circuit board 31, a jump element such as a resistor, a diode, or a transistor is assembled at the second jump region 317 included in the third trace 43 corresponding to the pins at the G5 position and the E7 position.

[0258] For the second pads in the twelfth category of pin-shared pads 3142 that are respectively connected to the pins at positions A6 and P6 in the first UFS storage chip and the EMMC storage chip, the third trace 43 connected thereto may include a second jumper region 317. When the first UFS storage chip is mounted on the circuit board 31, no jumper components are mounted in the second jumper region 317 included in the third trace 43 corresponding to the pins at positions A6 and P6, leaving the third trace 43 corresponding to the pins at positions A6 and P6 in an open circuit state. When the EMMC storage chip is mounted on the circuit board 31, a jumper component such as a resistor, a diode, or a transistor is mounted in the second jumper region 317 included in the third trace 43 corresponding to the pins at positions A6 and P6.

[0259] Alternatively, for the second pads of the twelfth pin-shared pads 3142 connected to the pins at positions A6 and P6 of the first UFS storage chip and the EMMC storage chip, respectively, the third traces 43 connected thereto may not include the second jumper region 317. When the first UFS storage chip or the EMMC storage chip is assembled on the circuit board 31, the third traces 43 corresponding to the pins at positions A6 and P6 are both in a short-circuit state.

[0260] Take the first memory chip as the second UFS memory chip, and the second memory chip as the EMMC memory chip as an example. The pins at the E7 position and the G5 position in the second UFS memory chip are all VSF pins (i.e., unused pins), the pins at the C4 position and the P6 position in the second UFS memory chip are all NU pins (i.e., unused pins), and the pins at the E7 position, the G5 position, the C4 position, and the P6 position in the EMMC memory chip are all VSS pins (i.e., ground pins). Therefore, the twelfth type of pin-shared pad 3142 includes the second pad connected to the pins at the E7 position, the G5 position, the C4 position, and the P6 position in the second UFS memory chip and the EMMC memory chip.

[0261] In this way, for the second pads in the twelfth category of pin-shared pads 3142 that are respectively connected to the pins at the G5 position and the E7 position in the second UFS storage chip and the EMMC storage chip, the third trace 43 connected thereto may include a second jump region 317. When the second UFS storage chip is assembled on the circuit board 31, no jump element is assembled at the second jump region 317 included in the third trace 43 corresponding to the pins at the G5 position and the E7 position, so that the third trace 43 corresponding to the pins at the G5 position and the E7 position is in an open circuit state; and when the EMMC storage chip is assembled on the circuit board 31, a jump element such as a resistor, a diode, or a transistor is assembled at the second jump region 317 included in the third trace 43 corresponding to the pins at the G5 position and the E7 position.

[0262] For the second pads in the twelfth category of pin-shared pads 3142 that are respectively connected to the pins at positions C4 and P6 in the second UFS storage chip and the EMMC storage chip, the third trace 43 connected thereto may include a second jumper region 317. When the second UFS storage chip is mounted on the circuit board 31, no jumper components are mounted in the second jumper region 317 included in the third trace 43 corresponding to the pins at positions C4 and P6, leaving the third trace 43 corresponding to the pins at positions C4 and P6 in an open circuit state. When the EMMC storage chip is mounted on the circuit board 31, a jumper component such as a resistor, a diode, or a transistor is mounted in the second jumper region 317 included in the third trace 43 corresponding to the pins at positions C4 and P6.

[0263] Alternatively, for the second pads in the twelfth category of pin-shared pads 3142 that are connected to the pins at positions C4 and P6 of the second UFS storage chip and the EMMC storage chip, respectively, the third traces 43 connected thereto may not include the second jumper region 317. When the second UFS storage chip or the EMMC storage chip is assembled on the circuit board 31, the third traces 43 corresponding to the pins at positions C4 and P6 are both in a short-circuit state.

[0264] Figure 25 is a schematic diagram of a connection relationship between the thirteenth type of pin-sharing pad and the third routing provided in an embodiment of the present application. Referring to Figure 25, for the thirteenth type of pin-sharing pad 3143 in the fourth type of pad 314, it can be a pad at the UFS signal pin / EMMC unused pin, that is, the thirteenth type of pin-sharing pad 3143 is used to connect with the signal pin of the first storage chip and the unused pin of the second storage chip. The thirteenth type of pin-sharing pad 3143 is connected to a routing line, and the routing line connected to the thirteenth type of pin-sharing pad 3143 is the third routing line 43 corresponding to the UFS storage chip and the EMMC storage chip. In addition, a signal pin of the processor chip 33 is also connected to the thirteenth type of pin-sharing pad 3143 through the third routing line 43.

[0265] In one embodiment, as shown in FIG. 25 , the third trace 43 connected to the thirteenth type pin shared pad 3143 includes a second jumper region 317 .

[0266] When a first memory chip is mounted on the circuit board 31, a jumper component is mounted at the second jumper region 317 of the third trace 43 connected to the thirteenth-category pin-shared pad 3143. When a second memory chip is mounted on the circuit board 31, no jumper component is mounted at the second jumper region 317 of the third trace 43 connected to the thirteenth-category pin-shared pad 3143, leaving the third trace 43 connected to the thirteenth-category pin-shared pad 3143 in an open circuit state.

[0267] Alternatively, the third trace 43 connected to the thirteenth type pin-shared pad 3143 does not include the second jumper region 317. Thus, when the first memory chip or the second memory chip is mounted on the circuit board 31, the third trace 43 connected to the thirteenth type pin-shared pad 3143 is in a short-circuit state.

[0268] Take the first storage chip as the first UFS storage chip and the second storage chip as the EMMC storage chip as an example. The pin at the D1 position in the first UFS storage chip is the DIN1_T pin (i.e., signal pin), the pin at the D2 position in the first UFS storage chip is the DIN1_C pin (i.e., signal pin), the pin at the F1 position in the first UFS storage chip is the DIN0_T pin (i.e., signal pin), the pin at the F2 position in the first UFS storage chip is the DIN0_C pin (i.e., signal pin), the pin at the H1 position in the first UFS storage chip is the REF_CLK pin (i.e., signal pin), the pin at the H2 position in the first UFS storage chip is the RST_N pin (i.e., signal pin), and the pin at the H1 position in the first UFS storage chip is the REF_CLK pin (i.e., signal pin). The pin at position K1 in the S memory chip is the DOUT0_C pin (i.e., a signal pin), the pin at position K2 in the first UFS memory chip is the DOUT0_T pin (i.e., a signal pin), the pin at position M1 in the first UFS memory chip is the DOUT1_C pin (i.e., a signal pin), and the pin at position M2 in the first UFS memory chip is the DOUT1_T pin (i.e., a signal pin); and the pins at positions D1, D2, F1, F2, H1, H2, K1, K2, M1, and M2 in the EMMC memory chip are all NU pins (i.e., unused pins). Therefore, the thirteenth category of pin-shared pads 3143 includes the second pads connected to the pins at positions D1, D2, F1, F2, H1, H2, K1, K2, M1, and M2 in the first UFS memory chip and the EMMC memory chip.

[0269] In this way, the third trace 43 connected to the thirteenth type pin-shared pad 3143 may include a second jump selection area 317. When the first UFS storage chip is assembled on the circuit board 31, a resistor, a diode, or a transistor is assembled at the second jump selection area 317 included in the third trace 43 corresponding to the pins located at the D1 position, the D2 position, the F1 position, the F2 position, the H1 position, the H2 position, the K1 position, the K2 position, the M1 position, and the M2 position. Jump selection elements such as a resistor, a diode, or a transistor are assembled; and when the EMMC storage chip is assembled on the circuit board 31, no jump selection elements are assembled at the second jump selection area 317 included in the third trace 43 corresponding to the pins located at the D1 position, the D2 position, the F1 position, the F2 position, the H1 position, the H2 position, the K1 position, the K2 position, the M1 position, and the M2 position. Therefore, these third traces 43 are in an open circuit state.

[0270] Alternatively, the third trace 43 connected to the thirteenth type pin-shared pad 3143 may not include the second jumper area 317. When the first UFS memory chip or EMMC memory chip is assembled on the circuit board 31, the third traces 43 corresponding to the pins at positions D1, D2, F1, F2, H1, H2, K1, K2, M1, and M2 are all in a short-circuit state.

[0271] In the case where the first memory chip is the second UFS memory chip, the positions of the multiple second pads included in the thirteenth category of pin-shared pads 3143, the functions of the connected pins, whether a jump element is assembled at each second jump selection area 317, and the type of jump element when the jump element is assembled at the second jump selection area 317 are the same as the positions of the multiple second pads included in the thirteenth category of pin-shared pads 3143 when the first memory chip is the first UFS memory chip, the functions of the connected pins, whether a jump element is assembled at each second jump selection area 317, and the type of jump element when the jump element is assembled at the second jump selection area 317, and are not described in detail here.

[0272] Figure 26 is a schematic diagram of a connection relationship between the fourteenth type of pin-shared pad and the third routing provided in an embodiment of the present application. Referring to Figure 26, for the fourteenth type of pin-shared pad 3144 in the fourth type of pad 314, it can be a pad at the unused pin / EMMC signal pin of the UFS, that is, the fourteenth type of pin-shared pad 3144 is used to connect to the unused pin of the first memory chip and the signal pin of the second memory chip. The fourteenth type of pin-shared pad 3144 is connected to a routing line, and the routing line connected to the fourteenth type of pin-shared pad 3144 is the third routing line 43 corresponding to the UFS memory chip and the EMMC memory chip. In addition, a signal pin of the processor chip 33 is also connected to the fourteenth type of pin-shared pad 3144 through the third routing line 43.

[0273] In one embodiment, as shown in FIG. 26 , the third trace 43 connected to the fourteenth type pin shared pad 3144 includes a second jumper region 317 .

[0274] When the first memory chip is mounted on the circuit board 31, no jumper component is mounted in the second jumper region 317 of the third trace 43 connected to the fourteenth-category pin-shared pad 3144, leaving the third trace 43 connected to the fourteenth-category pin-shared pad 3144 in an open circuit state. When the second memory chip is mounted on the circuit board 31, a jumper component is mounted in the second jumper region 317 of the third trace 43 connected to the fourteenth-category pin-shared pad 3144.

[0275] Alternatively, the third trace 43 connected to the fourteenth pin-shared pad 3144 does not include the second jumper region 317. Thus, when the first memory chip or the second memory chip is mounted on the circuit board 31, the third trace 43 connected to the fourteenth pin-shared pad 3144 is in a short-circuit state.

[0276] Take the first storage chip as the first UFS storage chip and the second storage chip as the EMMC storage chip as an example. The pins at the B3 position, the B6 position, and the M6 ​​position in the first UFS storage chip are all NU pins (i.e., unused pins), and the pin at the B3 position in the EMMC storage chip is the DAT4 pin (i.e., signal pin), the pin at the B6 position in the EMMC storage chip is the DAT7 pin (i.e., signal pin), and the pin at the M6 ​​position in the EMMC storage chip is the CLK pin (i.e., signal pin). Therefore, the fourteenth category of pin-shared pads 3144 include the second pads connected to the pins at the B3 position, the B6 position, and the M6 ​​position in the first UFS storage chip and the EMMC storage chip.

[0277] In this way, the third trace 43 connected to the fourteenth type pin-shared pad 3144 may include a second jump region 317. When the first UFS storage chip is assembled on the circuit board 31, no jump component is assembled at the second jump region 317 included in the third trace 43 connected to the pins at the B3 position, the B6 position, and the M6 ​​position, so that the third trace 43 connected to the pins at the B3 position, the B6 position, and the M6 ​​position is in an open circuit state; and when the EMMC storage chip is assembled on the circuit board 31, a jump component such as a resistor, a diode, or a transistor is assembled at the second jump region 317 included in the third trace 43 connected to the pins at the B3 position, the B6 position, and the M6 ​​position.

[0278] Alternatively, the third trace 43 connected to the fourteenth type pin shared pad 3144 may not include the second jumper area 317. When the first UFS memory chip or EMMC memory chip is assembled on the circuit board 31, the third trace 43 connected to the pins at positions B3, B6, and M6 are all in a short-circuit state.

[0279] Take the case where the first storage chip is a second UFS storage chip and the second storage chip is an EMMC storage chip as an example. The pins at positions A4, A5, B3, B4, B5, and M6 in the second UFS storage chip are all NU pins (i.e., unused pins), and the pin at position A4 in the EMMC storage chip is a DAT1 pin (i.e., a signal pin), the pin at position A5 in the EMMC storage chip is a DAT2 pin (i.e., a signal pin), the pin at position B3 in the EMMC storage chip is a DAT4 pin (i.e., a signal pin), and the pin at position B4 in the EMMC storage chip is a DAT5 pin (i.e., a signal pin).

[0280] The pin at position B5 in the EMMC memory chip is the DAT6 pin (i.e., a signal pin), and the pin at position M6 in the EMMC memory chip is the CLK pin (i.e., a signal pin). Therefore, the fourteenth category of pin-shared pads 3144 includes the second pads connected to the pins at positions A4, A5, B3, B4, B5, and M6 in the second UFS memory chip and the EMMC memory chip.

[0281] In this way, the third trace 43 connected to the fourteenth type pin-shared pad 3144 may include a second jump selection area 317. When the second UFS storage chip is assembled on the circuit board 31, no jump selection element is assembled at the second jump selection area 317 included in the third trace 43 connected to the pins at the A4 position, A5 position, B3 position, B4 position, B5 position and M6 position, so that the third trace 43 connected to the pins at the A4 position, A5 position, B3 position, B4 position, B5 position and M6 position is in an open circuit state; and when the EMMC storage chip is assembled on the circuit board 31, a resistor, a diode or a transistor is assembled at the second jump selection area 317 included in the third trace 43 connected to the pins at the A4 position, A5 position, B3 position, B4 position, B5 position and M6 position.

[0282] Alternatively, the third trace 43 connected to the fourteenth type pin-shared pad 3144 may not include the second jumper area 317. When a second UFS memory chip or EMMC memory chip is assembled on the circuit board 31, the third trace 43 connected to the pins at positions A4, A5, B3, B4, B5, and M6 are all in a short-circuit state.

[0283] It should be noted that, for the scenario shown in FIG. 25 , when the first memory chip is mounted on the circuit board 31, the resistor mounted at the second jumper region 317 of the third trace 43 connected to the thirteenth-category pin-shared pad 3143 can match the internal impedance of the first memory chip, thereby improving the signal transmission quality of the first memory chip. Correspondingly, for the scenario shown in FIG. 26 , when the second memory chip is mounted on the circuit board 31, the resistor mounted at the second jumper region 317 of the third trace 43 connected to the fourteenth-category pin-shared pad 3144 can match the internal impedance of the second memory chip, thereby improving the signal transmission quality of the second memory chip.

[0284] Therefore, as shown in Figures 23 to 26 , the third trace 43 connected to the fourth-type pad 314 includes a second jumper region 317. As shown in Figures 24 and 26 , when the circuit board 31 is used to carry a first memory chip and the fourth-type pad 314 is used to connect to an unused pin of the first memory chip, the second jumper region 317 included in the third trace 43 connected to the fourth-type pad 314 is not used to mount a jumper component. However, when the circuit board 31 is used to carry a second memory chip and the fourth-type pad 314 is used to connect to a ground pin or a signal pin of the second memory chip, the second jumper region 317 included in the third trace 43 connected to the fourth-type pad 314 is used to mount a jumper component. As shown in Figures 23 and 25, when the circuit board 31 is used to carry the first memory chip and the fourth-type pad 314 is used to connect to the ground pin or signal pin of the first memory chip, the second jump selection area 317 included in the third routing 43 connected to the fourth-type pad 314 is used to assemble the jump selection element or is not used to assemble the jump selection element; when the circuit board 31 is used to carry the second memory chip and the fourth-type pad 314 is used to connect to the unused pin of the second memory chip, the second jump selection area 317 included in the third routing 43 connected to the fourth-type pad 314 is not used to assemble the jump selection element.

[0285] Alternatively, for the fourth type of pads 314 including the eleventh type pin-shared pad 3141 , the twelfth type pin-shared pad 3142 , the thirteenth type pin-shared pad 3143 and the fourteenth type pin-shared pad 3144 , the third traces 43 connected thereto do not include the second jumper area 317 .

[0286] FIG27 is a schematic diagram of a connection relationship between the shared pad for the fifteenth type of pins and the third routing provided in an embodiment of the present application. Referring to FIG27 , the shared pad for the fifteenth type of pins 3145 in the fourth type of pad 314 can be a pad at an unused pin of the UFS / EMMC, i.e., the shared pad for the fifteenth type of pins 3145 is used to connect to the unused pins of the first memory chip and the unused pins of the second memory chip. The shared pad for the fifteenth type of pins 3145 is connected to a routing line, and the routing line connected to the shared pad for the fifteenth type of pins 3145 is the third routing line 43 corresponding to the UFS memory chip and the EMMC memory chip.

[0287] The third trace 43 connected to the shared pad 3145 for the fifteenth type of pins does not include the second jumper region 317. Thus, when the first memory chip or the second memory chip is mounted on the circuit board 31, the third trace 43 connected to the shared pad 3145 for the fifteenth type of pins is in a short-circuit state, causing the pins connected to the shared pad 3145 for the fifteenth type of pins to be in a floating state.

[0288] Take the first memory chip as the first UFS memory chip and the second memory chip as the EMMC memory chip as an example. In the first UFS memory chip and the EMMC memory chip, the memory chips located at position A1, A2, A7, A10, A11, A12, A13, A14, B1, B7, B10, B13, B14, C7, C10, C13, C14, D4, E9, E10, E12, E13, E14, and F10 , G13 position, G14 position, J13 position, J14 position, K6 position, K7 position, K10 position, L13 position, L14 position, M7 position, M8 position, M9 position, M10 position, M11 position, N1 position, N6 position, N7 position, N10 position, N13 position, N14 position, P1 position, P2 position, P7 position, P10 position, P13 position and P14 position pins are all unused pins. Therefore, the fifteenth category pin-shared pad 3145 includes the second pad connected to the pins at the above positions in the first UFS storage chip and the EMMC storage chip. In addition, the third trace 43 connected to the fifteenth category pin-shared pad 3145 does not include the second jump selection area 317. When the first UFS storage chip or the EMMC storage chip is assembled on the circuit board 31, the third trace 43 corresponding to the pins at the above positions are all in a short-circuit state.

[0289] Take the case where the first storage chip is the second UFS storage chip and the second storage chip is the EMMC storage chip as an example. In the second UFS storage chip and EMMC storage chip, the pins located at A1, A2, A10, A11, A12, A13, A14, B1, B10, B13, B14, C5, C10, C13, C14, D4, E5, E9, E10, E12, E13, E14, F10, G13, G14, J13, J14, K10, L13, L14, M7, M8, M9, M10, M11, N1, N6, N7, N10, N13, N14, P1, P2, P7, P10, P13, and P14 are all unused pins. Therefore, the fifteenth pin-shared pad 3145 includes the second pad connected to the pins at the aforementioned positions in the second UFS storage chip and the EMMC storage chip. Furthermore, the third trace 43 connected to the fifteenth pin-shared pad 3145 does not include the second jumper region 317. When the second UFS storage chip or the EMMC storage chip is mounted on the circuit board 31, the third traces 43 corresponding to the pins at the aforementioned positions are all in a short-circuit state.

[0290] In some embodiments, as shown in FIG5 , the plurality of second pads include a fifth-type pad 315 , which is used to connect to the ground pin of the first memory chip and the ground pin of the second memory chip. The third trace 43 connected to the fifth-type pad 315 includes a second jumper region 317 . When the circuit board 31 is used to support the first memory chip, the second jumper region 317 included in the third trace 43 connected to the fifth-type pad 315 is used to mount a jumper component. When the circuit board 31 is used to support the second memory chip, the second jumper region 317 included in the third trace 43 connected to the fifth-type pad 315 is used to mount a jumper component or is not used to mount a jumper component. Alternatively, the third trace 43 connected to the fifth-type pad 315 does not include the second jumper region 317 .

[0291] FIG28 is a schematic diagram of a connection relationship between the sixteenth type pin-shared pad and the third routing provided in an embodiment of the present application. Referring to FIG28 , for the sixteenth type pin-shared pad 3151 in the fifth type pad 315, it can be a pad at the UFS ground pin / EMMC ground pin, that is, the sixteenth type pin-shared pad 3151 is used to connect to the ground pin of the first memory chip and the ground pin of the second memory chip. The sixteenth type pin-shared pad 3151 is connected to a routing line, and the routing line connected to the sixteenth type pin-shared pad 3151 is the third routing line 43 corresponding to the UFS memory chip and the EMMC memory chip. In addition, the third routing line 43 connected to the sixteenth type pin-shared pad 3151 is also connected to the ground terminal GND in the circuit board 31.

[0292] In one embodiment, as shown in FIG. 28 , the third trace 43 connected to the sixteenth type pin shared pad 3151 includes a second jumper region 317 .

[0293] When a first memory chip is mounted on the circuit board 31, a jump element is mounted at the second jump region 317 of the third trace 43 connected to the sixteenth-category pin-shared pad 3151. When a second memory chip is mounted on the circuit board 31, a jump element is mounted or not mounted at the second jump region 317 of the third trace 43 connected to the sixteenth-category pin-shared pad 3151.

[0294] It can be understood that some pins connected to the pads at the UFS ground pin / EMMC ground pin may need to be grounded through components such as capacitors. Therefore, in this case, some third traces 43 connected to the pads at the UFS ground pin / EMMC ground pin need to include a second jump selection area 317.

[0295] Alternatively, the third trace 43 connected to the sixteenth pin-shared pad 3151 does not include the second jumper region 317. Thus, when the first memory chip or the second memory chip is mounted on the circuit board 31, the third trace 43 connected to the sixteenth pin-shared pad 3151 is in a short-circuit state.

[0296] Take the first memory chip as the first UFS memory chip and the second memory chip as the EMMC memory chip as an example. The pins at the C2 position, H10 position, J5 position, N2 position, N5 position, and P4 position in the first UFS memory chip are all VSS pins (i.e., ground pins), and the pin at the C2 position in the EMMC memory chip is a VDDi pin (i.e., ground pin), and the pins at the H10 position, J5 position, N2 position, N5 position, and P4 position in the EMMC memory chip are all VSS pins (i.e., ground pins). Therefore, the sixteenth type of pin-shared pad 3151 includes the second pad connected to the pins at the C2 position, H10 position, J5 position, N2 position, N5 position, and P4 position in the first UFS memory chip and the EMMC memory chip.

[0297] Thus, for the second pad in the sixteenth category of pin-shared pads 3151, which is respectively connected to the pin at position C2 in the first UFS storage chip and the EMMC storage chip, the third trace 43 connected thereto may include a second jump region 317. When the first UFS storage chip is mounted on the circuit board 31, a jump component such as a resistor, a diode, or a transistor is mounted at the second jump region 317 included in the third trace 43 connected to the pin at position C2; when the EMMC storage chip is mounted on the circuit board 31, a jump component such as a capacitor is mounted at the second jump region 317 included in the third trace 43 connected to the pin at position C2, or no jump component is mounted.

[0298] Moreover, for the second pad in the sixteenth category of pin-shared pads 3151, which are respectively connected to the pins at the H10 position, J5 position, N2 position, N5 position and P4 position in the first UFS storage chip and the EMMC storage chip, the third trace 43 connected thereto may not include the second jump selection area 317. When the first UFS storage chip or the EMMC storage chip is assembled on the circuit board 31, the third traces 43 corresponding to the pins at the H10 position, J5 position, N2 position, N5 position and P4 position are all in a short-circuit state.

[0299] In the case where the first memory chip is the second UFS memory chip, the positions of the multiple second pads included in the sixteenth category of pin-shared pads 3151, the functions of the connected pins, whether a jump element is assembled at each second jump selection area 317, and the type of jump element when the jump element is assembled at the second jump selection area 317 are the same as the positions of the multiple second pads included in the sixteenth category of pin-shared pads 3151 when the first memory chip is the first UFS memory chip, the functions of the connected pins, whether a jump element is assembled at each second jump selection area 317, and the type of jump element when the jump element is assembled at the second jump selection area 317, and are not described in detail here.

[0300] It should be understood that although a plurality of different jump selection methods are listed above for the jump selection area (first jump selection area 316 or second jump selection area 317) included in the routing line connected to the same pin, such as the jump selection method can be open circuit, short circuit, and the method of assembling a jump selection element such as a resistor, capacitor, diode or transistor, it does not mean that all jump selection methods of the pin are traversed and applied in the actual design. The selection of the jump selection method at the jump selection area included in the routing line connected to each pin can be selected according to the function of the specific pin and the external circuit, so as to make the overall design of the circuit board 31 as streamlined as possible. The embodiment of the present application does not specifically limit the jump selection method at the jump selection area included in the routing line connected to each pin.

[0301] In the embodiment of the present application, the jump element includes any one of a resistor, a capacitor, a diode and a transistor.

[0302] It should be noted that the circuit board 31 shown in FIG5 is merely for illustrative purposes. The traces connected to the individual pads in the first pad group and the jumper regions provided in the traces do not constitute limitations on the positions of the individual pads in the first pad group provided on the circuit board 31, the number of pads in the first pad group, the distribution of the traces, etc. The positions of the individual pads in the first pad group provided on the circuit board 31, the number of pads in the first pad group, the distribution of the traces, etc., can be set according to actual conditions. Furthermore, a power management chip 34 and a processor chip 33 may also be mounted on the circuit board 31 shown in FIG5 , and the power management chip 34 may include the aforementioned first power module 341 and second power module 342.

[0303] Figure 29 is a schematic diagram of an exemplary structure of a first memory chip mounted on a circuit board according to an embodiment of the present application. When the first memory chip is mounted on the circuit board 31 shown in Figure 5, for example, when the first memory chip is a UFS memory chip, a circuit board assembly as shown in Figure 29 can be obtained.

[0304] Among them, a resistor is installed at the first jump selection area 316 of the first trace 41 connected to the pad at the UFS power pin / EMMC power pin; a resistor is installed at the first jump selection area 316 of the first trace 41 connected to the pad at the UFS power pin / EMMC signal pin; a resistor is installed at the first jump selection area 316 of the first trace 41 connected to the pad at the UFS power pin / EMMC ground pin; a resistor is installed at the first jump selection area 316 of the first trace 41 connected to the pad at the UFS power pin / EMMC ground pin; A resistor is installed at the first jump selection area 316 of the first routing line 41 connected to the pad at the power pin; a resistor is installed at the first jump selection area 316 of the first routing line 41 connected to the pad at the UFS ground pin / EMMC signal pin; no jump selection element is installed at the second jump selection area 317 of the third routing line 43 connected to the pad at the UFS unused pin / EMMC power pin; a resistor is installed at the second jump selection area 317 of the third routing line 43 connected to the pad at the UFS power pin / EMMC unused pin; a resistor is installed at the second jump selection area 317 of the third routing line 43 connected to the pad at the UFS ground pin / EMMC unused pin; No jump element is installed at the second jump area 317 included in the third routing 43 connected to the pad at the pin / EMMC ground pin; a resistor is installed at the second jump area 317 included in the third routing 43 connected to the pad at the UFS signal pin / EMMC unused pin; no jump element is installed at the second jump area 317 included in the third routing 43 connected to the pad at the UFS unused pin / EMMC signal pin; the third routing 43 connected to the pad at the UFS unused pin / EMMC unused pin does not include the second jump area 317; a resistor is installed at the second jump area 317 included in the third routing 43 connected to the pad at the UFS ground pin / EMMC ground pin.

[0305] Figure 30 is a schematic diagram of an exemplary structure of a second memory chip mounted on a circuit board according to an embodiment of the present application. When the second memory chip is mounted on the circuit board 31 shown in Figure 5 , such as when the second memory chip is an EMMC memory chip, a circuit board assembly as shown in Figure 30 can be obtained.

[0306] Among them, a resistor is assembled at the first jump selection area 316 included in the second routing 42 connected to the pad at the UFS power pin / EMMC power pin; a resistor is assembled at the first jump selection area 316 included in the second routing 42 connected to the pad at the UFS power pin / EMMC signal pin; a resistor is assembled at the first jump selection area 316 included in the second routing 42 connected to the pad at the UFS power pin / EMMC ground pin; a resistor is assembled at the first jump selection area 316 included in the second routing 42 connected to the pad at the UFS ground pin / EMMC power pin; a resistor is assembled at the first jump selection area 316 included in the second routing 42 connected to the pad at the UFS ground pin / EMMC signal pin; a resistor is assembled at the second jump selection area 317 included in the third routing 43 connected to the pad at the UFS unused pin / EMMC power pin; a resistor is assembled at the third routing 43 connected to the pad at the UFS power pin / EMMC unused pin 3, no jump element is installed at the second jump area 317 included in the third routing line 43 connected to the pad at the UFS ground pin / EMMC unused pin; no jump element is installed at the second jump area 317 included in the third routing line 43 connected to the pad at the UFS unused pin / EMMC ground pin; a resistor is installed at the second jump area 317 included in the third routing line 43 connected to the pad at the UFS signal pin / EMMC unused pin; a resistor is installed at the second jump area 317 included in the third routing line 43 connected to the pad at the UFS unused pin / EMMC signal pin; the third routing line 43 connected to the pad at the UFS unused pin / EMMC unused pin does not include the second jump area 317; a capacitor is installed at the second jump area 317 included in the third routing line 43 connected to the pad at the UFS ground pin / EMMC ground pin.

[0307] In summary, the same circuit board 31 provided in the embodiment of the present application is compatible with the first memory chip and the second memory chip.

[0308] In some possible implementations, the first-type pin-shared pad 3111 in the first-type pad 311 is used to connect to the power pin of the first memory chip and the power pin of the second memory chip. When the first memory chip or the second memory chip is mounted on the circuit board 31, if the power pins of the processor chip 33 connected to the first-type pin-shared pad 3111 are the same power pin, the two traces can be merged into one trace.

[0309] FIG31 is a schematic diagram illustrating a connection relationship between the sixth type of pads and the third trace provided in an embodiment of the present application, and FIG32 is a schematic diagram illustrating another connection relationship between the sixth type of pads and the third trace provided in an embodiment of the present application. Referring to FIG31 and FIG32 , the circuit board 31 further includes a second pad group, which is used to connect to the processor chip 33. The circuit board 31 is also used to support a third power module 343. The plurality of second pads include a sixth type of pad 51, which is used to connect to the power pins of the first memory chip and the power pins of the second memory chip. When the circuit board 31 is used to support the first memory chip, the power pin of the first memory chip is sequentially connected to the first power pin of the processor chip 33 via the sixth type of pad 51, the third trace 43, and the third power module 343. When the circuit board 31 is used to support the second memory chip, the power pin of the second memory chip is sequentially connected to the second power pin of the processor chip 33 via the sixth type of pad 51, the third trace 43, and the third power module 343. The first power pin and the second power pin are the same power pin.

[0310] In one embodiment, as shown in FIG31 , the third trace 43 connected to the sixth type solder pad 51 includes a second jump selection area 317 ; when the circuit board 31 is used to carry the first memory chip or the second memory chip, the second jump selection area 317 included in the third trace 43 connected to the sixth type solder pad 51 is used to assemble a jump selection component.

[0311] In another embodiment, as shown in FIG32 , the third trace 43 connected to the sixth-type pad 51 does not include the second jumper region 317. When the circuit board 31 is used to support a first memory chip or a second memory chip, the third power module 343 is used to power the third trace 43 connected to the sixth-type pad 51. Furthermore, the voltage output by the third power module 343 when the first memory chip is mounted on the circuit board 31 may be different from the voltage output by the third power module 343 when the second memory chip is mounted on the circuit board 31.

[0312] In some embodiments, a size of the first memory chip is consistent with a size of the second memory chip.

[0313] In some embodiments, the target memory chip 32 and the processor chip 33 may be located on the first surface of the circuit board 31. When the first memory chip or the second memory chip is mounted on the circuit board 31, the jumper element mounted at the first jumper region 316 may be located on the second surface of the circuit board 31. The second surface and the first surface may be two surfaces disposed opposite each other on the circuit board.

[0314] In this way, for the two traces connected to the same pad, the jump select element assembled at the first jump select area 316 and the target memory chip 32 and the processor chip 33 can be distributed on both sides of the circuit board 31 to reduce the signal matching problem caused by the two traces.

[0315] In other embodiments, the target memory chip 32, the processor chip 33, and the jump selection element assembled at the first jump selection area 316 may also be located on the same surface of the circuit board 31, and the distance between the first jump selection area 316 and the target memory chip 32 is smaller than the distance between the first jump selection area 316 and the processor chip 33.

[0316] In this way, for the two routing lines connected to the same pad, the first jumper area 316 included therein can be as close as possible to the location of the target memory chip 32, so that after the jumper elements such as resistors are assembled at the first jumper area 316, the signal matching problem caused by the two routing lines can be reduced.

[0317] In some embodiments, for signal line compatibility scenarios, such as the scenario shown in FIG16 , the difference between the width of the two traces before and after the bifurcation is less than a preset value, which may be 0 or a value close to 0, so that the width of the two traces before and after the bifurcation remains substantially consistent. In this way, the impedance of the signals transmitted by the two traces can be adjusted.

[0318] The above description is mainly directed to the implementation method of being compatible with the first memory chip and the second memory chip on the same circuit board 31. Of course, the circuit board 31 in the embodiment of the present application can also be compatible with three or more types of memory chips.

[0319] Specifically, the circuit board 31 is used to carry the target memory chip 32. The target memory chip 32 includes any one of at least two types of memory chips. The number of pins of each type of the at least two types of memory chips is equal, and the pin arrangement of each type of the at least two types of memory chips is the same. The circuit board 31 includes a first pad group, which is used to connect to the target memory chip 32. The first pad group includes multiple first pads, each of which is connected to at least two traces. Each trace connected to at least some of the first pads includes a first jumper region 316, and the traces at the first jumper region 316 are disconnected. When the circuit board 31 is used to carry the target memory chip 32, the first jumper region 316 included in the target traces connected to at least some of the first pads is used to assemble a jumper component. The target trace is one of the at least two traces connected to the first pad that corresponds to the target memory chip 32.

[0320] In some embodiments, each pad included in the first pad group corresponds one-to-one to each pin included in the target memory chip 32. Specifically, the arrangement array of each pad included in the first pad group is the same as the arrangement array of each pin included in the target memory chip 32, and the number of pads included in the first pad group is equal to the number of pins included in the target memory chip 32.

[0321] In some embodiments, sizes of each memory chip in the at least two memory chips are the same.

[0322] Therefore, the same circuit board 31 in the embodiment of the present application can be compatible with at least two memory chips. Moreover, the at least two memory chips compatible with the same circuit board 31 include but are not limited to at least two of the first UFS memory chip, the second UFS memory chip, and the EMMC memory chip.

[0323] The above specific implementation methods further illustrate the purpose, technical solutions and beneficial effects of this application in detail. It should be understood that the above are only specific implementation methods of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of this application should be included in the scope of protection of this application.

Claims

1. A circuit board, characterized in that: The circuit board is used to carry a target memory chip, wherein the target memory chip includes any one of at least two memory chips, the number of pins of each memory chip in the at least two memory chips is equal, and the pin arrangement of each memory chip in the at least two memory chips is the same; The circuit board includes a first pad group, the first pad group is used to connect to the target memory chip; the first pad group includes a plurality of first pads, each of the first pads is connected to at least two routing lines, at least part of each routing line connected to the first pads includes a first jump selection area, and the routing at the first jump selection area is disconnected; In the case where the circuit board is used to carry the target memory chip, the target routing connected to at least part of the first pad includes the first jump selection area for assembling a jump selection element, and the target routing is one of the at least two routings connected to the first pad that corresponds to the target memory chip.

2. The circuit board according to claim 1, characterized in that: The target memory chip includes a first memory chip or a second memory chip; Each of the first pads is connected to two routing lines, and at least part of the two routing lines connected to the first pads include the first jump selection area; In the case where the circuit board is used to carry the first memory chip, the first jumper area included in the first routing line connected to at least part of the first pads is used to mount jumper elements; the first routing line is one of the two routing lines connected to the first pads that corresponds to the first memory chip; When the circuit board is used to carry the second storage chip, the first jump selection area included in the second routing line connected to at least part of the first pad is used to assemble a jump selection element; the second routing line is one of the two routing lines connected to the first pad that corresponds to the second storage chip.

3. The circuit board according to claim 2, characterized in that: The plurality of first pads include first-type pads, the first-type pads are used to connect to power pins of the first storage chip and / or power pins of the second storage chip, and the first-type pads are not used to connect to unused pins of the first storage chip or unused pins of the second storage chip; the circuit board is also used to carry a first power module; When the first type of pad is used to connect to the power pin of the first storage chip, the first power module is used to connect to the first type of pad through the first routing; and / or, when the first type of pad is used to connect to the power pin of the second storage chip, the first power module is used to connect to the first type of pad through the second routing.

4. The circuit board according to claim 3, characterized in that: The first routing line and the second routing line connected to the first type of pads both include the first jump selection area; In the case where the circuit board is used to carry the first memory chip, the first jumper region included in the first routing line connected to the first type of pad is used to mount a jumper element, and the first jumper region included in the second routing line connected to the first type of pad is not used to mount a jumper element; When the circuit board is used to carry the second storage chip, the first jump selection area included in the second routing line connected to the first type of pad is used to assemble a jump selection element, and the first jump selection area included in the first routing line connected to the first type of pad is not used to assemble a jump selection element.

5. The circuit board according to claim 3, characterized in that: The first routing line and / or the second routing line connected to the first power module do not include the first jump selection area, and the first routing line or the second routing line not connected to the first power module includes the first jump selection area; When the circuit board is used to carry the first storage chip, and the first type of pad is used to be connected to a power pin of the first storage chip, the first power module is used to power on the first trace connected to the first type of pad; And / or, when the circuit board is used to carry the second storage chip and the first type of pad is used to connect to the power pin of the second storage chip, the first power module is used to power on the second trace connected to the first type of pad.

6. The circuit board according to claim 5, characterized in that: The first routing line and the second routing line connected to the first power module do not include the first jump selection area; When the circuit board is used to carry the first storage chip, and the first type of pad is used to be connected to the power pin of the first storage chip, the first power module is used to power on the first wire connected to the first type of pad, and the first power module is used not to power on the second wire connected to the first type of pad; Furthermore, when the circuit board is used to carry the second storage chip and the first type of pad is used to connect to the power pin of the second storage chip, the first power module is used to power on the second routing connected to the first type of pad, and the first power module is used to not power on the first routing connected to the first type of pad.

7. The circuit board according to claim 5, characterized in that: The first routing line connected to the first power module does not include the first jump selection area, and the second routing line not connected to the first power module includes the first jump selection area; In a case where the circuit board is used to carry the first storage chip, and the first type of pad is used to be connected to a power pin of the first storage chip, the first power module is used to power on the first routing line connected to the first type of pad, and the first jump selection area included in the second routing line connected to the first type of pad is not used to mount a jump selection element; Furthermore, when the circuit board is used to carry the second storage chip and the first type of pad is used to connect to the signal pin or the ground pin of the second storage chip, the first jumper area included in the second routing connected to the first type of pad is used to assemble a jumper element, and the first power supply module is used to not power on the first routing connected to the first type of pad.

8. The circuit board according to claim 5, characterized in that: The second line connected to the first power module does not include the first jump selection area, and the first line not connected to the first power module includes the first jump selection area; In a case where the circuit board is used to carry the first storage chip, and the first type of pad is used to be connected to a signal pin or a ground pin of the first storage chip, the first jumper area included in the first routing line connected to the first type of pad is used to mount a jumper element, and the first power module is used to not power on the second routing line connected to the first type of pad; Furthermore, when the circuit board is used to carry the second storage chip, and the first type of pad is used to connect to the power pin of the second storage chip, the first power module is used to power on the second wiring connected to the first type of pad, and the first wiring connected to the first type of pad includes the first The jump area is not used to assemble jump components.

9. The circuit board according to claim 2, characterized in that: The plurality of first pads include second-type pads, and the second-type pads are used to connect with a signal pin of the first storage chip and a signal pin of the second storage chip, or to connect with a signal pin of the first storage chip and a ground pin of the second storage chip, or to connect with a ground pin of the first storage chip and a signal pin of the second storage chip; The first routing and the second routing connected to the second-type pads both include the first jump selection area; when the circuit board is used to carry the first storage chip, the first jump selection area included in the first routing connected to at least part of the second-type pads is used to assemble jump selection elements; when the circuit board is used to carry the second storage chip, the first jump selection area included in the second routing connected to the second-type pads is used to assemble jump selection elements.

10. The circuit board according to claim 2, characterized in that: The first pad group further includes a plurality of second pads, each of the second pads is connected to a routing line, and the routing line connected to the second pad is a third routing line; the third routing lines connected to some of the second pads include a second jump selection area, and the third routing lines at the second jump selection area are disconnected; and the third routing lines connected to another portion of the second pads do not include the second jump selection area; In the case where the circuit board is used to carry the first memory chip or the second memory chip, the second jumper area included in the third trace connected to at least part of the second pad is used to mount a jumper element.

11. The circuit board according to claim 10, characterized in that: The plurality of second pads include a third type of pad, and the third type of pad is used to connect with a power pin of the first memory chip and an unused pin of the second memory chip, or to connect with an unused pin of the first memory chip and a power pin of the second memory chip; The circuit board is also used to carry a second power supply module, and the second power supply module is used to be connected to the third type of pad through the third trace.

12. The circuit board according to claim 11, characterized in that: The third routing line connected to the third type of pad includes the second jump selection area; When the circuit board is used to carry the first memory chip, and the third type of pad is used to connect to the power pin of the first memory chip, the second jump region included in the third routing connected to the third type of pad is used to mount a jump element; when the circuit board is used to carry the second memory chip, and the third type of pad is used to connect to the unused pin of the second memory chip, the second jump region included in the third routing connected to the third type of pad is not used to mount a jump element; When the circuit board is used to carry the first memory chip and the third type of pad is used to connect to the unused pins of the first memory chip, the second jump selection area included in the third routing connected to the third type of pad is not used to assemble jump selection elements; when the circuit board is used to carry the second memory chip and the third type of pad is used to connect to the power pins of the second memory chip, the second jump selection area included in the third routing connected to the third type of pad is used to assemble jump selection elements.

13. The circuit board according to claim 11, characterized in that: The third routing line connected to the third type of pad does not include the second jump selection area; In the case where the circuit board is used to carry the first storage chip, and the third type of pad is used to connect to the power pin of the first storage chip, the second power module is used to connect the third type of pad to the power pin of the first storage chip. The third wiring is powered on; when the circuit board is used to carry the second storage chip and the third type of pad is used to connect to the unused pin of the second storage chip, the second power module is used not to power on the third wiring connected to the third type of pad; When the circuit board is used to carry the first storage chip and the third type of pad is used to connect to the unused pins of the first storage chip, the second power supply module is used to not power on the third routing connected to the third type of pad; when the circuit board is used to carry the second storage chip and the third type of pad is used to connect to the power pin of the second storage chip, the second power supply module is used to power on the third routing connected to the third type of pad.

14. The circuit board according to claim 10, characterized in that: The multiple second pads include a fourth type of pad, which is used to connect to unused pins of the first storage chip and / or unused pins of the second storage chip, and the fourth type of pad is not used to connect to the power pins of the first storage chip or the power pins of the second storage chip.

15. The circuit board according to claim 14, characterized in that: The third trace connected to the fourth type pad includes the second jump selection area; In the case where the circuit board is used to carry the first memory chip, and the fourth-type pad is used to connect to an unused pin of the first memory chip, the second jump region included in the third routing connected to the fourth-type pad is not used to mount a jump element; in the case where the circuit board is used to carry the second memory chip, and the fourth-type pad is used to connect to a ground pin or a signal pin of the second memory chip, the second jump region included in the third routing connected to the fourth-type pad is used to mount a jump element; When the circuit board is used to carry the first memory chip and the fourth-category pad is used to connect to the ground pin or the signal pin of the first memory chip, the second jump selection area included in the third routing connected to the fourth-category pad is used to mount a jump selection element or is not used to mount a jump selection element; when the circuit board is used to carry the second memory chip and the fourth-category pad is used to connect to the unused pin of the second memory chip, the second jump selection area included in the third routing connected to the fourth-category pad is not used to mount a jump selection element.

16. The circuit board according to claim 14, characterized in that: The third routing line connected to the fourth type pad does not include the second jump selection area.

17. The circuit board according to claim 10, characterized in that: The plurality of second pads include a fifth type of pad, and the fifth type of pad is used to connect to a ground pin of the first memory chip and a ground pin of the second memory chip; Wherein, the third routing wire connected to the fifth type of pad includes the second jump selection area; when the circuit board is used to carry the first memory chip, the second jump selection area included in the third routing wire connected to the fifth type of pad is used to assemble a jump selection element; when the circuit board is used to carry the second memory chip, the second jump selection area included in the third routing wire connected to the fifth type of pad is used to assemble a jump selection element or is not used to assemble a jump selection element; Alternatively, the third routing line connected to the fifth type of pad does not include the second jump selection area.

18. The circuit board according to claim 10, characterized in that: The circuit board also includes a second pad group, the second pad group is used to connect to the processor chip, and the circuit board is also used to carry a third power module; The plurality of second pads include a sixth type of pad, and the sixth type of pad is used to connect to the first memory chip. The power pin is connected to the power pin of the second storage chip; when the circuit board is used to carry the first storage chip, the power pin of the first storage chip is connected to the first power pin of the processor chip through the sixth type of pad, the third wiring and the third power module in sequence; when the circuit board is used to carry the second storage chip, the power pin of the second storage chip is connected to the second power pin of the processor chip through the sixth type of pad, the third wiring and the third power module in sequence; the first power pin and the second power pin are the same power pin; The third routing line connected to the sixth type of pad includes the second jump selection area; when the circuit board is used to carry the first memory chip or the second memory chip, the second jump selection area included in the third routing line connected to the sixth type of pad is used to assemble a jump selection element; Alternatively, the third routing line connected to the sixth type of pad does not include the second jump selection area; when the circuit board is used to carry the first storage chip or the second storage chip, the third power supply module is used to power on the third routing line connected to the sixth type of pad.

19. The circuit board according to any one of claims 1 to 18, characterized in that: The jump selection element includes any one of a resistor, a capacitor, a diode and a transistor.

20. The circuit board according to any one of claims 1 to 18, characterized in that: The sizes of the at least two types of memory chips are the same.

21. The circuit board according to any one of claims 1 to 18, characterized in that: The at least two storage chips include at least two of a first UFS storage chip, a second UFS storage chip and an EMMC storage chip; an interface version of the first UFS storage chip is different from an interface version of the second UFS storage chip.

22. A circuit board assembly, characterized in that: It comprises a target memory chip and a circuit board as claimed in any one of claims 1 to 21, wherein the target memory chip is connected to the circuit board.

23. An electronic device, characterized in that: It comprises a shell and a circuit board assembly as claimed in claim 22, wherein the circuit board assembly is arranged inside the shell.

24. A circuit board, characterized in that: The circuit board is used to carry a target memory chip, wherein the target memory chip includes any one of at least two memory chips, the number of pins of each memory chip in the at least two memory chips is equal, and the pin arrangement of each memory chip in the at least two memory chips is the same; The circuit board includes a first pad group, the first pad group is used to connect to the target memory chip; the first pad group includes a plurality of first pads, each of the first pads is connected to at least two routing lines, at least part of each routing line connected to the first pads includes a first jump selection area, and the routing at the first jump selection area is disconnected; In the case where the circuit board is used to carry the target memory chip, the first jumper area included in the target routing connected to at least part of the first pads is used to mount jumper elements, and the target routing is one routing corresponding to the target memory chip among the at least two routings connected to the first pads; The number of pads included in the first pad group is equal to the number of pins of the target memory chip; the first jump selection area is an unconnected area in the routing, and the jump selection component is an electronic component to be assembled.

25. The circuit board according to claim 24, characterized in that The target memory chip includes a first memory chip or a second memory chip; Each of the first pads is connected to two routing lines, and at least some of the first pads are connected to two routing lines. All include the first hopping area; In the case where the circuit board is used to carry the first memory chip, the first jumper area included in the first routing line connected to at least part of the first pads is used to mount jumper elements; the first routing line is one of the two routing lines connected to the first pads that corresponds to the first memory chip; When the circuit board is used to carry the second storage chip, the first jump selection area included in the second routing line connected to at least part of the first pad is used to assemble a jump selection element; the second routing line is one of the two routing lines connected to the first pad that corresponds to the second storage chip.

26. The circuit board according to claim 25, characterized in that The plurality of first pads include first-type pads, the first-type pads are used to connect to power pins of the first storage chip and / or power pins of the second storage chip, and the first-type pads are not used to connect to unused pins of the first storage chip or unused pins of the second storage chip; the circuit board is also used to carry a first power module; When the first type of pad is used to connect to the power pin of the first storage chip, the first power module is used to connect to the first type of pad through the first routing; and / or, when the first type of pad is used to connect to the power pin of the second storage chip, the first power module is used to connect to the first type of pad through the second routing.

27. The circuit board according to claim 26, characterized in that The first routing line and the second routing line connected to the first type of pads both include the first jump selection area; In the case where the circuit board is used to carry the first memory chip, the first jumper region included in the first routing line connected to the first type of pad is used to mount a jumper element, and the first jumper region included in the second routing line connected to the first type of pad is not used to mount a jumper element; When the circuit board is used to carry the second storage chip, the first jump selection area included in the second routing line connected to the first type of pad is used to assemble a jump selection element, and the first jump selection area included in the first routing line connected to the first type of pad is not used to assemble a jump selection element.

28. The circuit board according to claim 26, characterized in that The first routing line and / or the second routing line connected to the first power module do not include the first jump selection area, and the first routing line or the second routing line not connected to the first power module includes the first jump selection area; When the circuit board is used to carry the first storage chip, and the first type of pad is used to be connected to a power pin of the first storage chip, the first power module is used to power on the first trace connected to the first type of pad; And / or, when the circuit board is used to carry the second storage chip and the first type of pad is used to connect to the power pin of the second storage chip, the first power module is used to power on the second trace connected to the first type of pad.

29. The circuit board according to claim 28, characterized in that The first routing line and the second routing line connected to the first power module do not include the first jump selection area; When the circuit board is used to carry the first storage chip, and the first type of pad is used to be connected to the power pin of the first storage chip, the first power module is used to power on the first wire connected to the first type of pad, and the first power module is used not to power on the second wire connected to the first type of pad; Furthermore, the circuit board is used to carry the second storage chip, and the first type of pad is used to connect to the When the power pin of the second storage chip is connected, the first power module is used to power on the second routing line connected to the first type of pad, and the first power module is used not to power on the first routing line connected to the first type of pad.

30. The circuit board according to claim 28, characterized in that The first routing line connected to the first power module does not include the first jump selection area, and the second routing line not connected to the first power module includes the first jump selection area; In a case where the circuit board is used to carry the first storage chip, and the first type of pad is used to be connected to a power pin of the first storage chip, the first power module is used to power on the first routing line connected to the first type of pad, and the first jump selection area included in the second routing line connected to the first type of pad is not used to mount a jump selection element; Furthermore, when the circuit board is used to carry the second storage chip and the first type of pad is used to connect to the signal pin or the ground pin of the second storage chip, the first jumper area included in the second routing connected to the first type of pad is used to assemble a jumper element, and the first power supply module is used to not power on the first routing connected to the first type of pad.

31. The circuit board according to claim 28, characterized in that The second line connected to the first power module does not include the first jump selection area, and the first line not connected to the first power module includes the first jump selection area; In a case where the circuit board is used to carry the first storage chip, and the first type of pad is used to be connected to a signal pin or a ground pin of the first storage chip, the first jumper area included in the first routing line connected to the first type of pad is used to mount a jumper element, and the first power module is used to not power on the second routing line connected to the first type of pad; Furthermore, when the circuit board is used to carry the second storage chip and the first type of pad is used to connect to the power pin of the second storage chip, the first power module is used to power on the second routing connected to the first type of pad, and the first jump selection area included in the first routing connected to the first type of pad is not used to assemble a jump selection element.

32. The circuit board according to claim 25, characterized in that The plurality of first pads include second-type pads, and the second-type pads are used to connect with a signal pin of the first storage chip and a signal pin of the second storage chip, or to connect with a signal pin of the first storage chip and a ground pin of the second storage chip, or to connect with a ground pin of the first storage chip and a signal pin of the second storage chip; The first routing and the second routing connected to the second-type pads both include the first jump selection area; when the circuit board is used to carry the first storage chip, the first jump selection area included in the first routing connected to at least part of the second-type pads is used to assemble jump selection elements; when the circuit board is used to carry the second storage chip, the first jump selection area included in the second routing connected to the second-type pads is used to assemble jump selection elements.

33. The circuit board according to claim 25, characterized in that The first pad group further includes a plurality of second pads, each of the second pads is connected to a routing line, and the routing line connected to the second pad is a third routing line; the third routing lines connected to some of the second pads include a second jump selection area, and the third routing lines at the second jump selection area are disconnected; and the third routing lines connected to another portion of the second pads do not include the second jump selection area; When the circuit board is used to carry the first memory chip or the second memory chip, the second jumper area included in the third routing line connected to at least part of the second pad is used to assemble a jumper element; the second jumper area is an unconnected area in the third routing line.

34. The circuit board according to claim 33, characterized in that The plurality of second pads include a third type of pad, and the third type of pad is used to connect with a power pin of the first memory chip and an unused pin of the second memory chip, or to connect with an unused pin of the first memory chip and a power pin of the second memory chip; The circuit board is also used to carry a second power supply module, and the second power supply module is used to be connected to the third type of pad through the third trace.

35. The circuit board according to claim 34, characterized in that The third routing line connected to the third type of pad includes the second jump selection area; When the circuit board is used to carry the first memory chip, and the third type of pad is used to connect to the power pin of the first memory chip, the second jump region included in the third routing connected to the third type of pad is used to mount a jump element; when the circuit board is used to carry the second memory chip, and the third type of pad is used to connect to the unused pin of the second memory chip, the second jump region included in the third routing connected to the third type of pad is not used to mount a jump element; When the circuit board is used to carry the first memory chip and the third type of pad is used to connect to the unused pins of the first memory chip, the second jump selection area included in the third routing connected to the third type of pad is not used to assemble jump selection elements; when the circuit board is used to carry the second memory chip and the third type of pad is used to connect to the power pins of the second memory chip, the second jump selection area included in the third routing connected to the third type of pad is used to assemble jump selection elements.

36. The circuit board according to claim 34, characterized in that The third routing line connected to the third type of pad does not include the second jump selection area; When the circuit board is used to carry the first storage chip and the third type of pad is used to connect to the power pin of the first storage chip, the second power module is used to power on the third routing line connected to the third type of pad; when the circuit board is used to carry the second storage chip and the third type of pad is used to connect to the unused pin of the second storage chip, the second power module is used not to power on the third routing line connected to the third type of pad; When the circuit board is used to carry the first storage chip and the third type of pad is used to connect to the unused pins of the first storage chip, the second power supply module is used to not power on the third routing connected to the third type of pad; when the circuit board is used to carry the second storage chip and the third type of pad is used to connect to the power pin of the second storage chip, the second power supply module is used to power on the third routing connected to the third type of pad.

37. The circuit board according to claim 33, characterized in that The multiple second pads include a fourth type of pad, which is used to connect to unused pins of the first storage chip and / or unused pins of the second storage chip, and the fourth type of pad is not used to connect to the power pins of the first storage chip or the power pins of the second storage chip.

38. The circuit board according to claim 37, characterized in that The third trace connected to the fourth type pad includes the second jump selection area; In the case where the circuit board is used to carry the first memory chip, and the fourth-type pad is used to connect to an unused pin of the first memory chip, the second jump region included in the third routing connected to the fourth-type pad is not used to mount a jump element; in the case where the circuit board is used to carry the second memory chip, and the fourth-type pad is used to connect to a ground pin or a signal pin of the second memory chip, the second jump region included in the third routing connected to the fourth-type pad is used to mount a jump element; When the circuit board is used to carry the first memory chip and the fourth-category pad is used to connect to the ground pin or the signal pin of the first memory chip, the second jump selection area included in the third routing connected to the fourth-category pad is used to mount a jump selection element or is not used to mount a jump selection element; when the circuit board is used to carry the second memory chip and the fourth-category pad is used to connect to the unused pin of the second memory chip, the second jump selection area included in the third routing connected to the fourth-category pad is not used to mount a jump selection element.

39. The circuit board according to claim 37, characterized in that The third routing line connected to the fourth type pad does not include the second jump selection area.

40. The circuit board according to claim 33, characterized in that The plurality of second pads include a fifth type of pad, and the fifth type of pad is used to connect to a ground pin of the first memory chip and a ground pin of the second memory chip; Wherein, the third routing wire connected to the fifth type of pad includes the second jump selection area; when the circuit board is used to carry the first memory chip, the second jump selection area included in the third routing wire connected to the fifth type of pad is used to assemble a jump selection element; when the circuit board is used to carry the second memory chip, the second jump selection area included in the third routing wire connected to the fifth type of pad is used to assemble a jump selection element or is not used to assemble a jump selection element; Alternatively, the third routing line connected to the fifth type of pad does not include the second jump selection area.

41. The circuit board according to claim 33, characterized in that The circuit board also includes a second pad group, the second pad group is used to connect to the processor chip, and the circuit board is also used to carry a third power module; The plurality of second pads include a sixth type of pad, and the sixth type of pad is used to connect to a power pin of the first storage chip and a power pin of the second storage chip; when the circuit board is used to carry the first storage chip, the power pin of the first storage chip is connected to the first power pin of the processor chip in sequence through the sixth type of pad, the third wiring and the third power module; when the circuit board is used to carry the second storage chip, the power pin of the second storage chip is connected to the second power pin of the processor chip in sequence through the sixth type of pad, the third wiring and the third power module; the first power pin and the second power pin are the same power pin; The third routing line connected to the sixth type of pad includes the second jump selection area; when the circuit board is used to carry the first memory chip or the second memory chip, the second jump selection area included in the third routing line connected to the sixth type of pad is used to assemble a jump selection element; Alternatively, the third routing line connected to the sixth type of pad does not include the second jump selection area; when the circuit board is used to carry the first storage chip or the second storage chip, the third power supply module is used to power on the third routing line connected to the sixth type of pad.

42. The circuit board according to any one of claims 24 to 41, characterized in that The jump selection element includes any one of a resistor, a capacitor, a diode and a transistor.

43. The circuit board according to any one of claims 24 to 41, characterized in that The sizes of the at least two types of memory chips are the same.

44. The circuit board according to any one of claims 24 to 41, characterized in that The at least two storage chips include at least two of a first UFS storage chip, a second UFS storage chip and an EMMC storage chip; an interface version of the first UFS storage chip is different from an interface version of the second UFS storage chip.

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