Direct memory access system, data transport method, device and storage medium

Abstract

A direct memory access system, a data transport method, a device and a storage medium, which relate to the technical field of computers. The system comprises a macro instruction memory, a macro instruction controller, a macro instruction parsing engine and a data read-write transmission path. In the present application, a processor issues a macro instruction, wherein the macro instruction is used for instructing the transport of multi-dimensional structured data; the macro instruction controller sends the macro instruction to the macro instruction parsing engine; and the macro instruction parsing engine parses the macro instruction into a micro-operation code, and sends the micro-operation code to the data read-write transmission path, wherein the micro-operation code is used for instructing the transport of one-dimensional structured data in the multi-dimensional structured data. By means of the direct memory access system, the time required by the processor to generate an instruction for transporting the one-dimensional structured data, and the configuration overhead for issuing the instruction to the direct memory access system for execution can be greatly reduced, thereby improving the efficiency of data transport.

Description

Direct memory access system, data transfer method, device and storage medium

[0001] This application claims priority to the Chinese patent application filed on September 13, 2023, with application number 202311177686.7 and invention name “Direct Memory Access System, Data Transfer Method, Device and Storage Medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to a direct memory access system, a data transfer method, a device, and a storage medium. Background Art

[0003] A Direct Memory Access (DMA) system, also known as a direct data transfer hardware unit, can transfer data without the involvement of a Central Processing Unit (CPU).

[0004] In the related art, when executing data transfer, the processor in the computer device can send a data transfer instruction to the DMA system, and through the instruction, the read address, data length and write address of the data to be transferred are indicated to the DMA system. The DMA system reads the data from the bus according to the read address and data length, and writes the read data back to the bus in sequence starting from the write address.

[0005] However, in the above solution, the processor needs to first generate an instruction including a read address, data length, and write address according to the structure of the data to be moved. The instruction generation process takes a long time, thereby affecting the efficiency of data transfer.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a direct memory access system, a data transfer method, a device, and a storage medium, which can improve the efficiency of data transfer. The technical solution is as follows.

[0008] In one aspect, a direct memory access system is provided, the system comprising: a macroinstruction memory, a macroinstruction controller, a macroinstruction parsing engine, and a data read and write transmission path;

[0009] The macro instruction memory and the macro instruction controller are respectively connected to a processor in a computer device, and the macro instruction memory is connected to the macro instruction controller;

[0010] The macro instruction controller is connected to the macro instruction parsing engine, the macro instruction parsing engine is connected to the data reading and writing transmission path, and the data reading and writing transmission path is connected to the bus of the computer device;

[0011] The macroinstruction memory is used to store macroinstructions issued by the processor; the macroinstructions are used to instruct the transport of multi-dimensional structure data;

[0012] The macro instruction controller is configured to receive a trigger instruction issued by the processor, read the macro instruction from the macro instruction memory according to the trigger instruction, and send the macro instruction to the macro instruction parsing engine;

[0013] The macroinstruction parsing engine is used to parse the macroinstruction into a micro-operation code and send the micro-operation code to the data read and write transmission path; the micro-operation code is used to instruct the transfer of one-dimensional structure data in the multi-dimensional structure data;

[0014] The data read and write transmission path is used to read and write the one-dimensional structure data to the bus according to the micro-operation code.

[0015] On the other hand, a data transfer method is provided. The method is used in the direct memory access system as described above and is executed by a macro controller in the direct memory access system. The method includes:

[0016] Receive the trigger instruction issued by the processor;

[0017] Reading the macro instruction from the macro instruction memory according to the trigger instruction; the macro instruction is used to instruct the transport of multi-dimensional structure data;

[0018] The macroinstruction is sent to a macroinstruction parsing engine so that the macroinstruction parsing engine parses the macroinstruction into a micro-operation code, and the micro-operation code is sent to a data read and write transmission path, and the data read and write transmission path reads and writes one-dimensional structure data to the bus according to the micro-operation code; the micro-operation code is used to indicate the transfer of the one-dimensional structure data in the multi-dimensional structure data.

[0019] On the other hand, a data handling device is provided, which is used for a macro instruction controller in the direct memory access system as described above, and includes:

[0020] A trigger instruction receiving module is used to receive the trigger instruction sent by the processor;

[0021] A macro instruction reading module is used to read the macro instruction from the macro instruction memory according to the trigger instruction; the macro instruction is used to instruct the transport of multi-dimensional structure data;

[0022] The macroinstruction sending module is used to send the macroinstruction to the macroinstruction parsing engine so that the macroinstruction parsing engine can parse the macroinstruction into a micro-operation code and send the micro-operation code to the data read and write transmission path. The data read and write transmission path reads and writes one-dimensional structure data to the bus according to the micro-operation code; the micro-operation code is used to instruct the transfer of the one-dimensional structure data in the multi-dimensional structure data.

[0023] On the other hand, a computer device is provided, comprising the direct memory access system as described above.

[0024] On the other hand, a computer-readable storage medium is provided, in which at least one program is stored. The at least one program is loaded and executed by a controller to implement the data transfer method described above; the controller is a macro instruction controller in the direct memory access system described above.

[0025] On the other hand, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a controller, the computer program implements the data transfer method described above; the controller is a macro controller in the direct memory access system described above.

[0026] On the other hand, a chip is provided, comprising the direct memory access system as described above.

[0027] On the other hand, a computer device is provided, comprising the chip as described above.

[0028] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0029] What the processor sends to the DMA system is a macroinstruction for instructing the transport of multi-dimensional structured data; the macroinstruction controller in the DMA system sends the macroinstruction to the macroinstruction parsing engine; the macroinstruction parsing engine parses the macroinstruction into a micro-operation code for instructing the transport of one-dimensional structured data in the multi-dimensional structured data, and sends it to the data read-write transmission path, which executes the relocation of the one-dimensional structured data according to the micro-operation code. In the above scheme, the processor directly instructs the DMA system to transport the multi-dimensional structured data, and then the macroinstruction parsing engine in the DMA system decomposes the transport operation of the multi-dimensional structured data into multiple transport operations of one-dimensional structured data. Since the DMA system parses the macroinstruction much faster than the processor decomposes the transport operation of the multi-dimensional structured data, the above DMA system can greatly reduce the time required for the processor to generate instructions for transporting one-dimensional structured data, and reduce the configuration overhead of the processor sending the above instructions to the DMA system for execution, thereby improving the efficiency of data transport. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic diagram of a DMA system;

[0031] FIG2 is a schematic diagram of a DMA system that supports scatter-gather discrete transport;

[0032] FIG3 is a schematic diagram of the format of a DMA instruction or descriptor;

[0033] FIG4 is a flow chart of a DMA implementation of data transport;

[0034] FIG5 is a schematic structural diagram of a direct memory access system provided by an exemplary embodiment of the present application;

[0035] FIG6 is a schematic diagram illustrating an example of a hardware circuit parsing macro instructions involved in the present application;

[0036] FIG7 is a schematic structural diagram of a direct memory access system provided by another exemplary embodiment of the present application;

[0037] FIG8 is a schematic structural diagram of a direct memory access system provided by another exemplary embodiment of the present application;

[0038] FIG9 is a schematic diagram illustrating an example of format conversion involved in this application;

[0039] FIG10 is a structural diagram of a macro instruction provided by an exemplary embodiment of the present application;

[0040] FIG11 is a schematic diagram of the process of parsing and generating micro-op codes for macro instructions;

[0041] FIG12 is a micro-operation code provided by an exemplary embodiment of the present application;

[0042] FIG13 is a timing diagram of a data transport path for stream processing involved in the present application;

[0043] FIG14 is a schematic structural diagram of a direct memory access system provided by yet another exemplary embodiment of the present application;

[0044] FIG15 is a flowchart of the overall processing of data transfer by the DMA system provided by the present application;

[0045] FIG16 is a flow chart of a data transport method provided by an exemplary embodiment of the present application;

[0046] FIG17 is a schematic diagram of a data handling device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0047] Direct Memory Access (DMA), also known as a direct data transfer hardware unit, is a technology that enables data transfer without the involvement of a central processing unit (CPU). DMA transfers copy data from one address space to another, providing high-speed data transfer between peripherals and memory, or between memories.

[0048] The CPU has many functions such as transferring data, calculating, and controlling program transfer. It is the core of the system operation. The CPU is always processing a large number of transactions, but some transactions are not so important, such as data copying and storing data. If this part of the CPU resources can be saved and used by the CPU to process other complex transactions, the CPU resources can be better utilized.

[0049] Data transfers (especially large amounts of data) can be performed without CPU involvement. For example, if you want to copy data from device A to device B, as long as both devices provide a DMA data channel, the data can be directly copied from device A to device B without CPU processing. Therefore, DMA can free up the CPU to a certain extent, playing a crucial role in achieving efficient embedded systems and accelerating network data processing.

[0050] During DMA transfers, the DMA controller directly manages the bus, which introduces the issue of bus control transfer. Before a DMA transfer begins, the CPU must hand over bus control to the DMA controller. After the DMA transfer completes, the DMA controller must hand back bus control to the CPU. A complete DMA transfer typically involves four steps: DMA request, DMA response, DMA transfer, and DMA termination.

[0051] FIG1 shows a schematic diagram of a basic DMA system, as shown in FIG1 :

[0052] 1) The processor sends instructions to the DMA system, instructing the DMA system to perform data transfer operations. The DMA system interacts directly with the bus to perform data transfer operations, realizing the operation of transferring a piece of one-dimensional structured data from one storage address to another storage address;

[0053] 2) The DMA system consists of a controller, a read data interface, a first-in-first-out (FIFO) buffer, and a write data interface. The controller receives and interprets instructions from the processor, instructing the read data interface to generate read data requests from the bus and instructing the write data interface to generate write data requests from the bus. The FIFO buffer is used to cache data for asynchronous read and write operations.

[0054] 3) The processor sends transfer instructions to the DMA system one by one, instructing the DMA system to perform the transfer operation. One DMA system only corresponds to one instruction at a time.

[0055] FIG2 shows a schematic diagram of a DMA system that supports scatter-gather discrete transport, as shown in FIG2 :

[0056] 1) In this solution, the DMA system is used to batch-transfer multiple discrete data blocks, reducing the number of processor interventions and thus improving transfer efficiency. It is mainly used in scenarios where fragmented data is transferred.

[0057] 2) In this solution, a series of transfer instructions is defined as a descriptor. The processor pre-sends the instructions in batches to the descriptor linked list of the DMA system, and uses the linked list structure to express the order relationship between the instructions.

[0058] 3) The processor's instructions for instructing the DMA system to work are changed from explicit transfer instructions to trigger instructions, which trigger the DMA system to start execution from a certain position in the descriptor list.

[0059] FIG3 shows a schematic diagram of the format of a DMA instruction or descriptor.

[0060] As shown in Figures 1 and 2 above, DMA instructions or descriptors issued by the processor can instruct the DMA to directly initiate data read and write operations. Their common characteristic is that they can only handle the movement of simple one-dimensional data structures, where the one-dimensional structured data refers to a data block indicated by a starting point (such as a starting address) and a length. In other words, the one-dimensional structured data is data with continuous addresses.

[0061] Based on the DMA system structures shown in FIG1 and FIG2 , please refer to FIG4 , which shows a flow chart of DMA implementing data transfer. As shown in FIG4 , the steps of implementing data transfer in the DMA system structures shown in FIG1 and FIG2 are the same:

[0062] Step 401, receiving an instruction and determining whether to execute the instruction based on the status of the DMA system;

[0063] Step 402: If the instruction is determined to be executed, a read operation is initiated on the bus based on the read address and data size in the instruction, such as an Advanced eXtensible Interface (AXI) read transfer, Advanced Peripheral Bus (APB), Advanced High-performance Bus (AHB), or AXI Coherence Extension (ACE) read operation.

[0064] Step 403: Receive data returned from the bus and cache it into FIFO;

[0065] Step 404: Initiate a write operation to the bus according to the write address and data size in the instruction, such as an AXI write transfer, APB, AHB, ACE, or other write operation;

[0066] Step 405: write the data in the FIFO into the bus.

[0067] However, the DMA system architecture shown in Figures 1 and 2 is designed for transferring one-dimensional structured data. This means the processor must predetermine the read / write addresses and data lengths of the one-dimensional structured data to be transferred and then communicate this information to the DMA system. Because the processor determines the read / write addresses and data lengths of the one-dimensional structured data to be transferred via program code, generating a single instruction to transfer the one-dimensional structured data takes a significant amount of time. Consequently, the processor's efficiency in issuing data transfer instructions has become a bottleneck affecting data transfer efficiency.

[0068] Please refer to Figure 5, which shows a structural diagram of a direct memory access system provided by an exemplary embodiment of the present application. The system may include: a macroinstruction memory 501, a macroinstruction controller 502, a macroinstruction parsing engine 503 and a data read and write transmission path 504.

[0069] The macro instruction memory 501 and the macro instruction controller 502 are respectively connected to the processor in the computer device, and the macro instruction memory 501 is connected to the macro instruction controller 502 .

[0070] The above-mentioned processor may be a scalar processor.

[0071] The processor may be a computing device that implements computing functions by running computer instructions or codes. For example, the processor may be a central processing unit (CPU) of a computer device.

[0072] The above-mentioned macroinstruction memory 501 and macroinstruction controller 502 are respectively connected to the processor in the computer device, which means that the macroinstruction memory 501 and macroinstruction controller 502 are respectively electrically connected to the processor in the computer device, and the macroinstruction memory 501 and macroinstruction controller 502 can respectively receive instructions / signals / data sent by the processor.

[0073] The macro instruction memory 501 is connected to the macro instruction controller 502 , which means that the macro instruction memory 501 is electrically connected to the macro instruction controller 502 , and the macro instruction controller 502 can read instructions / data from the macro instruction memory 501 .

[0074] The macro memory 501 may be a random access memory (RAM), such as a resistance random access memory (ReRAM) or a dynamic random access memory (DRAM).

[0075] The macro-instruction controller 502 is connected to the macro-instruction parsing engine 503 , the macro-instruction parsing engine 503 is connected to the data reading and writing transmission path 504 , and the data reading and writing transmission path 504 is connected to the bus of the computer device.

[0076] The macro-instruction controller 502 is connected to the macro-instruction parsing engine 503 , which may mean that the macro-instruction controller 502 is electrically connected to the macro-instruction parsing engine 503 , and the macro-instruction controller 502 can send instructions / data to the macro-instruction parsing engine 503 .

[0077] The above-mentioned macro-instruction parsing engine 503 is connected to the data read-write transmission path 504 , which means that the macro-instruction parsing engine 503 is electrically connected to the data read-write transmission path 504 , and the macro-instruction parsing engine 503 can send instructions / data to the data read-write transmission path 504 .

[0078] The above-mentioned data read and write transmission path 504 and the bus of the computer device mean that the data read and write transmission path 504 is electrically connected to the bus interface of the computer device, and the data read and write transmission path 504 can read data from the bus of the computer device (or, read data from other memories of the computer device / memory connected to the computer device through the bus), and write data to the bus of the computer device (or, write data to other memories of the computer device / memory connected to the computer device through the bus).

[0079] The macroinstruction memory 501 is used to store macroinstructions issued by the processor; the macroinstructions are used to instruct the transport of multi-dimensional structured data.

[0080] In an embodiment of the present application, when it is necessary to move data of a complex structure (that is, a multi-dimensional structure), the processor of the computer device may not need to disassemble the multi-dimensional structure data, but directly generate a macro instruction indicating the read and write address and data volume of the multi-dimensional structure data, and send the macro instruction to the macro instruction memory 501 for storage by the macro instruction memory 501.

[0081] The macro instruction controller 502 is configured to receive a trigger instruction sent by the processor, read a macro instruction from the macro instruction memory 501 according to the trigger instruction, and send the macro instruction to the macro instruction parsing engine 503 .

[0082] When the computer device needs to transfer certain multi-dimensional structure data, the macro instruction controller 502 may be triggered by a trigger instruction to specify a macro instruction corresponding to the transfer operation of the multi-dimensional structure data.

[0083] The trigger instruction may indicate a macro instruction stored in the macro instruction memory 501 . For example, the trigger instruction may include an address of a macro instruction stored in the macro instruction memory 501 .

[0084] In some embodiments, one trigger instruction may instruct the macroinstruction controller 502 to retrieve a single macroinstruction, or one trigger instruction may instruct the macroinstruction controller 502 to retrieve multiple macroinstructions.

[0085] When a trigger instruction instructs the macroinstruction controller 502 to extract multiple macroinstructions, the trigger instruction can include the addresses of the multiple macroinstructions respectively; the macroinstruction controller 502 extracts the multiple macroinstructions respectively according to the addresses of the multiple macroinstructions. This solution has no restrictions on the storage locations of the multiple macroinstructions in the macroinstruction memory 501, and can expand the indication scenarios of multiple macroinstructions.

[0086] Alternatively, if the multiple macroinstructions are macroinstructions stored continuously in the macroinstruction memory 501, the trigger instruction can include the starting addresses and instruction numbers of the multiple macroinstructions, and the macroinstruction controller 502 can read the multiple macroinstructions in sequence starting from the starting address. In this solution, the trigger instruction only needs to carry an address and an instruction number, that is, it can instruct the macroinstruction controller 502 to extract multiple macroinstructions, which can save the transmission resources of the trigger instruction and improve the indication efficiency of the macro instruction.

[0087] The macroinstruction parsing engine 503 is used to parse the macroinstruction into a micro-operation code and send the micro-operation code to the data read / write transmission path 504; the micro-operation code is used to instruct the transfer of one-dimensional structure data in the multi-dimensional structure data.

[0088] In the embodiment of the present application, the macroinstruction parsing engine 503 can parse the macroinstruction through a hardware circuit to parse a macroinstruction into multiple micro-operation codes, and send the micro-operation codes to the data read and write transmission path 504.

[0089] The multidimensional structured data is composed of multiple pieces of one-dimensional structured data. The addresses of the multidimensional structured data may be continuous, or the addresses of the multidimensional structured data may be discontinuous. For example, among the multiple pieces of one-dimensional structured data that make up the multidimensional structured data, the addresses of each piece of one-dimensional structured data are continuous, while the addresses of different pieces of one-dimensional structured data are discontinuous.

[0090] For example, assuming that the multidimensional structure data is an n×m two-dimensional structure data, it can be regarded as a matrix composed of n one-dimensional structure data, and the length of each one-dimensional structure data is m; or, the n×m two-dimensional matrix data can also be regarded as a matrix composed of m one-dimensional structure data, and the length of each one-dimensional structure data is n.

[0091] Please refer to FIG6 , which shows an example schematic diagram of a hardware circuit parsing macro instruction involved in this application. As shown in FIG6 , a filling instruction of a two-dimensional data block includes the following instruction configuration:

[0092] Basic configuration:

[0093] data_type=INT32, dimen_0_size=0xA, dimen_1_size=0x2, read_addr=0x0, write_addr=0x0;

[0094] Extended configuration:

[0095] op_type=pad_op, left_pad_size=0x1, right_pad_size=0x1, top_pad_size=0x1, buttom_pad_size=0x1, internal_pad_size=0x1;

[0096] Among them, 0x represents a hexadecimal value.

[0097] The macro instruction parsing engine 503 parses a two-dimensional data block into five one-dimensional transport instructions, namely, three one-dimensional constant filling micro operations (uOPs) and two one-dimensional transport micro operations, specifically including:

[0098] uOP 1:

[0099] uop_type=constant_filling,data_type=INT32,data_size=left_pad_size+dimen_0_size+right_pad_size+right_pad_size=0xD,read_addr=NA,write_addr=0x0;

[0100] uOP 2:

[0101] uop_type=read_write,data_type=INT32,data_size=dimen_0_size=0xA,read_addr=0x0,write_addr=uop1_write_addr+uop1_data_size=0xD;

[0102] uOP 3:

[0103] uop_type=constant_filling,data_type=INT32,data_size=left_pad_size+left_pad_size+dimen_0_size+right_pad_size+right_pad_size=0xE,read_addr=NA,write_addr=uop2_write_addr+uop2_data_size=0xD+0xA=0x17;

[0104] uOP 4:

[0105] uop_type=read_write,data_type=INT32,data_size=dimen_0_size=10,read_addr=uop2_read_addr+uop2_data_size=0xA,write_addr=uop3_write_addr+uop3_data_size=0x17+0xE=0x25;

[0106] uOP 5:

[0107] uop_type=constant_filling, data_type=INT32, data_size=left_pad_size+left_pad_size+dimen_0_size+right_pad_size=0xD, read_addr=NA, write_addr=uop4_write_addr+uop4_data_size=0x25+0xA=0x2F;

[0108] Among them, 0x represents a hexadecimal value.

[0109] The above-mentioned macroinstruction parsing engine 503 can parse macroinstructions through hardware circuits, and determine the read and write addresses and data sizes of each one-dimensional structure data in the multidimensional structure data (the data structure is fixed to one dimension) according to the data structure, read and write addresses and data size of the multidimensional structure data in the macroinstructions, thereby generating corresponding micro-operation codes.

[0110] The data read and write transmission path 504 is used to read and write one-dimensional structured data to the bus according to the micro-operation code.

[0111] For example, for a micro-operation code, which includes the read address, write address and data size of one-dimensional structure data, the above-mentioned read address can be the starting address for data reading, and the above-mentioned write address can be the starting address for data writing; the data read and write transmission path 504 can first read the one-dimensional structure data of the length corresponding to the above-mentioned data size from the read address through the bus according to the read address, and then cache the one-dimensional structure data in the data read and write transmission path 504, and then, according to the write address, write the above-mentioned one-dimensional structure data in sequence from the write address through the bus, thereby completing the transfer of the one-dimensional structure data from the read address to the write address; wherein, for multiple micro-operation codes obtained by parsing a macro instruction, when the above-mentioned multiple micro-operation codes are processed, it can be considered that the transfer of the multi-dimensional structure data corresponding to the above-mentioned macro instruction is completed.

[0112] In summary, in the solution shown in the embodiment of the present application, the processor sends a macro instruction to the DMA system, which is used to instruct the transport of multi-dimensional structure data; the macro instruction controller in the DMA system sends the macro instruction to the macro instruction parsing engine; the macro instruction parsing engine parses the macro instruction into a micro operation code for instructing the transport of one-dimensional structure data in the multi-dimensional structure data, and sends it to the data read and write transmission path, and the data read and write transmission path executes the relocation of the one-dimensional structure data according to the micro operation code. In the above solution, the processor directly instructs the DMA system to transport the multi-dimensional structure data, and then the macro instruction parsing engine in the DMA system disassembles the transport operation of the multi-dimensional structure data into multiple transport operations of one-dimensional structure data. Since the speed at which the DMA system parses the macro instruction is much faster than the speed at which the processor disassembles the transport operation of the multi-dimensional structure data, the above DMA system can greatly reduce the time required for the processor to generate the instruction for transporting the one-dimensional structure data, as well as the configuration overhead of sending the above instruction to the DMA system for execution, thereby improving the efficiency of data transport.

[0113] Based on the DMA system structure shown in Figure 1 or Figure 2 above, the transfer of complex data structures in the computing system is generally first broken down by the processor into specific transfer data sizes and source and destination addresses (corresponding to the above-mentioned read addresses and write addresses), and then sent to the DMA for transfer. This system cannot meet the storage and computing bandwidth requirements of heterogeneous processors (such as AI processors and image / video encoding chips) for parallel data transmission, as well as the transfer requirements of complex data structures.

[0114] Specifically, the DMA system structure shown in Figure 1 or Figure 2 can only handle the transfer of simple one-dimensional data structures, that is, data blocks with only a starting point and length. This feature cannot be directly handled by DMA in the currently popular AI inference training processors when faced with complex and diverse data structures. It needs to be processed through software methods, that is, the internal processor uses a scalar instruction data structure to perform disassembly, which is disassembled into segments of exact lengths. Data blocks with read and write addresses can only be sent to DMA for transfer. This often requires a large amount of processor hardware resources and time, resulting in the effective performance of other business programs executed by the processor being reduced.

[0115] At the same time, the powerful computing power of artificial intelligence (AI) reasoning training processors requires very high data transfer bandwidth support to be fully utilized. The more serious impact of the above problem is that the conventional processor executes the data structure disassembly and then generates the transfer instruction processing, which takes too long, resulting in the data transfer bandwidth not meeting expectations. The bottleneck lies not in the DMA transfer performance, but in the link where the processor disassembles the complex data structure and then generates DMA instructions. The specific reason is that the disassembly process of a complex data structure may be implemented by the processor through a program segment, which requires a series of links such as instruction fetch, instruction parsing, instruction issuance, instruction execution pipeline, instruction writeback, instruction retirement, etc., and it is necessary to handle the dependencies between the previous and next instructions. This results in the processor needing to complete dozens or even hundreds of clock cycles to execute the program segment that disassembles a complex data structure and generates DMA instructions.

[0116] Based on the technical solution of the embodiment shown in FIG. 5 of the present application, a DMA system is provided that can automatically parse complex instruction sequences and efficiently transfer them, and has the function of synchronizing data with the processor and other subsystems:

[0117] 1) This DMA system can be applied to AI inference and training chips, the transfer of complex data structures, and scenarios where high computing power requires high transfer bandwidth;

[0118] 2) The DMA system can also be used in image codec chips, which have the same usage scenarios as AI reasoning and training, namely the scenario of moving complex data structures.

[0119] Based on the embodiment shown in FIG5 , please refer to FIG7 , which shows a schematic structural diagram of a direct memory access system provided by another exemplary embodiment of the present application. As shown in FIG7 , in the DMA system shown in FIG5 , a data read and write transmission path 504 includes multiple processing units, and the multiple processing units include at least a read data interface unit 504 a, a cache unit 504 b, and a write data interface unit 504 c.

[0120] The macro-instruction parsing engine 503 is connected to the read data interface unit 504a, and the macro-instruction parsing engine 503 is used to send the micro-operation code to the read data interface unit 504a;

[0121] The above-mentioned micro-operation codes are used to be transmitted sequentially among multiple processing units.

[0122] In an embodiment of the present application, the macroinstruction parsing engine 503 is connected to the read data interface unit 504a, which means that the macroinstruction parsing engine 503 is electrically connected to the read data interface unit 504a, so that the macroinstruction parsing engine 503 can send a signal to the read data interface unit 504a, thereby being able to send the micro-operation code to the read data interface unit 504a.

[0123] In an embodiment of the present application, multiple processing units in the above-mentioned data read and write transmission path 504 are connected in sequence, and during the data transfer process, starting from the read data interface unit 504a, the read data interface unit 504a receives the micro-operation code sent by the macro-instruction parsing engine 503, reads the one-dimensional structure data from the bus according to the micro-operation code, and sends the one-dimensional structure data and the micro-operation code together to the next processing unit. After a processing unit receives the one-dimensional structure data and micro-operation code sent by the previous processing unit, it passes the one-dimensional structure data and the micro-operation code to the next processing unit. If the micro-operation code instructs the current processing unit to perform a certain processing on the one-dimensional structure data, the current processing unit can also perform corresponding processing on the one-dimensional structure data, and then pass the processed one-dimensional structure data and micro-operation code to the next processing unit. After the write data interface unit 504c receives the one-dimensional structure data and micro-operation code sent by the previous processing unit, it writes the one-dimensional structure data into the bus according to the micro-operation code. In the above process, the macroinstruction parsing engine 503 only needs to send the micro-op code to the read data interface unit 504a, and does not need to send it to each processing unit that needs the micro-op code, which reduces the design and wiring difficulty of the DMA system. At the same time, it also reduces the bandwidth requirement between the macroinstruction parsing engine 503 and the data read and write transmission path 504, and improves the efficiency of the macroinstruction parsing engine 503 in transmitting micro-op codes to the data read and write transmission path 504.

[0124] Based on the embodiment shown in Figure 5 or Figure 7, in some embodiments, the macroinstruction parsing engine 503 is used to parse the data structure of the multidimensional structure data when parsing the macroinstruction into a micro-operation code, determine the read and write addresses and data size of the one-dimensional structure data in the multidimensional structure data; and generate a micro-operation code based on the read and write addresses and data size of the one-dimensional structure data.

[0125] Among them, the above-mentioned macroinstructions may include information such as the read address, write address, data structure, and data size of the multi-dimensional structure data. Combined with the data structure and data size of the above-mentioned multi-dimensional structure data, the macroinstruction parsing engine 503 can determine the data size of each one-dimensional structure data in the multi-dimensional structure data, and then combined with the read address and write address of the multi-dimensional structure data, the read address and write address of each one-dimensional structure data can be determined. Then, the macroinstruction parsing engine 503 can generate a micro-operation code containing the read address, write address and data size of the one-dimensional structure data, and each one-dimensional structure data can correspond to a micro-operation code.

[0126] Among them, the data structure of the above-mentioned multidimensional structured data may include the original data structure of the multidimensional structured data (also called the source-end data structure), and may also include the data structure of the multidimensional structured data after being moved (also called the destination-end data structure); among them, if the data structure of the multidimensional structured data only contains the source-end data structure, it can be considered that the data structure of the multidimensional structured data after being moved remains unchanged; if the data structure of the multidimensional structured data also includes the destination-end data structure, it is considered that the data structure of the multidimensional structured data after being moved changes.

[0127] Based on the embodiment shown in FIG7 , please refer to FIG8 , which shows a schematic structural diagram of a direct memory access system provided by another exemplary embodiment of the present application. As shown in FIG8 , in the DMA system shown in FIG7 , the macroinstruction is further used to instruct the execution of format conversion processing on multi-dimensional structure data, and the micro-operation code is further used to instruct the execution of format conversion processing on one-dimensional structure data;

[0128] The multiple processing units further include at least one of a pre-format conversion processing unit 504d and a post-format conversion processing unit 504e. The pre-format conversion processing unit 504d is located before the cache unit, and the post-format conversion processing unit 504e is located after the cache unit. The pre-format conversion processing unit 504d being located before the cache unit may mean that, in the order in which the multiple processing units are sequentially connected, the pre-format conversion processing unit is located before the cache unit. Correspondingly, the post-format conversion processing unit 504e being located after the cache unit may mean that, in the order in which the multiple processing units are sequentially connected, the post-format conversion processing unit is located after the cache unit.

[0129] The format conversion pre-processing unit 504d is used to perform format conversion pre-processing on the one-dimensional structure data according to the format conversion processing method indicated by the micro-operation code, and write the result data of the format conversion pre-processing into the cache unit 504b;

[0130] The format conversion post-processing unit 504e is configured to perform format conversion post-processing on the data in the cache unit 504b according to the format conversion processing mode indicated by the micro-operation code, and then send the data to the next processing unit.

[0131] The format conversion of data may include one or more combinations of data space conversions such as data type conversion, shifting, splicing, elimination, interleaving, mirroring, and filling. In traditional DMA systems, these are usually implemented by the processor through a combination of executing program instructions; in an embodiment of the present application, at least one processing unit of the format conversion pre-processing unit and the format conversion post-processing unit is set at at least one place before or after the cache unit to implement data format conversion through hardware circuits, thereby improving the efficiency of data format conversion.

[0132] Some format conversion operations need to be completed in several steps. Therefore, in the embodiment of the present application, a "pre-processing-cache-post-processing" structure is set in the data read and write transmission path 504 to process the data format conversion process step by step. For example, the format conversion operation of data mirroring + tail padding requires that a piece of data be segmented and reversed in the pre-processing and stored in the cache. The data is then retrieved in reverse order during the post-processing process, and finally output to the downstream after tail padding. There are many types of data format conversion operations, and each format conversion operation can correspond to a different format conversion pre-processing unit 504d or format conversion post-processing unit 504e. Generally speaking, a DMA structure can support a limited number of conversion types.

[0133] Please refer to Figure 9, which shows an example schematic diagram of the format conversion involved in the present application. As shown in Figure 9, the data format conversion operation is to broadcast a group of one-dimensional data (7, 8, 9) into a group of two-dimensional arrays ((7, 7, 7), (8, 8, 8), (9, 9, 9)). The hardware circuit involved includes at least the following circuit units: a multiplexer, a counter, and a replication unit.

[0134] Among them, the counter accumulates from 0 to N-1 (N is the number of elements in the input one-dimensional array) as the selection signal of the multiplexer, selects each element of the read data in turn, and copies each element through the broadcast number of the replication unit and writes it into the cache unit. The number of copies is the broadcast number configured by the instruction.

[0135] As shown in Figure 9, broadcasting a set of one-dimensional data (7, 8, 9) into a set of two-dimensional arrays ((7, 7, 7), (8, 8, 8), (9, 9, 9)) requires one read operation and three copy operations. Specifically, the following steps are required:

[0136] Step 1: Perform a read operation to input the one-dimensional data (7, 8, 9) into the format conversion pre-processing unit, and then perform a copy operation to obtain (7, 7, 7);

[0137] Step 2: Perform the second copy operation to obtain ((7, 7, 7), (8, 8, 8));

[0138] Step 3: Perform the third copy operation and finally obtain the two-dimensional array ((7, 7, 7), (8, 8, 8), (9, 9, 9)).

[0139] In some embodiments, the macro instruction includes a first format conversion configuration, which is a configuration for performing format conversion on the multi-dimensional structured data; for example, the first format conversion configuration may indicate a method for performing format conversion on the multi-dimensional structured data;

[0140] The macroinstruction parsing engine 503 is configured to generate a second format conversion configuration based on the first format conversion configuration when generating micro-operation codes based on the read / write addresses and data size of the one-dimensional structure data. The second format conversion configuration is a configuration for performing format conversion on the one-dimensional structure data. For example, the second format conversion configuration may indicate a method for performing format conversion on the one-dimensional structure data.

[0141] A micro-operation code is generated according to the read and write addresses, data size, and the second format conversion configuration of the one-dimensional structure data.

[0142] In an embodiment of the present application, when the DMA system supports data format conversion, a format conversion configuration can be set in the micro-operation code to support the control of the format conversion operation and improve the application flexibility of the format conversion.

[0143] In order to implement the format conversion configuration in the micro-op code, it is necessary to indicate it in the macro instruction. Since the macro instruction is an instruction set for multi-dimensional structure data, the format conversion configuration therein is also a format conversion configuration corresponding to the multi-dimensional structure data setting. Therefore, when the macro instruction parsing engine 503 parses the macro instruction to generate the micro-op code, it is necessary to generate the format conversion configuration for the one-dimensional structure data in the micro-op code according to the format conversion configuration set for the multi-dimensional structure data in the macro instruction, or in other words, according to the format conversion configuration set for the multi-dimensional structure data in the macro instruction, execute the update of the format conversion configuration to obtain the format conversion configuration for the one-dimensional structure data in the micro-op code.

[0144] In one possible implementation, in the process of generating a format conversion configuration for one-dimensional structure data in a micro-operation code based on the format conversion configuration set for multi-dimensional structure data in a macro instruction, the macro instruction parsing engine 503 can query the pre-stored correspondence between the first format conversion configuration and the second format conversion configuration to determine the second format conversion configuration corresponding to the first format conversion configuration.

[0145] In some embodiments, as shown in FIG8 , in the DMA system shown in FIG7 , the macroinstruction is further used to instruct the execution of an operation process on multi-dimensional structured data, and the micro-operation code is further used to instruct the execution of an operation process on one-dimensional structured data;

[0146] The multiple processing units also include a data operation unit 504f;

[0147] The data operation unit is used to perform operation processing on the input data according to the operation processing method indicated by the micro-operation code, and then send it to the next processing unit.

[0148] The above-mentioned data operations may include data type conversion, such as converting 32-bit integer type (32-bit integer, INT32) to FP32, and data calculations, such as the arithmetic and logic unit (ALU) of addition, subtraction, multiplication and division. These calculation operations can be implemented through hardware circuits, so that some data operations can be pre-executed in the DMA system to facilitate subsequent data processing, such as subsequent AI reasoning or training, or subsequent image encoding and decoding.

[0149] In some embodiments, the macroinstructions and micro-ops each include an operation configuration, which is a configuration of an operation process. For example, the operation configuration can be used to indicate the operation process mode, for example, the operation configuration can indicate that the operation process mode is one or more combinations of addition, subtraction, multiplication, division, and the like.

[0150] In the embodiment of the present application, when the DMA system supports data operations, the operation configuration can be set in the micro-op code to support the control of the operation and improve the application flexibility of the operation. To achieve the setting of the operation configuration in the micro-op code, it is necessary to indicate it in the macro instruction.

[0151] In some embodiments, as shown in FIG8 , in the DMA system shown in FIG7 , the macroinstruction and the micro-operation code further include a synchronization configuration, where the synchronization configuration is used to instruct to perform a status check on a target address, where the target address is at least one of a read address and a write address of data;

[0152] The macro instruction controller 502 is configured to check the state of the target address according to the synchronization configuration in the macro instruction when sending the macro instruction to the macro instruction parsing engine 503, and send the macro instruction to the macro instruction parsing engine 503 when the state of the target address meets a specified condition; the specified condition includes: when the target address includes a read address, the state of the read address is readable; when the target address includes a write address, the state of the write address is writable;

[0153] a read data interface unit 504a, configured to read one-dimensional structure data from the read address when the target address includes the read address and the state of the read address is readable;

[0154] The write data interface unit 504c is configured to write data to the write address when the target address includes the write address and the state of the write address is writable.

[0155] The synchronization status mentioned above refers to the status of the source end (i.e., the external device or memory from which data is read) and the sink end (i.e., the external device or memory to which data is written), i.e., whether the source end is readable and whether the sink end is writable. These status bits are generally represented by a 1-bit status bit. These status bits are stored in the processor and are globally visible. There are typically multiple groups, such as 32, to meet the read and write requirements of multiple DMA channels or arithmetic units. Optionally, each status group can have an identity document (ID).

[0156] For example, if a macroinstruction is configured with "Check the read status of ID0, but not the write status," the DMA system will first check whether ID0 is readable before executing a read operation on the address corresponding to the macroinstruction. Only if it is readable will the read operation be initiated. After the read operation is complete, the processor is notified to update the read status. For write operations, since the macroinstruction is configured not to check the status, the write operation is initiated directly. This process prioritizes the issuance of macroinstructions that can immediately execute data transfers, improving data transfer efficiency.

[0157] Among them, the above-mentioned synchronization check operation can be executed respectively in the macroinstruction controller 502, the read data interface unit 504a and the write data interface unit 504c, which requires setting the above-mentioned synchronization configuration in both the macroinstruction and the micro-operation code. Accordingly, the macroinstruction controller 502, the read data interface unit 504a and the write data interface unit 504c can first check the status of the read address / write address before executing the macroinstruction issuance, reading data and writing data, and determine whether to perform the corresponding operation based on the status of the read address / write address.

[0158] Among them, for the macroinstruction controller 502, when the result of the synchronization check is that the conditions are not met, the current macroinstruction can be stored in the instruction waiting queue, and the next macroinstruction can be processed. After waiting for a period of time, the synchronization check can be performed again on the macroinstructions in the instruction waiting queue to improve the concurrent processing capability of the macroinstructions.

[0159] Please refer to Figure 10, which shows a structure diagram of a macro instruction provided by an exemplary embodiment of the present application. As shown in Figure 10, the present application provides a DMA macro instruction for expressing multi-dimensional complex data structures and data operations such as transport, format conversion, and calculation.

[0160] Except for the read and write addresses, which describe the starting and destination addresses of the transfer in the same way as ordinary DMA instructions, the contents of other fields are described as follows.

[0161] 1) Source data structure:

[0162] a. Source data block structure information, including data types such as half-precision floating point (FP16), 8-bit integer (INT8), and single-precision floating point (FP32).

[0163] b. Data dimension information, i.e., the size of dimension 0, dimension 1, dimension 2, dimension 3, etc., that is, a data block is no longer described in traditional bytes, but is described in a data structure.

[0164] 2) Destination data structure: The destination data structure also includes data type and data dimension information, but its type and size can be different from those on the source. This represents the operation of extracting a portion of a multidimensional data block and performing data type conversion. This operation is particularly common in AI reasoning and training.

[0165] 3) Format conversion operation configuration: including but not limited to matrix transposition, data broadcasting, data mirroring, data padding, data shifting, data splicing and other operations.

[0166] 4) Operation configuration: including but not limited to data type conversion (such as FP32 to FP16), data accumulation, activation (RELU) operations, and other operations.

[0167] 5) Number of loops: A macro instruction can be executed once or multiple times.

[0168] 6) Read stepping and write stepping: in conjunction with the loop operation, the read and write address steps for each loop.

[0169] 7) Synchronization configuration: mainly includes synchronization check enable, synchronization update enable, and synchronization relationship ID of the source and sink ends.

[0170] Based on the macro instruction shown in FIG10 , a schematic diagram of the process of parsing the macro instruction to generate micro-op codes can be shown in FIG11 . FIG11 shows a schematic diagram of the process of parsing the macro instruction to generate micro-op codes, which specifically includes the following steps:

[0171] Step 1101: Analyze the macro instruction loop operation and update the read and write start address according to the read and write step;

[0172] Step 1102: parse the multidimensional data structure (corresponding to the multidimensional structure data above), extract the one-dimensional vector (corresponding to the one-dimensional structure data above), and calculate the vector read and write address and size;

[0173] Step 1103: Update other format conversion configurations based on the parsed one-dimensional vector;

[0174] Step 1104: Generate DMA micro-operation code (uOP).

[0175] In the above step 1103, updating other format conversion configurations refers to updating the size of the data involved in the format conversion and updating the dimension, because the complex data at this time has been reduced from multi-dimensional to single-dimensional.

[0176] Please refer to Figure 12, which shows a micro-op code provided by an exemplary embodiment of the present application. As shown in Figure 12, the present application describes a DMA micro-op code, which is similar to the content of a traditional DMA instruction or descriptor, consisting of "read / write address + data size", and newly added format conversion configuration and operation configuration fields, which are used to indicate the format conversion pre / post-processing module and data operation module respectively.

[0177] Based on the micro-op code shown in Figure 12 above, please refer to Figure 13, which shows a working timing diagram of a data transfer path for streaming processing involved in this application. As shown in Figure 13, the micro-op code generated by the parsing engine only needs to be passed to the read data interface module of the first-level link. In each subsequent link, the module only extracts the domain segment needed by this module, and after processing, the micro-op code and data (Date, D) are synchronously passed to the next-level module. This solves the problem of the front-to-back dependency of the control unit in the traditional DMA, which needs to transmit the control word to each module in the data channel separately and coordinate the working rhythm of each module.

[0178] Based on the embodiment shown in FIG. 5 , FIG. 7 or FIG. 8 , the above DMA system may further support multiple virtual channels to support simultaneous scheduling of multiple processors.

[0179] In some embodiments, based on the embodiment shown in Figure 8, please refer to Figure 14, which shows a structural diagram of a direct memory access system provided by another exemplary embodiment of the present application. As shown in Figure 14, in the DMA system shown in Figure 8, the macroinstruction controller 502 is used to receive macroinstructions sent by multiple processors respectively through multiple virtual channels 505, and send the macroinstructions sent by multiple processors respectively to the macroinstruction parsing engine 503 in sequence according to the priorities of the multiple virtual channels 505.

[0180] As shown in Figure 14, the DMA system involved in the embodiment of the present application can also add virtual channels to support simultaneous use by multiple users. As shown in Figure 14, multiple processors can simultaneously issue instructions to the DMA system. Each processor can register a DMA virtual channel. The DMA system controller can execute the corresponding trigger instructions in sequence based on the priority of each virtual channel.

[0181] As shown in any one of FIG. 5 , FIG. 7 , FIG. 8 and FIG. 14 , the DMA system provided in this application has the following characteristics.

[0182] 1) In this application, the processor sends a macro instruction to the DMA system, which describes a multi-dimensional complex data structure and its data operations such as transportation, format conversion, and calculation.

[0183] 2) The processor can issue macro instructions of the DMA system in batches and write them into the macro instruction memory of the DMA system.

[0184] 3) The processor issues a trigger instruction to instruct the DMA system to start executing the macroinstructions. The content of the trigger instruction may be the starting execution address in the macroinstruction memory of the DMA system and the number of instructions.

[0185] 4) The DMA system can execute multiple macroinstructions in batches. Since each macroinstruction may have data dependencies with other components in the chip, each macroinstruction can be configured with synchronization information. The DMA system checks the synchronization relationship and makes its own decisions on the timing of executing each instruction.

[0186] 5) The macroinstruction controller of the DMA system receives the trigger instruction from the processor, reads the macroinstruction from the macroinstruction memory, performs pre-parsing, checks the synchronization relationship, and determines whether to send the instruction to the parsing engine or store it in the waiting queue.

[0187] 6) The DMA system has a built-in macro-instruction parsing engine, which parses complex instructions through hardware circuitry, rather than requiring the processor to execute a program to parse complex instructions. The macro-instruction parsing engine primarily handles data structure parsing, breaking down abstract multi-dimensional data structures into multiple micro-ops recognizable by downstream data paths: read / write address + data size + configuration.

[0188] 7) In the data read and write transmission path component units of the DMA system of the present application, in addition to the traditional DMA read and write interface module and cache module, a format conversion module and a data operation module can be added. The purpose is to perform format conversion and some calculation operations along the data transmission path to achieve data processing without bandwidth loss.

[0189] 8) The present application provides a streaming DMA system. After the module processing of each link is completed, the load (data or instructions) and control words (synchronization relationship, instructions or micro-operation codes) are passed to the module of the next link, and then new processing operations can be received. There is no dependency between the modules in the previous and next links.

[0190] The overall processing flow chart of the DMA system for data transfer provided by this application can be shown in Figure 15. Please refer to Figure 15, the specific process is as follows:

[0191] Step 1501: Receive a DMA trigger instruction;

[0192] Step 1502: Read the DMA macro instruction according to the address carried by the trigger instruction;

[0193] Step 1503: Pre-parse the macro instructions and perform synchronization relationship check according to the synchronization configuration;

[0194] If synchronization fails, the macro instruction is transferred to the instruction waiting queue and synchronization checks are performed until synchronization succeeds;

[0195] If the synchronization is successful, proceed to the next step;

[0196] Step 1504: Parse the macroinstruction into micro-op codes;

[0197] Step 1505: Generate a read operation to the bus according to the instruction read address and data size, such as AXI read transfer, APB, AHB, ACE, etc. read operation;

[0198] Step 1506: Perform format conversion pre-processing according to the format conversion configuration;

[0199] Step 1507: Write the data and micro-op codes into the cache;

[0200] Step 1508: Perform format conversion post-processing according to the format conversion configuration;

[0201] Step 1509: Execute data computing operations according to the computing configuration;

[0202] Step 1510: Generate a write operation to the bus according to the instruction write address and data size, such as AXI write transfer, APB, AHB, ACE, etc. write operation;

[0203] Finally, return to step 1503 and execute the instruction completion report to instruct the controller to update the synchronization relationship.

[0204] Please refer to Figure 16, which shows a flow chart of a data transfer method provided by an exemplary embodiment of the present application. The method is used in the above-mentioned direct memory access system and is executed by a macro instruction controller in the direct memory access system. The method includes:

[0205] Step 1601: receiving a trigger instruction sent by a processor;

[0206] Step 1602: Read a macro instruction from a macro instruction memory according to a trigger instruction; the macro instruction is used to instruct the transfer of multi-dimensional structure data;

[0207] Step 1603, the macroinstruction is sent to the macroinstruction parsing engine so that the macroinstruction parsing engine parses the macroinstruction into a micro-operation code and sends the micro-operation code to the data read and write transmission path, which reads and writes the one-dimensional structure data to the bus according to the micro-operation code; the micro-operation code is used to indicate the transfer of one-dimensional structure data in the multi-dimensional structure data.

[0208] In some embodiments, the macroinstruction and the micro-operation code further include a synchronization configuration, the synchronization configuration being used to instruct to perform a status check on a target address, the target address being at least one of a read address and a write address of the data;

[0209] The above steps of sending the macro instructions to the macro instruction parsing engine include:

[0210] Check the status of the target address according to the synchronization configuration;

[0211] When the state of the target address meets the specified conditions, the macro instruction is sent to the macro instruction parsing engine;

[0212] The specified conditions include:

[0213] When the target address includes a read address, the status of the read address is readable;

[0214] When the target address includes a write address, the state of the write address is writable.

[0215] In some embodiments, receiving a trigger instruction sent by a processor includes:

[0216] receiving macro instructions respectively sent by multiple processors through multiple virtual channels;

[0217] Send the macro to the macro parsing engine, including:

[0218] According to the priorities of the multiple virtual channels, the macro instructions respectively sent by the multiple processors are sent to the macro instruction parsing engine in sequence.

[0219] In summary, in the solution shown in the embodiment of the present application, the processor sends a macro instruction to the DMA system, which is used to instruct the transport of multi-dimensional structure data; the macro instruction controller in the DMA system sends the macro instruction to the macro instruction parsing engine; the macro instruction parsing engine parses the macro instruction into a micro operation code for instructing the transport of one-dimensional structure data in the multi-dimensional structure data, and sends it to the data read and write transmission path, and the data read and write transmission path executes the relocation of the one-dimensional structure data according to the micro operation code. In the above solution, the processor directly instructs the DMA system to transport the multi-dimensional structure data, and then the macro instruction parsing engine in the DMA system disassembles the transport operation of the multi-dimensional structure data into multiple transport operations of one-dimensional structure data. Since the speed at which the DMA system parses the macro instruction is much faster than the speed at which the processor disassembles the transport operation of the multi-dimensional structure data, the above DMA system can greatly reduce the time required for the processor to generate instructions for transporting one-dimensional structure data, thereby improving the efficiency of data transport.

[0220] Please refer to FIG17 , which shows a schematic diagram of a data handling device provided by an exemplary embodiment of the present application. The device is used as a macro controller in the above-mentioned direct memory access system, and the device includes:

[0221] The trigger instruction receiving module 1701 is used to receive the trigger instruction sent by the processor;

[0222] The macro instruction reading module 1702 is used to read the macro instruction from the macro instruction memory according to the trigger instruction; the macro instruction is used to instruct the transfer of multi-dimensional structure data;

[0223] The macroinstruction sending module 1703 is used to send macroinstructions to the macroinstruction parsing engine so that the macroinstruction parsing engine can parse the macroinstructions into micro-operation codes and send the micro-operation codes to the data read and write transmission path. The data read and write transmission path reads and writes one-dimensional structure data to the bus according to the micro-operation codes; the micro-operation codes are used to indicate the transfer of one-dimensional structure data in multi-dimensional structure data.

[0224] In some embodiments, the macroinstruction and the micro-operation code further include a synchronization configuration, the synchronization configuration being used to instruct to perform a status check on a target address, the target address being at least one of a read address and a write address of the data;

[0225] The macro instruction sending module 1703 is used to check the status of the target address according to the synchronization configuration;

[0226] When the state of the target address meets the specified conditions, the macro instruction is sent to the macro instruction parsing engine;

[0227] The specified conditions include:

[0228] When the target address includes a read address, the status of the read address is readable;

[0229] When the target address includes a write address, the state of the write address is writable.

[0230] In some embodiments, the trigger instruction receiving module 1701 is configured to receive macro instructions respectively sent by multiple processors through multiple virtual channels;

[0231] The macro instruction sending module 1703 is used to send the macro instructions sent by the multiple processors to the macro instruction parsing engine in sequence according to the priorities of the multiple virtual channels.

[0232] In summary, in the solution shown in the embodiment of the present application, the processor sends a macro instruction to the DMA system, which is used to instruct the transport of multi-dimensional structure data; the macro instruction controller in the DMA system sends the macro instruction to the macro instruction parsing engine; the macro instruction parsing engine parses the macro instruction into a micro operation code for instructing the transport of one-dimensional structure data in the multi-dimensional structure data, and sends it to the data read and write transmission path, and the data read and write transmission path executes the relocation of the one-dimensional structure data according to the micro operation code. In the above solution, the processor directly instructs the DMA system to transport the multi-dimensional structure data, and then the macro instruction parsing engine in the DMA system disassembles the transport operation of the multi-dimensional structure data into multiple transport operations of one-dimensional structure data. Since the speed at which the DMA system parses the macro instruction is much faster than the speed at which the processor disassembles the transport operation of the multi-dimensional structure data, the above DMA system can greatly reduce the time required for the processor to generate instructions for transporting one-dimensional structure data, thereby improving the efficiency of data transport.

[0233] An embodiment of the present application further provides a computer device, which includes a direct memory access system as shown in any one of FIG. 5 , FIG. 7 , FIG. 8 and FIG. 14 .

[0234] An embodiment of the present application further provides a chip, which includes the direct memory access system shown in any one of Figures 5, 7, 8, and 14. The chip can be a chip other than a processor that is used to perform a direct memory access process. For example, the chip can be implemented as a DMA controller, or the chip can include one or more DMA controllers; the DMA controller includes the direct memory access system shown in any one of Figures 5, 7, 8, and 14.

[0235] An embodiment of the present application further provides a computer device, which may include the above-mentioned chip, and the chip includes the direct memory access system shown in any one of Figures 5, 7, 8 and 14 above.

[0236] An embodiment of the present application also provides a computer-readable storage medium, in which at least one program is stored, and the at least one program is loaded and executed by a controller to implement the above-mentioned data transfer method; the controller is a macro instruction controller in the direct memory access system shown in any of Figures 5, 7, 8 and 14 above.

[0237] Optionally, the computer-readable storage medium may include: Read Only Memory (ROM), Random Access Memory (RAM), Solid State Drives (SSD), or an optical disk. Among them, the random access memory may include Resistance Random Access Memory (ReRAM) and Dynamic Random Access Memory (DRAM). The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0238] An embodiment of the present application also provides a computer program product, including a computer program, which implements the above-mentioned data transfer method when executed by a controller; the controller can be a macro instruction controller in the direct memory access system shown in any of Figures 5, 7, 8 and 14 above.

Claims

1. A direct memory access system, characterized in that: The system comprises: a macro instruction memory, a macro instruction controller, a macro instruction parsing engine and a data reading and writing transmission path; The macro instruction memory and the macro instruction controller are respectively connected to a processor in a computer device, and the macro instruction memory is connected to the macro instruction controller; The macro instruction controller is connected to the macro instruction parsing engine, the macro instruction parsing engine is connected to the data reading and writing transmission path, and the data reading and writing transmission path is connected to the bus of the computer device; The macro instruction memory is used to store the macro instructions issued by the processor; the macro instructions are used to instruct the transport of multi-dimensional structure data; The macro instruction controller is used to receive the trigger instruction sent by the processor, read the macro instruction from the macro instruction memory according to the trigger instruction, and send the macro instruction to the macro instruction parsing engine; The macro instruction parsing engine is used to parse the macro instruction into a micro operation code and send the micro operation code to the data read and write transmission path; the micro operation code is used to instruct the transfer of one-dimensional structure data in the multi-dimensional structure data; The data read / write transmission path is used to read and write the one-dimensional structure data to the bus according to the micro-operation code.

2. The system according to claim 1, characterized in that The data read and write transmission path includes a plurality of processing units, and the plurality of processing units at least include a read data interface unit, a cache unit and a write data interface unit; The macro instruction parsing engine is connected to the read data interface unit, and the macro instruction parsing engine is used to send the micro operation code to the read data interface unit; The micro-operation code is used to be transmitted sequentially among the multiple processing units.

3. The system according to claim 1 or 2, characterized in that: The macroinstruction parsing engine is used to parse the macroinstruction into micro-operation code. Parsing the data structure of the multi-dimensional structure data to determine the read and write addresses and data size of the one-dimensional structure data in the multi-dimensional structure data; The micro-operation code is generated according to the read and write addresses and data size of the one-dimensional structure data.

4. The system according to any one of claims 1 to 3, characterized in that: The macroinstruction is further used to instruct to perform a format conversion process on the multi-dimensional structure data, and the micro-operation code is further used to instruct to perform a format conversion process on the one-dimensional structure data; The multiple processing units further include at least one of a pre-format conversion processing unit and a post-format conversion processing unit, wherein the pre-format conversion processing unit is located before the cache unit, and the post-format conversion processing unit is located after the cache unit; The format conversion pre-processing unit is used to perform format conversion pre-processing on the one-dimensional structure data according to the processing mode of the format conversion processing indicated by the micro-operation code, and write the result data of the format conversion pre-processing into the cache unit; The format conversion post-processing unit is used to perform format conversion post-processing on the data in the cache unit according to the format conversion processing processing mode indicated by the micro-operation code, and then send it to the next processing unit.

5. The system according to any one of claims 1 to 4, characterized in that: The macro instruction includes a first format conversion configuration, where the first format conversion configuration is a configuration for performing format conversion on the multi-dimensional structure data; The macro instruction parsing engine is used to generate a second format conversion configuration according to the first format conversion configuration when generating the micro operation code according to the read and write addresses and data size of the one-dimensional structure data, wherein the second format conversion configuration is a configuration for performing format conversion on the one-dimensional structure data; The micro-operation code is generated according to the read and write addresses, data size, and the second format conversion configuration of the one-dimensional structure data.

6. The system according to any one of claims 1 to 5, characterized in that: The macroinstruction is also used to instruct to perform arithmetic processing on the multi-dimensional structure data, and the micro-operation code is also used to instruct to perform arithmetic processing on the one-dimensional structure data; The multiple processing units also include a data computing unit; The data operation unit is used to perform operation processing on the input data according to the operation processing mode indicated by the micro-operation code, and then send it to the next processing unit.

7. The system according to any one of claims 1 to 6, characterized in that: The macroinstructions and the micro-operation codes respectively include operation configurations, and the operation configurations are configurations of the operation processing.

8. The system according to any one of claims 1 to 7, characterized in that: The macroinstruction and the micro-operation code further include a synchronization configuration, wherein the synchronization configuration is used to instruct to perform a status check on a target address, wherein the target address is at least one of a read address and a write address of data; The macro instruction controller is used to check the state of the target address according to the synchronization configuration in the macro instruction when sending the macro instruction to the macro instruction parsing engine, and send the macro instruction to the macro instruction parsing engine when the state of the target address meets a specified condition; the specified condition includes: when the target address includes a read address, the state of the read address is readable; when the target address includes a write address, the state of the write address is writable; The read data interface unit is used to read the one-dimensional structure data from the read address when the target address includes the read address and the state of the read address is readable; The write data interface unit is used to write data to the write address when the target address includes the write address and the state of the write address is writable.

9. The system according to any one of claims 1 to 8, characterized in that: The macroinstruction controller is used to receive macroinstructions respectively sent by multiple processors through multiple virtual channels, and send the macroinstructions respectively sent by the multiple processors to the macroinstruction parsing engine in sequence according to the priorities of the multiple virtual channels.

10. A data transport method, characterized in that: The method is used in a direct memory access system as shown in any one of claims 1 to 9, and the method is executed by a macro instruction controller in the direct memory access system, and the method comprises: Receive the trigger instruction sent by the processor; Reading the macro instruction from the macro instruction storage according to the trigger instruction; the macro instruction is used to instruct the transport of multi-dimensional structure data; The macroinstruction is sent to a macroinstruction parsing engine so that the macroinstruction parsing engine parses the macroinstruction into a micro-operation code, and the micro-operation code is sent to a data read and write transmission path, and the data read and write transmission path reads and writes one-dimensional structure data to a bus according to the micro-operation code; the micro-operation code is used to indicate the movement of the one-dimensional structure data in the multi-dimensional structure data.

11. The method according to claim 10, characterized in that The data read and write transmission path includes a plurality of processing units, and the plurality of processing units at least include a read data interface unit, a cache unit and a write data interface unit; The macro instruction parsing engine is connected to the read data interface unit, and the macro instruction parsing engine is used to send the micro operation code to the read data interface unit; The micro-operation code is used to be transmitted sequentially among the multiple processing units.

12. The method according to claim 10 or 11, characterized in that: The macroinstruction and the micro-operation code further include a synchronization configuration, wherein the synchronization configuration is used to instruct to perform a status check on a target address, wherein the target address is at least one of a read address and a write address of data; The step of sending the macro instruction to the macro instruction parsing engine comprises: checking the status of the target address according to the synchronization configuration; When the state of the target address satisfies a specified condition, sending the macro instruction to the macro instruction parsing engine; The specified conditions include: When the target address includes a read address, the state of the read address is readable; When the target address includes a write address, the state of the write address is writable.

13. A data handling device, characterized in that: The device is used for a macro instruction controller in a direct memory access system as shown in any one of claims 1 to 9, and the device comprises: A trigger instruction receiving module, used to receive a trigger instruction sent by a processor; A macro instruction reading module, used for reading the macro instruction from the macro instruction storage according to the trigger instruction; the macro instruction is used for instructing the transport of multi-dimensional structure data; A macroinstruction sending module is used to send the macroinstruction to a macroinstruction parsing engine so that the macroinstruction parsing engine parses the macroinstruction into a micro-operation code and sends the micro-operation code to a data read and write transmission path, and the data read and write transmission path reads and writes one-dimensional structure data to a bus according to the micro-operation code; the micro-operation code is used to indicate the transfer of the one-dimensional structure data in the multi-dimensional structure data.

14. The device according to claim 13, characterized in that The data read and write transmission path includes a plurality of processing units, and the plurality of processing units at least include a read data interface unit, a cache unit and a write data interface unit; The macro instruction parsing engine is connected to the read data interface unit, and the macro instruction parsing engine is used to send the micro operation code to the read data interface unit; The micro-operation code is used to be transmitted sequentially among the multiple processing units.

15. The device according to claim 13 or 14, characterized in that The macroinstruction and the micro-operation code further include a synchronization configuration, wherein the synchronization configuration is used to instruct to perform a status check on a target address, wherein the target address is at least one of a read address and a write address of data; The macro instruction sending module is used to check the state of the target address according to the synchronization configuration; When the state of the target address satisfies a specified condition, sending the macro instruction to the macro instruction parsing engine; The specified conditions include: When the target address includes a read address, the state of the read address is readable; When the target address includes a write address, the state of the write address is writable.

16. A computer device, characterized in that: The computer device comprises the direct memory access system according to any one of claims 1 to 9.

17. A computer-readable storage medium, characterized in that: The storage medium stores at least one program, which is loaded and executed by the controller to implement the data transfer method as described in any one of claims 10 to 12; the controller is a macro instruction controller in the direct memory access system as described in any one of claims 1 to 9.

18. A chip, characterized in that: The chip comprises a direct memory access system as claimed in any one of claims 1 to 9.

19. A computer device, characterized in that: The computer device comprises the chip as claimed in claim 18.

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