Display apparatus, gate driving circuit, shift register unit, and drivig method therefor

Abstract

A display apparatus, a gate driving circuit, a shift register unit, and a driving method for a shift register unit. The shift register unit comprises: an input sub-circuit (1), which is connected to a signal input terminal, a first clock signal terminal, and a first node; a first control sub-circuit (2), which is connected to a first power supply signal terminal, a second clock signal terminal, the first node, and a second node; a second control sub-circuit (3), which is connected to the first power supply signal terminal, the first node, and the second node; a third control sub-circuit (4), which is connected to the first power supply signal terminal, the second clock signal terminal, the first node, and the second node; a first output sub-circuit (6), which is connected to the first power supply signal terminal, the second clock signal terminal, the first node, the second node, and a first signal output terminal; and a second output sub-circuit (7), which is connected to a second power supply signal terminal, a third clock signal terminal, the first node, the second node, and a second signal output terminal. The shift register unit may simultaneously output a high-level signal and a low-level signal, effectively driving a pixel circuit.

Description

Display device, gate driving circuit, shift register unit and driving method thereof Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display device, a gate driving circuit, a shift register unit and a driving method thereof. Background Art

[0002] As screen size increases and resolution frequency increases, the scan time per line decreases, seriously affecting image quality compensation. Traditional LTPO (Low-Temperature Polycrystalline Oxide) circuits perform data writing and Vth compensation simultaneously. The shorter the scan time per line, the shorter the compensation time.

[0003] The existing GOA (Gate on Array) circuit cannot drive the LTPO pixel circuit well.

[0004] Summary of the Invention

[0005] The purpose of the present application is to provide a display device, a gate driving circuit, a shift register unit and a driving method thereof that can simultaneously output high-voltage and low-voltage signals.

[0006] The present application discloses a shift register unit, comprising:

[0007] an input subcircuit connected to the signal input terminal, the first clock signal terminal, and the first node, and configured to control the connection between the signal input terminal and the first node under the control of the potential of the first clock signal terminal;

[0008] a first control subcircuit connected to the first power signal terminal, the second clock signal terminal, the first node, and the second node, and configured to control the connection between the second clock signal terminal and the second node under the control of the potential of the first node;

[0009] a second control subcircuit, connected to the first power signal terminal, the first node, and the second node, and configured to control the connection between the first power signal terminal and the second node under the control of the potential of the first node;

[0010] a third control subcircuit, connected to the first power signal terminal, the second clock signal terminal, the first node, and the second node, and configured to control the connection between the first power signal terminal and the first node under the control of the potentials of the second node and the second clock signal terminal;

[0011] a first output sub-circuit, connected to the first power signal terminal, the second clock signal terminal, the first node, the second node, and the first signal output terminal, configured to control the first power signal terminal to be connected to the first signal output terminal under the control of the second node, and further configured to control the second clock signal terminal to be connected to the first signal output terminal under the control of the first node;

[0012] The second output sub-circuit is connected to the second power signal terminal, the third clock signal terminal, the first node, the second node and the second signal output terminal, and is used to control the second power signal terminal to be connected to the second signal output terminal under the control of the second node, and is also used to control the third clock signal terminal to be connected to the second signal output terminal under the control of the first node.

[0013] Optionally, the second output sub-circuit includes:

[0014] a tenth transistor, wherein a control electrode of the tenth transistor is connected to the second node, a first electrode of the tenth transistor is connected to the second power signal terminal, and a second electrode of the tenth transistor is connected to the second signal output terminal;

[0015] An eleventh transistor, wherein the control electrode of the eleventh transistor is connected to the first node, the first electrode of the eleventh transistor is connected to the third clock signal terminal, and the second electrode of the eleventh transistor is connected to the second signal output terminal.

[0016] Optionally, the shift register unit also includes a fourth control subcircuit, the fourth control subcircuit includes a ninth transistor, the control electrode of the ninth transistor is connected to the second power supply signal terminal, the first electrode of the ninth transistor is connected to the first node, and the second electrode of the ninth transistor is connected to the fourth node.

[0017] Optionally, the first control subcircuit includes:

[0018] a second transistor, wherein a control electrode of the second transistor is connected to the first node, and a first electrode of the second transistor is connected to the first power signal terminal;

[0019] a third transistor, wherein the control electrode of the second transistor is connected to the second electrode of the second transistor, the first electrode of the third transistor is connected to the second clock signal terminal, and the second electrode of the third transistor is connected to the second node;

[0020] A first energy storage unit, wherein one end of the first energy storage unit is connected between the second clock signal end and the first electrode of the third transistor, and the other end is connected between the control electrode of the third transistor and the second electrode of the second transistor.

[0021] Optionally, the second control subcircuit includes:

[0022] A sixth transistor, wherein a control electrode of the sixth transistor is connected to the first node, a first electrode of the sixth transistor is connected to the first power signal terminal and the third control sub-circuit, and a second electrode of the sixth transistor is connected to the second node.

[0023] Optionally, the third control subcircuit includes:

[0024] a seventh transistor, wherein a control electrode of the seventh transistor is connected to the second node, a first electrode of the seventh transistor is connected to the first power signal terminal and the second control sub-circuit, and a second electrode of the seventh transistor is connected to the eighth transistor;

[0025] The eighth transistor, the control electrode of the eighth transistor is connected to the second clock signal terminal, the first electrode of the eighth transistor is connected to the seventh transistor, and the second electrode of the eighth transistor is connected to the first node.

[0026] Optionally, the first output sub-circuit includes:

[0027] a fourth transistor, wherein a control electrode of the fourth transistor is connected to the second node, a first electrode of the fourth transistor is connected to the first power signal terminal, and a second electrode of the fourth transistor is connected to the first signal output terminal;

[0028] A fifth transistor, wherein a control electrode of the fifth transistor is connected to the first node, a first electrode of the fifth transistor is connected to the second clock signal terminal, and a second electrode of the fifth transistor is connected to the first signal output terminal.

[0029] Optionally, the first output sub-circuit further includes:

[0030] a second energy storage unit, the second energy storage unit being connected between the first signal output terminal and the first node;

[0031] A third energy storage unit is connected between the first signal output terminal and the second node.

[0032] Optionally, the input subcircuit includes:

[0033] A first transistor, wherein a control electrode of the first transistor is connected to the first clock signal terminal, a first electrode of the first transistor is connected to the signal input terminal, and a second electrode of the first transistor is connected to the first node.

[0034] The present application also discloses a gate driving circuit, which includes the above-mentioned shift register unit.

[0035] The present application also discloses a driving method for a shift register unit, the driving method being used to drive the above-mentioned shift register unit, the driving method comprising:

[0036] enabling the input sub-circuit to control a signal input terminal to be connected to a first node under the control of the potential of the first clock signal terminal;

[0037] enabling the first control subcircuit to control the second clock signal terminal to be connected to the second node under the control of the potential of the first node;

[0038] The first output sub-circuit controls the second clock signal terminal to be connected to the first signal output terminal under the control of the first node, and controls the first power terminal to be connected to the first signal output terminal under the control of the second node;

[0039] The second output sub-circuit controls the third clock signal terminal to be connected to the second signal output terminal under the control of the first node, and controls the second power supply terminal to be connected to the second signal output terminal under the control of the second node.

[0040] The present application also discloses a display panel, which includes the above-mentioned gate driving circuit. The display panel includes an active layer, a first gate layer, a second gate layer, and an electrode layer.

[0041] Optionally, the fifth transistor includes a plurality of transistor structures connected in parallel, and the eleventh transistor includes a plurality of transistor structures connected in parallel.

[0042] Compared with the related art, the shift register unit of the present application is provided with a second output sub-circuit, so that the GOA circuit can output high-level signals and low-level signals at the same time, so that the GOA circuit can effectively drive the LTPO pixel circuit.

[0043] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0045] FIG1 is a block diagram of a shift register unit according to an embodiment of the present disclosure.

[0046] FIG2 is a circuit diagram of a shift register unit according to an embodiment of the present disclosure.

[0047] FIG3 is an operation timing diagram of the shift register unit according to an embodiment of the present disclosure.

[0048] FIG4 is a schematic diagram of an active layer of a display panel according to an embodiment of the present disclosure.

[0049] FIG5 is a schematic diagram of an active layer and a first gate layer of a display panel according to an embodiment of the present disclosure.

[0050] FIG6 is a schematic diagram of an active layer, a first gate layer, and a second gate layer of a display panel according to an embodiment of the present disclosure.

[0051] FIG7 is a schematic diagram of an active layer, a first gate layer, a second gate layer, and an electrode layer of a display panel according to an embodiment of the present disclosure.

[0052] Explanation of the reference numerals: input subcircuit, 1; first control subcircuit, 2; second control subcircuit, 3; third control subcircuit, 4; fourth control subcircuit, 5; first output subcircuit, 6; second output subcircuit, 7; first transistor, T1; second transistor, T2; third transistor, T3; fourth transistor, T4; fifth transistor, T5; sixth transistor, T6; seventh transistor, T7; eighth transistor, T8; ninth transistor, T9; tenth transistor, T10; eleventh transistor, T11; first energy storage unit, C1 ; Second energy storage unit, C2; Third energy storage unit, C3; Signal input terminal, GSTV; First clock signal terminal, GCK; Second clock signal terminal, GCB; Third clock signal terminal, PCB; First power signal terminal, VGH; Second power signal terminal, VGL; First signal output terminal, GOUT; Second signal output terminal, NOUT; First node, N1; Second node, N2; Third node, N3; Fourth node, N4; Active layer, 100; First gate layer, 200; Second gate layer, 300; Electrode layer, 400. DETAILED DESCRIPTION

[0053] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of this specification, as detailed in the appended claims.

[0054] The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure. Unless otherwise defined, technical or scientific terms used in this specification should have the same ordinary meaning as those having ordinary skill in the art to which this application belongs. The terms "first," "second," and similar terms used in this specification and claims do not denote any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather indicate the presence of one. "Multiple" or "several" means two or more. Unless otherwise indicated, terms such as "front," "rear," "lower," and / or "upper" are used for convenience only and are not intended to limit the scope of the present disclosure to a specific location or spatial orientation. Terms such as "include" or "comprising" mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0055] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used in this specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0056] In the related art, the GOA circuit cannot drive the LTPO pixel circuit well.

[0057] To solve the above technical problems, the present application provides a shift register unit, which includes:

[0058] The input sub-circuit 1 is connected to the signal input terminal GSTV, the first clock signal terminal GCK and the first node N1, and is used to control the signal input terminal GSTV to be connected to the first node N1 under the control of the potential of the first clock signal terminal GCK.

[0059] a first control sub-circuit 2 connected to the first power signal terminal VGH, the second clock signal terminal GCB, the first node N1, and the second node N2, and configured to control the connection between the second clock signal terminal GCB and the second node N2 under the control of the potential of the first node N1;

[0060] The second control sub-circuit 3 is connected to the first power signal terminal VGH, the first node N1 and the second node N2, and is used to control the connection between the first power signal terminal VGH and the second node N2 under the potential control of the first node N1.

[0061] The third control sub-circuit 4 is connected to the first power signal terminal VGH, the second clock signal terminal GCB, the first node N1 and the second node N2, and is used to control the connection between the first power signal terminal VGH and the first node N1 under the potential control of the second node N2 and the second clock signal terminal GCB.

[0062] a first output sub-circuit 6 connected to the first power signal terminal VGH, the second clock signal terminal GCB, the first node N1, the second node N2, and the first signal output terminal GUOT, for controlling the first power signal terminal VGH to be connected to the first signal output terminal GOUT under the control of the second node N2, and for controlling the second clock signal terminal GCB to be connected to the first signal output terminal GOUT under the control of the first node N1;

[0063] The second output sub-circuit 7 is connected to the second power signal terminal VGL, the third clock signal terminal PCB, the first node N1, the second node N2 and the second signal output terminal NUOT, and is used to control the connection between the second power signal terminal VGL and the second signal output terminal NUOT under the control of the second node N2, and is also used to control the connection between the third clock signal terminal PCB and the second signal output terminal NUOT under the control of the first node N1.

[0064] In order to solve the above technical problems, the present application further provides a gate driving circuit and a display panel, including the above shift register unit.

[0065] The shift register unit of the present application can output high-voltage and low-voltage signals at the same time, and can effectively drive the LTPO pixel circuit.

[0066] The following will describe in detail the various embodiments of the present application that are consistent with the above-mentioned creative concepts.

[0067] The transistors used in this disclosure may be triodes, thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two electrodes of the transistor other than the control electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode. The energy storage unit used in this disclosure may be a capacitor.

[0068] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0069] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0070] As shown in Figures 1 and 2, input sub-circuit 1 is connected to signal input terminal GSTV, a first clock signal terminal GCK, and a first node N1. It is configured to control the connection between signal input terminal GSTV and first node N1 under the control of the potential of first clock signal terminal GCK. In an alternative embodiment, input sub-circuit 1 includes a first transistor T1. A first electrode of first transistor T1 is connected to signal input terminal GSTV, a second electrode of first transistor T1 is connected to first node N1, and a control electrode of first transistor T1 is connected to first clock signal GCK.

[0071] As shown in Figures 1 and 2, the first control subcircuit 2 is connected to the first power signal terminal VGH, the second clock signal terminal GCB, the first node N1, and the second node N2. It is configured to control the connection between the first power signal terminal VGH and the third node N3 under the control of the potential of the first node N1. It is also configured to control the connection between the second clock signal terminal GCB and the second node N2 under the control of the potential of the third node N3. In an optional embodiment, the first control subcircuit 2 includes a second transistor T2. The control electrode of the second transistor T2 is connected to the first node N1, the first electrode of the second transistor T2 is connected to the first power signal terminal VGH, and the second electrode of the second transistor T2 is connected to the third node N3. The first control subcircuit 2 also includes a third transistor T3. The control electrode of the third transistor T3 is connected to the third node N3, the first electrode of the third transistor T3 is connected to the second clock signal terminal GCB, and the second electrode of the third transistor T3 is connected to the second node N2. The first control subcircuit 2 further includes a first energy storage unit C1 , one end of which is connected between the second clock signal terminal GCB and the first electrode of the third transistor T3 , and the other end of which is connected between the control electrode of the third transistor T3 and the second electrode of the second transistor T2 .

[0072] As shown in Figures 1 and 2, the second control sub-circuit 3 is connected to the first power signal terminal VGH, a first node N1, and a second node N2. It is configured to control the connection between the first power signal terminal VGH and the second node N2 under the control of the potential of the first node N1. In an optional embodiment, the second control sub-circuit 3 includes a sixth transistor T6, wherein the control electrode of the sixth transistor T6 is connected to the first node N1, the first electrode of the sixth transistor T6 is connected to the first power signal terminal VGH, and the second electrode of the sixth transistor T6 is connected to the second node N2.

[0073] As shown in Figures 1 and 2, the third control sub-circuit 4 is connected to the first power signal terminal VGH, the second clock signal terminal GCB, the first node N1, and the second node N2, and is configured to control the connection between the first power signal terminal VGH and the first node N1 under the control of the potential of the second node N2 and the second clock signal terminal GCB. In an alternative embodiment, the third control sub-circuit 4 includes a seventh transistor T7 and an eighth transistor T8. The control electrode of the seventh transistor T7 is connected to the second node N2, the first electrode of the seventh transistor T7 is connected to the first power signal terminal VGH and the second control sub-circuit 3, and the second electrode of the seventh transistor T7 is connected to the eighth transistor T8. The control electrode of the eighth transistor T8 is connected to the second clock signal terminal GCB, the first electrode of the eighth transistor T8 is connected to the seventh transistor T7, and the second electrode of the eighth transistor T8 is connected to the first node N1.

[0074] As shown in Figures 1 and 2, in an optional embodiment, the shift register unit further includes a fourth control subcircuit 5. Optionally, the fourth control subcircuit 5 includes a ninth transistor T9, wherein a control electrode of the ninth transistor T9 is connected to the second power signal terminal VGL, a first electrode of the ninth transistor T9 is connected to the first node N1, and a second electrode of the ninth transistor T9 is connected to the fourth node N4.

[0075] As shown in Figures 1 and 2, the first output sub-circuit 6 is connected to the first power signal terminal VGH, the second clock signal terminal GCB, the first node N1, the second node N2, and the first signal output terminal GOUT. It is configured to control the connection between the first power signal terminal VGH and the first signal output terminal GOUT under the control of the second node N2, and to control the connection between the second clock signal terminal GCB and the first signal output terminal GOUT under the control of the first node N1. In an optional embodiment, the first output sub-circuit 6 includes a fourth transistor T4, the control electrode of which is connected to the second node N2, the first electrode of which is connected to the first power signal terminal VGH, and the second electrode of which is connected to the first signal output terminal GOUT. The first output sub-circuit 6 also includes a fifth transistor T5, the control electrode of which is connected to the first node N1, the first electrode of which is connected to the second clock signal terminal GCB, and the second electrode of which is connected to the first signal output terminal GOUT. The first output sub-circuit 6 also includes a second energy storage unit C2, which is connected between the first signal output terminal GOUT and the first node N1. The second energy storage unit C2 stores the signal at the first node N1. The first output sub-circuit 6 further includes a third energy storage unit C3 connected between the first signal output terminal GOUT and the second node N2. The third energy storage unit C3 stores the signal at the second node N2.

[0076] As shown in Figures 1 and 2, the second output sub-circuit 7 is connected to the second power signal terminal VGL, the third clock signal terminal PCB, the first node N1, the second node N2, and the second signal output terminal NOUT. It is configured to control the connection between the second power signal terminal VGL and the second signal output terminal NOUT under the control of the second node N2. It is also configured to control the connection between the third clock signal terminal PCB and the second signal output terminal NOUT under the control of the first node N1. In an optional embodiment, the second output sub-circuit 7 includes a tenth transistor T10, the control electrode of the tenth transistor T10 being connected to the second node N2, the first electrode of the tenth transistor T10 being connected to the second power signal terminal VGL, and the second electrode of the tenth transistor T10 being connected to the second signal output terminal NOUT. The second output sub-circuit 7 also includes an eleventh transistor T11, the control electrode of the eleventh transistor T11 being connected to the first node N1, the first electrode of the eleventh transistor T11 being connected to the third clock signal terminal PCB, and the second electrode of the eleventh transistor T11 being connected to the second signal output terminal NOUT.

[0077] The working process of the shift register unit in FIG2 is described in detail below in conjunction with the working timing diagram of the shift register unit shown in FIG3 . For example, all the transistors are P-type thin film transistors, and the conduction levels of all the transistors are low.

[0078] In the first phase S1, the signal input terminal GSTV outputs a low level, the first clock signal terminal GCK outputs a low level, the second clock signal terminal GCB outputs a high level, and the third clock signal terminal PCB outputs a low level. The first transistor T1 is turned on, the signal input terminal GSTV is connected to the first node N1, and a low level is written to the first node N1. The ninth transistor T9 is in a normally-on state, the first node N1 is connected to the fourth node N4, and a low level is written to the fourth node N4. The second transistor T2 is turned on, the first power supply signal terminal VGH is connected to the third node N3, and a high level is written to the third node N3. The third transistor T3 is turned off, the sixth transistor T6 is turned on, the first power supply signal terminal VGH is connected to the second node N2, and a high level is written to the second node N2. The fourth transistor T4 is turned off, the fifth transistor T5 is turned on, the first signal output terminal GOUT is connected to the second clock signal terminal GCB, and the first signal output terminal GOUT outputs a high level signal. The tenth transistor T10 is turned off, the eleventh transistor T11 is turned on, the third clock signal terminal PCB is connected to the second signal output terminal NOUT, and the second signal output terminal NOUT outputs a low level signal.

[0079] In the second phase S2, the output level of the signal input terminal GSTV changes from a low level to a high level. The first clock signal terminal GCK outputs a high level, the second clock signal terminal GCB outputs a low level, and the third clock signal terminal PCB outputs a high level. The first transistor T1 is turned off, the second energy storage unit C2 stores a low-level signal, the ninth transistor T9 is in a normally-on state, and the fourth node N4 and the first node N1 remain in a low-level state. The second transistor T2 is turned on, the first power supply signal terminal VGH is connected to the third node N3, and the third node N3 remains high. The third transistor T3 is turned off, the sixth transistor T6 is turned on, the first power supply signal terminal VGH is connected to the second node N2, and the second node N2 remains high. The fourth transistor T4 is turned off, the fifth transistor T5 is turned on, the first signal output terminal GOUT is connected to the second clock signal terminal GCB, and the first signal output terminal GOUT outputs a low-level signal. The tenth transistor T10 is turned off. The eleventh transistor T11 is turned on, the second signal output terminal NOUT is connected to the third clock signal terminal PCB, and the second signal output terminal NOUT outputs a high-level signal. When the fourth node N4 and the first node N1 continue to maintain a low level state, the signal at the second clock signal terminal GCB changes from a low level signal to a high level signal, and the signal at the third clock signal terminal PCB changes from a high level signal to a low level signal. At this time, the first signal output terminal GOUT outputs a high level signal, and the second signal output terminal NOUT outputs a low level signal.

[0080] In the third phase S3, the signal input terminal GSTV outputs a high level, the first clock signal terminal GCK outputs a low level, the second clock signal terminal GCB outputs a high level, and the third clock signal terminal PCB outputs a low level. The first transistor T1 is turned on, the signal input terminal GSTV is connected to the first node N1, and the first node N1 transitions from a low level to a high level. The ninth transistor T9 is in a normally open state, the first node N1 is connected to the fourth node N4, and the fourth node N4 transitions from a low level to a high level. The second transistor T2 is turned off, the third transistor T3 is turned off, and the second node N2 is disconnected from the second clock signal terminal GCB. The sixth transistor T6 transitions from an on state to an off state, and the second node N2 remains high. The fourth transistor T4 is turned off, and the fifth transistor T5 transitions from an on state to an off state. The first signal output terminal GOUT transitions from a connected state to a disconnected state from the second clock signal terminal GCB, and the first signal output terminal GOUT maintains its output of a high level signal. The tenth transistor T10 is turned off, the eleventh transistor T11 changes from the on state to the off state, the third clock signal terminal PCB and the second signal output terminal NOUT change from the connected state to the disconnected state, and the second signal output terminal NOUT maintains outputting a low level signal.

[0081] In the fourth phase S4, the signal input terminal GSTV outputs a high level, the first clock signal terminal GCK outputs a high level, the second clock signal terminal GCB outputs a low level, and the third clock signal terminal PCB outputs a high level. The first transistor T1 is turned off, the second energy storage unit C2 stores a high level signal, the ninth transistor T9 is in a normally open state, and the fourth node N4 and the first node N1 remain in a high level state. The second transistor T2 is turned off, the output of the second clock signal terminal GCB changes from a high level to a low level, and the control electrode of the third transistor T3 is changed to a low level through the first energy storage unit C1. The third transistor T3 is turned on, the second clock signal terminal GCB is connected to the second node N2, and the second node N2 is written to a low level. The seventh transistor T7 and the eighth transistor T8 are turned on, the first power supply signal terminal VGH is connected to the first node N1, and the first node N1 remains high. The fourth transistor T4 is turned on, the fifth transistor T5 is turned off, the first signal output terminal GOUT is connected to the first power supply signal terminal VGH, and the first signal output terminal GOUT outputs a high level signal. The tenth transistor T10 is turned on. The eleventh transistor T11 is turned off, and the second signal output terminal NOUT is connected to the second power signal terminal VGL. The second signal output terminal NOUT outputs a low-level signal. Until the next low-level signal input terminal GSTV is reached, the first signal output terminal GOUT continues to output a high-level signal, and the second signal output terminal NOUT continues to output a low-level signal. Therefore, the subsequent stages will not be repeated.

[0082] The present disclosure also provides a gate driving circuit, which may include a plurality of cascaded shift register units described in any one of the above embodiments.

[0083] The present application also discloses a driving method for a shift register unit, which is used to drive the above-mentioned shift register unit. The method includes:

[0084] The input sub-circuit is controlled to connect the signal input terminal to the first node under the control of the potential of the first clock signal terminal.

[0085] The input sub-circuit is controlled to connect the signal input terminal to the first node under the control of the potential of the first clock signal terminal.

[0086] The first control subcircuit controls the second clock signal terminal to be connected to the second node under the control of the potential of the first node.

[0087] The first output subcircuit controls the second clock signal terminal to be connected to the first signal output terminal under the control of the first node, and controls the first power terminal to be connected to the first signal output terminal under the control of the second node.

[0088] The second output sub-circuit controls the third clock signal terminal to be connected to the second signal output terminal under the control of the first node, and controls the second power terminal to be connected to the second signal output terminal under the control of the second node.

[0089] As shown in FIG. 4 to FIG. 7 , the present application further discloses a display panel including the above-mentioned gate driving circuit. The display panel includes an active layer 100 , a first gate layer 200 , a second gate layer 300 and an electrode layer 400 .

[0090] The first to eleventh transistors are formed on the active layer 100 and the first gate layer 200. A first energy storage unit C1, a second energy storage unit C2, and a third energy storage unit C3 are formed on the first gate layer 200 and the second gate layer 300. The fifth transistor T5 and the eleventh transistor T11 each include multiple transistors connected in parallel. Optionally, the fifth transistor T5 includes four transistors connected in parallel, and the eleventh transistor T11 includes four transistors connected in parallel.

[0091] Other embodiments of the present invention will readily occur to those skilled in the art upon consideration of the present invention and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present invention being indicated by the following claims.

[0092] It should be understood that the present description is not limited to the exact structure that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

[0093] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A shift register unit, characterized in that: include: An input subcircuit connected to the signal input terminal, the first clock signal terminal and the first node, and used for controlling the signal input terminal to be connected to the first node under the control of the potential of the first clock signal terminal; A first control subcircuit is connected to the first power signal terminal, the second clock signal terminal, the first node and the second node, and is used to control the second clock signal terminal to be connected to the second node under the control of the potential of the first node; a second control subcircuit, connected to the first power signal terminal, the first node and the second node, and configured to control the connection between the first power signal terminal and the second node under the potential control of the first node; a third control subcircuit, connected to the first power signal terminal, the second clock signal terminal, the first node, and the second node, and configured to control the connection between the first power signal terminal and the first node under the potential control of the second node and the second clock signal terminal; a first output subcircuit connected to the first power signal terminal, the second clock signal terminal, the first node, the second node, and the first signal output terminal, and configured to control the first power signal terminal to be connected to the first signal output terminal under the control of the second node, and also configured to control the second clock signal terminal to be connected to the first signal output terminal under the control of the first node; The second output sub-circuit is connected to the second power signal terminal, the third clock signal terminal, the first node, the second node and the second signal output terminal, and is used to control the second power signal terminal to be connected to the second signal output terminal under the control of the second node, and is also used to control the third clock signal terminal to be connected to the second signal output terminal under the control of the first node.

2. The shift register unit according to claim 1, characterized in that: The second output sub-circuit comprises: a tenth transistor, wherein a control electrode of the tenth transistor is connected to the second node, a first electrode of the tenth transistor is connected to the second power signal terminal, and a second electrode of the tenth transistor is connected to the second signal output terminal; An eleventh transistor, wherein a control electrode of the eleventh transistor is connected to the first node, a first electrode of the eleventh transistor is connected to the third clock signal terminal, and a second electrode of the eleventh transistor is connected to the second signal output terminal.

3. The shift register unit according to claim 1, characterized in that: The shift register unit also includes a fourth control subcircuit, which includes a ninth transistor, a control electrode of the ninth transistor being connected to the second power supply signal terminal, a first electrode of the ninth transistor being connected to the first node, and a second electrode of the ninth transistor being connected to a fourth node.

4. The shift register unit according to claim 1, characterized in that: The first control subcircuit comprises: a second transistor, wherein a control electrode of the second transistor is connected to the first node, and a first electrode of the second transistor is connected to the first power signal terminal; a third transistor, wherein the control electrode of the second transistor is connected to the second electrode of the second transistor, the first electrode of the third transistor is connected to the second clock signal terminal, and the second electrode of the third transistor is connected to the second node; A first energy storage unit, wherein one end of the first energy storage unit is connected between the second clock signal end and the first electrode of the third transistor, and the other end of the first energy storage unit is connected between the control electrode of the third transistor and the second electrode of the second transistor.

5. The shift register unit according to claim 1, characterized in that: The second control subcircuit comprises: A sixth transistor, wherein a control electrode of the sixth transistor is connected to the first node, a first electrode of the sixth transistor is connected to the first power signal terminal and the third control subcircuit, and a second electrode of the sixth transistor is connected to the second node.

6. The shift register unit according to claim 1, characterized in that: The third control subcircuit comprises: a seventh transistor, wherein a control electrode of the seventh transistor is connected to the second node, a first electrode of the seventh transistor is connected to the first power signal terminal and the second control subcircuit, and a second electrode of the seventh transistor is connected to the eighth transistor; The eighth transistor, the control electrode of the eighth transistor is connected to the second clock signal terminal, the first electrode of the eighth transistor is connected to the seventh transistor, and the second electrode of the eighth transistor is connected to the first node.

7. The shift register unit according to claim 1, characterized in that: The first output subcircuit comprises: a fourth transistor, wherein a control electrode of the fourth transistor is connected to the second node, a first electrode of the fourth transistor is connected to the first power signal terminal, and a second electrode of the fourth transistor is connected to the first signal output terminal; A fifth transistor, wherein a control electrode of the fifth transistor is connected to the first node, a first electrode of the fifth transistor is connected to the second clock signal terminal, and a second electrode of the fifth transistor is connected to the first signal output terminal.

8. The shift register unit according to claim 7, characterized in that: The first output sub-circuit further includes: A second energy storage unit, wherein the second energy storage unit is connected between the first signal output terminal and the first node; A third energy storage unit is connected between the first signal output terminal and the second node.

9. The shift register unit according to claim 1, characterized in that: The input subcircuit comprises: A first transistor, wherein a control electrode of the first transistor is connected to the first clock signal terminal, a first electrode of the first transistor is connected to the signal input terminal, and a second electrode of the first transistor is connected to the first node.

10. A gate drive circuit, characterized in that: It comprises a shift register unit as described in any one of claims 1 to 9.

11. A driving method of a shift register unit, characterized in that: The driving method is used to drive the shift register unit according to any one of claims 1 to 9, and the driving method comprises: The input subcircuit controls the signal input terminal to be connected to the first node under the control of the potential of the first clock signal terminal; The first control subcircuit controls the second clock signal terminal to be connected to the second node under the control of the potential of the first node; The first output subcircuit controls the second clock signal terminal to be connected to the first signal output terminal under the control of the first node, and controls the first power terminal to be connected to the first signal output terminal under the control of the second node; The second output subcircuit controls the third clock signal terminal to be connected to the second signal output terminal under the control of the first node, and controls the second power supply terminal to be connected to the second signal output terminal under the control of the second node.

12. A display panel, characterized in that: Comprising the gate driving circuit of claim 10, the display panel comprises an active layer, a first gate layer, a second gate layer and an electrode layer.

13. The display panel according to claim 12, characterized in that: The fifth transistor includes a plurality of transistor structures connected in parallel, and the eleventh transistor includes a plurality of transistor structures connected in parallel.

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