Shift register unit and driving method therefor, gate driving circuit, and display apparatus

Abstract

A shift register unit and a driving method therefor, a gate driving circuit, and a display apparatus, relating to the technical field of display. A pre-stage driving circuit may control a first power supply end or a second power supply end to be connected to a pre-stage output end, and transmit a pre-stage signal to the pre-stage output end. On the basis of the pre-stage signal and an output control signal provided by an output control end, a post-stage control circuit may control the pre-stage output end or the output control end to be connected to a post-stage output end coupled to a pixel, and when the output control end is controlled to be connected to the post-stage output end, the potential of the transmitted output control signal is greater than or equal to the potential of a first power supply signal provided by the first power supply end. Therefore, when the potential of the pre-stage signal is close to the potential of the first power supply signal but a step abnormality of an intermediate potential occurs, the potential of the signal to be transmitted to the pixel can be directly controlled to be close to the potential of the first power supply signal, so as to eliminate the step abnormality, ensure a good output stability, and further ensure a good display effect.

Description

Shift register unit and driving method thereof, gate driving circuit, and display device

[0001] This disclosure claims priority to Chinese patent application number 202311167558.4 filed on September 11, 2023, entitled “Shift register unit and driving method thereof, gate drive circuit, and display device,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a shift register unit and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0003] The gate drive circuit is one of the essential circuits for driving display panels. Currently, it is often integrated into the display substrate using gate drive on array (GOA) technology to facilitate narrow bezel designs. Accordingly, the gate drive circuit is also called a GOA circuit.

[0004] In related art, a GOA circuit generally includes multiple cascaded GOA units, each of which can be referred to as a shift register unit. Multiple GOA units are coupled to multiple rows of pixels in a display panel via their output terminals, and are used to output gate drive signals to the multiple rows of pixels row by row, thereby implementing row scanning drive to illuminate the multiple rows of pixels row by row, allowing the display panel to display an image. Furthermore, each GOA unit generally includes multiple P-type transistors, and each pixel generally includes multiple N-type transistors.

[0005] However, based on the principle that N-type transistors are turned on at a high potential, each GOA unit must output a low-potential gate drive signal for a long period of time. This can lead to the risk of characteristic shifts in the transistors within the GOA unit, resulting in poor output stability and, in turn, potentially causing display panel issues.

[0006] Summary of the Invention

[0007] Provided are a shift register unit and a driving method thereof, a gate driving circuit, and a display device. The technical solution is as follows:

[0008] In one aspect, a shift register unit is provided, comprising:

[0009] a pre-stage driving circuit, coupled to the driving control terminal, the first power terminal, the second power terminal, and the pre-stage output terminal, respectively, and configured to: control the connection and disconnection between the first power terminal and the pre-stage output terminal, and control the connection and disconnection between the second power terminal and the pre-stage output terminal, based on a driving control signal provided by the driving control terminal;

[0010] The post-stage control circuit is coupled to the front-stage output terminal, the output control terminal and the post-stage output terminal respectively, and the post-stage output terminal is used to couple with the pixels in the display panel. The post-stage control circuit is configured to: based on the front-stage signal from the front-stage output terminal and the output control signal provided by the output control terminal, control the front-stage output terminal to be connected with the post-stage output terminal, so that the front-stage output terminal transmits the front-stage signal to the post-stage output terminal, or control the output control terminal to be connected with the post-stage output terminal, so that the output control terminal transmits the output control signal to the post-stage output terminal, and the potential of the transmitted output control signal is not less than the potential of the first power supply signal provided by the first power supply terminal.

[0011] Optionally, the conduction time between the first power supply terminal and the front-stage output terminal is shorter than the conduction time between the second power supply terminal and the front-stage output terminal; the output control terminal includes: a first output control terminal and a second output control terminal, and the potential of the output control signal provided by the second output control terminal is not less than the potential of the first power supply signal; the rear-stage control circuit is configured as follows:

[0012] Based on the front-stage signal and the output control signal provided by the first output control terminal, the front-stage output terminal and the rear-stage output terminal are controlled to be on and off; and when the front-stage output terminal is controlled to be disconnected from the rear-stage output terminal, the second output control terminal is connected to the rear-stage output terminal.

[0013] Optionally, the post-stage control circuit includes:

[0014] a switch subcircuit, coupled to the first output control terminal, the front-stage output terminal, and the rear-stage output terminal, respectively, and configured to: control the on / off switching of the front-stage output terminal and the rear-stage output terminal based on the front-stage signal and the output control signal provided by the first output control terminal;

[0015] The isolation sub-circuit is coupled to the second output control terminal and the subsequent stage output terminal, respectively, and is configured to: isolate the second output control terminal and the subsequent stage output terminal, and when the switch sub-circuit controls the front stage output terminal to be disconnected from the subsequent stage output terminal, the second output control terminal and the subsequent stage output terminal are turned on.

[0016] Optionally, the switch subcircuit includes: a switch and a first resistor;

[0017] The control end of the switch is coupled to the first output control end, the input end of the switch is coupled to the front-stage output end, and the output end of the switch is coupled to the rear-stage output end;

[0018] One end of the first resistor is coupled to the pre-stage output end, and the other end of the first resistor is coupled to the first output control end.

[0019] Optionally, the switch includes: a switching transistor;

[0020] The gate of the switching transistor is coupled to the first output control terminal as the control terminal of the switch, the first electrode of the switching transistor is coupled to the front-stage output terminal as the input terminal of the switch, and the second electrode of the switching transistor is coupled to the rear-stage output terminal as the output terminal of the switch.

[0021] Optionally, the isolation sub-circuit includes: a second resistor;

[0022] One end of the second resistor is coupled to the second output control end, and the other end of the second resistor is coupled to the subsequent stage output end.

[0023] Optionally, the driving control terminal includes: a first clock terminal, a second clock terminal, a start signal terminal and a potential control terminal;

[0024] The pre-stage driving circuit is configured to: control the on-off connection between the first power supply terminal and the pre-stage output terminal, and control the on-off connection between the second power supply terminal and the pre-stage output terminal based on the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, the start signal provided by the start signal terminal, the potential control signal provided by the potential control terminal, and the first power supply signal and the second power supply signal provided by the second power supply terminal.

[0025] Optionally, the pre-stage driving circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a first capacitor, a second capacitor, and a third capacitor;

[0026] The gate of the first transistor is coupled to the first clock terminal, the first electrode of the first transistor is coupled to the start signal terminal, and the second electrode of the first transistor is coupled to the first node;

[0027] The gate of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the first clock terminal, and the first electrode of the second transistor is coupled to the second node;

[0028] The gate of the third transistor is coupled to the first clock terminal, the first electrode of the third transistor is coupled to the second power supply terminal, and the second electrode of the third transistor is coupled to the second node;

[0029] The gate of the fourth transistor is coupled to the tenth node, the first electrode of the fourth transistor is coupled to the second clock terminal, and the second electrode of the third transistor is coupled to the fifth node;

[0030] The gate of the fifth transistor is coupled to the second node, the first electrode of the fifth transistor is coupled to the first power supply terminal, and the second electrode of the fifth transistor is coupled to the fifth node;

[0031] The gate of the sixth transistor is coupled to the sixth node, the first electrode of the sixth transistor is coupled to the second clock terminal, and the second electrode of the sixth transistor is coupled to the third node;

[0032] The gate of the seventh transistor is coupled to the second clock terminal, the first electrode of the seventh transistor is coupled to the third node, and the second electrode of the seventh transistor is coupled to the fourth node;

[0033] The gate of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the first power supply terminal, and the second electrode of the eighth transistor is coupled to the fourth node;

[0034] The gate of the ninth transistor is coupled to the fourth node, the first electrode of the ninth transistor is coupled to the first power supply terminal, and the second electrode of the ninth transistor is coupled to the previous stage output terminal;

[0035] The gate of the tenth transistor is coupled to the seventh node, the first electrode of the tenth transistor is coupled to the second power supply terminal, and the second electrode of the tenth transistor is coupled to the previous stage output terminal;

[0036] The gate of the eleventh transistor is coupled to the second power supply terminal, the first electrode of the eleventh transistor is coupled to the second node, and the second electrode of the eleventh transistor is coupled to the sixth node;

[0037] The gate of the twelfth transistor is coupled to the second power supply terminal, the first electrode of the twelfth transistor is coupled to the first node, and the second electrode of the twelfth transistor is coupled to the seventh node;

[0038] The gate of the thirteenth transistor is coupled to the potential control terminal, the first electrode of the thirteenth transistor is coupled to the first power supply terminal, and the second electrode of the thirteenth transistor is coupled to the first node;

[0039] The gate of the fourteenth transistor is coupled to the first clock terminal, the first electrode of the fourteenth transistor is coupled to the start signal terminal, and the second electrode of the fourteenth transistor is coupled to the eighth node;

[0040] The gate of the fifteenth transistor is coupled to the second power supply terminal, the first electrode of the fifteenth transistor is coupled to the eighth node, and the second electrode of the fifteenth transistor is coupled to the ninth node;

[0041] The gate and the first electrode of the sixteenth transistor are both coupled to the ninth node, and the second electrode of the sixteenth transistor is coupled to the seventh node;

[0042] One end of the first capacitor is coupled to the sixth node, and the other end of the first capacitor is coupled to the third node; one end of the second capacitor is coupled to the fourth node, and the other end of the second capacitor is coupled to the first power supply terminal; one end of the third capacitor is coupled to the fifth node, and the other end of the third capacitor is coupled to the ninth node.

[0043] Optionally, the transistor in the pre-stage driving circuit is a P-type transistor, and the material of the P-type transistor includes low-temperature polysilicon;

[0044] The potential of the first power signal provided by the first power end is greater than the potential of the second power signal provided by the second power end.

[0045] In another aspect, a driving method of a shift register unit is provided, which is applied to the shift register unit as described in the above aspect; the method comprises:

[0046] The front-stage driving circuit controls the first power supply terminal and the second power supply terminal to be connected to the front-stage output terminal in sequence based on the driving control signal provided by the driving control terminal;

[0047] If the potential of the front-stage signal from the front-stage output terminal is less than the potential threshold, the rear-stage control circuit controls the front-stage output terminal and the rear-stage output terminal to be connected based on the front-stage signal and the output control signal provided by the output control terminal, so that the front-stage output terminal transmits the front-stage signal to the rear-stage output terminal;

[0048] If the potential of the front-stage signal is greater than the potential threshold, the rear-stage control circuit controls the output control terminal to be conductive with the rear-stage output terminal based on the front-stage signal and the output control signal provided by the output control terminal, so that the output control terminal transmits the output control signal to the rear-stage output terminal, and the potential of the transmitted output control signal is not less than the potential of the first power signal;

[0049] The potential threshold is between the potential of the first power signal and the potential of the second power signal provided by the second power terminal.

[0050] Optionally, the pre-stage driving circuit controls the conduction duration between the first power supply terminal and the pre-stage output terminal to be shorter than the conduction duration between the second power supply terminal and the pre-stage output terminal; the output control terminal includes: a first output control terminal and a second output control terminal, and the potential of the output control signal provided by the second output control terminal is not less than the potential of the first power signal;

[0051] The latter stage control circuit controls the former stage output terminal and the latter stage output terminal to be connected based on the former stage signal and the output control signal provided by the output control terminal, including:

[0052] The latter stage control circuit controls the former stage output terminal to be connected with the latter stage output terminal based on the former stage signal and the output control signal provided by the first output control terminal;

[0053] The latter stage control circuit controls the output control terminal to be connected to the latter stage output terminal based on the former stage signal and the output control signal provided by the output control terminal, including:

[0054] The subsequent stage control circuit controls the previous stage output terminal to disconnect from the subsequent stage output terminal based on the previous stage signal and the output control signal provided by the first output control terminal, and connects the second output control terminal to the subsequent stage output terminal.

[0055] Optionally, the potential of the output control signal provided by the first output control terminal is positively correlated with the potential threshold.

[0056] In yet another aspect, a gate driving circuit is provided, comprising: at least two cascaded shift register units as described in the above aspect.

[0057] In another aspect, a display device is provided, comprising: a display panel, and the gate driving circuit as described in the above-mentioned further aspect;

[0058] The display panel includes a plurality of pixels, and the gate driving circuit is coupled to the plurality of pixels and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

[0059] Optionally, the transistor in the pixel is an N-type transistor, and the material of the N-type transistor includes: oxide material. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0061] FIG1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure;

[0062] FIG2 is a waveform diagram of an output signal of a shift register unit in a related art;

[0063] FIG3 is a waveform diagram of an output signal of a shift register unit provided by an embodiment of the present disclosure;

[0064] FIG4 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0065] FIG5 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0066] FIG6 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure;

[0067] FIG7 is a flow chart of a driving method of a shift register unit provided in an embodiment of the present disclosure;

[0068] FIG8 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present disclosure;

[0069] FIG9 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0070] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0071] It should be noted that the transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as the first electrode, and the drain is referred to as the second electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is designated as the control electrode, which can also be referred to as the gate, the signal input end is designated as the source electrode, and the signal output end is designated as the drain electrode. Furthermore, the switching transistors used in the embodiments of the present disclosure can include either a P-type switching transistor or an N-type switching transistor. A P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, while an N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. Furthermore, multiple signals in each embodiment of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential merely represent that the potential of the signal has two state variables and do not imply that the first potential or the second potential has a specific value throughout the text.

[0072] At present, common display panels include organic light-emitting diode (OLED) display panels, which have the advantages of self-luminescence, fast response speed, and low energy consumption. In the field of OLED display, a GOA circuit including a P-type transistor is often used in combination with a pixel including an N-type transistor to achieve high-precision frequency conversion display drive. The material of the P-type transistor generally includes low-temperature polysilicon (LTPS) material, and the material of the N-type transistor generally includes oxide material. Accordingly, it is also called LTPO architecture. The material of the transistor refers to the material of the active layer included in the transistor.

[0073] However, tests have found that in the OLED LTPO architecture, because each GOA unit in the GOA circuit often needs to output a low-voltage drive signal for a long time, the transistors in the GOA unit are prone to negative characteristic offset problems. The output drive signal is prone to generating a VX platform (VX refers to the intermediate potential between the normal high potential and the normal low potential of the drive signal), resulting in poor output stability and reliability issues. The accelerated deterioration of this reliability problem can cause horizontal stripes on the OLED display panel.

[0074] The disclosed embodiment optimizes the design of the current GOA unit. The driving signal output by the optimized GOA unit does not have a VX platform, that is, the VX platform can be optimized, thereby eliminating the horizontal stripes caused by the charging difference between pixels in different rows due to the output instability difference. That is, different pixels can be reliably driven to emit light normally, so that the display effect of the display panel can be better.

[0075] FIG1 is a schematic diagram of the structure of a shift register unit provided by an embodiment of the present disclosure. As shown in FIG1 , the shift register unit includes: a front-stage driving circuit 01 and a rear-stage control circuit 02 .

[0076] Among them, the pre-stage driving circuit 01 is coupled to the driving control terminal V1, the first power supply terminal VGH, the second power supply terminal VGL and the pre-stage output terminal Out respectively, and the pre-stage driving circuit 01 is configured to: based on the driving control signal provided by the driving control terminal V1, control the on-off of the first power supply terminal VGH and the pre-stage output terminal Out, and control the on-off of the second power supply terminal VGL and the pre-stage output terminal Out.

[0077] For example, the pre-stage driver circuit 01 can, under the control of a driving control signal provided by the driving control terminal V1, control the first power terminal VGH to be conductively connected to the pre-stage output terminal Out, so that the first power signal provided by the first power terminal VGH can be transmitted to the pre-stage output terminal Out. In this case, the pre-stage driver circuit 01 can also control the second power terminal VGL to be decoupled from the pre-stage output terminal Out. Furthermore, the pre-stage driver circuit 01 can, under the control of a driving control signal, control the second power terminal VGL to be conductively connected to the pre-stage output terminal Out, so that the second power signal provided by the second power terminal VGL can be transmitted to the pre-stage output terminal Out. In this case, the pre-stage driver circuit 01 can also control the first power terminal VGH or the second power terminal VGL to be decoupled from the pre-stage output terminal Out. That is, during the same period, the pre-stage driver circuit 01 can control the first power terminal VGH or the second power terminal VGL to be conductively connected to the pre-stage output terminal Out to output the first power signal or the second power signal to the pre-stage output terminal Out.

[0078] Furthermore, the conduction period between the first power supply terminal VGH and the front-stage output terminal Out can be shorter than the conduction period between the second power supply terminal VGL and the front-stage output terminal Out. That is, the front-stage driver circuit 01 can permanently output the second power supply signal to the front-stage output terminal Out. In other words, the potential of the first power supply signal can be considered the effective potential output to the front-stage output terminal Out, while the potential of the second power supply signal can be considered the ineffective potential output to the front-stage output terminal Out. Driven by the effective potential, the pixel can be driven to emit light.

[0079] Optionally, the potential of the first power signal may be a high potential, and the potential of the second power signal may be a low potential. High potential and low potential are relative. Of course, in some other embodiments, the potential of the first power signal may also be a low potential, and the potential of the second power signal may also be a high potential.

[0080] Continuing with reference to FIG1 , the post-stage control circuit 02 is coupled to the pre-stage output terminal Out, the output control terminal ConV, and the post-stage output terminal Out-Put, respectively. The post-stage output terminal Out-Put is used to couple to a pixel 9 (not shown) in the display panel. The post-stage control circuit 02 is configured to: based on the pre-stage signal from the pre-stage output terminal Out and the output control signal provided by the output control terminal ConV, control the pre-stage output terminal Out to conduct with the post-stage output terminal Out-Put, so that the pre-stage output terminal Out transmits the pre-stage signal to the post-stage output terminal Out-Put; or control the output control terminal ConV to conduct with the post-stage output terminal Out-Put, so that the output control terminal ConV transmits the output control signal to the post-stage output terminal Out-Put, and the potential of the output control signal transmitted to the post-stage output terminal Out-Put is not less than (i.e., greater than or equal to) the potential of the first power supply signal provided by the first power supply terminal VGH.

[0081] In the related art, the shift register unit directly sets the pre-stage drive circuit 01 to couple with the pixel through the pre-stage output terminal Out to transmit the drive signal to the pixel and drive the pixel to emit light, that is, the post-stage control circuit 02 is not set. Based on this setting, due to the negative characteristic offset caused by the long-term output low potential, the drive signal transmitted to the pixel often appears to have a VX platform as shown in Figure 2. That is, assuming that the potential of the first power supply signal is 7.5 volts (V) and the potential of the second power supply signal is -8V, then an intermediate potential VX between 7.5V and -8V is likely to appear, and the duration of the intermediate potential VX is greater than or equal to 2H. In addition, the value of VX varies for different rows of pixels. For example, referring to Figure 2, it schematically shows three rows of pixels, namely the Nth row, the Mth row, and the Lth row. When driving the pixels in the Nth row, the Mth row, and the Lth row to emit light, the VX of the drive signal transmitted to the pixel is -4V, -2V, and 0, respectively. As a result, it is easy to cause the display abnormality problem of horizontal stripes as described in the above embodiment. N, M, and L are all integers greater than or equal to 1 and different from each other.

[0082] Based on this, the embodiment of the present disclosure additionally sets a post-stage control circuit 02 between the pre-stage output terminal Out and the pixel, so that the pre-stage driving circuit 01 is indirectly coupled to the pixel through the post-stage control circuit 02. That is, instead of directly setting the pre-stage output terminal Out to couple with the pixel, the post-stage control circuit 02 is set to indirectly couple the pre-stage output terminal Out with the pixel through the post-stage output terminal Out-Put. On this basis, combined with the working principle of the post-stage control circuit 02, it can be seen that the embodiment of the present disclosure can eliminate the VX platform and solve the display abnormality problem of bad horizontal stripes in the following manner. For example, the post-stage control circuit 02 is configured as follows:

[0083] If the potential of the pre-stage signal from the pre-stage output terminal Out is less than the potential threshold, the pre-stage output terminal Out and the post-stage output terminal Out-Put are controlled to be conductive, so that the pre-stage output terminal Out directly transmits the pre-stage signal to the pixel coupled to the post-stage output terminal Out-Put, driving the pixel to emit light. In other words, the driving signal transmitted to the pixel is the pre-stage signal. This can also be considered as synchronizing the pre-stage signal from the pre-stage output terminal Out to the post-stage output terminal Out-Put.

[0084] If the potential of the pre-stage signal from the pre-stage output terminal Out is greater than the potential threshold, the output control terminal ConV is controlled to be conductive with the post-stage output terminal Out-Put, so that the output control terminal ConV, rather than the pre-stage output terminal Out, transmits the output control signal to the pixel coupled to the post-stage output terminal Out-Put, thereby driving the pixel to emit light. In other words, the drive signal transmitted to the pixel is the output control signal. Furthermore, it should be noted that the potential of the output control signal transmitted to the pixel coupled to the post-stage output terminal Out-Put at this time is greater than or equal to the potential of the first power supply signal. Preferably, the potential of the transmitted output control signal is equal to the potential of the first power supply signal.

[0085] It should be noted that the potential threshold can be a predetermined value between the potential of the first power signal and the potential of the second power signal. In addition, in some embodiments of the present disclosure, the potential of the front-stage signal being less than the potential threshold can be used to indicate that the potential of the front-stage signal is close to the potential of the second power signal, and the potential difference between the potential of the front-stage signal and the first power signal is greater than the difference threshold; the potential of the front-stage signal being greater than the potential threshold can be used to indicate that the potential of the front-stage signal is close to the potential of the first power signal, and the potential difference between the potential of the front-stage signal and the first power signal is less than the difference threshold. Under such logic, once the potential of the front-stage signal is greater than the potential threshold, that is, close to the potential of the first power signal, a VX platform appears, the potential of the signal transmitted to the rear-stage output terminal Out-Put (that is, the driving signal ultimately transmitted to the pixel) can be directly controlled by the rear-stage control circuit 02 to be close to the potential of the first power signal, without synchronously transmitting the front-stage signal whose potential is the intermediate potential VX output by the front-stage output terminal Out to the rear-stage output terminal Out-Put, thereby eliminating the VX platform and improving the horizontal stripe defect problem. When the potential of the current stage signal is less than the potential threshold, that is, far away from the potential of the first power supply signal, the previous stage signal from the previous stage output terminal Out can be synchronized to the next stage output terminal Out-Put through the next stage control circuit 02, that is, the previous stage signal is transmitted to the pixel as a driving signal.

[0086] For example, in a scenario where the potential of the first power signal is 7.5V and the potential of the second power signal is -8V, the potential threshold may be -5V. Based on this, a comparison of the waveforms shown in FIG2 and FIG3 shows that once the potential of the pre-stage signal is higher than -5V (e.g., equal to -4V, -2, or 0), i.e., the potential of the pre-stage signal approaches the potential of the first power signal, i.e., the VX platform shown in FIG2 appears, the potential of the drive signal transmitted to the pixel via the post-stage output terminal Out-Put can be directly controlled by the post-stage control circuit 02 to be equal to the potential of the first power signal, i.e., to 7.5V, thereby eliminating the VX platform. Conversely, if the potential of the pre-stage signal is lower than -5V (e.g., equal to -8V), i.e., the potential of the pre-stage signal approaches the potential of the second power signal, the post-stage control circuit 02 can directly synchronize the pre-stage signal outputted from the pre-stage output terminal Out to the post-stage output terminal Out-Put, i.e., transmit a drive signal having a potential equal to the potential of the pre-stage signal, e.g., -8V, to the pixel. In this example, even if the driving signal transmitted to each row of pixels has potential fluctuations due to high temperature reliability and process fluctuations, the potential fluctuations can be controlled between 0 and -5V, ensuring output uniformity.

[0087] In summary, an embodiment of the present disclosure provides a shift register unit. The shift register unit includes a front-stage driving circuit and a rear-stage control circuit. The front-stage driving circuit can control the first power supply terminal or the second power supply terminal to be connected to the front-stage output terminal, and transmit the front-stage signal to the front-stage output terminal. The rear-stage control circuit can control the front-stage output terminal or the output control terminal to be connected to the rear-stage output terminal coupled to the pixel based on the front-stage signal and the output control signal provided by the output control terminal, and when the output control terminal is controlled to be connected to the rear-stage output terminal, the potential of the transmitted output control signal is greater than or equal to the potential of the first power signal provided by the first power supply terminal. In this way, when the potential of the front-stage signal is close to the potential of the first power signal but a step abnormality of the intermediate potential occurs, the potential of the drive signal transmitted to the pixel is directly controlled to be close to the potential of the first power signal, thereby eliminating the step abnormality, ensuring better output stability, and thus ensuring better display effect of the display panel.

[0088] FIG4 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG4 , the output control terminal ConV described in the embodiment of the present disclosure may include: a first output control terminal LV and a second output control terminal HV, wherein the potential of the output control signal provided by the second output control terminal HV is not less than the potential of the first power supply signal. Based on this, the post-stage control circuit 02 described in the embodiment of the present disclosure may be configured as follows:

[0089] Based on the previous stage signal and the output control signal provided by the first output control terminal LV, the previous stage output terminal Out and the subsequent stage output terminal Out-Put are controlled to be connected. Moreover, when the previous stage output terminal Out is controlled to be disconnected from the subsequent stage output terminal Out-Put, the second output control terminal HV is connected to the subsequent stage output terminal Out-Put.

[0090] For example, if the potential of the front-stage signal is less than the potential threshold, the rear-stage control circuit 02 can control the front-stage output terminal Out and the rear-stage output terminal Out-Put to be connected based on the front-stage signal with a smaller potential and the output control signal provided by the first output control terminal LV. On the basis of controlling the front-stage output terminal Out and the rear-stage output terminal Out-Put to be connected, the second output control terminal HV can be disconnected from the rear-stage output terminal Out-Put. If the potential of the front-stage signal is greater than the potential threshold, the rear-stage control circuit 02 can control the front-stage output terminal Out and the rear-stage output terminal Out-Put to be disconnected based on the front-stage signal with a larger potential and the output control signal provided by the first output control terminal LV. On the basis of controlling the front-stage output terminal Out and the rear-stage output terminal Out-Put to be disconnected, the second output control terminal HV can be connected to the rear-stage output terminal Out-Put.

[0091] It can also be seen from this that the potential of the output control signal provided by the first output control terminal LV should be greater than the potential of the second power signal and less than the potential of the output control signal provided by the second output control terminal HV. For example, assuming that the potential threshold is -5V, the potential of the first power signal is +8V, the potential of the second power signal is -8V, and the potential of the output control signal provided by the second output control terminal HV is equal to the potential of the first power signal, then the potential of the output control signal provided by the first output control terminal LV can be set to -3V, and the potential of the output control signal provided by the second output control terminal HV can be set to +8V. Of course, the potential of the output control signal provided by the first output control terminal LV can be positively correlated with the potential threshold. That is, the smaller the potential threshold, the smaller the potential of the output control signal provided by the first output control terminal LV can be set; conversely, the larger the potential threshold, the larger the potential of the output control signal provided by the first output control terminal LV can be set. In other words, the potential of the output control signal provided by the first output control terminal LV can be dynamically set and adjustable according to product characteristics.

[0092] Optionally, as described in the above embodiments, the potential of the first power supply signal provided in the embodiment of the present disclosure is a high potential, and the potential of the second power supply signal is a low potential. Accordingly, the potential of the output control signal provided by the first output control terminal LV is a low potential. The output control signal provided by the second output control terminal HV is a high potential. Of course, in some other embodiments, a clock signal terminal can also be set to replace the first output control terminal LV and the second output control terminal HV, and the clock signal terminal can be set to flexibly provide the required clock signal as the output control signal based on the potential of the previous stage signal.

[0093] Optionally, based on Figure 4 , Figure 5 shows a structural diagram of another shift register provided by an embodiment of the present disclosure. As shown in Figure 5 , the post-stage control circuit 02 provided by an embodiment of the present disclosure may include: a switch sub-circuit 021 and an isolation sub-circuit 022 .

[0094] The switch sub-circuit 021 can be coupled to the first output control terminal LV, the pre-stage output terminal Out, and the post-stage output terminal Out-Put, respectively. The switch sub-circuit 021 can be configured to control the on / off switching of the pre-stage output terminal Out and the post-stage output terminal Out-Put based on the pre-stage signal and the output control signal provided by the first output control terminal LV.

[0095] The isolation sub-circuit 022 can be coupled to the second output control terminal HV and the subsequent-stage output terminal Out-Put, respectively. The isolation sub-circuit 022 can be configured to isolate the second output control terminal HV from the subsequent-stage output terminal Out-Put and, when the switch sub-circuit 021 controls the previous-stage output terminal Out to be disconnected from the subsequent-stage output terminal Out-Put, connect the second output control terminal HV and the subsequent-stage output terminal Out-Put.

[0096] Optionally, based on Figure 5, Figure 6 shows a circuit structure diagram of a shift register unit provided by an embodiment of the present disclosure. As shown in Figure 6, the switch subcircuit 021 may include: a switch K1 and a first resistor R1. The isolation subcircuit 022 may include: a second resistor R2.

[0097] The control end of the switch K1 may be coupled to the first output control end LV, the input end of the switch K1 may be coupled to the previous stage output end Out, and the output end of the switch K1 may be coupled to the next stage output end Out-Put.

[0098] For example, still referring to FIG. 6 , it can be seen that the switch K1 may include: a switching transistor T0 .

[0099] Among them, the gate of the switching transistor T0 is coupled to the first output control terminal LV as the control terminal of the switch K1, the first electrode of the switching transistor T0 is coupled to the previous stage output terminal Out as the input terminal of the switch K1, and the second electrode of the switching transistor T0 is coupled to the next stage output terminal Out-Put as the output terminal of the switch K1.

[0100] Of course, in some other embodiments, the switch K1 may also include a single-pole single-throw switch.

[0101] One end of the first resistor R1 may be coupled to the previous-stage output terminal Out, and the other end of the first resistor R1 may be coupled to the first output control terminal LV.

[0102] One end of the second resistor R2 may be coupled to the second output control terminal HV, and the other end of the second resistor R2 may be coupled to the subsequent-stage output terminal Out-Put.

[0103] Optionally, referring to FIG. 4 and FIG. 5 , it can be seen that the driving control terminal V1 may include: a first clock terminal CK, a second clock terminal CB, a start signal terminal STV and a potential control terminal VEL.

[0104] The pre-stage driving circuit 01 can be configured to: control the on-off of the first power supply terminal VGH and the pre-stage output terminal Out, and control the on-off of the second power supply terminal VGL and the pre-stage output terminal Out based on the first clock signal provided by the first clock terminal CK, the second clock signal provided by the second clock terminal CB, the start signal provided by the start signal terminal STV, the potential control signal provided by the potential control terminal VEL, and the first power supply signal and the second power supply signal provided by the second power supply terminal VGL.

[0105] Optionally, continuing to refer to Figure 6, it can be seen that the pre-stage driving circuit 01 may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a first capacitor C1, a second capacitor C2 and a third capacitor C3.

[0106] The gate of the first transistor T1 may be coupled to the first clock terminal CK, the first electrode of the first transistor T1 may be coupled to the start signal terminal STV, and the second electrode of the first transistor T1 may be coupled to the first node N1.

[0107] A gate of the second transistor T2 may be coupled to the first node N1 , a first electrode of the second transistor T2 may be coupled to the first clock terminal CK, and a first electrode of the second transistor T2 may be coupled to the second node N2 .

[0108] A gate of the third transistor T3 may be coupled to the first clock terminal CK, a first electrode of the third transistor T3 may be coupled to the second power supply terminal VGL, and a second electrode of the third transistor T3 may be coupled to the second node N2.

[0109] A gate of the fourth transistor T4 may be coupled to the tenth node N10 , a first electrode of the fourth transistor T4 may be coupled to the second clock terminal CB, and a second electrode of the third transistor T3 may be coupled to the fifth node N5 .

[0110] A gate of the fifth transistor T5 may be coupled to the second node N2 , a first electrode of the fifth transistor T5 may be coupled to the first power supply terminal VGH, and a second electrode of the fifth transistor T5 may be coupled to the fifth node N5 .

[0111] A gate of the sixth transistor T6 may be coupled to the sixth node N6 , a first electrode of the sixth transistor T6 may be coupled to the second clock terminal CB, and a second electrode of the sixth transistor T6 may be coupled to the third node N3 .

[0112] A gate of the seventh transistor T7 may be coupled to the second clock terminal CB, a first electrode of the seventh transistor T7 may be coupled to the third node N3 , and a second electrode of the seventh transistor T7 may be coupled to the fourth node N4 .

[0113] A gate of the eighth transistor T8 may be coupled to the first node N1 , a first electrode of the eighth transistor T8 may be coupled to the first power supply terminal VGH, and a second electrode of the eighth transistor T8 may be coupled to the fourth node N4 .

[0114] A gate of the ninth transistor T9 may be coupled to the fourth node N4 , a first electrode of the ninth transistor T9 may be coupled to the first power supply terminal VGH, and a second electrode of the ninth transistor T9 may be coupled to the previous-stage output terminal Out.

[0115] A gate of the tenth transistor T10 may be coupled to the seventh node N7 , a first electrode of the tenth transistor T10 may be coupled to the second power supply terminal VGL, and a second electrode of the tenth transistor T10 may be coupled to the previous-stage output terminal Out.

[0116] A gate of the eleventh transistor T11 may be coupled to the second power supply terminal VGL, a first electrode of the eleventh transistor T11 may be coupled to the second node N2 , and a second electrode of the eleventh transistor T11 may be coupled to the sixth node N6 .

[0117] A gate of the twelfth transistor T12 may be coupled to the second power supply terminal VGL, a first electrode of the twelfth transistor T12 may be coupled to the first node N1 , and a second electrode of the twelfth transistor T12 may be coupled to the seventh node N7 .

[0118] A gate of the thirteenth transistor T13 may be coupled to the potential control terminal VEL, a first electrode of the thirteenth transistor T13 may be coupled to the first power supply terminal VGH, and a second electrode of the thirteenth transistor T13 may be coupled to the first node N1.

[0119] A gate of the fourteenth transistor T14 may be coupled to the first clock terminal CK, a first electrode of the fourteenth transistor T14 may be coupled to the start signal terminal STV, and a second electrode of the fourteenth transistor T14 may be coupled to the eighth node N8.

[0120] A gate of the fifteenth transistor T15 may be coupled to the second power supply terminal VGL, a first electrode of the fifteenth transistor T15 may be coupled to the eighth node N8 , and a second electrode of the fifteenth transistor T15 may be coupled to the ninth node N9 .

[0121] A gate electrode and a first electrode of the sixteenth transistor T16 may both be coupled to the ninth node N9 , and a second electrode of the sixteenth transistor T16 may be coupled to the seventh node N7 .

[0122] One end of the first capacitor C1 may be coupled to the sixth node N6, and the other end of the first capacitor C1 may be coupled to the third node N3. One end of the second capacitor C2 may be coupled to the fourth node N4, and the other end of the second capacitor C2 may be coupled to the first power supply terminal VGH. One end of the third capacitor C3 may be coupled to the fifth node N5, and the other end of the third capacitor C3 may be coupled to the ninth node N9.

[0123] Alternatively, referring to FIG6 , it can be seen that the transistors in the front-stage driver circuit 01 can all be P-type transistors, and the material of the P-type transistors can include low-temperature polysilicon (LTPS). In addition, the switching transistor T0 included in the rear-stage control circuit 02 can also be a P-type transistor made of LTPS material.

[0124] It should be noted that the pre-stage driver circuit 01 in the shift register unit shown in FIG6 can be considered to be a circuit with a 16T3C structure. In some other embodiments, the pre-stage driver circuit 01 can also be a circuit with other structures, such as 17T2C. This is not limited in the present embodiment.

[0125] Based on the structure shown in FIG6 , the operating principle of the post-stage control circuit 02 is described as follows, assuming that the potential of the first power supply signal is +7.5V, the potential of the first output control signal provided by the first output control terminal LV is set to -3V, the potential of the second output control signal provided by the second output control terminal HV is equal to the potential of the first power supply signal, that is, +7.5V, and the threshold voltage Vth of the switching transistor T0 is -2V.

[0126] When the voltage of the pre-stage signal transmitted by the pre-stage driver circuit O1 to the pre-stage output terminal Out is less than -5V, the switching transistor T0 can be turned on, thereby connecting the pre-stage output terminal Out and the post-stage output terminal Out-Put. At this time, the pre-stage signal with a voltage less than -5V can be synchronously transmitted to the post-stage output terminal Out-Put via the turned-on switching transistor T0, causing the post-stage output terminal Out-Put to output a low voltage. In other words, the voltage of the driving signal transmitted to the pixel via the post-stage output terminal Out-Put is low.

[0127] When the potential of the pre-stage signal transmitted by the pre-stage driver circuit O1 to the pre-stage output terminal Out is greater than -5V, the switching transistor T0 can be turned off, thereby disconnecting the pre-stage output terminal Out from the post-stage output terminal Out-Put. At this time, the second output control terminal HV can transmit an output control signal with a potential of +7.5V to the post-stage output terminal Out-Put, causing the post-stage output terminal Out-Put to output a high voltage. In other words, the potential of the drive signal transmitted to the pixel via the post-stage output terminal Out-Put is high and equal to the potential of the first power supply signal.

[0128] This also shows that the potential threshold in the above scenario can be -5 V. Based on this logic, comparing Figures 2 and 3 shows that the VX platform can be eliminated, making the potential difference of the drive signal transmitted to each row of pixels small or even zero, making the potential as uniform as possible, thereby ensuring a good display effect.

[0129] In summary, an embodiment of the present disclosure provides a shift register unit. The shift register unit includes a front-stage driving circuit and a rear-stage control circuit. The front-stage driving circuit can control the first power supply terminal or the second power supply terminal to be connected to the front-stage output terminal, and transmit the front-stage signal to the front-stage output terminal. The rear-stage control circuit can control the front-stage output terminal or the output control terminal to be connected to the rear-stage output terminal coupled to the pixel based on the front-stage signal and the output control signal provided by the output control terminal, and when the output control terminal is controlled to be connected to the rear-stage output terminal, the potential of the transmitted output control signal is greater than or equal to the potential of the first power signal provided by the first power supply terminal. In this way, when the potential of the front-stage signal is close to the potential of the first power signal but a step abnormality of the intermediate potential occurs, the potential of the drive signal transmitted to the pixel is directly controlled to be close to the potential of the first power signal, thereby eliminating the step abnormality, ensuring better output stability, and thus ensuring better display effect of the display panel.

[0130] FIG7 is a flow chart of a driving method of a shift register unit provided in an embodiment of the present disclosure, which is applied to the shift register unit described in the above embodiment of the present disclosure. As shown in FIG7 , the method includes:

[0131] Step 701: The front-stage driving circuit controls the first power supply terminal and the second power supply terminal to be connected to the front-stage output terminal in sequence based on the driving control signal provided by the driving control terminal.

[0132] Step 702: If the potential of the front-stage signal from the front-stage output terminal is less than the potential threshold, the rear-stage control circuit controls the front-stage output terminal and the rear-stage output terminal to be connected based on the front-stage signal and the output control signal provided by the output control terminal, so that the front-stage output terminal transmits the front-stage signal to the rear-stage output terminal.

[0133] Step 703: If the potential of the front-stage signal is greater than the potential threshold, the rear-stage control circuit controls the output control terminal to be connected with the rear-stage output terminal based on the front-stage signal and the output control signal provided by the output control terminal, so that the output control terminal transmits the output control signal to the rear-stage output terminal, and the potential of the transmitted output control signal is not less than the potential of the first power supply signal.

[0134] The potential threshold is between the potential of the first power signal and the potential of the second power signal provided by the second power terminal.

[0135] Optionally, the conduction time length between the first power supply terminal and the front-stage output terminal controlled by the front-stage driving circuit may be shorter than the conduction time length between the second power supply terminal and the front-stage output terminal controlled by the front-stage driving circuit.

[0136] Optionally, referring to FIG4 to FIG6 , it can be seen that the output control terminal ConV may include: a first output control terminal LV and a second output control terminal HV, and the potential of the output control signal provided by the second output control terminal HV is not less than the potential of the first power supply signal. On this basis,

[0137] The post-stage control circuit controls the conduction between the pre-stage output terminal and the post-stage output terminal based on the pre-stage signal and the output control signal provided by the output control terminal, that is, the above step 702 may include: the post-stage control circuit controls the conduction between the pre-stage output terminal and the post-stage output terminal based on the pre-stage signal and the output control signal provided by the first output control terminal.

[0138] The subsequent stage control circuit controls the output control terminal to be connected to the subsequent stage output terminal based on the previous stage signal and the output control signal provided by the output control terminal. That is, the above step 703 may include:

[0139] The subsequent control circuit controls the previous stage output terminal to disconnect from the subsequent stage output terminal based on the previous stage signal and the output control signal provided by the first output control terminal, and connects the second output control terminal to the subsequent stage output terminal.

[0140] Optionally, in some embodiments, the potential of the output control signal provided by the first output control terminal may be positively correlated with the potential threshold.

[0141] Since the driving method of the shift register unit can have substantially the same implementation manner and technical effects as the shift register unit described in the previous embodiment, it will not be described again here for the purpose of brevity.

[0142] FIG8 is a schematic diagram of the structure of a gate drive circuit provided by an embodiment of the present disclosure. As shown in FIG8 , the gate drive circuit includes: at least two cascaded shift register units 00 as described in the above-mentioned embodiment of the present disclosure. For example, FIG8 shows three cascaded shift register units 00_1, 00_2, and 00_3.

[0143] The output terminal Out-Put of each stage of the shift register unit 00 can be cascaded with the shift register unit 00 of the next stage, and can be coupled to the pixels in the display panel to transmit gate drive signals to the pixels, thereby driving the pixels to emit light. Here, the shift register unit 00 included in the gate drive circuit can be coupled to the pixels through the gate line Gate to instruct the data signal line to transmit data signals to the pixels.

[0144] Of course, in some other embodiments, other display driving circuits besides the gate driving circuit may also include the shift register unit 00 as described in the above-mentioned embodiment of the present disclosure to ensure better output stability, thereby better improving the display effect of the display panel. For example, a light-emitting driving circuit is coupled to the pixel through the light-emitting control line EM to instruct the driving power line VDD to transmit the driving power signal to the pixel. That is, the light-emitting driving circuit may also be a GOA circuit integrated in the substrate, including a plurality of cascaded GOA units. Alternatively, a reset driving circuit is coupled to the pixel through the reset line Reset to instruct the reset power line Vinit to transmit the reset power signal to the pixel. That is, the reset driving circuit may also be a GOA circuit integrated in the substrate, including a plurality of cascaded GOA units. All of this is merely a schematic illustration.

[0145] FIG9 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG9 , the display device includes: a display panel 100 and a gate driving circuit 000 as shown in FIG8 .

[0146] The display panel 100 includes a plurality of pixels (not shown in the figure), and the gate driving circuit 000 is coupled to the plurality of pixels and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

[0147] Optionally, the transistor in the pixel may be an N-type transistor, and the material of the N-type transistor may include an oxide material. Thus, in combination with the LTPS GOA circuit described in the above embodiment, the display device may be a LTPO architecture setting.

[0148] As described in the above embodiment, the gate driver circuit 000 can be coupled to multiple rows of pixels in a one-to-one correspondence via multiple gate lines. In other embodiments, the display device may further include a light-emitting driver circuit and a reset driver circuit. Both the light-emitting driver circuit and the reset driver circuit also include the shift register unit described in the above embodiment, coupled to multiple rows of pixels in a one-to-one correspondence to drive the pixels to emit light.

[0149] Optionally, the display device described in the embodiments of the present disclosure may be any product or component having a display function, such as an OLED display device and an active-matrix organic light-emitting diode (AMOLED) display device.

[0150] AMOLED displays offer low power consumption, a wide operating temperature range, low cost, high contrast, wide viewing angles, a wide color gamut, and thin display panels, enabling flexible displays and are poised to become the next generation of display technology. OLED displays meet most of the high-performance and high-capacity requirements of today's information age. They can be used for indoor and outdoor lighting, decorative wallpaper, and foldable electronic newspapers. They can also be incorporated into portable electronic products such as mobile phones, tablets, and wearable electronics.

[0151] It should be noted that the terms used in the examples of this disclosure are only used to explain the examples and are not intended to limit the present disclosure. Unless otherwise defined, technical terms or scientific terms used in the embodiments of this disclosure should have the common meanings understood by people with ordinary skills in the field to which this disclosure belongs.

[0152] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Connected" or "coupled" refers to an electrical connection. Similarly, words such as "one" or "a" do not indicate a quantity limitation, but rather indicate the presence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before "include" or "comprises" cover the elements or objects listed after "include" or "comprises" and their equivalents, and do not exclude other elements or objects. "Up", "down", "left" or "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0153] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A shift register unit, comprising: A front-stage driving circuit is coupled to the driving control terminal, the first power terminal, the second power terminal and the front-stage output terminal respectively, and the front-stage driving circuit is configured to: based on the driving control signal provided by the driving control terminal, control the on-off of the first power terminal and the front-stage output terminal, and control the on-off of the second power terminal and the front-stage output terminal; A post-stage control circuit is coupled to the front-stage output terminal, the output control terminal and the post-stage output terminal respectively, and the post-stage output terminal is used to couple with the pixels in the display panel. The post-stage control circuit is configured to: based on the front-stage signal from the front-stage output terminal and the output control signal provided by the output control terminal, control the front-stage output terminal to be connected with the post-stage output terminal so that the front-stage output terminal transmits the front-stage signal to the post-stage output terminal, or control the output control terminal to be connected with the post-stage output terminal so that the output control terminal transmits the output control signal to the post-stage output terminal, and the potential of the transmitted output control signal is not less than the potential of the first power supply signal provided by the first power supply terminal.

2. The shift register unit according to claim 1, wherein: The conduction time between the first power supply terminal and the front-stage output terminal is shorter than the conduction time between the second power supply terminal and the front-stage output terminal; The output control terminal comprises: a first output control terminal and a second output control terminal, wherein the potential of the output control signal provided by the second output control terminal is not less than the potential of the first power supply signal; The post-stage control circuit is configured to: control the connection and disconnection of the front-stage output terminal and the post-stage output terminal based on the front-stage signal and the output control signal provided by the first output control terminal; and when the front-stage output terminal is controlled to be disconnected from the post-stage output terminal, the second output control terminal is connected to the post-stage output terminal.

3. The shift register unit according to claim 2, wherein: The post-stage control circuit comprises: a switch subcircuit, coupled to the first output control terminal, the front-stage output terminal and the rear-stage output terminal respectively, and configured to: control the on-off of the front-stage output terminal and the rear-stage output terminal based on the front-stage signal and the output control signal provided by the first output control terminal; The isolation subcircuit is coupled to the second output control terminal and the subsequent output terminal respectively, and is configured to: isolate the second output control terminal and the subsequent output terminal, and when the switch subcircuit controls When the front-stage output terminal is disconnected from the rear-stage output terminal, the second output control terminal and the rear-stage output terminal are connected.

4. The shift register unit according to claim 3, wherein: The switch subcircuit comprises: a switch and a first resistor; The control end of the switch is coupled to the first output control end, the input end of the switch is coupled to the previous stage output end, and the output end of the switch is coupled to the next stage output end; One end of the first resistor is coupled to the previous stage output end, and the other end of the first resistor is coupled to the first output control end.

5. The shift register unit according to claim 4, wherein: The switch comprises: a switching transistor; Among them, the gate of the switching transistor is coupled to the first output control end as the control end of the switch, the first electrode of the switching transistor is coupled to the front-stage output end as the input end of the switch, and the second electrode of the switching transistor is coupled to the rear-stage output end as the output end of the switch.

6. The shift register unit according to any one of claims 3 to 5, wherein: The isolation subcircuit includes: a second resistor; One end of the second resistor is coupled to the second output control end, and the other end of the second resistor is coupled to the subsequent output end.

7. The shift register unit according to any one of claims 1 to 6, wherein: The driving control terminal includes: a first clock terminal, a second clock terminal, a start signal terminal and a potential control terminal; The pre-stage driving circuit is configured to: control the on-off of the first power supply terminal and the pre-stage output terminal, and control the on-off of the second power supply terminal and the pre-stage output terminal based on the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, the start signal provided by the start signal terminal, the potential control signal provided by the potential control terminal, and the first power supply signal and the second power supply signal provided by the second power supply terminal.

8. The shift register unit according to claim 7, wherein: The front-stage driving circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a first capacitor, a second capacitor and a third capacitor; Wherein, the gate of the first transistor is coupled to the first clock terminal, the first electrode of the first transistor is coupled to the start signal terminal, and the second electrode of the first transistor is coupled to the first node; The gate of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the first clock terminal, and the first electrode of the second transistor is coupled to the second node; The gate of the third transistor is coupled to the first clock terminal, the first electrode of the third transistor is coupled to the second power supply terminal, and the second electrode of the third transistor is coupled to the second node; The gate of the fourth transistor is coupled to the tenth node, the first electrode of the fourth transistor is coupled to the second clock terminal, and the second electrode of the third transistor is coupled to the fifth node; The gate of the fifth transistor is coupled to the second node, the first electrode of the fifth transistor is coupled to the first power supply terminal, and the second electrode of the fifth transistor is coupled to the fifth node; The gate of the sixth transistor is coupled to the sixth node, the first electrode of the sixth transistor is coupled to the second clock terminal, and the second electrode of the sixth transistor is coupled to the third node; The gate of the seventh transistor is coupled to the second clock terminal, the first electrode of the seventh transistor is coupled to the third node, and the second electrode of the seventh transistor is coupled to the fourth node; The gate of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the first power supply terminal, and the second electrode of the eighth transistor is coupled to the fourth node; The gate of the ninth transistor is coupled to the fourth node, the first electrode of the ninth transistor is coupled to the first power supply terminal, and the second electrode of the ninth transistor is coupled to the previous stage output terminal; The gate of the tenth transistor is coupled to the seventh node, the first electrode of the tenth transistor is coupled to the second power supply terminal, and the second electrode of the tenth transistor is coupled to the previous stage output terminal; The gate of the eleventh transistor is coupled to the second power supply terminal, the first electrode of the eleventh transistor is coupled to the second node, and the second electrode of the eleventh transistor is coupled to the sixth node; The gate of the twelfth transistor is coupled to the second power supply terminal, the first electrode of the twelfth transistor is coupled to the first node, and the second electrode of the twelfth transistor is coupled to the seventh node; The gate of the thirteenth transistor is coupled to the potential control terminal, the first electrode of the thirteenth transistor is coupled to the first power supply terminal, and the second electrode of the thirteenth transistor is coupled to the first node; The gate of the fourteenth transistor is coupled to the first clock terminal, the first electrode of the fourteenth transistor is coupled to the start signal terminal, and the second electrode of the fourteenth transistor is coupled to the eighth node; The gate of the fifteenth transistor is coupled to the second power supply terminal, the first electrode of the fifteenth transistor is coupled to the eighth node, and the second electrode of the fifteenth transistor is coupled to the ninth node; The gate electrode and the first electrode of the sixteenth transistor are coupled to the ninth node, and the second electrode of the sixteenth transistor is coupled to the seventh node; One end of the first capacitor is coupled to the sixth node, and the other end of the first capacitor is coupled to the third node; one end of the second capacitor is coupled to the fourth node, and the other end of the second capacitor is coupled to the first power supply terminal; one end of the third capacitor is coupled to the fifth node, and the other end of the third capacitor is coupled to the ninth node.

9. The shift register unit according to any one of claims 1 to 8, wherein: The transistor in the front-stage driving circuit is a P-type transistor, and the material of the P-type transistor includes low-temperature polysilicon; The potential of the first power signal provided by the first power terminal is greater than the potential of the second power signal provided by the second power terminal.

10. A driving method of a shift register unit, applied to the shift register unit according to any one of claims 1 to 9; the method comprising: The front-stage driving circuit controls the first power supply terminal and the second power supply terminal to be connected to the front-stage output terminal in sequence based on the driving control signal provided by the driving control terminal; If the potential of the front-stage signal from the front-stage output terminal is less than the potential threshold, the rear-stage control circuit controls the front-stage output terminal to be connected with the rear-stage output terminal based on the front-stage signal and the output control signal provided by the output control terminal, so that the front-stage output terminal transmits the front-stage signal to the rear-stage output terminal; If the potential of the front-stage signal is greater than the potential threshold, the rear-stage control circuit controls the output control terminal to be connected to the rear-stage output terminal based on the front-stage signal and the output control signal provided by the output control terminal, so that the output control terminal transmits the output control signal to the rear-stage output terminal, and the potential of the transmitted output control signal is not less than the potential of the first power supply signal; The potential threshold is between the potential of the first power signal and the potential of the second power signal provided by the second power terminal.

11. The method according to claim 10, wherein: The front-stage driving circuit controls the conduction time between the first power supply terminal and the front-stage output terminal to be shorter than the conduction time between the second power supply terminal and the front-stage output terminal; The output control terminal comprises: a first output control terminal and a second output control terminal, wherein the potential of the output control signal provided by the second output control terminal is not less than the potential of the first power supply signal; The latter stage control circuit controls the former stage output terminal to be connected with the latter stage output terminal based on the former stage signal and the output control signal provided by the output control terminal, including: The latter stage control circuit controls the former stage output terminal to be connected with the latter stage output terminal based on the former stage signal and the output control signal provided by the first output control terminal; The latter stage control circuit controls the output control terminal to be connected with the latter stage output terminal based on the former stage signal and the output control signal provided by the output control terminal, including: The subsequent stage control circuit controls the previous stage output terminal to be disconnected from the subsequent stage output terminal based on the previous stage signal and the output control signal provided by the first output control terminal, and connects the second output control terminal to the subsequent stage output terminal.

12. The method according to claim 11, wherein: The potential of the output control signal provided by the first output control terminal is positively correlated with the potential threshold.

13. A gate drive circuit, the gate drive circuit comprising: At least two cascaded shift register units according to any one of claims 1 to 9.

14. A display device, comprising: A display panel, and a gate driving circuit as claimed in claim 13; The display panel includes a plurality of pixels, the gate driving circuit is coupled to the plurality of pixels and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

15. The display device according to claim 14, wherein: The transistor in the pixel is an N-type transistor, and the material of the N-type transistor includes: an oxide material.

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