Display substrate and preparation method therefor, and display apparatus

Abstract

A display substrate and a preparation method therefor, and a display apparatus. The display substrate comprises a plurality of circuit units, wherein each circuit unit comprises a pixel driving circuit, the pixel driving circuit comprising a plurality of transistors. In a direction perpendicular to a plane of the display substrate, the display substrate comprises a first conductive layer, a semiconductor layer, a second conductive layer and a third conductive layer, which are arranged on a base, wherein the first conductive layer comprises at least one first adapter electrode; the semiconductor layer comprises active layers of the plurality of transistors; the second conductive layer comprises at least one second adapter electrode; the third conductive layer comprises at least one third adapter electrode; and the second adapter electrode is simultaneously connected to the first adapter electrode and the active layer of one transistor through an adapter-structure via hole, and the third adapter electrode is connected to the active layer of another transistor through a single-hole-structure via hole. In the present disclosure, a top-gate bottom-layer connecting structure and a top gate structure are combined, thereby effectively improving the display resolution.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 14, 2023, with application number 202311189780.4 and invention name “Display substrate, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] On the one hand, the present disclosure provides a display substrate, comprising multiple circuit units, at least one circuit unit comprising a pixel driving circuit, and the pixel driving circuit comprising at least multiple transistors; in a direction perpendicular to the plane of the display substrate, the display substrate comprises at least a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer arranged on a substrate and arranged in sequence along a direction away from the substrate, the first conductive layer comprising at least one first switching electrode, the semiconductor layer comprising active layers of multiple transistors, the second conductive layer comprising at least one second switching electrode, and the third conductive layer comprising at least one third switching electrode; the second switching electrode is simultaneously connected to the first switching electrode and the active layer of one transistor through a switching structure via, the third switching electrode is connected to the active layer of another transistor through a single-hole structure via, the switching structure via comprising a deep half-hole and a shallow half-hole, the deep half-hole exposing the first switching electrode, and the shallow half-hole exposing the active layer.

[0007] In an exemplary embodiment, the multiple transistors include at least a first transistor, the first transistor includes at least a first active layer, and the first active layer is arranged in the semiconductor layer; the first conductive layer includes a first connecting electrode serving as the first transfer electrode, and the second conductive layer also includes an initial signal line, and the initial signal line is connected to the first connecting electrode and the first active layer at the same time through a transfer structure via.

[0008] In an exemplary embodiment, the plurality of transistors include at least a first transistor, the first transistor includes at least a first active layer, and the first active layer is arranged in the semiconductor layer; the third conductive layer also includes an initial signal line, and the initial signal line is connected to the first active layer through a single-hole structure via.

[0009] In an exemplary embodiment, the plurality of transistors include at least a second transistor, the second transistor includes at least a second active layer, and the second active layer is arranged in the semiconductor layer; the first conductive layer includes a second connecting electrode serving as the first switching electrode, the second conductive layer includes a fifth connecting electrode serving as the second switching electrode, and the fifth connecting electrode is connected to the second connecting electrode and the second active layer at the same time through a switching structure via.

[0010] In an exemplary embodiment, the plurality of transistors include at least a fourth transistor, the fourth transistor includes at least a fourth active layer, and the fourth active layer is arranged in the semiconductor layer; the first conductive layer also includes a data signal line, and the second conductive layer includes a sixth connecting electrode serving as the second transfer electrode, and the sixth connecting electrode is connected to the data signal line and the fourth active layer at the same time through a transfer structure via.

[0011] In an exemplary embodiment, the multiple transistors include at least a fifth transistor, the fifth transistor includes at least a fifth active layer, and the fifth active layer is arranged in the semiconductor layer; the first conductive layer also includes a first power line, and the second conductive layer includes a seventh connecting electrode serving as the second transfer electrode, and the seventh connecting electrode is connected to the first power line and the fifth active layer at the same time through a transfer structure via.

[0012] In an exemplary embodiment, the plurality of transistors include at least a fifth transistor, the fifth transistor includes at least a fifth active layer, and the fifth active layer is arranged in the semiconductor layer; the third conductive layer also includes a first power line, and the first power line is connected to the fifth active layer through a single-hole structure via.

[0013] In an exemplary embodiment, the plurality of transistors include at least a sixth transistor, the sixth transistor includes at least a sixth active layer, and the sixth active layer is arranged in the semiconductor layer; the third conductive layer includes an anode connection electrode serving as the third switching electrode, and the anode connection electrode is connected to the sixth active layer through a single-hole structure via.

[0014] In an exemplary embodiment, the plurality of transistors include at least a seventh transistor, the seventh transistor includes at least a seventh active layer, and the seventh active layer is arranged in the semiconductor layer; the first conductive layer also includes a first power line, and the second conductive layer includes an eighth connecting electrode serving as the second transfer electrode, and the eighth connecting electrode is connected to the first power line and the seventh active layer at the same time through a transfer structure via.

[0015] In an exemplary embodiment, the plurality of transistors include at least a seventh transistor, the seventh transistor includes at least a seventh active layer, and the seventh active layer is arranged in the semiconductor layer; the third conductive layer also includes a first power line, and the first power line is connected to the seventh active layer through a single-hole structure via.

[0016] In an exemplary embodiment, at least one transistor includes a gate electrode disposed in the second conductive layer.

[0017] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor, which includes at least a first electrode plate arranged in the first conductive layer, a second electrode plate arranged in the second conductive layer, and a third electrode plate arranged in the third conductive layer, the orthographic projection of the second electrode plate on the substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the substrate plane, the orthographic projection of the third electrode plate on the substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the substrate plane, and the first electrode plate is connected to the third electrode plate.

[0018] In an exemplary embodiment, at least one circuit unit further includes at least one power connection line extending along a first direction and at least one first power line extending along a second direction, the first power line being connected to the power connection line to form a mesh connectivity structure for transmitting a first power signal, and the first direction and the second direction intersect.

[0019] In an exemplary embodiment, the first power line is arranged in the first conductive layer, the power connection line is arranged in the third conductive layer, the second conductive layer includes an eighth connection connection serving as the second switching electrode, the eighth connection connection is connected to the first power line through a via, and the power connection line is connected to the eighth connection connection through a via.

[0020] In an exemplary embodiment, the first power line and the power connection line are disposed in the same layer and are connected to each other as an integral structure.

[0021] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0022] In another aspect, the present disclosure further provides a method for manufacturing a display substrate, wherein the display substrate includes a plurality of circuit units, at least one of which includes a pixel driving circuit, and the pixel driving circuit includes at least a plurality of transistors; the manufacturing method includes:

[0023] A first conductive layer, a semiconductor layer, a second conductive layer and a third conductive layer are formed in sequence on a substrate and along a direction away from the substrate, wherein the first conductive layer includes at least one first switching electrode, the semiconductor layer includes active layers of multiple transistors, the second conductive layer includes at least one second switching electrode, and the third conductive layer includes at least one third switching electrode; the second switching electrode is simultaneously connected to the first switching electrode and the active layer of one transistor through a switching structure via, and the third switching electrode is connected to the active layer of another transistor through a single-hole structure via, and the switching structure via includes a deep half hole and a shallow half hole, the deep half hole exposes the first switching electrode, and the shallow half hole exposes the active layer.

[0024] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0026] FIG1 is a schematic structural diagram of a display device;

[0027] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0028] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0029] FIG4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0030] FIG5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0031] FIG6 is a cross-sectional view taken along line AA in FIG5 ;

[0032] 7A and 7B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0033] 8A, 8B and 8C are schematic diagrams of a display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0034] 9A and 9B are schematic diagrams of a display substrate after forming a second insulating layer pattern according to the present disclosure;

[0035] 10A, 10B, 10C and 10D are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0036] 11A and 11B are schematic diagrams of a display substrate after a third insulating layer pattern is formed thereon according to the present disclosure;

[0037] 12A and 12B are schematic diagrams of a display substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0038] FIG13 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0039] FIG14 is a schematic diagram of another display substrate after forming a first conductive layer pattern according to the present disclosure;

[0040] 15A and 15B are schematic diagrams of another display substrate after semiconductor layer patterns are formed according to the present disclosure;

[0041] FIG16 is a schematic diagram of another display substrate after forming a second insulating layer pattern according to the present disclosure;

[0042] 17A and 17B are schematic diagrams of another display substrate after forming a second conductive layer pattern according to the present disclosure;

[0043] FIG18 is a schematic diagram of another display substrate after forming a third insulating layer pattern according to the present disclosure;

[0044] 19A and 19B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0045] FIG20 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0046] FIG21 is a schematic diagram of another display substrate after forming a first conductive layer pattern according to the present disclosure;

[0047] 22A and 22B are schematic diagrams of another display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0048] FIG23 is a schematic diagram of another display substrate after forming a second insulating layer pattern according to the present disclosure;

[0049] 24A and 24B are schematic diagrams of another display substrate after forming a second conductive layer pattern according to the present disclosure;

[0050] FIG25 is a schematic diagram of another display substrate after forming a third insulating layer pattern according to the present disclosure;

[0051] 26A and 26B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure.

[0052] Description of the accompanying drawings:

[0053] 10—substrate; 11—first connecting electrode; 12—second connecting electrode;

[0054] 13—third connecting electrode; 15—fifth connecting electrode; 16—sixth connecting electrode;

[0055] 17—seventh connecting electrode; 18—eighth connecting electrode; 21—first active layer;

[0056] 22—second active layer; 23—third active layer; 24—fourth active layer;

[0057] 25—fifth active layer; 26—sixth active layer; 27—seventh active layer;

[0058] 31—first scanning signal line; 32—second scanning signal line; 33—third scanning signal line;

[0059] 34—luminous signal line; 35—initial signal line; 41—anode connection electrode;

[0060] 42—power connection line; 51—first electrode plate; 52—second electrode plate;

[0061] 53—third electrode plate; 60—data signal line; 61—data connection block;

[0062] 70—first power line; 71—first power connection block; 72—second power connection block;

[0063] 81—first insulating layer; 82—second insulating layer; 83—third insulating layer;

[0064] 101—substrate; 102—driving circuit layer; 103—light-emitting structure layer;

[0065] 104—Encapsulation structure layer. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0067] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0068] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0069] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0070] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0071] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0072] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0073] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0074] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0075] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0076] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have some minor deformations due to tolerances, such as chamfers, rounded edges, and deformation. The term "approximately" in this disclosure does not strictly define the boundaries, but allows for values ​​within the range of process and measurement errors.

[0077] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0078] FIG2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG2 , the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0079] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) that emit green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond, pentagonal, or hexagonal in shape, and the four subpixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in this disclosure.

[0080] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0081] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of four sub-pixels in the display area. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0082] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, which may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0083] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. On a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one of the circuit units may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, at least one of the light-emitting units may include a light-emitting device, the light-emitting device being connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device being configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0084] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0085] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of circuit units, at least one of which comprises a pixel driving circuit, wherein the pixel driving circuit comprises at least a plurality of transistors; in a direction perpendicular to the plane of the display substrate, the display substrate comprises at least a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer, which are arranged on a base and sequentially arranged in a direction away from the base, wherein the first conductive layer comprises at least one first switching electrode, the semiconductor layer comprises active layers of a plurality of transistors, the second conductive layer comprises at least one second switching electrode, and the third conductive layer comprises at least one third switching electrode; the second switching electrode is simultaneously connected to the first switching electrode and the active layer of one transistor through a switching structure via hole, and the third switching electrode is connected to the active layer of another transistor through a single-hole structure via hole, wherein the switching structure via hole comprises a deep half hole and a shallow half hole, wherein the deep half hole exposes the first switching electrode, and the shallow half hole exposes the active layer.

[0086] In an exemplary embodiment, the plurality of transistors include at least a first transistor, the first transistor including at least a first active layer, the first active layer being disposed in the semiconductor layer. The first conductive layer includes a first connecting electrode serving as the first transfer electrode, the second conductive layer further includes an initial signal line, the initial signal line being connected to both the first connecting electrode and the first active layer via a transfer structure via, or the third conductive layer further includes an initial signal line, the initial signal line being connected to the first active layer via a single-hole structure via.

[0087] In an exemplary embodiment, the plurality of transistors includes at least a second transistor, the second transistor includes at least a second active layer, and the second active layer is disposed in the semiconductor layer. The first conductive layer includes a second connecting electrode serving as the first switching electrode, and the second conductive layer includes a fifth connecting electrode serving as the second switching electrode. The fifth connecting electrode is connected to both the second connecting electrode and the second active layer through a switching structure via.

[0088] In an exemplary embodiment, the plurality of transistors includes at least a fourth transistor, the fourth transistor includes at least a fourth active layer, and the fourth active layer is disposed in the semiconductor layer. The first conductive layer further includes a data signal line, and the second conductive layer includes a sixth connection electrode serving as the second switching electrode, the sixth connection electrode being connected to both the data signal line and the fourth active layer via a switching structure via.

[0089] In an exemplary embodiment, the plurality of transistors includes at least a fifth transistor, the fifth transistor includes at least a fifth active layer, and the fifth active layer is disposed in the semiconductor layer. The first conductive layer further includes a first power line, the second conductive layer includes a seventh connection electrode serving as the second transfer electrode, the seventh connection electrode being connected to both the first power line and the fifth active layer via a transfer structure via. Alternatively, the third conductive layer further includes a first power line, and the first power line is connected to the fifth active layer via a single-hole structure via.

[0090] In an exemplary embodiment, the plurality of transistors includes at least a sixth transistor, the sixth transistor includes at least a sixth active layer, and the sixth active layer is disposed in the semiconductor layer. The third conductive layer includes an anode connection electrode serving as the third switching electrode, the anode connection electrode being connected to the sixth active layer via a single-hole structure via.

[0091] In an exemplary embodiment, the plurality of transistors includes at least a seventh transistor, the seventh transistor includes at least a seventh active layer, and the seventh active layer is disposed in the semiconductor layer. The first conductive layer further includes a first power line, the second conductive layer includes an eighth connection electrode serving as the second transfer electrode, the eighth connection electrode being connected to both the first power line and the seventh active layer via a transfer structure via. Alternatively, the third conductive layer further includes a first power line, and the first power line is connected to the seventh active layer via a single-hole structure via.

[0092] In an exemplary embodiment, at least one transistor includes a gate electrode disposed in the second conductive layer.

[0093] The display substrate of this embodiment is described below with reference to some examples.

[0094] Figure 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 4, in an exemplary embodiment, the pixel driving circuit according to the exemplary embodiment of the present disclosure adopts a 7T1C structure. The pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to six signal lines (a first scanning signal line S1, a second scanning signal line S2, an emission signal line EM, an initial signal line INIT, a data signal line DATA, and a first power line VDD).

[0095] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is respectively connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, the second electrode of the seventh transistor T7, and the first end of the storage capacitor C, the second node N2 is respectively connected to the second electrode of the second transistor T2, the first electrode of the third transistor T3, and the second electrode of the fifth transistor T5, the third node N3 is respectively connected to the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first electrode of the sixth transistor T6, and the fourth node N4 is respectively connected to the second electrode of the first transistor T1, the second electrode of the sixth transistor T6, and the second end of the storage capacitor C.

[0096] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the fourth node N4 .

[0097] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the initialization signal line INIT, and a second electrode of the first transistor T1 is connected to the fourth node N4. When a turn-on signal is applied to the first scan signal line S1, the first transistor T1 is turned on and transmits an initialization voltage to the fourth node N4, thereby initializing the second end of the storage capacitor C and the first electrode of the light-emitting device EL.

[0098] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the second node N2. When a turn-on signal is applied to the second scan signal line S2, the second transistor T2 conducts electricity between the first node N1 and the second node N2.

[0099] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor. The third transistor T3 determines the magnitude of a driving current flowing between the first power line VDD and the light emitting device EL based on a potential difference between its gate electrode and the first electrode.

[0100] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the second scan signal line S2, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the third node N3. When a turn-on signal is applied to the second scan signal line S2, the fourth transistor T4 inputs a data voltage of the data signal line DATA to the third node N3.

[0101] In an exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. A gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4. When a turn-on signal is applied to the light emitting signal line EM, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the light emitting device EL, thereby causing the light emitting device EL to emit light.

[0102] In an exemplary embodiment, a gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, a first electrode of the seventh transistor T7 is connected to the first power supply line VDD, and a second electrode of the seventh transistor T7 is connected to the first node N1. When a turn-on signal is applied to the first scan signal line S1, the seventh transistor T7 is turned on and transmits the first power supply voltage to the first node N1.

[0103] In an exemplary embodiment, the light emitting device EL may be an OLED including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode). The first electrode of the light emitting device EL is connected to the fourth node N4, and the second electrode of the light emitting device EL is connected to the second power supply line VSS.

[0104] In an exemplary embodiment, the signal of the first power line VDD is a continuously provided high-level signal, and the signal of the second power line VSS is a continuously provided low-level signal. The first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS can be configured to provide a constant second voltage signal to the light-emitting device EL, wherein the first voltage signal is greater than the second voltage signal. The initial signal line INIT can be configured to provide an initial voltage signal to the pixel driving circuit. The initial voltage signal can be a constant voltage signal, and its magnitude can be between the first voltage signal provided by the first power line VDD and the second voltage signal provided by the second power line VSS, but this disclosure is not limited thereto.

[0105] In an exemplary embodiment, the seven transistors of the pixel driving circuit can be N-type transistors or P-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of display substrate processing, and improve product yield.

[0106] In an exemplary embodiment, the first to seventh transistors T1 to T7 in each pixel driving circuit may be low-temperature polysilicon transistors, or oxide transistors. The active layer of the oxide transistor may be an oxide semiconductor. Oxide thin-film transistors have advantages such as high electron mobility, low operating voltage, and low leakage. Using a display substrate provided with oxide thin-film transistors can achieve low-frequency driving, reduce power consumption, and improve display quality.

[0107] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 of the pixel driving circuit can be low-temperature polysilicon transistors and metal oxide transistors. The low-temperature polysilicon transistors and the oxide transistors are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate. The advantages of both can be utilized to achieve low-frequency driving, reduce power consumption, and improve display quality.

[0108] In an exemplary embodiment, taking the example that the first transistor T1 to the seventh transistor T7 included in the pixel driving circuit are all N-type transistors, the operation process of the pixel driving circuit may include the following stages.

[0109] The first phase A1 is called the initialization phase. The first scan signal line S1 provides a high-level signal, turning on the first transistor T1 and the seventh transistor T7. Turning on the first transistor T1 causes the initial voltage signal provided by the initial signal line INIT to be supplied to the fourth node N4, initializing the second end of the storage capacitor C and the first electrode of the light-emitting device EL. This clears the existing data voltage in the storage capacitor C and the pre-stored voltage at the first electrode of the light-emitting device EL, completing the initialization. Turning on the seventh transistor T7 causes the first voltage signal output from the first power line VDD to be supplied to the first node N1 through the seventh transistor T7, charging the first end of the storage capacitor C. Since the first end of the storage capacitor C is at a high level, the third transistor T3 turns on.

[0110] The second phase A2 is called the data writing phase or the threshold compensation phase. The second scan signal line S2 provides a high-level signal, turning on the second transistor T2 and the fourth transistor T4. Turning on the second transistor T2 connects the first node N1 to the second node N2. Turning on the fourth transistor T4 causes the data voltage output by the data signal line DATA to be provided to the first node N1 via the third node N3, the turned-on third transistor T3, the second node N2, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the first end of the storage capacitor C.

[0111] The third phase A3 is called the light-emitting phase. The light-emitting signal line EM provides a high-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The first voltage signal output from the first power line VDD provides a driving voltage to the first electrode of the light-emitting device EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting device EL to emit light.

[0112] During the driving process of the pixel driving circuit, the current flowing through the light emitting device EL has nothing to do with the threshold voltage of the third transistor T3 , so the pixel driving circuit can better compensate for the threshold voltage of the third transistor T3 .

[0113] FIG5 is a schematic diagram of a planar structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of a circuit unit. On a plane parallel to the display substrate, the display substrate may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, and at least one circuit unit may include a pixel driving circuit. As shown in FIG5 , the pixel driving circuit is respectively connected to a first scanning signal line 31, a second scanning signal line 32, a third scanning signal line 33, a light-emitting signal line 34, an initial signal line 35, a data signal line 60, and a first power line 70. The first scanning signal line 31, the second scanning signal line 32, and the third scanning signal line 33 are configured to provide scanning signals to the pixel driving circuit, respectively, the light-emitting signal line 34 is configured to provide a light-emitting control signal to the pixel driving circuit, and the initial signal line 35, the data signal line 60, and the first power line 70 are configured to provide an initial signal, a first power signal, and a data signal to the pixel driving circuit, respectively.

[0114] In an exemplary embodiment, the shapes of the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the light emitting signal line 34 and the initial signal line 35 can be straight lines or broken lines with the main parts extending along the first direction X, and the shapes of the data signal line 60 and the first power line 70 can be straight lines or broken lines with the main parts extending along the second direction Y, and the first direction X and the second direction Y intersect.

[0115] In the present disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, the main portion extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B." In an exemplary embodiment, the first direction X may be the direction of unit rows, and the second direction Y may be the direction of unit columns.

[0116] In an exemplary embodiment, the pixel driving circuit may include at least a storage capacitor and a plurality of transistors, the plurality of transistors may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and the storage capacitor may include a stacked first plate 51, a second plate 52, and a third plate 53.

[0117] In example embodiments, the first to seventh transistors T1 to T7 may be low-temperature polysilicon transistors, or may be oxide transistors.

[0118] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the first scan signal line 31, a gate electrode of the second transistor T2 and a gate electrode of the fourth transistor T4 are connected to the second scan signal line 32, a gate electrode of the seventh transistor T7 is connected to the third scan signal line 33, and a gate electrode of the fifth transistor T5 and a gate electrode of the sixth transistor T6 are connected to the light emitting signal line 34.

[0119] In an exemplary embodiment, a first electrode of the first transistor T1 is connected to the initial signal line 35 , a first electrode of the fourth transistor T4 is connected to the data signal line 60 , a first electrode of the fifth transistor T5 is connected to the first power line 70 , and a first electrode of the seventh transistor T7 is connected to the first power line 70 .

[0120] In an exemplary embodiment, in a direction perpendicular to the substrate, the display substrate may include a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer disposed on the substrate and sequentially disposed in a direction away from the substrate. The first plate 51 of the storage capacitor, the data signal line 60, and the first power line 70 may be disposed in the first conductive layer, the active layer of the first transistor T1 to the seventh transistor T7 may be disposed in the semiconductor layer, the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the light emitting signal line 34, the initial signal line 35, and the second plate 52 of the storage capacitor may be disposed in the second conductive layer, and the third plate 53 of the storage capacitor may be disposed in the third conductive layer.

[0121] In an exemplary embodiment, the first conductive layer may further include at least one first switching electrode, the second conductive layer may further include at least one second switching electrode, and the third conductive layer may further include at least one third switching electrode.

[0122] In an exemplary embodiment, the second switching electrode in the second conductive layer can be simultaneously connected to the first switching electrode in the first conductive layer and the active layer of a transistor in the semiconductor layer through a switching structure via, and the third switching electrode in the third conductive layer can be connected to the active layer of another transistor in the semiconductor layer through a single-hole structure via.

[0123] In an exemplary embodiment, the transfer structure via hole may include a deep half hole and a shallow half hole, wherein the deep half hole exposes the first transfer electrode in the first conductive layer and the shallow half hole exposes the active layer in the semiconductor layer. The single hole structure via hole may include a single via hole that only exposes the active layer in the semiconductor layer.

[0124] In an exemplary embodiment, the first transistor T1 includes at least a first active layer, which is disposed in the semiconductor layer. The first conductive layer may include a first connection electrode 11 serving as a first transfer electrode. The initial signal line 35 located in the second conductive layer may be connected to both the first connection electrode 11 located in the first conductive layer and the first active layer located in the semiconductor layer via a first via V1 serving as a transfer structure via.

[0125] In an exemplary embodiment, the second transistor T2 includes at least a second active layer, which is disposed in the semiconductor layer. The first conductive layer may include a second connection electrode 12 serving as a first transition electrode, and the second conductive layer may include a fifth connection electrode 15 serving as a second transition electrode. The fifth connection electrode 15 in the second conductive layer may be connected to both the second connection electrode 12 in the first conductive layer and the second active layer in the semiconductor layer via a second via V2 serving as a transition structure via.

[0126] In an exemplary embodiment, the fourth transistor T4 includes at least a fourth active layer, which is disposed in the semiconductor layer. The second conductive layer may include a sixth connection electrode 16 serving as a second switching electrode. The sixth connection electrode 16 in the second conductive layer may be connected to both the data signal line 60 in the first conductive layer and the fourth active layer in the semiconductor layer via a third via V3 serving as a switching structure via.

[0127] In an exemplary embodiment, the fifth transistor T5 includes at least a fifth active layer, which is disposed in the semiconductor layer. The second conductive layer may include a seventh connection electrode 17 serving as a second switching electrode. The seventh connection electrode 17 in the second conductive layer may be connected to both the first power line 70 in the first conductive layer and the fifth active layer in the semiconductor layer via a fourth via V4 serving as a switching structure via.

[0128] In an exemplary embodiment, the sixth transistor T6 includes at least a sixth active layer, which is disposed in the semiconductor layer. The third conductive layer may include an anode connection electrode 41 serving as a third switching electrode. The anode connection electrode 41 in the third conductive layer may be connected to the sixth active layer in the semiconductor layer via a twelfth via hole V12 serving as a single-hole structured via hole.

[0129] In an exemplary embodiment, the seventh transistor T7 includes at least a seventh active layer, which is disposed in the semiconductor layer. The second conductive layer may include an eighth connection electrode 18 serving as a second switching electrode. The eighth connection electrode 18 in the second conductive layer may be connected to both the first power line 70 in the first conductive layer and the seventh active layer in the semiconductor layer via a fifth via V5 serving as a switching structure via.

[0130] In an exemplary embodiment, at least one circuit unit may further include at least one power connection line 42 extending along the first direction X, and the power connection line 42 is connected to the first power line 70 to form a mesh connection structure for transmitting the first power signal.

[0131] Figure 6 is a cross-sectional view taken along line AA in Figure 5. As shown in Figure 6, the display substrate may include a first conductive layer disposed on a substrate 10, a first insulating layer 81 disposed on a side of the first conductive layer away from the substrate 10, a semiconductor layer disposed on a side of the first insulating layer 81 away from the substrate 10, a second insulating layer 82 disposed on a side of the semiconductor layer away from the substrate 10, a second conductive layer disposed on a side of the second insulating layer 82 away from the substrate 10, a third insulating layer 83 disposed on a side of the second conductive layer away from the substrate 10, and a third conductive layer disposed on a side of the third insulating layer 83 away from the substrate 10.

[0132] In an exemplary embodiment, the first conductive layer may include at least the second connecting electrode 12 and the first plate 51 of the storage capacitor, the semiconductor layer may include at least the second active layer 22, the third active layer 23 and the sixth active layer 26, the second conductive layer may include at least the fifth connecting electrode 15, the second scanning signal line 32, the light-emitting signal line 34 and the second plate 52 of the storage capacitor, and the third conductive layer may include at least the anode connecting electrode 41 and the third plate 53 of the storage capacitor.

[0133] In an exemplary embodiment, the orthographic projection of the second electrode plate 52 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 51 on the substrate, the second electrode plate 52 and the first electrode plate 51 form a first capacitor of the storage capacitor, the orthographic projection of the third electrode plate 53 on the substrate overlaps with the orthographic projection of the second electrode plate 52 on the substrate, the second electrode plate 52 and the third electrode plate 53 form a second capacitor of the storage capacitor, the third electrode plate 53 is connected to the first electrode plate 51 through a via, and the first capacitor and the second capacitor in parallel constitute the storage capacitor of the pixel driving circuit.

[0134] In an exemplary embodiment, the fifth connection electrode 15 in the second conductive layer can be connected to both the second connection electrode 12 in the first conductive layer and the second active layer 22 in the semiconductor layer through a second via hole serving as a transfer structure via hole. In an exemplary embodiment, the second connection electrode 12 is also connected to the second electrode plate 52 through a via hole.

[0135] In an exemplary embodiment, the anode connection electrode 41 in the third conductive layer may be connected to the sixth active layer 26 in the semiconductor layer through a twelfth via hole that is a single-hole structure via hole.

[0136] The following is an exemplary description of the preparation process of the substrate shown in this exemplary embodiment. The "patterning process" mentioned in this disclosure includes processes such as depositing a film layer, coating a photoresist on the film layer, mask exposure, development, etching, and stripping the photoresist for metal materials, inorganic materials, or transparent conductive materials. For organic materials, it includes processes such as coating an organic material, mask exposure, and development. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be achieved by any one or more of spraying, spin coating, and inkjet printing. Etching can be achieved by any one or more of dry etching and wet etching, and this disclosure does not limit this. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0137] In an exemplary embodiment, taking a circuit unit as an example, the preparation process of the display substrate in this embodiment may include the following operations.

[0138] (11) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the substrate, as shown in FIG7A . In an exemplary embodiment, the first conductive layer may be referred to as a shield layer.

[0139] In an exemplary embodiment, the first conductive layer of each circuit unit in the display substrate may include at least a first connection electrode 11 , a second connection electrode 12 , a third connection electrode 13 , a first plate 51 of a storage capacitor, a data signal line 60 , and a first power line 70 .

[0140] In an exemplary embodiment, the first electrode plate 51 may be rectangular, with chamfered corners. The first electrode plate 51 may be located in the middle of the circuit unit in both the first direction X and the second direction Y. The first electrode plate 51 may serve as the lower plate of the storage capacitor and also as a shielding structure for the third transistor T3, shielding the channel region of the third transistor T3 to reduce the impact of light on the electrical characteristics of the third transistor T3 and stabilize the light-irradiated characteristics of the oxide semiconductor.

[0141] In an exemplary embodiment, a first opening 54 may be provided on one side of the first electrode plate 51 opposite to the second direction Y. The first opening 54 may be block-shaped (such as rectangular) and configured to accommodate the second end of the second connecting electrode 12 .

[0142] In an exemplary embodiment, the first connection electrode 11 may be in a block shape (e.g., rectangular) and may be disposed on one side of the first electrode plate 51 in the second direction Y. In an exemplary embodiment, the first connection electrode 11 may serve as a first transfer electrode of the present disclosure and may be configured to be connected to an initial signal line formed subsequently.

[0143] In an exemplary embodiment, the second connection electrode 12 may be in the shape of a strip extending along the second direction Y and may be disposed on a side of the first electrode plate 51 opposite to the second direction Y. The first end of the second connection electrode 12 may be an end away from the first electrode plate 51, and the second end of the second connection electrode 12 may be an end closer to the first electrode plate 51. The second end of the second connection electrode 12 may be disposed within the first opening 54 of the first electrode plate 51. In an exemplary embodiment, the second connection electrode 12 may serve as a first transition electrode of the present disclosure. The first end of the second connection electrode 12 is configured to connect to a fifth connection electrode to be formed subsequently, and the second end of the second connection electrode 12 is configured to connect to a second electrode to be formed subsequently.

[0144] In an exemplary embodiment, the third connection electrode 13 may be in the shape of a strip extending along the second direction Y and may be disposed on one side of the first electrode plate 51 in the second direction Y. A first end of the third connection electrode 13 is connected to the first electrode plate 51, and a second end of the third connection electrode 13 extends in a direction away from the first electrode plate 51. In an exemplary embodiment, the third connection electrode 13 is configured to be connected to a subsequently formed anode connection electrode.

[0145] In an exemplary embodiment, the third connection electrode 13 and the first electrode plate 51 may be an integral structure connected to each other.

[0146] In an exemplary embodiment, the data signal line 60 may be in a straight line or a zigzag line extending along the second direction Y, and may be disposed on one side of the first electrode plate 51 in the first direction X.

[0147] In an exemplary embodiment, a data connection block 61 may be provided on the data signal line 60. The data connection block 61 may be block-shaped (e.g., rectangular) and may be provided on a side of the data signal line 60 close to the first electrode plate 51. A first end of the data connection block 61 is connected to the data signal line 60, and a second end of the data connection block 61 extends away from the data signal line 60. In an exemplary embodiment, the data connection block 61 may serve as a first transfer electrode of the present disclosure and be configured to connect to a subsequently formed sixth connection electrode.

[0148] In an exemplary embodiment, the data signal line 60 and the data connection block 61 may be an integral structure connected to each other.

[0149] In an exemplary embodiment, the shape of the first power line 70 can be a straight line or a broken line extending along the second direction Y, and can be arranged on the side of the first electrode plate 51 in the opposite direction of the first direction X, that is, the data signal line 60 and the first power line 70 are respectively arranged on both sides of the first electrode plate 51 in the first direction X.

[0150] In an exemplary embodiment, a first power connection block 71 may be provided on the first power line 70. The first power connection block 71 may be block-shaped (e.g., rectangular) and may be provided on a side of the first power line 70 close to the first electrode plate 51 and located on one side of the first electrode plate 51 in the second direction Y. A first end of the first power connection block 71 is connected to the first power line 70, and a second end of the first power connection block 71 extends away from the first power line 70. In an exemplary embodiment, the first power connection block 71 may serve as a first transition electrode of the present disclosure, configured to connect to a subsequently formed seventh connection electrode.

[0151] In an exemplary embodiment, the first power line 70 and the first power connection block 71 may be an integral structure connected to each other.

[0152] In an exemplary embodiment, a second power connection block 72 may be provided on the first power line 70. The second power connection block 72 may be block-shaped (e.g., rectangular) and may be provided on a side of the first power line 70 that is close to the first electrode plate 51 and located on a side of the first electrode plate 51 that is opposite to the second direction Y. A first end of the second power connection block 72 is connected to the first power line 70, and a second end of the second power connection block 72 extends away from the first power line 70. In an exemplary embodiment, the second power connection block 72 may serve as a first transition electrode of the present disclosure, configured to connect to a subsequently formed eighth connection electrode.

[0153] In an exemplary embodiment, the first power line 70 and the second power connection block 72 may be an integral structure connected to each other.

[0154] In an exemplary embodiment, the first power line 70 , the first power connection block 71 , and the second power connection block 72 may be an integral structure connected to each other.

[0155] Fig. 7B is a cross-sectional view taken along line AA in Fig. 7A. As shown in Fig. 7B, a first conductive layer is provided on the substrate 10, and the first conductive layer may include at least a second connecting electrode 12 and a first electrode plate 51 of a storage capacitor.

[0156] (12) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a plan view schematic diagram of the semiconductor layer in FIG8A .

[0157] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display substrate may include the first active layer 21 of the first transistor T1 to the seventh active layer 27 of the seventh transistor T7 , and the first active layer 21 to the seventh active layer 27 are connected to each other as an integral structure.

[0158] In an exemplary embodiment, in the first direction X, the first active layer 21, the fourth active layer 24, and the sixth active layer 26 may be located on one side of the third active layer 23 in the first direction X, and the second active layer 22, the fifth active layer 25, and the seventh active layer 27 may be located on a side of the third active layer 23 opposite to the first direction X. In the second direction Y, the first active layer 21, the fifth active layer 25, and the sixth active layer 26 may be located on one side of the third active layer 23 in the second direction Y, and the second active layer 22, the fourth active layer 24, and the seventh active layer 27 may be located on a side of the third active layer 23 opposite to the second direction Y.

[0159] In an exemplary embodiment, the third active layer 23 may have a strip shape extending along the first direction X, and the first active layer 21, the second active layer 22, the fourth active layer 24, the fifth active layer 25, the sixth active layer 26, and the seventh active layer 27 may have a strip shape extending along the second direction Y.

[0160] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The second region 21-2 of the first active layer may serve as the second region 26-2 of the sixth active layer, i.e., the second region 21-2 of the first active layer and the second region 26-2 of the sixth active layer may be connected to each other. The first region 22-1 of the second active layer may serve as the second region 27-2 of the seventh active layer, i.e., the first region 22-1 of the second active layer and the second region 27-2 of the seventh active layer may be connected to each other. The second region 22-2 of the second active layer may also serve as the first region 23-1 of the third active layer and the second region 25-2 of the fifth active layer, i.e., the second region 22-2 of the second active layer, the first region 23-1 of the third active layer, and the second region 25-2 of the fifth active layer may be connected to each other. The second region 23-2 of the third active layer can simultaneously serve as the second region 24-2 of the fourth active layer and the first region 26-1 of the sixth active layer, that is, the second region 23-2 of the third active layer, the second region 24-2 of the fourth active layer, and the first region 26-1 of the sixth active layer can be connected to each other. The first region 21-1 of the first active layer, the first region 24-1 of the fourth active layer, the first region 25-1 of the fifth active layer, and the first region 27-1 of the seventh active layer can be provided separately.

[0161] In an exemplary embodiment, the orthographic projection of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the first electrode 51 on the substrate, so that the first electrode 51 can block the channel region of the third active layer 23, reduce the influence of light on the electrical characteristics of the third transistor T3, and stabilize the illumination characteristics of the oxide semiconductor.

[0162] In an exemplary embodiment, the orthographic projection of the first region 21-1 of the first active layer on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 11 on the substrate, so that the subsequently formed initial signal line can be simultaneously connected to the first connection electrode 11 and the first region 21-1 of the first active layer.

[0163] In an exemplary embodiment, the orthographic projection of the first region 22-1 of the second active layer (also the second region 27-2 of the seventh active layer) on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode 12 on the substrate, so that the subsequently formed fifth connecting electrode can be simultaneously connected to the second connecting electrode 12 and the first region 22-1 of the second active layer (also the second region 27-2 of the seventh active layer).

[0164] In an exemplary embodiment, the orthographic projection of the first region 24-1 of the fourth active layer on the substrate at least partially overlaps with the orthographic projection of the data connection block 61 on the substrate, so that the subsequently formed sixth connection electrode can be simultaneously connected to the data connection block 61 and the first region 24-1 of the fourth active layer.

[0165] In an exemplary embodiment, the orthographic projection of the first region 25-1 of the fifth active layer on the substrate at least partially overlaps with the orthographic projection of the first power connection block 71 on the substrate, so that the subsequently formed seventh connection electrode can be simultaneously connected to the first power connection block 71 and the first region 25-1 of the fifth active layer.

[0166] In an exemplary embodiment, the orthographic projection of the first region 27-1 of the seventh active layer on the substrate at least partially overlaps with the orthographic projection of the second power connection block 72 on the substrate, so that the subsequently formed eighth connection electrode can be simultaneously connected to the second power connection block 72 and the first region 27-1 of the seventh active layer.

[0167] In one exemplary embodiment, the semiconductor layer may be made of an oxide, meaning that the first to seventh transistors T1 to T7 are oxide transistors. Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage. In this exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc oxynitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In this exemplary embodiment, the semiconductor layer may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0168] In another exemplary embodiment, the semiconductor layer may be made of polysilicon, that is, the first to seventh transistors T7 may be polysilicon transistors.

[0169] Figure 8C is a cross-sectional view taken along line AA in Figure 8A. As shown in Figure 8C, a first conductive layer is disposed on a substrate 10, a first insulating layer 81 is disposed on a side of the first conductive layer away from the substrate 10, and a semiconductor layer is disposed on a side of the first insulating layer 81 away from the substrate 10. The semiconductor layer may include at least a second active layer 22, a third active layer 23, and a sixth active layer 26. The orthographic projection of the second active layer 22 on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode 12 on the substrate, and the orthographic projection of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 51 on the substrate. The first electrode plate 51, as a shielding structure, can shield the channel region of the third active layer 23, reducing the impact of light on the electrical characteristics of the third transistor T3 and stabilizing the light-irradiation characteristics of the oxide semiconductor.

[0170] (13) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate having the aforementioned pattern formed thereon, patterning the second insulating film using a patterning process to form a second insulating layer covering the semiconductor layer, wherein the second insulating layer is provided with a plurality of via holes, as shown in FIG. 9A .

[0171] In an exemplary embodiment, the plurality of via holes of each circuit unit in the display substrate includes at least a first via hole V1 , a second via hole V2 , a third via hole V3 , a fourth via hole V4 , a fifth via hole V5 , and a sixth via hole V6 .

[0172] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate at least partially overlaps with the orthographic projections of the first connection electrode 11 and the first region 21-1 of the first active layer on the substrate. The first via hole V1 may be a transition structure via hole, including a deep half hole and a shallow half hole. The second insulating layer and the first insulating layer in the deep half hole are etched away, exposing the surface of the first connection electrode 11. The second insulating layer in the shallow half hole is etched away, exposing the surface of the first region 21-1 of the first active layer. As a transition structure via hole of the present disclosure, the first via hole V1 is configured to allow a subsequently formed initial signal line to simultaneously connect to the first connection electrode 11 and the first region 21-1 of the first active layer through the via hole.

[0173] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate at least partially overlaps with the orthographic projections of the first end of the second connecting electrode 12 away from the first electrode plate 51 and the first region 22-1 of the second active layer (also the second region 27-2 of the seventh active layer) on the substrate. The second via V2 may be a transition structure via, comprising a deep half-hole and a shallow half-hole. The second insulating layer and the first insulating layer within the deep half-hole are etched away, exposing the surface of the first end of the second connecting electrode 12. The second insulating layer within the shallow half-hole is etched away, exposing the surface of the first region 22-1 of the second active layer (also the second region 27-2 of the seventh active layer). As a transition structure via of the present disclosure, the second via V2 is configured to simultaneously connect a subsequently formed fifth connecting electrode to the first end of the second connecting electrode 12 and the first region 22-1 of the second active layer (also the second region 27-2 of the seventh active layer) through the via.

[0174] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate at least partially overlaps with the orthographic projections of the data connection block 61 and the first area 24-1 of the fourth active layer on the substrate, respectively. The third via hole V3 can be a transfer structure via hole, including a deep half hole and a shallow half hole. The second insulating layer and the first insulating layer in the deep half hole are etched away to expose the surface of the data connection block 61, and the second insulating layer in the shallow half hole is etched away to expose the surface of the first area 24-1 of the fourth active layer. The third via hole V3, as a transfer structure via hole disclosed in the present invention, is configured to allow the subsequently formed sixth connection electrode to be simultaneously connected to the data connection block 61 and the first area 24-1 of the fourth active layer through the via hole.

[0175] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps with the orthographic projections of the first power connection block 71 and the first area 25-1 of the fifth active layer on the substrate, respectively. The fourth via hole V4 can be a transfer structure via hole, including a deep half hole and a shallow half hole. The second insulating layer and the first insulating layer in the deep half hole are etched away to expose the surface of the first power connection block 71, and the second insulating layer in the shallow half hole is etched away to expose the surface of the first area 25-1 of the fifth active layer. The fourth via hole V4, as a transfer structure via hole disclosed in the present invention, is configured to allow the subsequently formed seventh connection electrode to be simultaneously connected to the first power connection block 71 and the first area 25-1 of the fifth active layer through the via hole.

[0176] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate at least partially overlaps with the orthographic projections of the second power connection block 72 and the first area 27-1 of the seventh active layer on the substrate, respectively. The fifth via V5 can be a transfer structure via, including a deep half hole and a shallow half hole. The second insulating layer and the first insulating layer in the deep half hole are etched away to expose the surface of the second power connection block 72, and the second insulating layer in the shallow half hole is etched away to expose the surface of the first area 27-1 of the seventh active layer. The fifth via V5, as a transfer structure via of the present invention, is configured to allow the subsequently formed eighth connection electrode to be simultaneously connected to the second power connection block 72 and the first area 27-1 of the seventh active layer through the via.

[0177] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second end of the second connecting electrode 12 close to the first electrode plate 51 on the substrate. The sixth via hole V6 is a single-hole structure via hole. The second insulating layer and the first insulating layer in the sixth via hole V6 are etched away to expose the surface of the second end of the second connecting electrode 12. The sixth via hole V6 is configured to connect the subsequently formed second electrode plate to the second end of the second connecting electrode 12 through the via hole.

[0178] In an exemplary embodiment, during the process of forming the second insulating layer pattern, a dry etching process is used to form a plurality of vias, and simultaneously, a primary conductive process is performed on the semiconductor layer exposed within the vias. During the primary conductive process, the edge portion of the semiconductor layer covered by the second insulating layer near the vias is also conductively conductive. Specifically, the semiconductor layer that has been primarily conductively conductive extends away from the vias, forming a primary conductive region.

[0179] Figure 9B is a cross-sectional view taken along line AA in Figure 9A. As shown in Figure 9B, a first conductive layer is disposed on a substrate 10, a first insulating layer 81 is disposed on a side of the first conductive layer away from the substrate 10, a semiconductor layer is disposed on a side of the first insulating layer 81 away from the substrate 10, and a second insulating layer 82 is disposed on a side of the semiconductor layer away from the substrate 10. At least a second via V2 and a sixth via V6 are disposed on the second insulating layer 82. The second via V2 is a transition structure via, comprising a deep half-hole V21 and a shallow half-hole V22. The second insulating layer 82 and the first insulating layer 81 within the deep half-hole V21 are etched away, exposing the surface of the first end of the second connecting electrode 12. The second insulating layer 82 within the shallow half-hole V22 is etched away, exposing the surface of the second active layer 22. The sixth via V6 is a single-hole structure via. The second insulating layer 82 and the first insulating layer 81 within the sixth via V6 are etched away, exposing the surface of the second end of the second connecting electrode 12.

[0180] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the second conductive film through a patterning process to form a second conductive layer pattern disposed on the second insulating layer, as shown in FIG. 10A and FIG. 10B , where FIG. 10B is a schematic diagram of the second conductive layer in FIG. 10A . In an exemplary embodiment, the second conductive layer may be referred to as a gate metal (GATE) layer.

[0181] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a fifth connecting electrode 15, a sixth connecting electrode 16, a seventh connecting electrode 17, an eighth connecting electrode 18, a first scanning signal line 31, a second scanning signal line 32, a third scanning signal line 33, a light emitting signal line 34, an initial signal line 35 and a second plate 52 of the storage capacitor.

[0182] In an exemplary embodiment, the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the light emitting signal line 34, and the initial signal line 35 may be in the shape of a straight line or a zigzag line extending along the first direction X. The light emitting signal line 34 may be located on one side of the first electrode plate 51 in the second direction Y, the first scan signal line 31 may be located on a side of the light emitting signal line 34 away from the first electrode plate 51, the initial signal line 35 may be located on a side of the first scan signal line 31 away from the first electrode plate 51, the second scan signal line 32 may be located on a side of the first electrode plate 51 opposite to the second direction Y, and the third scan signal line 33 may be located on a side of the second scan signal line 32 away from the first electrode plate 51.

[0183] In an exemplary embodiment, the orthographic projection of the first scan signal line 31 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate, and the overlapping area can serve as the gate electrode of the first transistor T1, so that the first scan signal line 31 can control the conduction or disconnection of the first transistor T1.

[0184] In an exemplary embodiment, the orthographic projections of the second scan signal line 32 on the substrate at least partially overlap with the orthographic projections of the second active layer and the fourth active layer on the substrate, respectively. The area overlapping with the second active layer can serve as the gate electrode of the second transistor T2, and the area overlapping with the fourth active layer can serve as the gate electrode of the fourth transistor T4, so that the second scan signal line 32 can simultaneously control the conduction or disconnection of the second transistor T2 and the fourth transistor T4.

[0185] In an exemplary embodiment, the orthographic projection of the third scan signal line 33 on the substrate at least partially overlaps with the orthographic projection of the seventh active layer on the substrate, and the overlapping area can serve as the gate electrode of the seventh transistor T7, so that the third scan signal line 33 can control the conduction or disconnection of the seventh transistor T7.

[0186] In an exemplary embodiment, the first scan signal line 31 and the third scan signal line 33 may be connected to the same signal line, that is, the first scan signal line 31 and the third scan signal line 33 may synchronously control the on or off of the first transistor T1 and the seventh transistor T7 .

[0187] In an exemplary embodiment, the orthographic projections of the light-emitting signal line 34 on the substrate at least partially overlap with the orthographic projections of the fifth active layer and the sixth active layer on the substrate, respectively. The area overlapping with the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the area overlapping with the sixth active layer can serve as the gate electrode of the sixth transistor T6, so that the light-emitting signal line 34 can simultaneously control the conduction or disconnection of the fifth transistor T5 and the sixth transistor T6.

[0188] In an exemplary embodiment, the initial signal line 35 can be connected to the first connection electrode 11 and the first region 21 - 1 of the first active layer through the first via hole V1 as a transfer structure via hole, thereby enabling the initial signal line 35 to write the initial signal into the first electrode of the first transistor T1 .

[0189] In an exemplary embodiment, the fifth connection electrode 15 may be block-shaped (e.g., rectangular) and may be disposed between the second scan signal line 32 and the third scan signal line 33. The fifth connection electrode 15 is connected to both the first end of the second connection electrode 12 and the first region of the second active layer (also the second region of the seventh active layer) via a second via hole V2 serving as a transition structure via. In an exemplary embodiment, the fifth connection electrode 15 may serve as a second transition electrode of the present disclosure.

[0190] In an exemplary embodiment, the sixth connection electrode 16 may be block-shaped (e.g., rectangular) and may be disposed between the second scan signal line 32 and the third scan signal line 33. The sixth connection electrode 16 is connected to both the data connection block 61 and the first region of the fourth active layer via a third via V3, which functions as a transfer structure via. Since the data connection block 61 is connected to the data signal line 60, the data signal line 60 writes the data signal to the first electrode of the fourth transistor T4. In an exemplary embodiment, the sixth connection electrode 16 may serve as a second transfer electrode of the present disclosure.

[0191] In an exemplary embodiment, the seventh connection electrode 17 can be block-shaped (e.g., rectangular) and can be disposed between the first scan signal line 31 and the light-emitting signal line 34. The seventh connection electrode 17 is connected to both the first power connection block 71 and the first region of the fifth active layer via a fourth via V4, which functions as a transfer structure via. Because the first power connection block 71 is connected to the first power line 70, the first power line 70 writes the first power signal to the first electrode of the fifth transistor T5. In an exemplary embodiment, the seventh connection electrode 17 can serve as a second transfer electrode of the present disclosure.

[0192] In an exemplary embodiment, the eighth connection electrode 18 may be block-shaped (e.g., rectangular) and may be disposed on a side of the third scan signal line 33 away from the first electrode plate 51. The eighth connection electrode 18 is connected to both the second power connection block 72 and the first region of the seventh active layer via a fifth via V5, which functions as a transition structure via. Because the second power connection block 72 is connected to the first power line 70, the first power line 70 writes the first power signal to the first electrode of the seventh transistor T7. In an exemplary embodiment, the eighth connection electrode 18 may serve as a second transition electrode of the present disclosure.

[0193] In an exemplary embodiment, the shape of the second electrode plate 52 can be rectangular, the corners of the rectangle can be chamfered, and it can be set between the second scanning signal line 32 and the light-emitting signal line 34. The positive projection of the second electrode plate 52 on the substrate at least partially overlaps with the positive projection of the first electrode plate 51 on the substrate, and the second electrode plate 52 is connected to the second end of the second connecting electrode 12 through the sixth via V6.

[0194] In an exemplary embodiment, the orthographic projection of the second electrode plate 52 on the substrate at least partially overlaps the orthographic projection of the third active layer on the substrate, and the second electrode plate 52 can serve as the gate electrode of the third transistor T3. The orthographic projection of the second electrode plate 52 on the substrate at least partially overlaps the orthographic projection of the first electrode plate 51 on the substrate, and the second electrode plate 52 can serve as the middle electrode of the storage capacitor. The first electrode plate 51 and the second electrode plate 52 can form the first capacitance of the storage capacitor. Because the second connection electrode 12 is connected to the first region of the second active layer (also the second region of the seventh active layer) via the fifth connection electrode 15, the first electrode of the second transistor T2, the second electrode of the seventh transistor T7, and the second electrode plate 52 have the same potential, forming the first node N1 of the pixel driving circuit.

[0195] In an exemplary embodiment, a second opening 55 may be provided on the edge of the second electrode plate 52 close to the light-emitting signal line 34. The second opening 55 may be in the shape of a block (such as a rectangle) and may be provided on the side close to the data signal line 60. The orthographic projection of the second opening 55 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 51 on the substrate. The second opening 55 is configured to accommodate a thirteenth via hole formed subsequently.

[0196] In an exemplary embodiment, since structures such as the data signal line and the first power line are arranged in the first conductive layer, the active layer of the multiple transistors is arranged in the semiconductor layer, and structures such as the gate electrodes and the multiple connecting electrodes of the multiple transistors are arranged in the second conductive layer, the multiple connecting electrodes located in the second conductive layer realize the connection between the semiconductor layer and the first conductive layer, and thus the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are transistors with a top gate bottom connect (TGBC) structure.

[0197] Figures 10C and 10D are cross-sectional views taken along line AA in Figure 10A. A first conductive layer is disposed on a substrate 10, a first insulating layer 81 is disposed on a side of the first conductive layer away from the substrate 10, a semiconductor layer is disposed on a side of the first insulating layer 81 away from the substrate 10, a second insulating layer 82 is disposed on a side of the semiconductor layer away from the substrate 10, and a second conductive layer is disposed on a side of the second insulating layer 82 away from the substrate 10. The second conductive layer may include at least a fifth connecting electrode 15, a second scanning signal line 32, a light-emitting signal line 34, and a second plate 52 of a storage capacitor. The fifth connecting electrode 15 may be simultaneously connected to the first end of the second connecting electrode 12 and the second active layer 22 via a second via hole serving as a transition structure via hole. The orthographic projection of the second plate 52 on the substrate at least partially overlaps with the orthographic projection of the first plate 51 on the substrate. The second plate 52 is connected to the second end of the second connecting electrode 12 via a sixth via hole V6.

[0198] In the exemplary embodiment, during the process of forming the second conductive layer pattern, a wet etching process is first used to form the second conductive layer pattern, thereby achieving simultaneous connection of the fifth connecting electrode 15 to the second connecting electrode 12 and the second active layer 22 via a transfer structure via, and connection of the second electrode plate 52 to the second connecting electrode 12 via a single-hole structure via. In the exemplary embodiment, a first distance L is provided between the edge of the fifth connecting electrode 15 located in the shallow half-hole region and the edge of the shallow half-hole, meaning that the fifth connecting electrode 15 does not fully cover the shallow half-hole, as shown in FIG. 10C .

[0199] In an exemplary embodiment, after forming the second conductive layer pattern using a wet etching process, a dry etching process is used to etch the second insulating layer 82 in areas outside the second conductive layer using a self-aligned process, utilizing the second conductive layer as a mask. While the second insulating layer 82 in areas outside the second conductive layer is etched away, the exposed semiconductor layer is subjected to a second conductorization process, as shown in FIG10D . During the second conductorization process, the edge of the semiconductor layer covered by the second conductive layer is also conductorized. Specifically, the second conductorized semiconductor layer extends toward the first conductorized area, forming a double conductorized region in the overlapping area of ​​the first and second conductorized regions. This ensures a reliable connection between the second conductive layer and the semiconductor layer.

[0200] (15) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate having the aforementioned pattern formed thereon, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer pattern, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG. 11A .

[0201] In an exemplary embodiment, the plurality of via holes in each circuit unit in the display substrate includes at least an eleventh via hole V11 , a twelfth via hole V12 , a thirteenth via hole V13 , and a fourteenth via hole V14 .

[0202] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the third connecting electrode 13 on the substrate, the third insulating layer and the first insulating layer in the eleventh via hole V11 are etched away to expose the surface of the third connecting electrode 13, and the eleventh via hole V11 is configured to connect a subsequently formed anode connecting electrode to the third connecting electrode 13 through the via hole.

[0203] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region 26-2 of the sixth active layer (also the second region 21-2 of the first active layer) on the substrate, and the third insulating layer in the twelfth via hole V12 is etched away to expose the surface of the second region 26-2 of the sixth active layer (also the second region 21-2 of the first active layer). The twelfth via hole V12 can serve as a single-hole structure via hole of the present invention and is configured to connect a subsequently formed anode connection electrode to the second region 26-2 of the sixth active layer (also the second region 21-2 of the first active layer) through the via hole.

[0204] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second opening 55 on the second electrode plate 52 on the substrate, the third insulating layer and the first insulating layer in the thirteenth via hole V13 are etched away, exposing the surface of the first electrode plate 51, and the thirteenth via hole V13 is configured to connect the subsequently formed third electrode plate to the first electrode plate 51 through the via hole.

[0205] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the eighth connecting electrode 18 on the substrate, the third insulating layer in the fourteenth via hole V14 is etched away to expose the surface of the eighth connecting electrode 18, and the fourteenth via hole V14 is configured to connect a subsequently formed power connection line to the eighth connecting electrode 18 through the via hole.

[0206] FIG11B is a cross-sectional view taken along line AA in FIG11A . As shown in FIG11B , a first conductive layer is disposed on a substrate 10, a first insulating layer 81 is disposed on a side of the first conductive layer away from the substrate 10, a semiconductor layer is disposed on a side of the first insulating layer 81 away from the substrate 10, a second insulating layer 82 is disposed on a side of the semiconductor layer away from the substrate 10, a second conductive layer is disposed on a side of the second insulating layer 82 away from the substrate 10, and a third insulating layer 83 is disposed on a side of the second conductive layer away from the substrate 10. At least a twelfth via hole V12 and a thirteenth via hole V13 are disposed on the third insulating layer 83. The twelfth via hole V12 exposes the surface of the sixth active layer 26, and the thirteenth via hole V13 exposes the surface of the first electrode plate 51.

[0207] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the third insulating layer, as shown in FIG12A and FIG12B , where FIG12B is a plan view schematic diagram of the third conductive layer in FIG12A . In an exemplary embodiment, the third conductive layer may be referred to as a source-drain metal (SD) layer.

[0208] In an exemplary embodiment, the third conductive layer of each circuit unit in the display substrate includes at least an anode connection electrode 41 , a power connection line 42 , and a third electrode plate 53 of a storage capacitor.

[0209] In an exemplary embodiment, the anode connection electrode 41 may be in the shape of a strip extending along the first direction X. A first end of the anode connection electrode 41 is connected to the third connection electrode 13 via an eleventh via hole V11, and a second end of the anode connection electrode 41 is connected to the second region 26-2 of the sixth active layer (also the second region 21-2 of the first active layer) via a twelfth via hole V12. Because the third connection electrode 13 is connected to the first electrode plate 51, the anode connection electrode 41 ensures that the second electrode of the first transistor T1, the second electrode of the sixth transistor T6, and the first electrode plate 51 have the same potential, forming a fourth node N4 of the pixel driving circuit.

[0210] In an exemplary embodiment, the power connection line 42 may be in the shape of a straight line or a zigzag line extending along the first direction X. It may be disposed on the side of the third scan signal line 33 away from the second electrode plate 52. The power connection line 42 is connected to the eighth connection electrode 18 via the fourteenth via hole V14. Since the eighth connection electrode 18 is connected to the second power connection block 72, and the second power connection block 72 is connected to the first power line 70, interconnection is achieved between the power connection line 42, whose main portion extends along the first direction X, and the first power line 70, whose main portion extends along the second direction Y. The power connection line 42 and the first power line 70 form a mesh-like interconnect structure on the display substrate for transmitting the first power signal. This not only effectively reduces the resistance of the first power line and the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal across the display substrate, effectively improving display uniformity and enhancing display quality.

[0211] In an exemplary embodiment, the third electrode plate 53 may be rectangular, with chamfered corners, and may be disposed between the second scanning signal line 32 and the light-emitting signal line 34. The third electrode plate 53 is connected to the first electrode plate 51 via a thirteenth via hole V13. In an exemplary embodiment, the orthographic projection of the third electrode plate 53 on the substrate at least partially overlaps the orthographic projection of the second electrode plate 52 on the substrate. The third electrode plate 53 may serve as the upper plate of the storage capacitor, and the third electrode plate 53 and the second electrode plate 52 may form a second capacitor of the storage capacitor.

[0212] In the exemplary embodiment, since the first plate 51 has the potential of the fourth node N4 in the pixel driving circuit, and the third plate 53 is connected to the first plate 51 through a via, the third plate 53 also has the potential of the fourth node N4 in the pixel driving circuit. Since the second plate 52 has the potential of the first node N1 in the pixel driving circuit, the second plate 52 having the potential of the first node N1 and the first plate 51 having the potential of the fourth node N4 form a first capacitor of the storage capacitor, and the second plate 52 having the potential of the first node N1 and the third plate 53 having the potential of the fourth node N4 form a second capacitor of the storage capacitor. The first capacitor and the second capacitor connected in parallel constitute the storage capacitor of the pixel driving circuit.

[0213] In an exemplary embodiment, since the active layers of multiple transistors are arranged in the semiconductor layer, the gate electrodes of multiple transistors are arranged in the second conductive layer, structures such as the anode connection electrode are arranged in the third conductive layer, and the anode connection electrode located in the third conductive layer is connected to the semiconductor layer, the sixth transistor T6 is a transistor with a top gate structure.

[0214] In an exemplary embodiment, a first conductive layer is disposed on a substrate 10, a first insulating layer 81 is disposed on a side of the first conductive layer away from the substrate 10, a semiconductor layer is disposed on a side of the first insulating layer 81 away from the substrate 10, a second insulating layer 82 is disposed on a side of the semiconductor layer away from the substrate 10, a second conductive layer is disposed on a side of the second insulating layer 82 away from the substrate 10, a third insulating layer 83 is disposed on a side of the second conductive layer away from the substrate 10, and a third conductive layer is disposed on a side of the third insulating layer 83 away from the substrate 10. The third conductive layer may include at least an anode connecting electrode 41 and a third electrode plate 53. The anode connecting electrode 41 is connected to the sixth active layer 26 through a twelfth via hole V12, and the third electrode plate 53 is connected to the first electrode plate 51 through a thirteenth via hole V13, as shown in FIG.

[0215] (17) Forming a flat layer pattern. In an exemplary embodiment, forming the flat layer pattern may include: coating a flat film on the substrate on which the aforementioned pattern is formed, patterning the flat film using a patterning process to form a flat layer covering the third conductive layer pattern, wherein at least an anode via is provided on the flat layer in each circuit unit. The orthographic projection of the anode via on the substrate is within the range of the orthographic projection of the anode connection electrode on the substrate, the flat layer in the anode via is removed to expose the surface of the anode connection electrode, and the anode via is configured to allow a subsequently formed anode to be connected to the anode connection electrode through the via.

[0216] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, an initial signal line, a data signal line, and a first power line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, and a planar layer arranged in sequence on the substrate. The first conductive layer may include at least a first electrode, a data signal line, and a first power line, the semiconductor layer may include at least an active layer of multiple transistors, the second conductive layer may include at least a second electrode, a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, and an initial signal line, and the third conductive layer may include at least a third electrode, an anode connection electrode, and a power connection line.

[0217] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and one or more of textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0218] In an exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first conductive layer, the second conductive layer, and the third conductive layer may be made of a metal material such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or may be made of an alloy material composed of a metal such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure or a multilayer composite structure such as Ti / Al / Ti. The planar layer may be made of an organic material such as a resin or polyimide.

[0219] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer and an encapsulation structure layer may be sequentially prepared on the driving circuit layer, which will not be described in detail here.

[0220] In a display substrate employing a top-gate bottom-connection (TGBC) structure, a connecting electrode located in the second conductive layer connects the semiconductor layer to the first conductive layer via a transition structure via. The inventors of this application have discovered that, because the transition structure vias include a deep half-hole and a shallow half-hole and require simultaneous overlap of the first conductive layer, the semiconductor layer, and the second conductive layer, the transition structure vias are not only large in area, but also require a larger outer edge around each transition structure via to account for exposure alignment accuracy, etching deviation, and etching-induced non-uniformity. This results in a larger area occupied by the pixel drive circuit, limiting improvements in the display resolution of the display substrate. Furthermore, the complex process of fabricating the transition structure vias affects product yield.

[0221] The embodiment of the present disclosure provides a display substrate that combines a TGBC structure with a Top Gate structure, which not only reduces the occupied area of ​​the pixel driving circuit, which is conducive to improving the display resolution, but also reduces the complexity of the punching process, which is conducive to improving the product yield. In the display substrate of the embodiment of the present disclosure, the first transistor T1 connected to the initial signal line, the second transistor T2 connected to the second electrode, the fourth transistor T4 connected to the data signal line, and the fifth transistor T5 and the seventh transistor T7 connected to the first power line adopt a TGBC structure, and the sixth transistor T6 connected to the anode connection electrode adopts a Top Gate structure. Compared with a display substrate in which all transistors adopt a TGBC structure, the display substrate of the present disclosure reduces the number of transfer structure vias, reducing 6 transfer structure vias to 5 transfer structure vias, which can effectively reduce the occupied area of ​​the pixel driving circuit and effectively improve the display resolution. In addition, reducing the number of transfer structure vias can reduce the complexity of the punching process, reduce production costs, and effectively improve product yield. Compared with display substrates in which all transistors adopt a Top Gate structure, the display substrate disclosed herein can reduce the coupling capacitance between the data signal line and the first power line and other signals and reduce crosstalk between signals by setting the data signal line and the first power line in the first conductive layer, and can also effectively reduce the delay time RC of the data signal line, thereby effectively reducing logic power consumption.

[0222] The embodiment of the present disclosure forms a sandwich structure with a three-layer metal layout by utilizing a first conductive layer, a second conductive layer, and a third conductive layer. The first capacitor and the second capacitor of the parallel structure constitute a storage capacitor. On the one hand, this can effectively increase the capacitance value of the storage capacitor. On the other hand, it can reduce the plate area while ensuring the capacitance value of the storage capacitor, further reducing the occupied area of ​​the pixel driving circuit, and effectively improving the display resolution.

[0223] In the embodiment of the present disclosure, a power connection line having a main portion extending along a first direction X and a first power line having a main portion extending along a second direction Y are provided, and the first power line and the power connection line are interconnected, so that the first power line and the power connection line form a mesh structure on the display substrate for transmitting a first power signal. This not only effectively reduces the resistance of the first power line and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improves display uniformity, and enhances display quality.

[0224] In an exemplary embodiment, the present disclosure effectively reduces the resistance of the scanning signal lines and the light-emitting signal lines by setting the scanning signal lines and the light-emitting signal lines in the source-drain metal (SD) layer, reduces the voltage drop of the scanning signal and the light-emitting signal lines, and effectively improves the compensation speed.

[0225] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0226] Figure 13 is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a circuit unit. As shown in Figure 13 , in this exemplary embodiment, the main structure of the display substrate is substantially the same as that of the embodiment shown in Figure 5 , with the difference being that the first transistor T1 connected to the initial signal line in this embodiment employs a Top Gate structure.

[0227] In an exemplary embodiment, the first conductive layer is not provided with a first connecting electrode as a first switching electrode, the initial signal line 35 is provided in the third conductive layer, and the initial signal line 35 located in the third conductive layer is connected to the first active layer located in the semiconductor layer through the fifteenth via hole V15 which is a single-hole structure via hole.

[0228] In an exemplary embodiment, the structures of the second to seventh transistors T2 to T7 of this embodiment are substantially the same as those of the embodiment shown in FIG. 5 .

[0229] In an exemplary embodiment, taking a circuit unit as an example, the preparation process of the display substrate in this embodiment may include the following operations.

[0230] (21) Forming a first conductive layer pattern. In an exemplary embodiment, the process of forming the first conductive layer pattern and the structure of the first conductive layer are substantially the same as those shown in FIG7A , except that the first conductive layer of each circuit unit is not provided with a first connection electrode, as shown in FIG14 .

[0231] In an exemplary embodiment, the first conductive layer of each circuit unit in the display substrate may include at least a second connection electrode 12, a third connection electrode 13, a first plate 51 of a storage capacitor, a data signal line 60 and a first power line 70, and the above structure is substantially the same as that of the aforementioned embodiment.

[0232] In an exemplary embodiment, the first power line 70 may be provided with a second power connection block 72 , the first power line 70 may not be provided with a first power connection block, and the data signal line 60 may not be provided with a data connection block.

[0233] (22) Forming a semiconductor layer pattern. In an exemplary embodiment, the process of forming a semiconductor layer pattern and the structure of the semiconductor layer are substantially the same as those shown in FIG8A and FIG8B , as shown in FIG15A and FIG15B , where FIG15B is a plan view schematically illustrating the semiconductor layer in FIG15A .

[0234] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display substrate may include first to seventh active layers 21 to 27 , and the first to seventh active layers 21 to 27 are an integrated structure connected to each other, which is substantially the same as the aforementioned embodiment.

[0235] In the exemplary embodiment, since the first conductive layer is not provided with the first connection electrode, the orthographic projection of the first region 21-1 of the first active layer on the substrate does not overlap with the orthographic projection of the first conductive layer on the substrate. The first conductive layer is not provided with the data connection block and the first power connection block. The orthographic projection of the first region 24-1 of the fourth active layer on the substrate at least partially overlaps with the orthographic projection of the data signal line 60 on the substrate, and the orthographic projection of the first region 25-1 of the fifth active layer on the substrate at least partially overlaps with the orthographic projection of the first power line 70 on the substrate.

[0236] (23) Forming a second insulating layer pattern. In an exemplary embodiment, the process of forming the second insulating layer pattern and the plurality of via structures are substantially the same as those shown in FIG. 9A , except that the plurality of vias of each circuit unit does not have the first via, as shown in FIG. 16 .

[0237] In an exemplary embodiment, the multiple vias of each circuit unit in the display substrate include at least a second via V2, a third via V3, a fourth via V4, a fifth via V5 and a sixth via V6. The second vias V2 to the fifth via V5 are transfer structure vias, and the sixth via V6 is a single-hole structure. The via structure is substantially the same as that in the aforementioned embodiment, except that the third via V3 simultaneously exposes the surface of the data signal line 60 and the first area of ​​the fourth active layer, and the fourth via V4 simultaneously exposes the surface of the first power line 70 and the first area of ​​the fifth active layer.

[0238] (24) Forming a second conductive layer pattern. In an exemplary embodiment, the process of forming the second conductive layer pattern and the structure of the second conductive layer are substantially the same as those shown in FIG. 10A and FIG. 10B , except that the second conductive layer of each circuit unit is not provided with an initial signal line, as shown in FIG. 17A and FIG. 17B , FIG. 17B is a schematic diagram of the second conductive layer in FIG. 17A .

[0239] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a fifth connecting electrode 15, a sixth connecting electrode 16, a seventh connecting electrode 17, an eighth connecting electrode 18, a first scanning signal line 31, a second scanning signal line 32, a third scanning signal line 33, a light-emitting signal line 34 and a second plate 52 of the storage capacitor. The above structure is basically the same as that of the aforementioned embodiment, except that the sixth connecting electrode 16 is simultaneously connected to the data signal line 60 and the first area of ​​the fourth active layer through the third via hole V3, and the seventh connecting electrode 17 is simultaneously connected to the first power line 70 and the first area of ​​the fifth active layer through the fourth via hole V4.

[0240] In an exemplary embodiment, since structures such as the data signal line and the first power line are arranged in the first conductive layer, the active layer of the multiple transistors is arranged in the semiconductor layer, and structures such as the gate electrodes and the multiple connecting electrodes of the multiple transistors are arranged in the second conductive layer, the multiple connecting electrodes located in the second conductive layer realize the connection between the semiconductor layer and the first conductive layer, and thus the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are transistors with a top-gate bottom-connected TGBC structure.

[0241] (25) Forming a third insulating layer pattern. In an exemplary embodiment, the process of forming the third insulating layer pattern and the plurality of via structures are substantially the same as those shown in FIG. 11A , except that the plurality of vias of each circuit unit further includes a fifteenth via V15 , as shown in FIG. 18 .

[0242] In an exemplary embodiment, the multiple vias in each circuit unit in the display substrate include at least: an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14 and a fifteenth via V15, and the structures of the eleventh via V11 to the fourteenth via V14 are substantially the same as those in the aforementioned embodiment.

[0243] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the third insulating layer in the fifteenth via V15 is etched away to expose the surface of the first region of the first active layer, and the fifteenth via V15 is configured to connect a subsequently formed initial signal line to the first region of the first active layer through the via.

[0244] (26) Forming a third conductive layer pattern. In an exemplary embodiment, the process of forming the third conductive layer and the structure of the third conductive layer are substantially the same as those shown in FIG. 12A and FIG. 12B , except that the third conductive layer of each circuit unit further includes an initial signal line, as shown in FIG. 19A and FIG. 19B , FIG. 19B is a schematic diagram of the second conductive layer in FIG. 19A .

[0245] In an exemplary embodiment, the third conductive layer of each circuit unit in the display substrate includes at least: an anode connecting electrode 41, a power connection line 42, a third plate 53 of the storage capacitor and an initial signal line 35, and the structures of the anode connecting electrode 41, the power connection line 42 and the third plate 53 are basically the same as those in the aforementioned embodiment.

[0246] In an exemplary embodiment, the shape of the initial signal line 35 can be a straight line or a broken line extending along the first direction X, and can be located on the side of the first scanning signal line 31 away from the first electrode 51. The initial signal line 35 can be connected to the first region of the first active layer through the fifteenth via V15, thereby enabling the initial signal line 35 to write the initial signal into the first electrode of the first transistor T1.

[0247] In an exemplary embodiment, since the active layers of the plurality of transistors are arranged in the semiconductor layer, the gate electrodes of the plurality of transistors are arranged in the second conductive layer, structures such as the anode connection electrode and the initial signal line are arranged in the third conductive layer, and the anode connection electrode and the initial signal line located in the third conductive layer are connected to the semiconductor layer, the first transistor T1 and the sixth transistor T6 are transistors with a Top Gate structure.

[0248] (27) Forming a planar layer pattern In the exemplary embodiment, the process of forming the planar layer pattern and the anode via structure are substantially the same as those in the aforementioned embodiment.

[0249] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, an initial signal line, a data signal line and a first power line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer and a flat layer arranged in sequence on the substrate. The first conductive layer may include at least a first electrode, a data signal line and a first power line, the semiconductor layer may include at least an active layer of multiple oxide transistors, the second conductive layer may include at least a second electrode, a first scanning signal line, a second scanning signal line, a third scanning signal line and a light-emitting signal line, and the third conductive layer may include at least a third electrode, an anode connection electrode, a power connection line and an initial signal line.

[0250] The embodiment of the present disclosure provides a display substrate that combines a TGBC structure with a Top Gate structure. This not only reduces the area occupied by the pixel driving circuit, which is beneficial to improving the display resolution, but also reduces the complexity of the punching process, which is beneficial to improving the product yield. In the display substrate of the embodiment of the present disclosure, the second transistor T2 connected to the second electrode, the fourth transistor T4 connected to the data signal line, and the fifth transistor T5 and the seventh transistor T7 connected to the first power line adopt a TGBC structure, and the first transistor T1 connected to the initial signal line and the sixth transistor T6 connected to the anode connection electrode adopt a Top Gate structure. Compared with a display substrate in which all transistors adopt a TGBC structure, the display substrate of the present disclosure reduces the number of transfer structure vias, reducing 6 transfer structure vias to 4 transfer structure vias, which can effectively reduce the area occupied by the pixel driving circuit and effectively improve the display resolution. In addition, reducing the number of transfer structure vias can reduce the complexity of the punching process, reduce production costs, and effectively improve product yield. Compared with display substrates in which all transistors adopt a Top Gate structure, the display substrate disclosed herein can reduce the coupling capacitance between the data signal line and the first power line and other signals and reduce crosstalk between signals by setting the data signal line and the first power line in the first conductive layer, and can also effectively reduce the delay time RC of the data signal line, thereby effectively reducing logic power consumption.

[0251] The technical effects of the parallel structure of the first capacitor and the second capacitor in the embodiment of the present disclosure forming a storage capacitor, the first power line and the power connection line forming a mesh structure, the scanning signal line and the light-emitting signal line being arranged in the source-drain metal (SD) layer, etc. are the same as those in the aforementioned embodiment and will not be repeated here.

[0252] Figure 20 is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a circuit unit. As shown in Figure 20 , in this exemplary embodiment, the main structure of the display substrate is substantially the same as that of the embodiment shown in Figure 5 , with the difference being that the fifth transistor T5 and the seventh transistor T7 connected to the first power line in this embodiment employ a Top Gate structure.

[0253] In an exemplary embodiment, the first power line is not provided in the first conductive layer, the seventh connection electrode and the eighth connection electrode are not provided in the first conductive layer, the first power line 70 is provided in the third conductive layer, and the first power line 70 located in the third conductive layer is connected to the fifth active layer through the sixteenth via hole V16 as a single-hole structure via hole, and is connected to the seventh active layer through the seventeenth via hole V17 as a single-hole structure via hole.

[0254] In an exemplary embodiment, the structures of the first to fourth transistors T1 to T4 of this embodiment are substantially the same as those of the embodiment shown in FIG. 5 .

[0255] In an exemplary embodiment, the power connection line 42 and the first power line 70 may be an integral structure connected to each other.

[0256] In an exemplary embodiment, taking a circuit unit as an example, the preparation process of the display substrate in this embodiment may include the following operations.

[0257] (31) Forming a first conductive layer pattern. In an exemplary embodiment, the process of forming the first conductive layer pattern and the structure of the first conductive layer are substantially the same as those shown in FIG7A , except that the first conductive layer of each circuit unit is not provided with a first power supply line, as shown in FIG21 .

[0258] In an exemplary embodiment, the first conductive layer of each circuit unit in the display substrate may include at least a first connection electrode 11, a second connection electrode 12, a third connection electrode 13, a first plate 51 of a storage capacitor, and a data signal line 60, on which a data connection block 61 is provided. The above structure is substantially the same as that in the aforementioned embodiment.

[0259] (32) Forming a semiconductor layer pattern. In an exemplary embodiment, the process of forming a semiconductor layer pattern and the structure of the semiconductor layer are substantially the same as those shown in FIG8A and FIG8B , as shown in FIG22A and FIG22B , where FIG22B is a plan view schematically illustrating the semiconductor layer in FIG22A .

[0260] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display substrate may include first to seventh active layers 21 to 27 , and the first to seventh active layers 21 to 27 are an integrated structure connected to each other, which is substantially the same as the aforementioned embodiment.

[0261] In an exemplary embodiment, an orthographic projection of the first region 21-1 of the first active layer on the substrate at least partially overlaps with an orthographic projection of the first connection electrode 11 on the substrate, and an orthographic projection of the first region 24-1 of the fourth active layer on the substrate at least partially overlaps with an orthographic projection of the data connection block 61 on the substrate.

[0262] In an exemplary embodiment, since the first conductive layer is not provided with a first power line, the orthographic projection of the first region 25-1 of the fifth active layer on the substrate does not overlap with the orthographic projection of the first conductive layer on the substrate, and the orthographic projection of the first region 27-1 of the seventh active layer on the substrate does not overlap with the orthographic projection of the first conductive layer on the substrate.

[0263] (33) Forming a second insulating layer pattern. In an exemplary embodiment, the process of forming the second insulating layer pattern and the plurality of via structures are substantially the same as those shown in FIG. 9A , except that the plurality of vias of each circuit unit does not include the fourth and fifth vias, as shown in FIG. 23 .

[0264] In an exemplary embodiment, the multiple vias of each circuit unit in the display substrate include at least: a first via V1, a second via V2, a third via V3 and a sixth via V6. The first via V1 to the third via V3 are transfer structure vias, and the sixth via V6 is a single-hole structure. The via structure is basically the same as that in the aforementioned embodiment.

[0265] (34) Forming a second conductive layer pattern. In an exemplary embodiment, the process of forming the second conductive layer pattern and the structure of the second conductive layer are substantially the same as those shown in FIG. 10A and FIG. 10B , except that the second conductive layer of each circuit unit is not provided with the seventh connection electrode and the eighth connection electrode, as shown in FIG. 24A and FIG. 24B , FIG. 24B is a schematic diagram of the second conductive layer in FIG. 24A .

[0266] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a fifth connecting electrode 15, a sixth connecting electrode 16, a first scanning signal line 31, a second scanning signal line 32, a third scanning signal line 33, a light-emitting signal line 34, an initial signal line 35 and a second plate 52 of the storage capacitor, and the above structure is basically the same as that of the aforementioned embodiment.

[0267] In an exemplary embodiment, since structures such as data signal lines are arranged in the first conductive layer, the active layers of multiple transistors are arranged in the semiconductor layer, and structures such as gate electrodes, multiple connecting electrodes and initial signal lines of multiple transistors are arranged in the second conductive layer, the multiple connecting electrodes and initial signal lines located in the second conductive layer realize the connection between the semiconductor layer and the first conductive layer, and thus the first transistor T1, the second transistor T2 and the fourth transistor T4 are transistors with a top-gate bottom-connection TGBC structure.

[0268] (35) Forming a third insulating layer pattern. In an exemplary embodiment, the process of forming the third insulating layer pattern and the plurality of via structures are substantially the same as those shown in FIG. 11A , except that the plurality of vias of each circuit unit further includes a sixteenth via V16 and a seventeenth via V17, as shown in FIG. 25 .

[0269] In an exemplary embodiment, the multiple vias in each circuit unit in the display substrate include at least: an eleventh via V11, a twelfth via V12, a thirteenth via V13, a sixteenth via V16 and a seventeenth via V17, and the structures of the eleventh via V11 to the thirteenth via V13 are substantially the same as those in the aforementioned embodiment.

[0270] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the third insulating layer in the sixteenth via hole V16 is etched away, exposing the surface of the first region of the fifth active layer, and the sixteenth via hole V16, as a single-hole structure via hole disclosed in the present invention, is configured to connect a subsequently formed first power line to the first region of the fifth active layer through the via hole.

[0271] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the third insulating layer in the seventeenth via hole V17 is etched away, exposing the surface of the first region of the seventh active layer, and the seventeenth via hole V17, as a single-hole structure via hole disclosed in the present invention, is configured to connect a subsequently formed first power line to the first region of the seventh active layer through the via hole.

[0272] (36) Forming a third conductive layer pattern. In an exemplary embodiment, the process of forming the third conductive layer and the structure of the third conductive layer are substantially the same as those shown in FIG. 12A and FIG. 12B , except that the third conductive layer of each circuit unit further includes a power connection line 42 and a first power line 70 , as shown in FIG. 26A and FIG. 26B , FIG. 26B is a schematic diagram of the second conductive layer in FIG. 26A .

[0273] In an exemplary embodiment, the third conductive layer of each circuit unit in the display substrate includes at least: an anode connection electrode 41, a power connection line 42, a third plate 53 of the storage capacitor and a first power line 70, and the structures of the anode connection electrode 41 and the third plate 53 are substantially the same as those in the aforementioned embodiment.

[0274] In an exemplary embodiment, the shape of the first power line 70 can be a straight line or a broken line extending along the second direction Y, and can be arranged on the side of the first electrode plate 51 in the opposite direction of the first direction X. On the one hand, the first power line 70 is connected to the first area of ​​the fifth active layer through the sixteenth via V16, and on the other hand, it is connected to the first area of ​​the seventh active layer through the seventeenth via V17, thereby realizing that the first power line 70 can write the first power signal into the first electrode of the fifth transistor T5 and the first electrode of the seventh transistor T7 respectively.

[0275] In an exemplary embodiment, the power connection line 42 may be in the shape of a straight line or a broken line extending along the first direction X, and may be disposed on a side of the third scan signal line 33 away from the second electrode plate 52. The power connection line 42 is connected to the first power line 70, thereby achieving mutual connection between the power connection line 42 extending along the first direction X and the first power line 70 extending along the second direction Y of the main body. The power connection line 42 and the first power line 70 form a mesh structure on the display substrate that transmits the first power signal in a mesh-like interconnected structure.

[0276] In an exemplary embodiment, the power connection line 42 and the first power line 70 may be an integral structure connected to each other.

[0277] In an exemplary embodiment, since the active layers of multiple transistors are arranged in the semiconductor layer, the gate electrodes of multiple transistors are arranged in the second conductive layer, structures such as the anode connection electrode and the first power line are arranged in the third conductive layer, and the anode connection electrode and the first power line located in the third conductive layer are connected to the semiconductor layer, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are transistors with a Top Gate structure.

[0278] (37) Forming a planar layer pattern. In the exemplary embodiment, the process of forming the planar layer pattern and the anode via structure are substantially the same as those in the aforementioned embodiment.

[0279] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, an initial signal line, a data signal line and a first power line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer and a flat layer arranged in sequence on the substrate. The first conductive layer may include at least a first electrode and a data signal line, the semiconductor layer may include at least an active layer of a plurality of oxide transistors, the second conductive layer may include at least a second electrode, a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line and an initial signal line, and the third conductive layer may include at least a third electrode, an anode connection electrode, a power connection line and a first power line.

[0280] The embodiment of the present disclosure provides a display substrate that combines a TGBC structure with a Top Gate structure. This not only reduces the area occupied by the pixel driving circuit, which is beneficial to improving the display resolution, but also reduces the complexity of the punching process, which is beneficial to improving the product yield. In the display substrate of the embodiment of the present disclosure, the first transistor T1 connected to the initial signal line, the second transistor T2 connected to the second electrode, and the fourth transistor T4 connected to the data signal line adopt a TGBC structure, and the fifth transistor T5 connected to the first power line, the sixth transistor T6 connected to the anode connection electrode, and the seventh transistor T7 connected to the first power line adopt a Top Gate structure. Compared with a display substrate in which all transistors adopt a TGBC structure, the display substrate of the present disclosure reduces the number of transfer structure vias, reducing 6 transfer structure vias to 3 transfer structure vias, which can effectively reduce the area occupied by the pixel driving circuit and effectively improve the display resolution. In addition, reducing the number of transfer structure vias can reduce the complexity of the punching process, reduce production costs, and effectively improve product yield. Compared with display substrates in which all transistors adopt a Top Gate structure, the display substrate disclosed herein can reduce the coupling capacitance between the data signal line and other signals and reduce crosstalk between signals by setting the data signal line in the first conductive layer, and can also effectively reduce the delay time RC of the data signal line, thereby effectively reducing logic power consumption.

[0281] The technical effects of the parallel structure of the first capacitor and the second capacitor in the embodiment of the present disclosure forming a storage capacitor, the first power line and the power connection line forming a mesh structure, the scanning signal line and the light-emitting signal line being arranged in the source-drain metal (SD) layer, etc. are the same as those in the aforementioned embodiment and will not be repeated here.

[0282] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0283] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0284] The present disclosure also provides a method for manufacturing a display substrate, for manufacturing the display substrate provided in the above embodiment. The display substrate includes a plurality of circuit units, at least one of which includes a pixel driving circuit, and the pixel driving circuit includes at least a plurality of transistors. The manufacturing method may include:

[0285] A first conductive layer, a semiconductor layer, a second conductive layer and a third conductive layer are formed in sequence on a substrate and along a direction away from the substrate, wherein the first conductive layer includes at least one first switching electrode, the semiconductor layer includes active layers of multiple transistors, the second conductive layer includes at least one second switching electrode, and the third conductive layer includes at least one third switching electrode; the second switching electrode is simultaneously connected to the first switching electrode and the active layer of one transistor through a switching structure via, and the third switching electrode is connected to the active layer of another transistor through a single-hole structure via, and the switching structure via includes a deep half hole and a shallow half hole, the deep half hole exposes the first switching electrode, and the shallow half hole exposes the active layer.

[0286] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0287] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of circuit units, at least one of which comprises a pixel driving circuit, wherein the pixel driving circuit comprises at least a plurality of transistors; in a direction perpendicular to the plane of the display substrate, the display substrate comprises at least a first conductive layer, a semiconductor layer, a second conductive layer and a third conductive layer which are arranged on a substrate and sequentially arranged in a direction away from the substrate, wherein the first conductive layer comprises at least one first switching electrode, the semiconductor layer comprises active layers of a plurality of transistors, the second conductive layer comprises at least one second switching electrode, and the third conductive layer comprises at least one third switching electrode; the second switching electrode is connected to the first switching electrode and the active layer of one transistor at the same time through a switching structure via hole, the third switching electrode is connected to the active layer of another transistor through a single-hole structure via hole, the switching structure via hole comprises a deep half hole and a shallow half hole, the deep half hole exposes the first switching electrode, and the shallow half hole exposes the active layer.

2. The display substrate according to claim 1, wherein: The multiple transistors include at least a first transistor, the first transistor includes at least a first active layer, and the first active layer is arranged in the semiconductor layer; the first conductive layer includes a first connecting electrode serving as the first transfer electrode, and the second conductive layer also includes an initial signal line, and the initial signal line is connected to the first connecting electrode and the first active layer at the same time through a transfer structure via.

3. The display substrate according to claim 1, wherein: The multiple transistors include at least a first transistor, the first transistor includes at least a first active layer, and the first active layer is arranged in the semiconductor layer; the third conductive layer also includes an initial signal line, and the initial signal line is connected to the first active layer through a single-hole structure via.

4. The display substrate according to claim 1, wherein: The multiple transistors include at least a second transistor, the second transistor includes at least a second active layer, and the second active layer is arranged in the semiconductor layer; the first conductive layer includes a second connecting electrode serving as the first switching electrode, the second conductive layer includes a fifth connecting electrode serving as the second switching electrode, and the fifth connecting electrode is connected to the second connecting electrode and the second active layer at the same time through a switching structure via.

5. The display substrate according to claim 1, wherein: The multiple transistors include at least a fourth transistor, the fourth transistor includes at least a fourth active layer, and the fourth active layer is arranged in the semiconductor layer; the first conductive layer also includes a data signal line, the second conductive layer includes a sixth connecting electrode serving as the second transfer electrode, and the sixth connecting electrode is connected to the data signal line and the fourth active layer at the same time through a transfer structure via.

6. The display substrate according to claim 1, wherein: The plurality of transistors include at least a fifth transistor, the fifth transistor includes at least a fifth active layer, and the fifth active layer is disposed in the semiconductor layer; The first conductive layer further includes a first power line, and the second conductive layer includes a seventh connection electrode serving as the second switching electrode. The seventh connection electrode is connected to the first power line and the fifth active layer simultaneously through a switching structure via.

7. The display substrate according to claim 1, wherein: The plurality of transistors include at least a fifth transistor, the fifth transistor includes at least a fifth active layer, and the fifth active layer is disposed in the semiconductor layer; The third conductive layer further includes a first power line, and the first power line is connected to the fifth active layer through a single-hole structure via.

8. The display substrate according to claim 1, wherein: The multiple transistors include at least a sixth transistor, the sixth transistor includes at least a sixth active layer, and the sixth active layer is arranged in the semiconductor layer; the third conductive layer includes an anode connecting electrode serving as the third switching electrode, and the anode connecting electrode is connected to the sixth active layer through a single-hole structure via.

9. The display substrate according to claim 1, wherein: The multiple transistors include at least a seventh transistor, the seventh transistor includes at least a seventh active layer, and the seventh active layer is arranged in the semiconductor layer; the first conductive layer also includes a first power line, the second conductive layer includes an eighth connecting electrode serving as the second switching electrode, and the eighth connecting electrode is connected to the first power line and the seventh active layer at the same time through a switching structure via.

10. The display substrate according to claim 1, wherein: The plurality of transistors include at least a seventh transistor, the seventh transistor includes at least a seventh active layer, and the seventh active layer is disposed in the semiconductor layer; The third conductive layer further includes a first power line, and the first power line is connected to the seventh active layer through a single-hole structure via.

11. The display substrate according to any one of claims 1 to 10, wherein: At least one transistor includes a gate electrode disposed in the second conductive layer.

12. The display substrate according to any one of claims 1 to 10, wherein: The pixel driving circuit also includes a storage capacitor, which includes at least a first electrode plate arranged in the first conductive layer, a second electrode plate arranged in the second conductive layer, and a third electrode plate arranged in the third conductive layer, the orthographic projection of the second electrode plate on the substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the substrate plane, the orthographic projection of the third electrode plate on the substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the substrate plane, and the first electrode plate is connected to the third electrode plate.

13. The display substrate according to any one of claims 1 to 10, wherein: At least one circuit unit also includes at least one power connection line extending along a first direction and at least one first power line extending along a second direction, the first power line is connected to the power connection line to form a mesh connection structure for transmitting a first power signal, and the first direction and the second direction intersect.

14. The display substrate according to claim 13, wherein: The first power line is arranged in the first conductive layer, the power connection line is arranged in the third conductive layer, the second conductive layer includes an eighth connection connection as the second switching electrode, the eighth connection connection is connected to the first power line through a via, and the power connection line is connected to the eighth connection connection through a via.

15. The display substrate according to claim 13, wherein: The first power line and the power connection line are arranged in the same layer and are an integrated structure connected to each other.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

17. A method for preparing a display substrate, the display substrate comprising a plurality of circuit units, at least one of which comprises a pixel driving circuit, and the pixel driving circuit comprises at least a plurality of transistors; the method comprising: A first conductive layer, a semiconductor layer, a second conductive layer and a third conductive layer are sequentially formed on a substrate and in a direction away from the substrate, wherein the first conductive layer includes at least one first switching electrode, the semiconductor layer includes an active layer of a plurality of transistors, the second conductive layer includes at least one second switching electrode, and the third conductive layer includes at least one third switching electrode; The second transfer electrode is connected to the first transfer electrode and the active layer of a transistor at the same time through a transfer structure via, and the third transfer electrode is connected to the active layer of another transistor through a single-hole structure via. The transfer structure via includes a deep half hole and a shallow half hole, the deep half hole exposes the first transfer electrode, and the shallow half hole exposes the active layer.

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