Surface-mount ceramic electronic element suitable for low-voltage-grid voltage, and manufacturing method

Abstract

A surface-mount ceramic electronic element suitable for a low-voltage-grid voltage, and a manufacturing method. The element comprises N surface-mount electronic ceramic chips, an electrically conductive connection assembly, and an insulating wrapping and packaging layer, wherein n≥1; and the N surface-mount electronic ceramic chips are stacked on top of each other to form a laminated surface-mount assembly. Each surface-mount electronic ceramic chip comprises a ceramic body, a first electrode, and a second electrode, wherein the ceramic body has an upper end face, a lower end face, and a first side face and a second side face between the upper end face and the lower end face; the first electrode covers part of the upper end face and at least part of the first side face; the second electrode covers part of the lower end face and at least part of the second side face; and the electrically conductive connection assembly is connected to side face electrodes of the N surface-mount electronic ceramic chips, so as to connect the N surface-mount electronic ceramic chips in parallel and fix same in positions thereof. Then, an insulating material is used for packaging, and only connection electrode ends are exposed, and are bent and formed to serve as end terminals of the surface-mount ceramic electronic element.

Description

Chip-type ceramic electronic component suitable for low-voltage grid voltage and manufacturing method

[0001] This application claims priority to the Chinese patent application filed on September 15, 2023 (application number: 202311194834.6). Technical Field

[0002] The present invention relates to the technical field of electronic ceramic components including varistors, and in particular to a surface-mount ceramic electronic component suitable for low-voltage grid voltage and a manufacturing method thereof. Background Art

[0003] A low-voltage power grid refers to a power supply line that transmits power over short distances and is directly connected to electrical appliances. For AC power, transmission lines with a voltage below 1000V are called low-voltage power grids. The most commonly used low-voltage power grid voltages are 110V, 220V, and 380V.

[0004] In the current electronics manufacturing industry, surface mount technology (SMT) using chip components has become the mainstream production process, occupying 80% to 90% of the market share for printed circuit board (PCB) processing. However, in a few areas, such as power modules, the electrical characteristics of some components have led to slow progress in chip-type structures. They are still mainly processed using traditional lead insertion and welding methods. Varistors are one of them. In low-voltage power grids, high-energy surges caused by lightning induction or the operation of heavy-load equipment often occur. Due to instantaneous overcurrent, varistors need to withstand large surge current impacts. The current withstand capacity of varistors is proportional to the surface area of ​​the electrode end. The chip structure of varistors with larger areas presents great technical difficulties.

[0005] Currently, multilayer varistors with a surface-mount structure are already available. These typically feature a chip-type multilayer varistor with the same structure and process as a multilayer ceramic capacitor (MLCC). This varistor uses a tape casting process to create a ceramic green film layer, typically several microns thick. Electrodes are then printed on top, and the film layer is cast again. This repeated stacking process is followed by cutting, drying, and sintering at high temperature. During the sintering process, the organic additives in the ceramic green film and the electrode slurry vaporize and volatilize, while the low-melting-point inorganic components (glass phase) melt and bond together to form a monolithic structure, also known as a "monolithic" structure, which forms the main body of the multilayer chip varistor. Because the ceramic green film layer created by the tape casting process cannot be too thick, the operating voltage of this multilayer chip varistor is not very high, rarely exceeding 50 volts. Furthermore, because it is sintered into a single piece, its ability to withstand thermal shock stress caused by surges is insufficient, affecting the component's surge withstand capability, allowing it to absorb only a few tenths of a joule to several joules of surge energy. Widely used in the external jacks of battery-powered mobile electronic devices such as laptops and mobile phones to absorb electrostatic induction surges with relatively small surge energy and operational overvoltage surges caused by hot plugging.

[0006] It can be seen from this that the surface-mount multi-layer ceramic electronic components produced by the casting method cannot be used in low-voltage power grid voltages, such as AC 220V, because the ceramic green film layer cannot be made thicker, the operating voltage is low, and the energy tolerance is too low.

[0007] Currently, single-layer varistors with chip structures and single-layer medium- and high-voltage capacitors with similar manufacturing processes have been developed. For example, Chinese patent application number 2013203516840 discloses a rectangular strip varistor device. The device first forms a rectangular ceramic body (ceramic body) of the varistor, then coats both end faces with metal electrodes. Thin copper strips are welded to the metal end electrodes, and the electrode-coated ceramic body is then insulated and encapsulated with resin. The exposed copper strips are then shaped to form lead terminals for easy surface mount soldering. Because the ceramic body of this chip varistor structure can be made thicker, it can be used with low-voltage grid voltages, such as AC 220V. However, given the high operating voltage and the need to withstand transient pulses of high voltage and high current caused by strong surges such as lightning, the bending and forming of the lead-out copper strip at the end must fully consider sufficient insulation space to ensure that there are no short circuits or high-voltage arc discharge breakdowns during surge discharge. This leads to shortcomings such as a complex structure of the end lead-out part, excessive space occupation, and the inability to stack ceramic tiles in parallel. Due to the limited end electrode area of ​​the single-layer ceramic body, the allowable flow rate is too small. To increase the flow rate, the end electrode area needs to be increased, thereby increasing the length and width of the component. This is inconsistent with the requirements of modern electronic technology for small size and high performance. Therefore, the application range of single-layer chip-type varistors in the low-voltage grid voltage field is currently greatly limited. In the low-voltage grid voltage application field, traditional lead plug-in welding products are still the mainstream method.

[0008] Summary of the Invention

[0009] The purpose of the present invention is to overcome the problems that the existing multi-layer chip varistor / capacitor ceramic green film layer produced by the casting method cannot be made thicker, has a low operating voltage, and has a low energy tolerance; the existing single-layer chip varistor / capacitor electrical parameter capacity is too small and cannot be used in low-voltage grid voltage application scenarios. The present invention provides a chip-type ceramic electronic component and method suitable for low-voltage grid voltage. The stacked chip-type ceramic electronic component provided by the present invention includes multiple single-piece formed chip-type electronic ceramic chips. The stacked chip-type ceramic electronic component is formed by stacking and fixing the multiple chip-type electronic ceramic chips in parallel and then encapsulating them. In actual use environments, varistors and capacitors may be used in parallel at the same time. The stacked chip-type ceramic electronic component provided by the present invention can combine varistors and capacitors into an integrated component, effectively reducing the number of plug-ins and costs.

[0010] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0011] A surface-mount ceramic electronic component suitable for low-voltage grid voltage, characterized by comprising:

[0012] N surface-mount electronic ceramic chips, conductive connection components, and insulating encapsulation layers; where N ≥ 1;

[0013] N said patch-type electronic ceramic chips are stacked on each other to form a laminated patch assembly, said laminated patch assembly is fixedly connected to a conductive connection assembly, and said insulating encapsulation layer is used to encapsulate the fixedly connected assembly;

[0014] The surface-mount electronic ceramic chip comprises a ceramic body and an electrode group, wherein the electrode group is disposed on the outer surface of the ceramic body, and the electrode group comprises a first electrode and a second electrode; the ceramic body has upper and lower end surfaces and side surfaces between the upper and lower end surfaces, wherein the side surfaces include at least a first side surface and a second side surface, the first electrode covers a portion of the upper end surface and at least a portion of the first side surface, forming an end surface electrode portion and a side surface electrode portion of the first electrode; the second electrode covers a portion of the lower end surface and at least a portion of the second side surface, forming an end surface electrode portion and a side surface electrode portion of the second electrode;

[0015] The overlapping surfaces of the stacked chip assembly are end surfaces of the chip-type electronic ceramic chips, and the chip-type electronic ceramic chips are stacked symmetrically with adjacent end surface electrodes on the overlapping surfaces. The stacked chip assembly includes: a third electrode and a fourth electrode, wherein the third electrode is formed by N side electrodes on the same side of the stacked N chip-type electronic ceramic chips, and the fourth electrode is formed by N side electrodes on the other side of the stacked N chip-type electronic ceramic chips. The conductive connection assembly is connected to the third and fourth electrodes to connect the N chip-type electronic ceramic chips in parallel and fix the positions of the N chip-type electronic ceramic chips.

[0016] The insulating encapsulating layer is used to encapsulate the laminated patch assembly and part of the conductive connection assembly, and the remaining unencapsulated part of the conductive connection assembly is the terminal electrode.

[0017] According to a specific embodiment, in the above-mentioned surface-mount ceramic electronic component applicable to low-voltage grid voltage, the conductive connection component includes: a first lead-out electrode and a second lead-out electrode;

[0018] The first lead electrode is welded to the third electrode of the stacked patch assembly, and the second lead electrode is welded to the fourth electrode of the stacked patch assembly;

[0019] The insulating encapsulating material encapsulates the stacked patch assembly after the lead electrodes are welded, and the first lead electrode and the second lead electrode are respectively extended out of a portion of the insulating encapsulating layer to form terminal electrodes.

[0020] According to a specific embodiment, in the above-mentioned chip-type ceramic electronic component suitable for low-voltage grid voltage, the first lead electrode and the second lead electrode are sheet electrodes, which pass through the extension section of the insulating encapsulation layer and are bent tightly against the surface of the insulating encapsulation layer to serve as end electrodes of the chip-type ceramic electronic component.

[0021] It should be noted that the sheet-shaped lead-out electrode extension section that passes through the insulating encapsulation layer is already useful when it does not need to be bent and formed. The electrode extension section is directly inserted into the soldering socket of the printed circuit board, and then it can be processed and soldered in the traditional way. This installation method is more suitable for certain occasions where the electrical parameter capacity is too large, resulting in oversized components and overweight. It can be connected more firmly and has stronger vibration resistance. At this point, except that it cannot be classified as a surface-mount component, it already has all the other technical features of the present invention. Compared with the parallel use of N independent lead-inserted components, it has the advantages of occupying a smaller installation area and lower cost due to the shared lead-out electrode and insulating encapsulation layer.

[0022] According to a specific embodiment, in the above-mentioned patch-type ceramic electronic component suitable for low-voltage grid voltage, the conductive connection component is in the shape of a cap, and the third and fourth electrode ends of the laminated patch component are respectively inserted into the bottom of the cap of the conductive connection component and welded to the conductive connection component; a gap is left between the inner surface of the raised edge of the cap-shaped conductive connection component and the periphery of the laminated patch component;

[0023] The laminated chip assembly to which the conductive connection assembly is welded is encapsulated using insulating encapsulating material. The encapsulating material should fill the gap and completely wrap the remaining surface of the laminated chip assembly, leaving only the outer surface of the cap-shaped conductive connection assembly exposed as the terminal electrode of the chip-type ceramic electronic component.

[0024] This approach allows the bottom of the cap to double as part of the encapsulation layer, shortening the length of the SMD ceramic electronic component without affecting the size of the built-in multilayer SMD assembly. Filling the gap with insulating encapsulation material prevents the raised edge of the cap-shaped conductive connector from shorting out the built-in multilayer SMD assembly and ensures sufficient dielectric strength. The gap width must be greater than 0.3mm. This ensures only the bottom inner surface of the cap-shaped conductive connector is soldered to the third and fourth electrodes of the multilayer SMD assembly. The raised outer surface of the cap edge represents the copper solder joints for the terminal electrodes to the printed circuit board. This raised outer surface increases the soldering area to the board, improving soldering reliability.

[0025] According to a specific embodiment, in the above-mentioned surface-mount ceramic electronic component suitable for low-voltage grid voltage, the first electrode and the second electrode of the electrode group of the surface-mount electronic ceramic chip are formed in one step using a sputtering process. The thickness of the first electrode and the second electrode is uniform, and the electrode thickness is within the range of 2um to 15um. The nominal thickness error rate does not exceed a preset value, and the preset value range is [-15%, 15%]. The end surface electrode edge of the first electrode is separated from the second side surface by a distance d, and the end surface electrode edge of the second electrode is also separated from the first side surface by a distance d.

[0026] Electrodes manufactured using the sputtering process have the advantages of being non-oxidized, having high material purity, a dense structure, uniform thickness, strong adhesion, and high conductivity. By setting the deposition direction of the electrode particles and the placement angle of the ceramic workpiece, the end face and side face of the electrode can be processed at one time. The conductive connection component only needs to be connected to the side face of the electrode and does not need to extend to the end face. This does not reduce the electrical performance of the electronic component and allows the function of the electronic component to be realized without attenuation. Connecting the conductive connection component only to the side face of the electrode is a necessary condition for implementing the scheme of the present invention, connecting N surface-mount electronic ceramic chips in parallel, and fixing the positions of the N surface-mount electronic ceramic chips.

[0027] Setting the partition d between the electrodes at the edge of the end face of the ceramic body can maximize the effective end face electrode area, thereby maximizing the electrical parameter value of the single-chip surface-mount electronic ceramic chip.

[0028] According to a specific embodiment, in the aforementioned low-voltage grid-compatible chip ceramic electronic component, the stacked chip assembly comprises N chip ceramic chips having the same function. The chip ceramic chips having the same function may be varistor chips; or they may be capacitor chips.

[0029] Electronic components suitable for low-voltage grid voltages typically operate at several hundred volts. Varistor and capacitor chips are typically millimeter-thick in thickness, but ceramic green sheets manufactured using the tape casting method cannot achieve this thickness. Therefore, multi-layer electronic components manufactured using the tape casting method are unsuitable for low-voltage grid voltages. However, traditional pressing and sintering ceramic processes can easily produce millimeter-thick ceramic sheets. Furthermore, when multiple chips with the same function are stacked and connected in parallel, their electrical parameters are exponentially improved compared to single-layer surface-mount components, expanding the application range of surface-mount components in the low-voltage grid voltage range.

[0030] According to a specific embodiment, in the aforementioned low-voltage grid-compatible chip-type ceramic electronic component, the N chip-type electronic ceramic chips in the stacked chip assembly include at least two chip-type electronic ceramic chips with different functions. The chip-type electronic ceramic chips with different functions may include both a varistor chip and a capacitor chip.

[0031] In some applications, it's necessary to connect two or more electronic components with different functions in parallel, such as connecting a varistor and a capacitor in parallel. The present invention can achieve this goal by simply selecting surface-mount electronic ceramic chips with different functions and overlapping and connecting them in parallel. The selected chips must be of the same length so that they can be aligned and then welded to the conductive connection assembly for parallel connection and fixed position. The width is optimally consistent, and the thickness can be different, as long as the performance requirements are met. This allows a single component to be equivalent to two independent components connected in parallel. However, because the conductive connection electrodes and insulating encapsulation layer are shared, the products implemented by the present invention have a smaller installation footprint and lower manufacturing costs.

[0032] According to a specific embodiment, in the above-mentioned SMD ceramic electronic component suitable for low-voltage grid voltage, gaps are left on the overlapping surfaces of the N SMD electronic ceramic chips of the stacked SMD assembly.

[0033] The gap can be formed naturally by exploiting the unevenness of the chip end faces when stacking surface-mount electronic ceramic chips, or by positioning the chips using a specialized fixture during assembly and soldering of the stacked chip assembly. Alternatively, the gap can be formed by applying a soft insulating material such as paraffin wax or silicone rubber to the chip end faces before stacking them. A gap width of less than 0.1 mm is preferred to prevent the overlapping chips from compressing and generating stress when surge absorbers such as varistor chips heat up and expand in size due to a surge, thereby preventing the components from experiencing reduced surge resistance and service life.

[0034] Another aspect of the present invention provides a method for manufacturing the above-mentioned surface-mount ceramic electronic component suitable for low-voltage grid voltage, the method comprising:

[0035] Processing N of the surface-mount electronic ceramic chips, and stacking the N surface-mount electronic ceramic chips on each other to form a laminated surface-mount component;

[0036] Welding the laminated patch component and the conductive connection component together;

[0037] Encapsulating the welded components with an insulating encapsulation material;

[0038] The reserved electrode material extending out of the insulating encapsulation layer is formed into the terminal electrode of the surface-mount ceramic electronic component.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] 1. The stacked chip-type ceramic electronic component provided in an embodiment of the present invention includes N chip-type electronic ceramic chips, all of which are connected in parallel. This can significantly improve electrical parameters compared to single-layer chip-type ceramic electronic components. Because individually fabricated chip-type electronic ceramic chips can be easily made into millimeter-thick ceramic chips, several orders of magnitude thicker than the thickness of a tape-cast ceramic green film, the operating voltage can be increased to several hundred volts. Furthermore, the overlapping surfaces of the stacked chip-type electronic ceramic chips are not connected. When the temperature of the chips rises sharply due to a surge, causing the ceramic body to expand, each chip has room to expand. This eliminates harmful stress caused by compression of the ceramic body, preventing the resulting decrease in surge tolerance and shortened component life. This feature is very important for surge absorption components such as varistors.

[0041] 2. The energy tolerance of the multilayer chip varistor using this technical solution can reach hundreds of joules; therefore, the multilayer chip ceramic electronic component provided by the embodiment of the present invention is very suitable for replacing traditional lead plug-in components and is used in the field of low-voltage power grid voltage.

[0042] 3. The production of electronic ceramic chips is standard parts production. Based on the stacked chip ceramic electronic components provided by the present invention, standard parts can be selected for flexible combination and stacking during production to form electronic components with specified parameters, thereby reducing processing costs.

[0043] 4. In addition, the present invention also provides a solution for connecting SMD electronic ceramic chips with different functions in parallel to form a stacked SMD ceramic electronic component. This is equivalent to connecting two or more independent components with different functions in parallel, but has greater advantages in reducing the installation area and lowering costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] FIG1 is a schematic diagram of a stacked structure of surface-mount ceramic electronic chips according to an exemplary embodiment of the present invention;

[0045] FIG2 is a schematic diagram of a first structure of a surface-mount electronic ceramic chip according to an exemplary embodiment of the present invention;

[0046] FIG3 is a schematic diagram of a first structure of a connection between a surface-mount ceramic electronic chip and a sheet-shaped conductive connection component according to an exemplary embodiment of the present invention;

[0047] FIG4 is a schematic diagram of the structure of the connection between the surface-mount ceramic electronic chip and the lead-out electrode according to an exemplary embodiment of the present invention;

[0048] FIG5 is a schematic structural diagram of an exemplary embodiment of the present invention in which an insulating encapsulation layer encapsulates the components shown in FIG3 and FIG4;

[0049] FIG6 is a schematic structural diagram of a cap-shaped conductive connection assembly according to an exemplary embodiment of the present invention;

[0050] FIG7 is a schematic structural diagram of an exemplary embodiment of the present invention in which an insulating encapsulation layer connects and encapsulates the components shown in FIG6 ;

[0051] FIG8 is a schematic top view of a surface-mount ceramic electronic chip according to an exemplary embodiment of the present invention;

[0052] FIG9 is a second structural diagram of a surface-mount ceramic electronic chip according to an exemplary embodiment of the present invention;

[0053] FIG10 is a schematic diagram of the structure of deposited electrode metal material according to an exemplary embodiment of the present invention;

[0054] Figure numerals: 100 - SMD electronic ceramic chip, 101 - first electrode, 102 - second electrode; 103 - ceramic body, 105 - partition, 200 - conductive connection component, 201 - first lead electrode, 202 - second lead electrode, 203 - end electrode, 300 - insulating encapsulation layer, 400 - laminated chip component. DETAILED DESCRIPTION

[0055] The present invention will be further described in detail below in conjunction with test examples and specific embodiments. However, this should not be understood as limiting the scope of the present invention to the following embodiments, and all technologies implemented based on the present invention fall within the scope of the present invention.

[0056] Example 1

[0057] A surface-mount ceramic electronic component suitable for low-voltage grid voltage, characterized by comprising: N surface-mount electronic ceramic chips 100, a conductive connection component 200, and an insulating encapsulation layer 300; wherein N ≥ 1;

[0058] As shown in FIG. 1 , three (N=3) surface mount electronic ceramic chips 100 are stacked on top of each other to form a stacked surface mount assembly 400 .

[0059] As shown in FIG2 , a surface-mount electronic ceramic chip 100 includes a ceramic body 103 and an electrode group. The ceramic body 103 is rectangular and is disposed on the outer surface of the ceramic body. The electrode group includes a first electrode 101 and a second electrode 102. The ceramic body 103 has upper and lower end surfaces and side surfaces between the upper and lower end surfaces. The side surfaces include at least a first side surface and a second side surface. The first electrode 101 covers a portion of the upper end surface and at least a portion of the first side surface, forming an end surface electrode portion and a side surface electrode portion of the first electrode 101. The second electrode 102 covers a portion of the lower end surface and at least a portion of the second side surface, forming an end surface electrode portion and a side surface electrode portion of the second electrode 102.

[0060] As shown in Figure 1, the overlapping surfaces of the stacked chip assembly are the end surfaces of the chip-type electronic ceramic chips 100. The chip-type electronic ceramic chips 100 are stacked symmetrically with the adjacent end surface electrodes on the overlapping surfaces. The third electrode of the stacked chip assembly is formed by the side electrodes on the same side of the three stacked chip-type electronic ceramic chips 100, and the fourth electrode of the stacked chip assembly is formed by the side electrodes on the other side of the three stacked chip-type electronic ceramic chips 100.

[0061] The three chip-type electronic ceramic chips 100 that make up the stacked chip assembly can all be varistor chips, or all be capacitor chips, or have both varistor chips and capacitor chips. The lengths of the chips must be consistent so that they can be overlapped and aligned and then welded in parallel with the conductive connection components to fix their positions. It is best to keep the width consistent, and the thickness can be different, as long as the respective electrical performance requirements are met. Depending on the different voltages of the low-voltage power grid in the application scenario, the thickness of a single chip of the chip-type electronic ceramic chip 100 is between 0.5mm and 5mm.

[0062] As shown in Figures 3 and 4, the conductive connection component 200 is connected to the third and fourth electrodes of the stacked chip assembly. The conductive connection component includes a first lead-out electrode 201 and a second lead-out electrode 202. The first lead-out electrode 201 is welded to the third electrode of the stacked chip assembly 400, and the second lead-out electrode 202 is welded to the fourth electrode of the stacked chip assembly 400. This connects the three chip-type electronic ceramic chips 100 in parallel and secures their positions. After securing, a gap remains between the overlapping surfaces of the chips. This gap is formed naturally when the chip-type electronic ceramic chips 100 are stacked, taking advantage of the unevenness of the chip end surfaces.

[0063] The laminated chip assembly with the sheet-shaped lead electrodes welded thereto is encapsulated with a hot injection insulating material to form an insulating encapsulation layer 300 , and the first lead electrode 201 and the second lead electrode 202 are respectively extended out of the insulating encapsulation layer for a section to form an end electrode 203 .

[0064] As shown in Figure 5 , the extension of the first lead electrode 201 extending from the insulating encapsulation layer and the extension of the second lead electrode 202 extending from the insulating encapsulation layer 300 are bent and formed close to the outer surface of the insulating encapsulation layer to serve as the terminal electrodes of the chip-type ceramic electronic component. The sheet-shaped lead electrodes 201 and 202 are made of copper, but can also be made of other easily solderable conductive metals or alloys.

[0065] Example 2

[0066] A surface-mount ceramic electronic component suitable for low-voltage grid voltage, characterized by comprising: N surface-mount electronic ceramic chips 100, a conductive connection component 200, and an insulating encapsulation layer 300; wherein N ≥ 1;

[0067] As shown in FIG1 , three (N=3) surface-mount electronic ceramic chips 100 are stacked on top of each other to form a stacked surface-mount component.

[0068] As shown in FIG2 , a surface-mount electronic ceramic chip 100 includes a ceramic body 103 and an electrode group. The ceramic body 103 is rectangular and is disposed on the outer surface of the ceramic body. The electrode group includes a first electrode 101 and a second electrode 102. The ceramic body 103 has upper and lower end surfaces and side surfaces between the upper and lower end surfaces. The side surfaces include at least a first side surface and a second side surface. The first electrode 101 covers a portion of the upper end surface and at least a portion of the first side surface, forming an end surface electrode portion and a side surface electrode portion of the first electrode 101. The second electrode 102 covers a portion of the lower end surface and at least a portion of the second side surface, forming an end surface electrode portion and a side surface electrode portion of the second electrode 102.

[0069] As shown in Figure 1, the overlapping surfaces of the stacked chip assembly are the end surfaces of the chip-type electronic ceramic chips 100. The chip-type electronic ceramic chips 100 are stacked symmetrically with the adjacent end surface electrodes on the overlapping surfaces. The third electrode of the stacked chip assembly is formed by the side electrodes on the same side of the three stacked chip-type electronic ceramic chips 100, and the fourth electrode of the stacked chip assembly is formed by the side electrodes on the other side of the three stacked chip-type electronic ceramic chips 100.

[0070] The three chip-type electronic ceramic chips 100 that make up the stacked chip assembly can all be varistor chips, or all be capacitor chips, or have both varistor chips and capacitor chips. The lengths of the chips must be consistent so that they can be overlapped and aligned and then welded in parallel with the conductive connection components to fix their positions. It is best to keep the width consistent, and the thickness can be different, as long as the respective electrical performance requirements are met. Depending on the different voltages of the low-voltage power grid in the application scenario, the thickness of a single chip of the chip-type electronic ceramic chip 100 is between 0.5mm and 5mm.

[0071] The conductive connection assembly is connected to the third and fourth electrodes of the laminated patch assembly. As shown in FIG6 , the conductive connection assembly 200 is in the shape of a cap and is stamped from a thin copper sheet. It can also be made from other easily solderable conductive metals or alloys. In this embodiment, the cap thickness is 0.3 mm. The third and fourth electrode ends of the laminated patch assembly 400 are respectively inserted into the bottom of the cap of the conductive connection assembly and welded to the conductive connection assembly, connecting the three patch-type electronic ceramic chips 100 in parallel and fixing the positions of the three patch-type electronic ceramic chips 100. A gap is left on the overlapping surfaces of the fixed chips. The gap is naturally formed by utilizing the unevenness of the chip end faces when the patch-type electronic ceramic chips 100 are stacked. A gap is left between the inner surface of the raised edge of the cap-shaped conductive connection assembly and the periphery of the laminated patch assembly. In this embodiment, the gap width is 0.7 mm.

[0072] As shown in FIG7 , the laminated chip assembly to which the conductive connection assembly is welded is encapsulated using a hot injection molding insulating material. The hot-melt liquid encapsulating material fills the gap and completely wraps the remaining surface of the laminated chip assembly, leaving only the outer surface of the cap-shaped conductive connection assembly exposed as the terminal electrode of the chip-type ceramic electronic component.

[0073] This approach allows the bottom of the cap to double as part of the encapsulation layer, shortening the length of the SMD ceramic electronic component without affecting the size of the built-in multilayer SMD assembly. Filling the gap with insulating encapsulation material prevents short circuits between the raised edge of the cap-shaped conductive connector and the built-in multilayer SMD assembly, while ensuring sufficient dielectric strength. This ensures only the bottom inner surface of the cap-shaped conductive connector is welded to the third and fourth electrodes of the multilayer SMD assembly. The raised outer surface of the cap edge represents the terminal electrode solder joint to the copper foil of the printed circuit board. This raised outer surface increases the soldering area to the circuit board, improving soldering reliability.

[0074] Example 3

[0075] As shown in Figures 8 and 9, a surface-mount electronic ceramic chip 100 includes: a ceramic body 103 and an electrode group, wherein the ceramic body 103 is rectangular; the electrode group is arranged on the outer surface of the ceramic body, and the electrode group includes: a first electrode 101 and a second electrode 102; the ceramic body 103 has upper and lower end faces and side faces between the upper and lower end faces, wherein the side faces include at least a first side face and a second side face, and the first electrode 101 covers a portion of the upper end face and at least a portion of the first side face, forming an end face electrode portion and a side face electrode portion of the first electrode 101. The second electrode 102 covers a portion of the lower end face and at least a portion of the second side face, forming an end face electrode portion and a side face electrode portion of the second electrode 102;

[0076] The first and second electrodes of the surface-mount electronic ceramic chip 100 are formed in a single process using a sputtering process. The sputtering target is copper, but other easily weldable metals or alloys can also be used. The thickness of the first and second electrodes 101, 102 is uniform, ranging from 2 to 15 microns, with a nominal thickness error rate not exceeding a preset value within the range of [-15% to 15%]. A gap 105 (length d) is left between the end face of the first electrode 101 and the second side surface, and a gap d is also left between the end face of the second electrode 102 and the first side surface.

[0077] The electrodes manufactured by the sputtering process have the advantages of no oxidation, high material purity, dense structure, uniform thickness, strong adhesion, and high conductivity. By setting the electrode atomic deposition direction and the placement angle of the ceramic workpiece, as shown in Figure 10, the end face and side face of the electrode can be processed at one time. At the corners of the end face and side face of the ceramic body, the chamfers can be smoothly transitioned to make the electrode thickness at the corners more uniform. The conductive connection component only needs to be connected to the side part of the electrode and does not need to extend to the end face part. It will not reduce the electrical performance of the electronic component and can realize the function of the electronic component without attenuation. Connecting the conductive connection component only to the side part of the electrode is a necessary condition for implementing the scheme of the present invention, connecting N patch-type electronic ceramic chips 100 in parallel, and fixing the positions of the N patch-type electronic ceramic chips 100.

[0078] Setting the partition d between the electrodes at the edge of the end surface of the ceramic body can maximize the effective end surface electrode area, thereby maximizing the electrical parameter value of the single-chip surface-mount electronic ceramic chip 100.

[0079] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip-type ceramic electronic component suitable for low-voltage grid voltage, characterized in that: include: N surface-mount electronic ceramic chips (100), a conductive connection component (200) and an insulating encapsulation layer (300); wherein N≥1; N patch-type electronic ceramic chips (100) are stacked on top of each other to form a laminated patch assembly (400), the laminated patch assembly (400) is fixedly connected to a conductive connection assembly (200), and the insulating encapsulation layer (300) is used to encapsulate the fixedly connected assembly; The surface-mount electronic ceramic chip (100) comprises: a ceramic body and an electrode group, wherein the electrode group is arranged on the outer surface of the ceramic body, and the electrode group comprises: a first electrode (101) and a second electrode (102); the ceramic body (103) has an upper and lower end surface and a side surface between the upper and lower end surfaces, wherein the side surface comprises at least a first side surface and a second side surface, and the first electrode (101) covers a portion of the upper end surface and at least a portion of the first side surface, forming an end surface electrode portion and a side surface electrode portion of the first electrode; the second electrode (102) covers a portion of the lower end surface and at least a portion of the second side surface, forming an end surface electrode portion and a side surface electrode portion of the second electrode; The overlapping surface of the laminated patch component is the end surface of the patch-type electronic ceramic chip (100), and the patch-type electronic ceramic chips (100) are stacked and arranged according to the symmetrical relationship between the end surface electrodes adjacent to the overlapping surface; the laminated patch component comprises: a third electrode and a fourth electrode, the third electrode being jointly formed by N side electrodes on the same side of the stacked N patch-type electronic ceramic chips (100), and the fourth electrode being jointly formed by N side electrodes on the other side of the stacked N patch-type electronic ceramic chips (100); the conductive connection component (200) is connected to the third and fourth electrodes to realize parallel connection of the N patch-type electronic ceramic chips (100) and to fix the positions of the N patch-type electronic ceramic chips (100); The insulating encapsulating layer (300) is used to encapsulate the laminated patch assembly (400) and part of the conductive connection assembly (200), and the remaining unencapsulated part of the conductive connection assembly (200) is a terminal electrode.

2. The chip-type ceramic electronic component suitable for low-voltage grid voltage according to claim 1, characterized in that: The conductive connection assembly comprises: a first lead-out electrode (201) and a second lead-out electrode (202); The first lead electrode (201) is connected to the third electrode of the stacked patch assembly (400) by welding, and the second lead electrode (202) is connected to the fourth electrode of the stacked patch assembly (400) by welding; The insulating encapsulating layer (300) encapsulates the stacked patch assembly after the lead electrodes are welded, and the first lead electrode (201) and the second lead electrode (202) are respectively extended out of a portion of the insulating encapsulating layer (300) to form the terminal electrode (203).

3. The surface-mount ceramic electronic component suitable for low-voltage grid voltage according to claim 2, characterized in that: The first lead electrode (201) and the second lead electrode (202) are sheet electrodes, extending out of an extension section of the insulating encapsulating layer (300), being bent and shaped closely against a surface of the insulating encapsulating layer (300), and serving as terminal electrodes (203) of the surface-mount ceramic electronic component.

4. The surface-mount ceramic electronic component suitable for low-voltage grid voltage according to claim 1, characterized in that: The conductive connection component (200) is in the shape of a cap, and the third and fourth electrode ends of the laminated patch component (400) are respectively inserted into the bottom of the cap of the conductive connection component (200) and are welded to the conductive connection component; a gap is left between the inner surface of the raised edge of the cap-shaped conductive connection component and the periphery of the laminated patch component; The insulating encapsulation layer (300) encapsulates the laminated patch component (400) to which the conductive connection component (200) is welded, and the encapsulation material fills the gap and completely encapsulates the remaining surface of the laminated patch component (400), leaving only the outer surface of the cap-shaped conductive connection component exposed to the outside, serving as the terminal electrode (203) of the patch-type ceramic electronic component.

5. The chip-type ceramic electronic component suitable for low-voltage grid voltage according to claim 1, characterized in that: The electrode group includes the first electrode (101) and the second electrode (102) which are formed by one-step processing using a sputtering process; the thickness of the first electrode (101) and the second electrode (102) are uniform, the electrode thickness is within the range of 2um to 15um, and the nominal thickness error rate does not exceed a preset value, and the preset value range is [-15%, 15%]; A distance d is left between the end surface electrode edge of the first electrode (101) and the second side surface, and a distance d is also left between the end surface electrode edge of the second electrode (102) and the first side surface.

6. The surface-mount ceramic electronic component suitable for low-voltage grid voltage according to any one of claims 1 to 4, characterized in that: The laminated patch assembly (400) is composed of N patch-type electronic ceramic chips (100) having the same function.

7. The chip-type ceramic electronic component suitable for low-voltage grid voltage according to claim 6, characterized in that: The SMD electronic ceramic chip (100) having the same function is a varistor chip.

8. The surface-mount ceramic electronic component suitable for low-voltage grid voltage according to claim 6, characterized in that: The surface-mount electronic ceramic chip (100) having the same function is a capacitor chip.

9. The surface-mount ceramic electronic component suitable for low-voltage grid voltage according to any one of claims 1 to 4, characterized in that: The N SMD electronic ceramic chips (100) of the stacked SMD component include at least two SMD electronic ceramic chips (100) with different functions.

10. The chip-type ceramic electronic component suitable for low-voltage grid voltage according to claim 9, characterized in that: The two surface-mount electronic ceramic chips (100) with different functions are a varistor chip and a capacitor chip.

11. The chip-type ceramic electronic component suitable for low-voltage grid voltage according to any one of claims 1 to 10, characterized in that: Gaps are left on the overlapping surfaces of the N surface-mount electronic ceramic chips (100) of the stacked surface-mount assembly (400).

12. A method for manufacturing a surface-mount ceramic electronic component suitable for low-voltage grid voltage as claimed in any one of claims 1 to 11, characterized in that: The method comprises: Processing N of the surface mount electronic ceramic chips (100), and stacking the N surface mount electronic ceramic chips (100) on top of each other to form a laminated surface mount assembly (400); Welding the laminated patch assembly (400) and the conductive connection assembly (200) together; Using an insulating encapsulation material to encapsulate the welded components to form an insulating encapsulation layer (300); The reserved electrode extending out of the insulating encapsulation layer (300) is formed into a terminal electrode of a patch-type ceramic electronic component.

Images