Semiconductor structure, ranging sensor chip and operation method, and device

Abstract

The embodiments of the present application relate to the technical field of electronics. Provided are a semiconductor structure, a ranging sensor chip and an operation method, and a device, which are used for optimizing the performance of ranging sensor chips. The characteristics of on-chip integration and non-volatility of a non-volatile memory are used, and the solution of an on-chip volatile memory being combined with an external non-volatile memory in a conventional ranging sensor chip is replaced with the solution of a non-volatile memory being integrated in a ranging sensor chip, so as to use the non-volatile memory to meet storage requirements of a processor and functional circuits in the ranging sensor chip. Many beneficial functions, e.g., simplifying an architecture, reducing the area, reducing a delay and simplifying a solution of single-board hardware, are implemented.

Description

Semiconductor structure, ranging sensor chip, working method and equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 11, 2023, with application number 202311173994.2 and application name “Semiconductor structure, ranging sensor chip and working method and equipment”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a semiconductor structure, a ranging sensor chip, and a working method and device. Background Art

[0003] A ranging sensor can measure the distance between an object and the sensor. For example, a time-of-flight (ToF) sensor uses optical principles to measure distance. A ToF sensor uses a tiny laser to emit infrared light. The light bounces off any object and returns to the ToF sensor. Based on the time difference between the light being emitted and the light being reflected by the object and returning to the ToF sensor, the ToF sensor can measure the distance between the object and the sensor.

[0004] ToF sensors can be widely used in devices that need to detect distance, and the performance of ToF sensors directly affects the performance of the devices.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a semiconductor structure, a ranging sensor chip, and a working method and device for optimizing the performance of the ranging sensor chip.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] In a first aspect of an embodiment of the present application, a semiconductor structure is provided for use in a ranging sensor chip including a photoelectric conversion module. The semiconductor structure can be a bare chip or a packaged chip. The semiconductor structure includes a non-volatile memory, an analog front end, and a processor. The non-volatile memory is used to store software code; the analog front end is used to couple with the photoelectric conversion module, receive the electrical signal output by the photoelectric conversion module, process the electrical signal, and output it; the processor is coupled to the non-volatile memory and the analog front end, and is used to read the software code, process the signal output by the analog front end, and generate distance data.

[0009] The semiconductor structure provided by the embodiment of the present application has a non-volatile memory integrated inside. The software code required for the semiconductor structure to perform processing operations is directly stored in the non-volatile memory inside the semiconductor structure, and is no longer stored in an external non-volatile memory. In this way, when the semiconductor structure performs processing operations, the processor can directly retrieve the software code from the non-volatile memory without having to go through the process of loading from the external non-volatile memory to the internal volatile memory, so that the startup speed of the semiconductor structure is fast, the workflow is simple, and the delay of the semiconductor structure can be reduced. Moreover, by utilizing the characteristics of the non-volatile memory being integrated on-chip and non-volatile, it replaces the external non-volatile memory required by the traditional semiconductor structure, which can streamline the architecture of the semiconductor structure, save area, and simplify the hardware single-board solution.

[0010] In a possible implementation, the volatile memory is further configured to store curing parameters representing identity information of the semiconductor structure; and the processor is further configured to read and / or write the curing parameters.

[0011] Using non-volatile memory to implement the functionality of a one-time programmable memory reduces the possibility of data being decrypted through reverse microscopic observation, thereby increasing the security of the semiconductor structure. Furthermore, by replacing one-time programmable memory with non-volatile memory, the semiconductor structure no longer needs to have one-time programmable memory, reducing the number of memory types required and simplifying the semiconductor structure's fabrication process and layout.

[0012] In one possible implementation, the semiconductor structure further includes a statistical analysis circuit configured to perform statistical analysis on the signal output by the analog front end and output the result to the processor. By performing preliminary statistical analysis on the signal output by the analog front end using the hardware statistical analysis circuit and then transmitting the result to the processor for processing, the accuracy and efficiency of the processor can be improved.

[0013] In one possible implementation, the semiconductor structure further includes a statistical analysis circuit coupled between the analog front end and the processor. The hardware statistical analysis circuit performs preliminary statistical analysis on the analog front end output signal and then transmits the result to the processor for processing, thereby improving the accuracy and efficiency of the processor.

[0014] In one possible implementation, the statistical analysis circuit includes a statistical circuit, a compensation circuit, a low-pass filter circuit, a noise calculation circuit, an echo detection circuit, and an echo analysis circuit. The statistical circuit is configured to statistically process the signal output by the analog front end and output it. The compensation circuit is configured to compensate the received signal and output it. The low-pass filter circuit is configured to filter out noise from the received signal and output it. The noise calculation circuit is configured to calculate and output the noise from the received signal. The echo detection circuit is configured to detect and output peak information of the received signal. The echo analysis circuit is configured to analyze the received signal and output the analysis results to a processor. This statistical analysis circuit has a simple structure and high accuracy.

[0015] In one possible implementation, the statistical analysis circuit includes a statistical circuit, a compensation circuit, a low-pass filter circuit, a noise calculation circuit, an echo detection circuit, and an echo analysis circuit. The statistical circuit is coupled to an analog front end; the compensation circuit is coupled to the statistical circuit; the low-pass filter circuit is coupled to the compensation circuit; the noise calculation circuit is coupled to the low-pass filter circuit; the echo detection circuit is coupled to the noise calculation circuit; and the echo analysis circuit is coupled to the echo detection circuit and a processor. This statistical analysis circuit has a simple structure and high accuracy.

[0016] In one possible implementation, at least one of the statistical circuit, the low-pass filter circuit, and the echo detection circuit is further coupled to a non-volatile memory. Using the non-volatile memory to provide storage for the statistical analysis circuit eliminates the need for static random access memory (SRAM) in the semiconductor structure, reduces the number of memory types, simplifies the semiconductor structure's fabrication process and layout, and reduces the area and power consumption of the semiconductor structure.

[0017] In one possible implementation, the semiconductor structure further includes volatile memory; and at least one of the statistical circuit, the low-pass filter circuit, the echo detection circuit, and the processor is further coupled to the volatile memory. Using the volatile memory to provide storage for the statistical analysis circuit can improve the access speed of the statistical analysis circuit.

[0018] In one possible implementation, the semiconductor structure further includes an input / output interface coupled to the non-volatile memory for writing to or reading from the outside of the semiconductor structure. In this way, data stored in the external memory can be transferred to the non-volatile memory via the input / output interface to meet different needs.

[0019] In one possible implementation, the non-volatile memory includes one or more of a flash memory, a magnetoresistive random access memory, a resistive random access memory, a phase-change random access memory, and a ferroelectric memory. This is an implementation with a simple structure.

[0020] According to a second aspect of an embodiment of the present application, a ranging sensor chip is provided, comprising a semiconductor structure and a photoelectric conversion module; the semiconductor structure is coupled to the photoelectric conversion module; and the semiconductor structure comprises any one of the semiconductor structures of the first aspect.

[0021] The ranging sensor chip provided in the second aspect of the embodiment of the present application includes the semiconductor structure in the first aspect, and its beneficial effects are the same as those of the semiconductor structure, which will not be repeated here.

[0022] According to a third aspect of the embodiments of the present application, a device is provided, including a ranging sensor chip and a controller, wherein the ranging sensor chip is coupled to the controller; the ranging sensor chip includes the ranging sensor chip according to the second aspect.

[0023] The device provided in the third aspect of the embodiment of the present application includes the semiconductor structure of the first aspect, and its beneficial effects are the same as those of the semiconductor structure, which will not be repeated here.

[0024] According to a fourth aspect of an embodiment of the present application, a method for operating a ranging sensor chip is provided. The ranging sensor chip includes a semiconductor structure and a photoelectric conversion module; the semiconductor structure includes a non-volatile memory, an analog front end, and a processor. The method includes: the analog front end receives an electrical signal output by the photoelectric conversion module, processes the electrical signal, and outputs the signal; the processor directly reads software code from the non-volatile memory, processes the signal output by the analog front end, and generates distance data.

[0025] In the operating method of the ranging sensor chip provided in the embodiments of the present application, the software code required for the processor to perform processing operations is stored directly in the non-volatile memory within the semiconductor structure, rather than in an external non-volatile memory. This allows the processor to retrieve the software code directly from the non-volatile memory when the semiconductor structure performs processing operations, eliminating the need to load the code from the external non-volatile memory into the internal volatile memory. This results in a fast startup speed for the ranging sensor chip, a simple workflow, and reduced latency in the semiconductor structure.

[0026] In a possible implementation, the working method further includes: at the power-on startup moment, the processor directly reads the curing parameters representing the identity information of the semiconductor structure from the non-volatile memory.

[0027] The fixed parameters required for the ranging sensor chip to start up are stored directly in the non-volatile memory within the semiconductor structure, rather than in external non-volatile memory. This allows the ranging sensor chip to retrieve the fixed parameters directly from its internal non-volatile memory during power-up, eliminating the need to load the fixed parameters from external non-volatile memory into internal volatile memory. This results in fast startup and a simple workflow, reducing latency within the ranging sensor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is an appearance diagram of a device provided in an embodiment of the present application;

[0029] FIG2 is a schematic structural diagram of a ranging sensor chip according to an embodiment of the present application;

[0030] 3A-3C are topological diagrams of a semiconductor structure provided in an embodiment of the present application;

[0031] FIG4 is a diagram showing the relationship between a circuit in a semiconductor structure and a non-volatile memory according to an embodiment of the present application;

[0032] FIG5 is a diagram showing the relationship between a circuit in another semiconductor structure and a non-volatile memory according to an embodiment of the present application;

[0033] FIG6 is a diagram showing the relationship between a circuit in another semiconductor structure and a non-volatile memory according to an embodiment of the present application;

[0034] FIG7 is a diagram showing the relationship between a circuit in another semiconductor structure and a non-volatile memory according to an embodiment of the present application;

[0035] FIG8 is a diagram showing the relationship between a circuit in another semiconductor structure and a non-volatile memory according to an embodiment of the present application;

[0036] FIG9 is a diagram showing the relationship between a circuit in another semiconductor structure and a non-volatile memory according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0038] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc., may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0039] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative descriptions and clarifications, and may change accordingly according to changes in the orientation of the components in the drawings.

[0040] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "coupling" can mean direct electrical connection or indirect electrical connection through an intermediate medium. The term "contact" can mean direct contact or indirect contact through an intermediate medium.

[0041] In the embodiments of the present application, "and / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0042] The embodiments of the present application provide a device, which is, for example, a consumer electronic product, a home electronic product, an in-vehicle electronic product, etc. with a ranging requirement. Among them, consumer electronic products include mobile phones, tablet computers (pads), laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, drones, etc. Home electronic products include smart door locks, rechargeable small household appliances (for example, sweeping robots), etc. In-vehicle electronic products include in-vehicle navigation systems, cars, etc. The embodiments of the present application do not impose any special restrictions on the specific forms of the above-mentioned devices.

[0043] FIG1 is an appearance diagram of a device provided in an embodiment of the present application.

[0044] In some embodiments, as shown in FIG1 , the embodiments of the present application are illustrated by taking device 1 as an example of a vehicle. Of course, the embodiments of the present application are not limited to device 1 being a vehicle; device 1 can be any device with a ranging requirement, and device 1 includes the ranging sensor chip provided in the embodiments of the present application.

[0045] For example, a vehicle may include a ranging sensor chip 10 and a controller 40. The ranging sensor chip 10 is used to generate distance data and transmit the distance data to the controller 40 for corresponding control processing. For example, the ranging sensor chip 10 detects the distance data, and the controller 40 performs control processing, which, in combination with other components in the vehicle, can achieve autonomous driving of the vehicle.

[0046] Of course, the vehicle can be a fuel vehicle, a new energy vehicle, or a hybrid vehicle.

[0047] The ranging sensor chip 10 may include, for example, a time-of-flight (ToF) sensor. Laser-emitted light pulses are reflected by an object and then received by the ranging sensor chip 10. The distance between the object and the ranging sensor chip 10 is determined by calculating the time of flight of the light. The controller 40 may include, for example, a microcontroller unit (MCU) of the device 1.

[0048] The ranging sensor chip 10 can measure the distance between an object and the ranging sensor. Through the ranging sensor chip 10, mobile phones can realize functions such as facial payment and electronic banking, and drones, VR, AR, sweeping robots, and cars can realize functions such as obstacle avoidance.

[0049] FIG2 is a schematic structural diagram of a distance measuring sensor chip according to an embodiment of the present application.

[0050] In some embodiments, as shown in FIG2 , a distance measurement sensor chip 10 includes a pixel photosensitive area and a circuit logic area. The pixel photosensitive area includes a pixel die, and the circuit logic area includes a logic die. The pixel die can convert optical signals into electrical signals, and the logic die processes and calculates the electrical signals to obtain corresponding distance data, which can be transmitted to the next-level chip (e.g., a microcontroller MCU coupled thereto).

[0051] The logic wafer includes an analog front end (AFE), a histogram statistics circuit 21′, a differential nonlinearity (DNL) compensation circuit 22′, a low-pass filter circuit 23, an echo detection circuit 24, an echo analysis circuit 25, a noise calculation circuit 27, a processor 26, a first static random access memory (SRAM) SRAM1, a second static random access memory SRAM2, a third static random access memory SRAM3, a fourth static random access memory SRAM4, and a one-time programmable memory (OTP).

[0052] The analog front end (AFE) receives the electrical signal output by the pixel chip. The signal flows sequentially through the AFE, histogram statistics circuit 21', DNL compensation circuit 22', low-pass filter circuit 23, noise calculation circuit 27, echo detection circuit 24, echo analysis circuit 25, and processor 26. Processor 26 outputs distance data. For example, processor 26 transmits the distance output to the microcontroller MCU.

[0053] The histogram statistics circuit 21′ is also coupled to a first static random access memory (SRAM1), which is used to store the signal output by the histogram statistics circuit 21′. The low-pass filter circuit 23 and the echo detection circuit 24 are also coupled to a second static random access memory (SRAM2), which is used to store the signal output by the low-pass filter circuit 23. The echo detection circuit 24 is used to read the signal from the second static random access memory (SRAM2).

[0054] The processor 26 is also coupled to a third static random access memory (SRAM3), a fourth static random access memory (SRAM4), and a one-time programmable memory (OTP). The third static random access memory (SRAM3) is used to store the software code required by the processor 26 for processing operations. The third static random access memory (SRAM3) is also connected to a non-volatile memory (NVM) external to the ranging sensor chip 10. After the ranging sensor chip 10 is powered on, the non-volatile memory transfers the software code to the third static random access memory (SRAM3). The fourth static random access memory (SRAM4) is used to store signals output by the processor 26, and the one-time programmable memory (OTP) is used to store hardened parameters that represent the identity information of the ranging sensor chip 10.

[0055] Taking the ranging sensor chip shown in FIG2 as an example, the ranging sensor chip can be roughly divided into three parts.

[0056] The first part is the process of powering on the ranging sensor chip, during which the processor 26 reads the software code to put the ranging sensor chip into working state.

[0057] The second part is that the ranging sensor chip receives the electrical signal output by the pixel wafer, and after a series of data processing, outputs it to the microcontroller MCU.

[0058] The third part stores some fixed parameters that characterize the identity information of the ranging sensor chip.

[0059] From the perspective of data storage, the storage function involved in the ranging sensor chip is provided by the volatile memory inside the ranging sensor chip and the non-volatile memory outside the ranging sensor chip.

[0060] Among them, according to whether the stored signal in the memory still exists after the external power supply of the chip is removed, the memory can be divided into volatile memory and non-volatile memory.

[0061] Volatile memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM), requires a continuous external power supply to store information. When the external power supply is depleted, the stored information disappears. Figure 2 illustrates an example in which the volatile memory included in the ranging sensor chip 10 is SRAM.

[0062] The non-volatile memory does not lose the information stored in the non-volatile memory when the external power is off. The non-volatile memory included in the ranging sensor chip 10 in FIG2 is a serial peripheral interface flash memory (SPI flash) as an example for illustration.

[0063] In other words, from a data storage perspective, the ranging sensor chip 10 involves two parts of data storage. One part is the external SPI flash memory outside the ranging sensor chip 10, which is a non-volatile memory used to store data that needs to be preserved during power outages. The other part is the internal SRAM and one-time programmable memory (OTP) of the ranging sensor chip 10, which are volatile memories. The SRAM is responsible for reading data from the SPI flash memory, participating in data processing, and serving as a cache. The OTP memory is used to store fixed parameters. The OTP memory can be, for example, an electronic fuse (eFuse) or an anti-electronic fuse (antifuse).

[0064] While the ranging sensor chip 10 shown in FIG2 can measure the distance of an object, it requires an external non-volatile memory (e.g., a serial peripheral interface flash memory (SPI)) to store data when the ranging sensor chip 10 is powered off (e.g., software code required for the ranging sensor chip 10 to start up, software code required for the ranging sensor chip 10 to process data, etc.). This increases the number of pads on the ranging sensor chip 10 and the complexity of the single-board solution. Furthermore, because the software code required for the ranging sensor chip 10 to start up and for the processor 26 to operate is stored in the external non-volatile memory, the ranging sensor chip 10 must first load the startup data and processed data from the external non-volatile memory into the internal volatile memory and then transfer it to the processor 26 before it can begin processing and complete the power-on startup process. This results in a long startup time for the ranging sensor chip 10 and a complex workflow. In addition, the ranging sensor chip 10 integrates multiple volatile memories (e.g., a first static random access memory SRAM1, a second static random access memory SRAM2, a third static random access memory SRAM3, and a fourth static random access memory SRAM4). Using large-capacity static random access memory SRAMs for on-chip storage increases the area of ​​the ranging sensor chip 10. Furthermore, volatile memories require continuous power to store data, resulting in high power consumption for the ranging sensor chip 10. Furthermore, the one-time programmable memory (OTP) writes data by breaking down transistors, which can be cracked under a microscope, resulting in low security for the ranging sensor chip 10. Optimizing any of these issues can improve the performance of the ranging sensor chip 10.

[0065] Based on this, an embodiment of the present application provides a ranging sensor chip 10 , which removes the serial peripheral interface flash memory SPI flash coupled to the third static random access memory SRAM3 , so as to optimize the performance of the ranging sensor chip 10 .

[0066] FIG3A is a topological schematic diagram of a semiconductor structure provided in an embodiment of the present application.

[0067] An embodiment of the present application provides a semiconductor structure. The semiconductor structure can be applied to the ranging sensor chip 10 provided in the embodiment of the present application. The semiconductor structure is coupled to the photoelectric conversion module in the ranging sensor chip 10.

[0068] As shown in FIG. 3A , the semiconductor structure 20 includes a non-volatile memory NVM, an analog front end AFE, and a processor 26 .

[0069] The analog front end AFE is used to couple with the photoelectric conversion module 30 , receive the electrical signal output by the photoelectric conversion module 30 , and process the electrical signal before outputting it.

[0070] The analog front end AFE processes the electrical signal, including converting the electrical signal (analog signal) into a digital signal and adding a timestamp to the digital signal, which is referred to as a timestamp digital signal in the embodiment of the present application.

[0071] The non-volatile memory NVM is used to store software codes, including, for example, software codes required for the processor 26 to perform calculations.

[0072] The processor 26 is coupled to the analog front end AFE and the non-volatile memory NVM, and is used to read the software code in the non-volatile memory NVM, receive the timestamp digital signal output by the analog front end AFE, process the timestamp digital signal according to the software code, and generate distance data.

[0073] The processor 26 includes, for example, one or more of a central processing unit (CPU), an arithmetic and logic unit (ALU), or a microcontroller MCU.

[0074] That is, the software codes required for the semiconductor structure 20 to perform computational processing are no longer stored in an external non-volatile memory coupled to the semiconductor structure 20 , but are directly stored in the non-volatile memory NVM within the semiconductor structure 20 .

[0075] It should be noted that the embodiments of the present application do not limit the semiconductor structure 20 to not having any volatile memory integrated therein. The structure of the semiconductor structure 20 may be such that only non-volatile memory NVM is integrated therein, or the structure of the semiconductor structure 20 may be such that non-volatile memory NVM and other non-volatile memory are integrated therein, or the structure of the semiconductor structure 20 may be such that non-volatile memory NVM and volatile memory are integrated therein. As long as the semiconductor structure 20 has non-volatile memory NVM integrated therein, it falls within the scope of protection of the semiconductor structure 20 provided by the embodiments of the present application.

[0076] The semiconductor structure 20 provided in the embodiment of the present application has a non-volatile memory NVM integrated inside. The software code required for the semiconductor structure 20 to perform processing operations is directly stored in the non-volatile memory NVM inside the semiconductor structure 20, and is no longer stored in an external non-volatile memory. In this way, when the semiconductor structure 20 performs processing operations, the processor 26 can directly retrieve the software code from the non-volatile memory NVM without having to go through the process of loading from the external non-volatile memory to the internal volatile memory. The startup speed of the semiconductor structure 20 is fast, the workflow is simple, and the delay of the semiconductor structure 20 can be reduced. Moreover, by utilizing the characteristics of the non-volatile memory NVM being integrated on the chip and non-volatile, it replaces the external non-volatile memory required by the traditional semiconductor structure 20, which can streamline the architecture of the semiconductor structure 20, save area, and simplify the hardware single-board solution.

[0077] In some embodiments, the volatile memory NVM is further used to store curing parameters representing identity information of the semiconductor structure 20 , and the processor 26 is further used to read and / or write the curing parameters.

[0078] In other words, the curing parameters are no longer stored in the one-time programmable memory (OTP), but directly in the volatile memory (NVM). By performing a special curing process on the non-volatile memory (NVM), the non-volatile memory (NVM) can be made one-time programmable.

[0079] In this way, using non-volatile memory NVM to implement the functionality of the one-time programmable memory (OTP) reduces the possibility of data in the memory being decrypted through reverse observation using microscopes such as scanning electron microscopes (SEM) and transmission electron microscopes (TEM), thereby increasing the security of the semiconductor structure 20. Furthermore, by using non-volatile memory NVM instead of the one-time programmable memory (OTP), the semiconductor structure 20 no longer needs to include the one-time programmable memory (OTP), reducing the number of memory types in the semiconductor structure 20 and simplifying the manufacturing process and layout of the semiconductor structure 20.

[0080] In some embodiments, please refer to Figure 3A, the semiconductor structure 20, in addition to including a processor 26, a non-volatile memory NMV, and an analog front end AFE, also includes a statistical analysis circuit 28. The statistical analysis circuit 28 is used to perform statistical analysis on the signal output by the analog front end AFE and output the processing result to the processor 26.

[0081] For example, the statistical analysis circuit 28 is coupled between the analog front end AFE and the processor 26. The structure of the statistical analysis circuit 28 is, for example, constructed by a hardware circuit structure.

[0082] It should be noted that in the embodiment of the present application, "A is coupled between B and C" means that A is located between B and C along the transmission direction of the data flow. For example, the data line is transmitted to B, then to A, and then to C. This is not limited to A being located between B and C on the layout of the semiconductor structure 20. The three circuits A, B, and C can be arranged in any layout.

[0083] The hardware statistical analysis circuit 28 performs preliminary statistical analysis on the signal output by the analog front end AFE, and then transmits the result to the processor 26 for processing, which can improve the accuracy and efficiency of the processor 26.

[0084] 3B and 3C are schematic topological diagrams of a semiconductor structure provided in an embodiment of the present application.

[0085] In some embodiments, the statistical analysis circuit 28 needs a storage function when performing preliminary statistical analysis on the signal output by the analog front end AFE.

[0086] For example, as shown in FIG. 3B , the statistical analysis circuit 28 is coupled to the non-volatile memory NVM, and the non-volatile memory NVM provides a temporary buffering function required by the statistical analysis circuit 28 .

[0087] Alternatively, for example, as shown in FIG3C , the statistical analysis circuit 28 is coupled to a volatile memory (eg, a static random access memory SRAM), and the volatile memory provides a temporary buffering function required by the statistical analysis circuit 28 .

[0088] In some embodiments, the statistical analysis circuit 28 includes a statistical circuit 21, a compensation circuit 22, a low-pass filter circuit 23, a noise calculation circuit 27, an echo detection circuit 24, and an echo analysis circuit 25. Of course, the statistical analysis circuit 28 is not limited to including the above-mentioned circuit modules, and other circuit modules may be added, or one or more of the above-mentioned circuit modules may be reduced. The embodiment of the present application is only for illustration, and the statistical analysis circuit 28 applicable to ToF sensors in the related art is applicable to the embodiment of the present application.

[0089] The statistical circuit 21 is coupled to the analog front end AFE, and is configured to perform statistical processing on the received signal and transmit the statistical processing result to the compensation circuit 22 .

[0090] For example, the statistical circuit 21 includes a histogram statistical circuit 21′. Because the photons received by the photoelectric conversion module 30 are not received at the same time, the timestamp digital signal output by the analog front end (AFE) has a time distribution. The histogram statistical circuit 21′ calculates the timestamp digital signal according to the time distribution of the received photons and performs histogram statistics. Of course, the statistical circuit 21 can also expose other statistical circuits; the histogram statistical circuit 21′ is only an example.

[0091] At the same time, the statistical circuit 21 also needs to store the statistical results.

[0092] In some embodiments, as shown in FIG3B , the statistical circuit 21 is configured to store the statistical results in a non-volatile memory NVM.

[0093] For example, as shown in FIG3A , the statistical circuit 21 is coupled to the analog front end AFE and the non-volatile memory NVM.

[0094] Non-volatile memory NVM is used to implement the function of static random access memory SRAM. There is no need to set up static random access memory SRAM in the semiconductor structure 20. The types of memory in the semiconductor structure 20 are reduced, which can simplify the preparation process and layout difficulty of the semiconductor structure 20 and reduce the area and power consumption of the semiconductor structure 20.

[0095] In other embodiments, as shown in FIG3C , the semiconductor structure 20 further includes a volatile memory (e.g., static random access memory (SRAM)). The volatile memory serves as a cache to temporarily store the statistical results output by the statistical circuit 21 or to store data generated during the statistical process. Using a volatile memory to provide storage for the statistical circuit 21 can improve the access speed of the statistical circuit 21.

[0096] In some embodiments, the compensation circuit 22 is configured to perform compensation processing on the received signal and then output the result.

[0097] Since the analog signal is inconsistent during differentiation, after being counted by the histogram statistics circuit 21 ′, the data needs to be compensated before being output, so as to improve the accuracy of signal processing.

[0098] For example, the compensation circuit 22 includes a DNL compensation circuit 22'. The DNL compensation circuit 22' reduces the error of histogram statistics through a differential algorithm.

[0099] In some embodiments, the compensation circuit 22 is coupled to an output terminal of the statistical circuit 21 for receiving data output by the statistical circuit 21 .

[0100] Of course, the semiconductor structure 20 may not include the compensation circuit 22 , or the compensation circuit 22 may be disposed at other locations. FIG. 3B is merely an illustration.

[0101] In some embodiments, the low-pass filter circuit 23 is configured to filter out noise signals from the received signal before outputting the signal. For example, the low-pass filter circuit 23 filters out high-frequency signals from the received signal to remove noise signals from the signal. The specific frequency of the high-frequency signals to be filtered out is not limited in this embodiment of the application; the frequency band of the filtered noise signals can be set based on the specific application scenario.

[0102] For example, the low-pass filter circuit 23 is coupled to the compensation circuit 22 and receives the signal output by the compensation circuit 22 .

[0103] In some embodiments, the low-pass filter circuit 23 is further configured to filter out noise signals from the received signals and then store them.

[0104] For example, as shown in FIG3B , the low-pass filter circuit 23 is used to filter out noise signals from the received signal and then store the received signal in the non-volatile memory NVM.

[0105] For example, the low-pass filter circuit 23 is coupled to the compensation circuit 22 and the non-volatile memory NVM. In the case where the semiconductor structure 20 does not include the compensation circuit 22, the low-pass filter circuit 23 is coupled to the statistical circuit 21 and the non-volatile memory NVM.

[0106] Non-volatile memory NVM is used to implement the function of static random access memory SRAM. There is no need to set up static random access memory SRAM in the semiconductor structure 20. The types of memory in the semiconductor structure 20 are reduced, which can simplify the preparation process and layout difficulty of the semiconductor structure 20 and reduce the area and power consumption of the semiconductor structure 20.

[0107] Alternatively, for example, as shown in FIG3C , the semiconductor structure 20 further includes a volatile memory (eg, a static random access memory SRAM), and the volatile memory serves as a cache to temporarily store the signal output by the low-pass filter circuit 23 .

[0108] For example, the low-pass filter circuit 23 is coupled to the compensation circuit 22 and the static random access memory SRAM. In the case where the semiconductor structure 20 does not include the compensation circuit 22, the low-pass filter circuit 23 is coupled to the statistical circuit 21 and the static random access memory SRAM.

[0109] The volatile memory is used to provide a storage function for the low-pass filter circuit 23 , thereby improving the access speed of the low-pass filter circuit 23 .

[0110] In some embodiments, the noise calculation circuit 27 is configured to calculate and output a noise signal in a received signal.

[0111] Illustratively, the noise calculation circuit 27 is coupled to the low-pass filter circuit 23 for calculating the noise signal.

[0112] In some embodiments, the echo detection circuit 24 is configured to detect and output peak information of a received signal.

[0113] If there are multiple obvious peaks and troughs in the histogram, we will extract the histogram near the peak. The extracted peak information includes the location of the peak value, the half-height width of the peak, the slope of the peak rising and falling edges, the confidence of the peak relative to the noise floor (signal-to-noise ratio), and other information.

[0114] For example, the echo detection circuit 24 is coupled to the noise calculation circuit 27 . In the case where the semiconductor structure 20 does not include the noise calculation circuit 27 , the echo detection circuit 24 may be coupled to the low-pass filter circuit 23 , for example.

[0115] In some embodiments, the echo detection circuit 24 also needs to retrieve cached data from the memory.

[0116] For example, as shown in FIG. 3B , the low-pass filter circuit 23 is coupled to the non-volatile memory NVM.

[0117] Alternatively, as shown in FIG3C , the low-pass filter circuit 23 is coupled to the volatile memory NVM.

[0118] In some embodiments, the echo analysis circuit 25 is used to analyze the received signal and output the analysis result to the processor 26. For example, the echo analysis circuit 25 calculates the centroid position information (also called center position information) of the peak based on the peak information.

[0119] For example, the echo analysis circuit 25 is coupled between the echo detection circuit 24 and the processor 26 , and transmits the analysis result to the processor 26 .

[0120] After receiving the analysis result (eg, centroid position information), the processor 26 reads the software code and fixed parameters required for the calculation stored in the non-volatile memory NVM, and processes the centroid position information to generate distance data.

[0121] 3B and 3C , when the processor 26 generates the distance data, it also needs to directly receive the signal output by the compensation circuit 22 . For example, the compensation circuit 22 is further coupled to the processor 26 .

[0122] Of course, the various circuit modules in the semiconductor structure 20 are not limited to the coupling relationship illustrated in the embodiment of the present application, and may also be other coupling relationships. The embodiment of the present application is only an illustration.

[0123] In some embodiments, the processor 26 needs to use a storage function when processing the centroid position information to generate distance data.

[0124] For example, as shown in FIG3B , the non-volatile memory NVM provides processor 26 with a temporary cache function required for generating distance data. Processor 26 is configured to write data to the non-volatile memory NVM. When processor 26 needs to temporarily cache data, it can write the data to the non-volatile memory NVM. Furthermore, processor 26 is configured to read data from the non-volatile memory NVM. Processor 26 can retrieve temporarily cached data from the non-volatile memory NVM to complete processing functions.

[0125] For example, the processor 26 is coupled to a non-volatile memory NVM.

[0126] Non-volatile memory NVM is used to implement the function of static random access memory SRAM. There is no need to set up static random access memory SRAM in the semiconductor structure 20. The types of memory in the semiconductor structure 20 are reduced, which can simplify the preparation process and layout difficulty of the semiconductor structure 20 and reduce the area and power consumption of the semiconductor structure 20.

[0127] Alternatively, for example, as shown in FIG3C , the semiconductor structure 20 further includes a volatile memory (eg, static random access memory SRAM), and the volatile memory serves as a cache to provide temporary storage for the processor 26 .

[0128] For example, processor 26 is coupled to volatile memory.

[0129] The distance data generated by the processor 26 may be transmitted to a next-level chip, such as the controller 40 (eg, MCU) of the device 1 , so that the device 1 can respond.

[0130] It can be seen from the above description that the software code storage, fixed parameter storage, and data cache functions required by the processor 26 can all be provided by the on-chip non-volatile memory NVM.

[0131] The semiconductor structure 20 provided in the embodiment of the present application can be a bare chip (die) or a packaged chip (chip), and the embodiment of the present application does not limit this. In addition, the order of the circuit modules in the semiconductor structure 20 can be swapped. The core of the embodiment of the present application lies in the interactive structure of the circuit modules and the non-volatile memory NVM in the semiconductor structure 20. The order between the circuit modules can be adjusted based on the difference between the algorithm and the actual application scenario, and whether the circuit modules are included can also be increased or decreased based on the difference between the algorithm and the actual application scenario. Of course, the semiconductor structure 20 is not limited to only including the above-mentioned circuit modules illustrated in the embodiment of the present application, but can also include other circuit modules, and the structures in the relevant technologies are all applicable to the embodiment of the present application. Moreover, when other circuit modules require storage functions, they can all be coupled to the non-volatile memory NVM or volatile memory in the semiconductor structure 20.

[0132] In some embodiments, the semiconductor structure 20 further includes a photoelectric conversion module 30. That is, the photoelectric conversion module 30 and the semiconductor structure 20 are integrated on the same substrate, and the semiconductor structure 20 is packaged to form the ranging sensor chip 10 provided in the embodiment of the present application.

[0133] In other embodiments, the semiconductor structure 20 does not include the photoelectric conversion module 30 , and the semiconductor structure 20 and the photoelectric conversion module 30 are packaged together in the same package chip to constitute the ranging sensor chip 10 provided in the embodiments of the present application.

[0134] The photoelectric conversion module 30 includes, for example, a plurality of photodiodes arranged in an array, and converts optical signals into electrical signals through the photodiodes.

[0135] The embodiment of the present application further provides a working method of a ranging sensor chip 10 , where the ranging sensor chip 10 , for example, includes any of the aforementioned ranging sensor chips 10 .

[0136] Working methods, including:

[0137] At the power-on startup moment, the processor 26 directly reads the curing parameters representing the identity information of the semiconductor structure 20 (or the ranging sensor chip 10 ) from the non-volatile memory NVM.

[0138] In the operating method of the ranging sensor chip 10 provided in the embodiments of the present application, the hardened parameters required for startup of the ranging sensor chip 10 are stored directly in the non-volatile memory NVM within the semiconductor structure 20, rather than in an external non-volatile memory. This allows the ranging sensor chip 10 to retrieve the hardened parameters directly from its internal non-volatile memory NVM during power-up and startup, eliminating the need to load the hardened parameters from the external non-volatile memory into the internal volatile memory. This results in fast startup of the ranging sensor chip 10, a simple workflow, and reduced latency.

[0139] In some embodiments, the working method further comprises:

[0140] The analog front end AFE receives the electrical signal output by the photoelectric conversion module 30 , processes the electrical signal, and then outputs it.

[0141] The processor 26 directly reads the software code from the non-volatile memory NVM to process the signal output by the analog front end AFE to generate distance data.

[0142] In the operating method of the ranging sensor chip 10 provided in the embodiments of the present application, the software code required by the processor 26 for processing operations is stored directly in the non-volatile memory NVM within the semiconductor structure 20, rather than in an external non-volatile memory. This allows the processor 26 to retrieve the software code directly from the non-volatile memory NVM when the semiconductor structure 20 performs processing operations, eliminating the need to load the software code from the external non-volatile memory into the internal volatile memory. This results in a fast startup speed and a simple workflow for the ranging sensor chip 10, reducing latency within the semiconductor structure 20.

[0143] In some embodiments, the processor 26 directly reads the software code from the non-volatile memory NVM to process the signal output by the analog front end AFE to generate distance data, including:

[0144] The statistical circuit 21 receives the signal output by the analog front end (AFE), performs statistical processing on the signal, and then outputs it. The compensation circuit 22 receives the signal output by the statistical circuit 21, performs statistical processing on the signal, and then outputs it. The low-pass filter circuit 23 receives the signal output by the compensation circuit 22, filters out noise from the signal, and then outputs it. The echo detection circuit 24 receives the signal output by the low-pass filter circuit 23, detects peak information in the signal, and then outputs it. The echo analysis circuit 25 receives the peak information from the echo detection circuit 24, generates centroid position information, and then outputs it. The processor 26 receives the centroid position information output by the echo analysis circuit 25, processes the centroid position information, and then outputs distance data.

[0145] During the operation of the ranging sensor chip 10 , the storage functions required by the ranging sensor chip 10 may all be provided by the non-volatile memory NVM, and the storage functions required by the ranging sensor chip 10 may also be partially provided by the volatile memory.

[0146] In some embodiments, after the processor 26 performs calculations, the data stored in the non-volatile memory NVM will be updated or rewritten.

[0147] Regarding the structure of the non-volatile memory NVM in the semiconductor structure 20, in some embodiments, the non-volatile memory NVM includes a control circuit and a memory array, wherein the control circuit is coupled to the memory array to control reading of the memory array. The memory array includes a plurality of memory cells.

[0148] Regarding the manner in which the non-volatile memory NVM provides storage functions for various circuits in the semiconductor structure 20:

[0149] In some embodiments, the non-volatile memory NVM is physically divided into a plurality of memory modules, and the circuits coupled to the non-volatile memory NVM in the semiconductor structure 20 are coupled to one or more memory modules.

[0150] For example, the control circuit includes a plurality of control branches, the storage array includes a plurality of array modules, and the non-volatile memory NVM includes a plurality of storage modules, each storage module includes a control branch and an array module.

[0151] Then, the circuit coupled to the non-volatile memory NVM is called an X circuit. Taking the semiconductor structure 20 shown in FIG3B as an example, the X circuit can be the processor 26, the statistical circuit 21, the low-pass filter circuit 23, and the echo detection circuit 24 in the semiconductor structure 20 shown in FIG3B.

[0152] 4-9 are diagrams showing the relationship between a circuit in a semiconductor structure and a non-volatile memory according to an embodiment of the present application.

[0153] As shown in FIG4 , each X circuit is coupled to one or more storage modules. When the X circuit is an intermediate transmission circuit, the X circuit is also coupled to an upstream X circuit and a downstream X circuit. An input end of the X circuit receives a signal from the upstream X circuit, processes the received signal, and transmits it to the downstream X circuit.

[0154] In some embodiments, as shown in FIG5 , the storage module may be integrated into the X circuit, or may be located outside the X circuit, and may be appropriately configured as needed.

[0155] In some embodiments, transistors included in the logic portion of part or all of the circuits in the semiconductor structure 20 and transistors in the non-volatile memory NVM are integrated on the same chip.

[0156] In some other embodiments, the non-volatile memory NVM is divided into multiple storage regions by addresses, and the circuits coupled to the non-volatile memory NVM in the semiconductor structure 20 correspond to one or more storage regions.

[0157] For example, as shown in FIG6 , each X circuit is coupled to a control circuit. When the X circuit is an intermediate transmission circuit, the X circuit is also coupled to an upstream X circuit and a downstream X circuit. An input end of the X circuit receives a signal from the upstream X circuit, processes the received signal, and transmits it to the downstream X circuit.

[0158] In some embodiments, the semiconductor structure 20 further includes an input / output interface I / O, which is coupled to the non-volatile memory NVM for writing to or reading from the outside of the semiconductor structure 20 .

[0159] In some embodiments, some X circuits in the semiconductor structure 20 only read data from the non-volatile memory NVM. Some X circuits in the semiconductor structure 20 not only read data from the non-volatile memory NVM but also write data processed by themselves to the non-volatile memory NVM. The non-volatile memory NVM stores the written data and updates or does not update the previous data as needed.

[0160] The input / output interface I / O is directly coupled to the non-volatile memory NVM, and the non-volatile memory NVM is externally connected to other structures via the input / output interface I / O.

[0161] For example, the non-volatile memory NVM is connected to the external device 1 via the input / output interface I / O to obtain the system chip.

[0162] Alternatively, for example, the non-volatile memory NVM is externally connected to other non-volatile memories via an input / output interface I / O.

[0163] In some embodiments, as shown in FIG. 7 , the input / output interface I / O exists independently, and the X circuit is coupled to the input / output interface I / O via the non-volatile memory NVM.

[0164] In some other embodiments, as shown in FIG. 8 , the input / output interface I / O is integrated into the X circuit, and the X circuit can be directly coupled to the input / output interface I / O.

[0165] In some other embodiments, as shown in FIG. 9 , some input / output interfaces I / O exist independently, and some input / output interfaces I / O are integrated into the X circuit.

[0166] Of course, the logic part of the X circuit may be integrated with the control branch of the non-volatile memory NVM, or may not be integrated with the control branch. The drawings in the embodiments of the present application are only for illustration and do not limit the present invention in any way.

[0167] Regarding the type of non-volatile memory NVM, in some embodiments, the non-volatile memory NVM includes one or more of read-only memory (ROM) and flash memory, ferroelectric random-access memory (FeRAM, ferroelectric field effect transistor, FeFET), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM) and phase-change random access memory (PCRAM).

[0168] Flash memory is characterized by adding a floating gate, oxide-nitride-oxide-silicon oxygen nitride oxide silicon (ONO-SONOS) or nanocrystals to the gate of a transistor to store electrons for reading and writing data.

[0169] Magnetoresistive random access memory (MRAM) utilizes a toggle mechanism, spin transfer torque (STT), spin orbit torque (SOT), or voltage-controlled magnetic anisotropy (VCMA) mechanism to combine transistors with magnetic tunneling junctions (MTJs). Information is stored in the relative magnetic moments of the two layers of magnetic material in the MTJ.

[0170] Resistive random access memory (RRAM) combines transistors with variable resistors. The variable resistors create and disappear conductive paths between the resistor layers by applying a voltage. Examples of RRAM include oxygen vacancy memories (OxRAM) and conductive bridge memories (CBRAM).

[0171] Phase-change random access memory (PCRAM) is characterized by combining transistors with phase-change materials, where the resistance of the phase-change material changes as the crystal phase changes.

[0172] Ferroelectric memories are divided into two categories: FeRAM and FeFET. FeRAM combines the drain of a transistor with a ferroelectric material, while FeFET adds a layer of ferroelectric material to the gate of the transistor, storing information in the ferroelectric polarity. For example, FeRAM can be a 1T-1C (1 transistor + 1 capacitor) structure, while FeFET can be a 1T-1G (1 transistor + 1 gate) structure.

[0173] The manner in which the volatile memory provides storage functions for each circuit in the semiconductor structure 20 may be the same as the manner in which the non-volatile memory NVM provides storage functions for each circuit in the semiconductor structure 20 .

[0174] In some embodiments, the volatile memory is physically divided into a plurality of memory modules, and the circuits coupled to the volatile memory in the semiconductor structure 20 are correspondingly coupled to one or more memory modules.

[0175] For example, the control circuit includes a plurality of control branches, the memory array includes a plurality of array modules, and the volatile memory includes a plurality of memory modules, each memory module including a control branch and an array module.

[0176] The circuit coupled to the volatile memory is referred to as an X circuit. Taking the semiconductor structure 20 shown in FIG3C as an example, the X circuit may include the processor 26, the statistical circuit 21, the low-pass filter circuit 23, and the echo detection circuit 24 in the semiconductor structure 20 shown in FIG3C . The connection relationship between the circuits within the semiconductor structure 20 and the volatile memory can refer to the connection relationship between the circuits within the semiconductor structure 20 and the non-volatile memory NVM shown in FIG4-9 .

[0177] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that: Applicable to a distance measuring sensor chip including a photoelectric conversion module; The semiconductor structure comprises: Non-volatile memory; used to store software code; An analog front end, used to couple with the photoelectric conversion module, receive the electrical signal output by the photoelectric conversion module, and process the electrical signal before outputting it; The processor is coupled to the non-volatile memory and is used to read the software code and process the signal output by the analog front end to generate distance data.

2. The semiconductor structure according to claim 1, characterized in that: The volatile memory is further used to store curing parameters representing the identity information of the semiconductor structure; and the processor is further used to read and / or write the curing parameters.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The semiconductor structure also includes a statistical analysis circuit, which is used to perform statistical analysis processing on the signal output by the analog front end and output the processing result to the processor.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor structure further includes a statistical analysis circuit coupled between the analog front end and the processor.

5. The semiconductor structure according to claim 3 or 4, characterized in that: The statistical analysis circuit includes a statistical circuit, a compensation circuit, a low-pass filter circuit, a noise calculation circuit, an echo detection circuit and an echo analysis circuit; The statistical circuit is used for performing statistical processing on the signal output by the analog front end and then outputting the signal; The compensation circuit is used to perform compensation processing on the received signal and then output it; The low-pass filter circuit is used to filter out the noise signal in the received signal and then output it; The noise calculation circuit is used to calculate the noise signal in the received signal and output it; The echo detection circuit is used to detect the peak information of the received signal and output it; The echo analysis circuit is used to analyze the received signal and output the analysis result to the processor.

6. The semiconductor structure according to any one of claims 3 to 5, characterized in that: The statistical analysis circuit includes a statistical circuit, a compensation circuit, a low-pass filter circuit, a noise calculation circuit, an echo detection circuit and an echo analysis circuit; The statistical circuit is coupled to the analog front end; The compensation circuit is coupled to the statistical circuit; The low-pass filter circuit is coupled to the compensation circuit; The noise calculation circuit is coupled to the low-pass filter circuit; The echo detection circuit is coupled to the noise calculation circuit; The echo analysis circuit is coupled to the echo detection circuit and the processor.

7. The semiconductor structure according to claim 5 or 6, characterized in that: At least one of the statistical circuit, the low-pass filtering circuit, and the echo detection circuit is also coupled to the non-volatile memory.

8. The semiconductor structure according to claim 5 or 6, characterized in that: The semiconductor structure further includes a volatile memory; at least one of the statistical circuit, the low-pass filter circuit, the echo detection circuit and the processor is also coupled to the volatile memory.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that: The semiconductor structure further includes an input / output interface coupled to the non-volatile memory.

10. A distance measuring sensor chip, characterized in that: It comprises a semiconductor structure and a photoelectric conversion module; the semiconductor structure is coupled to the photoelectric conversion module; the semiconductor structure comprises the semiconductor structure according to any one of claims 1 to 9.

11. A device, characterized in that: It comprises a distance measuring sensor chip and a controller, wherein the distance measuring sensor chip is coupled to the controller; the distance measuring sensor chip comprises the distance measuring sensor chip according to claim 10.

12. A method for operating a ranging sensor chip, characterized in that: The distance measuring sensor chip includes a semiconductor structure and a photoelectric conversion module; the semiconductor structure includes a non-volatile memory, an analog front end and a processor; The working method comprises: The analog front end receives the electrical signal output by the photoelectric conversion module, processes the electrical signal and then outputs it; The processor directly reads the software code from the non-volatile memory to process the signal output by the analog front end to generate Distance data.

13. The working method according to claim 12, characterized in that: The working method also includes: At the power-on startup moment, the processor directly reads the curing parameters representing the identity information of the semiconductor structure from the non-volatile memory.

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