Method for producing mosfet transistors incorporating air cavities to reduce capacitive coupling in radiofrequency regime

Abstract

The invention relates to a method for manufacturing a microelectronic device (100) having a cavity (20) comprising at least one transistor (11a), the method comprising at least the following step:  Removing the materials from a stack of dielectric layers (1) of the microelectronic device (100), selectively with respect to the materials of a set of interconnection lines (2) and a cover (3) of an active area by vapor-phase HF etching, thus forming the cavity (20) extending laterally in a direction x at least until exposing the walls of the set of interconnection lines (2) opposite the first transistor (11a), and in a direction z perpendicular to the direction x until exposing an upper face of the cover (3) of the active area.

Description

[0001] Method for producing MOSFET transistors incorporating air cavities for reducing capacitive coupling in radiofrequency regime

[0002] TECHNICAL FIELD OF THE INVENTION

[0003] The present invention relates to the field of microelectronic technologies. It finds a particularly advantageous application in the manufacture of RF (“Radiofrequency”) switches with MOS (“Metal-Oxide-Semiconductor”) transistors and cavities.

[0004] STATE OF THE ART

[0005] To meet the continuous evolution of communication standards, the multiplicity of RF switches is a necessity. The existence of several communication standards requires the reduction of insertion losses in the RF switch. To achieve this, the transistors that compose it must have as low a resistance as possible in linear operating mode. A technological lever for reducing the resistance of a RON transistor consists of reducing the length of its channel and therefore of its gate. In return, this gate reduction leads to a substantial increase in the off-state capacitance COFF, the magnitude of which can lead to a degradation of the RONCOFF time constant. Variations in RON and COFF generally follow antagonistic trends, because any process variation tending to improve one of the two parameters results in a simultaneous degradation of the other.

[0006] One solution to partially decouple the interdependence between RON and COFF is to replace the dielectric layers between the metal lines of the device interconnect network with another material of lower dielectric permittivity such as air, thus allowing the reduction of the COFF capacitance independently of RON. This can be achieved by partially removing the dielectric layers between the metal connection lines in post-process mode after completion of the RF switch manufacturing process, thus giving rise to cavities above the transistors.

[0007] Document US 10707120 B1 discloses a method for producing air cavities above transistor gates in the dielectric layers between the metal connection lines. These air cavities are produced by several successive dry etchings, a first anisotropic etching allowing the formation of holes in a first dielectric layer, and a second isotropic dry etching allowing the formation of a reduced air cavity in a second dielectric layer above the transistors. However, this etching is not selective, and the level of isotropy and the geometry of the etching in the second dielectric layer strongly depend on the size of the openings in the first layer and the etching parameters, which limits the lateral extension of the air cavity, and consequently the removal of the dielectric layers.

[0008] Document EP 3859777 A1 discloses a device with air cavities produced by several successive etchings, a first anisotropic and non-selective dry etching allows the formation of a trench crossing several dielectric layers between the metal connection lines and stopping in a dielectric layer above the transistor without exposing an etching stop layer covering the transistor, and a second isotropic wet etching by HF acid (Hydrofluoric or Hydrogen Fluoride) allows the formation of a cavity which also extends in a reduced manner in a dielectric layer between metal interconnections.

[0009] Document US 10211146 B2 discloses another method for producing air cavities above transistors by two successive etchings. A first anisotropic and non-selective dry etching allows the formation of a first straight air cavity crossing the different dielectric layers between the metal connection lines. A second isotropic wet etching by HF acid allows the lateral extension of the cavity.

[0010] The present invention proposes to overcome at least in part the drawbacks of known methods. In particular, an objective of the present invention is to propose a method for producing cavities, in particular in an RF switch, which makes it possible to effectively reduce the RONCOFF time constant of the transistor(s).

[0011] SUMMARY OF THE INVENTION

[0012] To achieve this objective, according to one embodiment, a method is provided for manufacturing a cavity microelectronic device comprising at least a first transistor, the first transistor comprising a first channel surmounted by a first gate extending laterally in a direction y, a first source and a first drain, the method comprising the following steps:

[0013] • providing on a substrate: an active area having an active layer comprising the first channel, the first source and the first drain of the first transistor, and the first gate above the active layer surmounting the first channel, a cover of the active area comprising at least one mechanical stress layer covering the active layer and the first gate, a stack of dielectric layers above the cover of the active area comprising at least a first dielectric layer and a second dielectric layer superimposed in a z direction perpendicular to the y direction. a set of at least two interconnection lines passing in the z direction through the stack of dielectric layers and the cover of the active area to, respectively, the first source and the first drain so as to form an electrical contact, respectively, with the first source and the first drain,each line of said set of interconnection lines comprising at least a first contact extending in the z direction through the first dielectric layer and the covering of the active zone, and a first metal interconnection extending laterally in the second dielectric layer in the y direction, said first contact being in contact with a lower face of the first metal interconnection and with an upper face, respectively, of the first source and the first drain, a passivation layer covering the stack of dielectric layers and the set of interconnection lines, depositing a first barrier layer on the passivation layer, the first barrier layer being based on one of the following materials: AI2O3, AIN and SiN, x rich in Si,

[0014] • forming openings in the passivation layer and in the first barrier layer by dry etching exposing the stack of dielectric layers,

[0015] • removing, through the openings, the materials of the stack of dielectric layers selectively with respect to the materials of the set of interconnection lines and of the cover of the active zone by HF vapor phase etching, thus forming a cavity extending laterally in a direction x perpendicular to the directions y and z at least until the exposure of the walls of the set of interconnection lines opposite the first transistor, and in the direction z until the exposure of an upper face of the cover of the active zone.

[0016] A principle of the method according to the invention consists in etching the dielectric material by vapor phase HF. The dielectric material forming the stack of dielectric layers and the metallic material forming the set of interconnection lines are chosen so that one is etched selectively with respect to the other by vapor phase HF. This selectivity as well as the isotropic nature of vapor phase HF etching allow complete removal of the dielectric material and consequently, the substantial reduction of the COFF capacitance independently of the RON resistance of the transistor, in particular the reduction of the contribution of the parasitic capacitance induced by the volume of the area comprising the interconnections, to the total COFF capacitance of the microelectronic device.While the state of the art reflects a constant prejudice according to which the creation of a cavity in the dielectric parts obeys lateral extension limits to avoid the degradation of the metallic connection elements, the process here proposes the use of a specific etching offering a great selectivity between the materials involved.

[0017] Another aspect of the invention relates to a microelectronic device, comprising:

[0018] • a substrate and an active layer above the substrate,

[0019] • at least one first transistor, comprising a first channel surmounted by a first gate, a first source and a first drain, the first channel, the first source and the first drain being in the active layer, the first gate extending laterally in the y direction above the active layer, the first transistor and the active layer forming an active zone,

[0020] • a cover of the active zone comprising at least one mechanical stress layer covering the active layer and the first grid,

[0021] • a set of at least two interconnection lines crossing in the z direction the coverage of the active zone up to, respectively, the first source and the first drain so as to form an electrical contact, respectively, with the first source and the first drain, each line of said set of interconnection lines comprising at least a first contact extending in the z direction, and a first metal interconnection extending laterally in the y direction, said first contact being in contact with a lower face of the first metal interconnection and with an upper face, respectively, of the first source and the first drain,

[0022] • a passivation layer covering all interconnection lines,

[0023] • a first barrier layer overlying the passivation layer, the first barrier layer being based on one of the following materials: AI2O3, AIN and SiN x rich in Si, and

[0024] • a cavity above the active zone, the device being characterized in that the cavity extends laterally in the x direction so as to expose walls of all the interconnection lines opposite the first transistor, and in the z direction so as to expose an upper face of the cover of the active zone.

[0025] Other objects, features, and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated.

[0026] BRIEF DESCRIPTION OF THE FIGURES

[0027] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0028] Figure 1 schematically illustrates a top view in an xy plane of an RF switch made according to the present invention.

[0029] Figures 2 to 6 schematically illustrate, along a cross-section in an xz plane, the different stages of manufacturing a cavity RF switch according to the present invention. A preferably orthonormal reference frame, comprising the x, y, z axes, is shown in these figures.

[0030] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, on the schematic diagrams, the thicknesses and / or dimensions of the different layers, patterns and reliefs are not strictly representative of reality.

[0031] DETAILED DESCRIPTION OF THE INVENTION

[0032] Before commencing a detailed review of embodiments of the invention, optional features which may optionally be used in combination or alternatively are set out below:

[0033] In one example, the width of the first metal interconnects extends laterally in the x-direction beyond the width of the first contacts, such that the RF vapor etched cavity further exposes at least the portion of the underside of the first metal interconnects extending beyond the width of the first contacts.

[0034] According to one example, the materials of the stack of dielectric layers have a dielectric permittivity less than or equal to 2, and are preferably based on SiO oxides x .

[0035] For example, the materials of all interconnect lines are based on metals such as aluminum, copper or tungsten coated with a layer of titanium nitride.

[0036] For example, the first metal interconnects were made of aluminum or copper.

[0037] In one example, the first contacts are based on Tungsten (W) coated with a layer of Titanium Nitride (TiN).

[0038] In one example, the materials of the dielectric layer stack have a selectivity ratio SD : M greater than 100 compared to the materials of all interconnecting lines.

[0039] According to one example, the covering of the active area further comprises a second barrier layer covering the constraint layer.

[0040] In one example, a passivation barrier layer is deposited across the openings in the cavity so as to cover at least an upper face of the mechanical stress layer and the exposed walls of the interconnect line assembly.

[0041] In one example, the stack of dielectric layers further comprises a third dielectric layer and a fourth dielectric layer above the third dielectric layer, superposed with the first dielectric layer and the second dielectric layer along the z direction.

[0042] According to one example, each line of the set of metal interconnect lines further comprises a via extending through the third dielectric layer in the z direction, and a second metal interconnect extending laterally in the fourth dielectric layer in the y direction, said via being in contact with an upper face of the first metal interconnect and a lower face of the second metal interconnect.

[0043] In one example, the second metal interconnects are made of aluminum or copper.

[0044] In one example, the vias are copper-based when the second metal interconnects are copper-based.

[0045] In one example, the vias are based on Tungsten (W) coated with a layer of Titanium Nitride (TiN) when the second metal interconnections are based on aluminum.

[0046] In one example, the first contacts of all interconnecting lines are pillar-shaped.

[0047] According to one example, the microelectronic device further comprises at least one second transistor adjacent to the first transistor in the x direction, comprising a second channel surmounted by a second gate extending laterally in the y direction, a second source and a second drain.

[0048] In one example, the cavity is filled with air or a gas having a dielectric permittivity less than 2.

[0049] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition or application of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0050] A layer can also be composed of several sub-layers of the same material or of different materials.

[0051] A substrate, film or layer "based" on a material A means a substrate, film or layer comprising this material A only or this material A and possibly other materials, for example doping elements or alloying elements. Thus, a spacer based on silicon nitride Si x N y may for example comprise non-stoichiometric silicon nitride (SiN), or stoichiometric silicon nitride (Sisl^ ), or even a silicon oxy-nitride (SiON).

[0052] The word "dielectric" describes a material whose electrical conductivity is low enough in the given application to serve as an insulator.

[0053] Several embodiments of the invention implementing successive steps of the manufacturing process are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them.

[0054] Furthermore, the term "step" means the carrying out of a part of the process, and can designate a set of sub-steps.

[0055] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term "step" does not necessarily mean actions that are unitary and inseparable in time and in the sequence of phases of the process.

[0056] The term "selective etching with respect to" or "etching exhibiting selectivity with respect to" means an etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching rate of material A greater than the etching rate of material B. Selectivity is the ratio between the etching rate of material A and the etching rate of material B. It is denoted SAB. A SAB selectivity of 10:1 means that the etching rate of material A is 10 times greater than the etching rate of material B.

[0057] A preferably orthonormal reference frame, comprising the x, y, z axes, is shown in the attached figures.

[0058] The relative terms "on", "overcomes", "under", "underlying" refer to positions taken along the z direction. A "lateral" dimension corresponds to a dimension along a direction of the xy plane. A "lateral" or "laterally" extension means an extension along one or more directions of the xy plane.

[0059] An element located "perpendicular to" or "in line with" another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the cross-sectional figures.

[0060] The terms "substantially", "approximately", "in the order of" mean to within 10%, and preferably to within 5%. Furthermore, the terms "between ... and ..." and equivalents mean that the limits are included, unless otherwise stated.

[0061] The following description presents an example of implementation of the method according to the invention in the context of developing a complex 3D device. The scope of this description is obviously not limiting of the invention.

[0062] Figure 1 schematically illustrates a top view in an xy plane of an RF switch. Said RF switch represents an application of the manufacturing process detailed below. It comprises several MOS (“Metal-Oxide-Semiconductor”) transistors T1, T2, T3, arranged in parallel in an x ​​direction, and two levels of metal interconnections M1, M2. The metal interconnections M1, M2 are used to connect the sources and drains of the transistors T1, T2, T3 and to control the switching of the transistors T1, T2, T3. An RF switch having a comb configuration like that illustrated in Figure 1, further comprises two other metal levels M3, M4 not illustrated.

[0063] Figures 2 to 6 schematically illustrate the different steps of the manufacturing process of a cavity RF switch according to the present invention.

[0064] For the sake of simplification, Figures 2 to 6 represent a transverse section in an xz plane of a microelectronic device 100 at each stage of the manufacturing process. The microelectronic device 100 does not correspond exactly to the device illustrated in Figure 1 for reasons of simplification. Those skilled in the art will easily adapt Figures 2 to 6 to visualize the different stages of the manufacturing process of a device as illustrated in Figure 1.

[0065] Each step of the manufacturing method of a cavity RF switch according to the present invention will be detailed below.

[0066] As illustrated in Figure 2, a first step consists in providing a microelectronic device 100 manufactured by a method well known to those skilled in the art. The microelectronic device 100 comprises at least one, but preferably a plurality of MOS transistors 11a, 11b. Each transistor 11a, 11b respectively comprises a channel 12a, 12b, a source 13a, 13b, a drain 14a, 14b and a gate 15a, 15b. Each gate 15a, 15b is separated from the channel 12a, 12b respectively, by a thin dielectric layer not illustrated. This thin layer, referred to as a gate dielectric, is preferably based on a material preferably chosen from the materials: SiO x , If x O y N zor a hafnium oxide. An active layer 10 fabricated above a substrate S, comprises the channels 12a, 12b, the sources 13a, 13b and the drains 14a, 14b of the transistors 11a, 11b. Each gate 15a, 15b surmounts the channel 12a, 12b of the corresponding transistor 11a, 11b, and extends laterally above the active layer 10 in a direction y perpendicular to the direction x. Spacers 16 line the sides of the gates 15a, 15b, forming a continuous ring in an xy plane around each gate 15a, 15b, with a closed contour. The active layer 10 and the gates 15a, 15b of the transistors 11a, 11b are included in an active zone of the microelectronic device 100 called FEOL (“Front-End-Of-Line” in English, or start of line).

[0067] The substrate S may be an SOI (Silicon-on-insulator) type substrate. These known substrates comprise, according to the terminology commonly used by those skilled in the art, a carrier silicon substrate "Si bulk" (or massive silicon) and a silicon oxide layer called "BOX" (Buried Oxide, or buried oxide). MOS transistors on SOI substrates are particularly well suited to the RF switching function because they benefit from isolation by the buried oxide. This isolation makes it possible to attenuate the effects of parasitic propagation of the RF signal (crosstalk) by the substrate S.

[0068] The microelectronic device 100 further comprises a cover 3 of the active zone comprising at least one mechanical stress layer 70, covering the active layer 10, the spacers 16 and the gates 15a, 15b. The cover 3 of the active zone may further comprise a siliciding layer, not illustrated, below the mechanical stress layer 70. The siliciding layer covers the active layer 10, the spacers 16 and the gates 15a, 15b. It is preferably based on cobalt silicide (CoSi2), nickel silicide (eg, NiSi) or an equivalent alloy.The mechanical stress layer 70 known by the English term CESL (Contact Etch-Stop Layer), commonly used as a barrier during an etching process, further serves to increase the mobility of the carriers (electrons or holes) in the channels 12a, 12b of the transistors 11a, 11b by applying a mechanical stress which modifies the mesh size of the crystal lattice of the channel 12a, 12b. The mechanical stress layer 70 is preferably based on Si nitrides. y N z . The cover 3 of the active area may comprise a plurality of layers.

[0069] The microelectronic device 100 further comprises a zone called BEOL (Back-End-Of-Line), comprising a stack of dielectric layers 1 superimposed with the cover 3 of the active zone in a z direction perpendicular to the xy plane, and a set of interconnection lines 2 crossing in the z direction the stack of dielectric layers 1 and the cover 3 of the active zone up to the sources 13a, 13b and drains 14a, 14b. The interconnection lines 2 form electrical contacts with the sources 13a, 13b and the drains 14a, 14b respectively, and each comprise at least two levels of metal interconnections M1, M2 alternating with a first contact 31 and a via 32. The metal interconnections M1, M2 are based on metal materials M, preferably based on aluminum (Al) or copper (Cu).

[0070] The stack of dielectric layers 1 comprises alternating dielectric layers 41, 42 alternating with dielectric layers 51, 52 in the z direction. The metal interconnections M1, M2 extend laterally in the y direction through the dielectric layers 51, 52, respectively. The dielectric layers 41, 42 and the dielectric layers 51, 52 are based on dielectric materials D, preferably based on SiO oxides x These materials are characterized by relative dielectric permittivities s r typically of the order of 4. The dielectric materials of the stack of dielectric layers 1 are intended to be replaced by another material of dielectric permittivity s r < 2, like air for example (e r~l). This replacement can be achieved by selectively removing the materials of the dielectric layer stack 1 with respect to the metallic materials of the set of interconnect lines 2 by a vapor phase HF etching step. Generally, the materials of the dielectric layer stack 1 and the metallic materials of the set of interconnect lines 2 are chosen so that one can be selectively etched with respect to the other by vapor phase HF. In the case of SiO x and aluminum for example, the selectivity ratio SSIOXAI is greater than 100.

[0071] The first contacts 31 are in the form of pillars which extend in the z direction through the first dielectric layer 41 and the cover 3 of the active zone. The first contacts 31 are in contact with lower faces of the first metal interconnections M1 and in contact with upper faces of the sources 13a, 13b and the drains 14a, 14b respectively. The first contacts 31 are based on a metallic material M, preferably based on Tungsten (W) coated with a layer of Titanium Nitride (TiN).

[0072] The vias 32 are cylindrical in shape, filled with a metallic material M, preferably copper-based when the second metallic interconnections M2 are copper-based, or tungsten (W)-based coated with a layer of titanium nitride (TiN) when the second metallic interconnections M2 are aluminum-based.

[0073] The vias 32 extend through the third dielectric layer 42 in the z direction. The vias 32 are in contact with upper faces of the first metal interconnections M1 and lower faces of the second metal interconnections M2.

[0074] The first metal interconnections M1 and the second metal interconnections M2 may have the same width in the x direction, or different widths. The first contacts 31 and the vias 32 may also have the same width or different widths in the x direction. Furthermore, the width of the first metal interconnections M1 and the second metal interconnections M2 extends laterally in the x direction beyond the width of the first contacts 31 and the vias 32.

[0075] The microelectronic device 100 further comprises a passivation layer 60, covering the stack of dielectric layers 1 and the set of interconnection lines 2. The passivation layer 60 is preferably based on oxide (SiO x ) and Si nitrides y N z . A first thin and conformal barrier layer 80 is advantageously deposited on the passivation layer 60, and serves to protect the surface of the microelectronic device 100 during the HF vapor phase etching step. The first barrier layer 80 has a thickness preferably between 10 nm and 150 nm, and is based on a material preferably chosen from dielectric materials: AI2O3, AIN or SiN xrich in Si. Stoichiometric silicon nitride SiaN4, generally deposited by LPCVD ("Low Pressure Chemical Vapor Deposition"), displays a composition ratio Si / N=3 / 4=0.75. The refractive index is a parameter that commonly characterizes silicon nitride layers. This refractive index, measured at a wavelength of around 600 nm, is generally between n=1.95 for PECVD ("Plasma Enhanced Chemical Vapor Deposition") silicon nitride and 2.05 for LPVCD silicon nitride. This index can take all the values ​​in this interval (1.95-2.05) depending on the deposition technique, deposition conditions (gas, flow rate, pressure, RF power if PECVD, etc.)

[0076] Silicon-rich silicon nitride stands out from the 'Si N' layers xstandard' in its Si / N composition ratio which is on average of the order of 1.7. Its refractive index at 600 nm wavelength also stands out from that of standard layers by reaching the value of the order of 2.4. Otherwise, the refractive index is a marker whose increase is indicative of a concentration of Si in SiN x higher. A layer of "SiN x rich in Si" can therefore be characterized by the Si / N ratio which is typically between 1 and 2. This characterization can be accompanied by mentioning a refractive index typically between 2.05 and 2.5 at a wavelength of 600 nm. According to one example, a layer of AI2O3, having a thickness between 40 nm and 150 nm can constitute an effective barrier to the diffusion of HF in the vapor phase. The first barrier layer 80 is preferably produced by atomic layer deposition ALD (acronym for "Atomic Layer Deposition").

[0077] As illustrated in Figure 3, openings 101 are then made through the passivation layer 60 and the first barrier layer 80 by dry etching. The openings 101 are preferably made in two stages. First openings 101 in the passivation layer 60 are defined by a first dry etching in a first stage before the deposition of the first barrier layer 80. Second openings are then defined by a second dry etching in the first barrier layer 80 in line with the openings 101 of the passivation layer 60 in a second stage, following the deposition of the first barrier layer 80. The openings 101 passing through the passivation layer 60 and the first barrier layer 80 can furthermore be made in a single stage by dry etching.

[0078] As illustrated in Figure 4, the dielectric material D of the stack of dielectric layers 1 is then selectively removed through the openings 101 by HF vapor phase etching, with respect to the materials M of the set of interconnection lines 2, and with respect to the materials of the cover 3 of the active zone, of the passivation layer 60 and of the first barrier layer 80, thus creating cavities 20 above the transistors 11a, 11b. The vapor phase HF etching being isotropic and selective to the dielectric material D of the stack of dielectric layers 1, allows the cavities 20 to extend laterally along the direction x at least until the exposure of the walls of all the interconnection lines 2 facing the first transistor 11a as well as the part of the width of the metal interconnections M1, M2 extending beyond the width of the first contacts 31 and the vias 32.The cavities 20 also extend along the z direction until an upper face of the cover 3 of the active zone is exposed. The removal of the dielectric material D from the stack of dielectric layers 1 until the walls of all the interconnection lines 2 are exposed, allows the reduction of the capacitance COFF independently of the resistance RON of the transistors 11a, 11b, in particular the reduction of the contribution of the capacitance of the BEOL zone to the total capacitance COFF of the microelectronic device 100.

[0079] Following the vapor phase HF etching, the upper face of the cover 3 of the active area is exposed to the air present within the cavities 20, which can alter the properties of the FEOL active area of ​​the microelectronic device 100 in the event of the presence of humidity in the air filling the cavities 20. To overcome this problem, two embodiments of the present invention are possible. The two embodiments are illustrated schematically in Figure 5 and Figure 6 respectively.

[0080] As illustrated in Figure 5, according to the first embodiment of the present invention, the cover 3 of the active zone further comprises a second barrier layer 90 covering the mechanical stress layer 70. This second barrier layer 90 is deposited on the mechanical stress layer 70 during the manufacture of the microelectronic device 100, before the production of the stack of dielectric layers 1 and prior to the formation of the cavities 20. The second barrier layer 90 is based on a material preferably chosen from the dielectric materials: AI2O3, AIN or SiN xrich in Si. The second barrier layer 90 serves to protect the active FEOL area of ​​the microelectronic device 100 in order to prevent any penetration of humidity or other elements which could alter or degrade the properties of the transistors 11a, 11b. In addition, the choice of a material with high thermal conductivity such as AIN for example, allows the second barrier layer 90 to direct the heat flows in the active FEOL area towards the set of interconnection lines 2. According to another variant of the present invention, the second barrier layer 90 can be deposited between two dielectric layers in the BEOL area of ​​the microelectronic device 100.

[0081] As illustrated in Figure 6, according to the second embodiment of the present invention, following the formation of the cavities 20, a passivation barrier layer 95 is deposited through the openings 101 in the cavities 20. The passivation barrier layer 95 serves to cover in particular the upper face of the cover 3 of the active zone as well as the exposed parts of the set of interconnection lines 2 and the sides of the openings 101. The passivation barrier layer 95 is based on a material preferably chosen from the dielectric materials: AI2O3, AIN or SiN xrich in Si. The passivation barrier layer 95 may further be based on the same material as that of the first barrier layer 80 so as to form a continuous layer with the first barrier layer 80. The passivation barrier layer 95 serves to protect the active FEOL zone of the microelectronic device 100 in order to prevent any penetration of humidity or other elements which could alter or degrade the properties of the transistors 11a, 11b. The passivation barrier layer 95 also serves to protect the set of interconnection lines 2. According to one example, a passivation layer 95 based on AIN or aluminum nitride which is a dielectric with a thermal conductivity between 120 W / m / K and 180 W / m / K, makes it possible to ensure better thermal management in the active FEOL zone of the microelectronic device 100, and this for antenna RF switches operating at an RF power of up to 36 dBm for example.An advantageous variant can be implemented by simultaneously combining the two embodiments of the present invention detailed above.

[0082] In view of the above description, it is clear that the proposed method offers a particularly effective solution for removing dielectric materials from the BEOL zone of an RF switch. This solution is also advantageously compatible with standard microelectronics methods. The invention is however not limited to the embodiments previously described.

Claims

CLAIMS 1. Method for manufacturing a microelectronic device (100) with a cavity (20) comprising at least a first transistor (11a), said first transistor (11a) comprising a first channel (12a) surmounted by a first gate (15a) extending laterally in a direction y, a first source (13a) and a first drain (14a), said method comprising the following steps: • provide on a substrate (S): an active area having an active layer (10) comprising the first channel (12a), the first source (13a) and the first drain (14a) of the first transistor (11a), and the first gate (15a) above the active layer (10) surmounting the first channel (11a), a cover (3) of the active area comprising at least one mechanical stress layer (70) covering the active layer (10) and the first gate (15a), a stack of dielectric layers (1) above the cover (3) of the active area comprising at least a first dielectric layer (41) and a second dielectric layer (51) superimposed in a z direction perpendicular to the y direction, a set of at least two interconnection lines (2) crossing in the z direction the stack of dielectric layers (1) and the cover (3) of the active area up to, respectively, the first source (13a) and the first drain (13b) so as to form an electrical contact,respectively, with the first source (13a) and the first drain (14a), each line of said set of interconnection lines (2) comprising at least a first contact (31) extending in the z direction through the first dielectric layer (41) and the cover (3) of the active zone, and a first metal interconnection (M1) extending laterally in the second dielectric layer (51) in the y direction, said first contact (31) being in contact with a lower face of the first metal interconnection (M1) and with an upper face, respectively, of the first source (13a) and of the first drain (14a), a passivation layer (60) covering the stack of dielectric layers (1) and the set of interconnection lines (2), • depositing a first barrier layer (80) on the passivation layer (60), the first barrier layer (80) being based on one of the following materials: AI2O3, AIN and SiN xrich in Si, • forming in the passivation layer (60) and in the first barrier layer (80) openings (101) by dry etching exposing the stack of dielectric layers (1), • removing through the openings (101) the materials of the stack of dielectric layers (1) selectively with respect to the materials of the set of interconnection lines (2) and of the cover (3) of the active zone by HF vapor phase etching, thus forming a cavity (20) extending laterally in a direction x perpendicular to the directions y and z at least until the exposure of the walls of the set of interconnection lines (2) facing the first transistor (11a), and in the direction z until the exposure of an upper face of the cover (3) of the active zone.

2. Method for manufacturing a microelectronic device (100) according to the preceding claim, in which the width of the first metal interconnections (M1) extends laterally in the x direction beyond the width of the first contacts (31), so that the cavity (20) etched by HF in the vapor phase further exposes at least the part of the lower face of the first metal interconnections (M1) extending beyond the width of the first contacts (31).

3. Method for manufacturing a microelectronic device (100) according to any one of the preceding claims, in which the materials of the stack of dielectric layers (1) have a dielectric permittivity less than or equal to 2, and are preferably based on SiO oxides x .

4. Method for manufacturing a microelectronic device (100) according to any one of the preceding claims, in which the materials of all the interconnection lines (2) are based on metals such as aluminum, copper or tungsten coated with a layer of titanium nitride.

5. Method of manufacturing a microelectronic device (100) according to any one of the preceding claims, in which the materials of the stack of dielectric layers (1) have a selectivity ratio SD : M greater than 100 with respect to the materials of all interconnecting lines (2).

6. A method of manufacturing a microelectronic device (100) according to any one of the preceding claims, wherein the cover (3) of the active area further comprises a second barrier layer (90) covering the mechanical stress layer (70).

7. A method of manufacturing a microelectronic device (100) according to any one of claims 1 to 5, wherein a passivation barrier layer (95) is deposited through the openings (101) in the cavity (20) so as to cover at least an upper face of the mechanical stress layer (70) and the exposed walls of the set of interconnection lines (2).

8. A method of manufacturing a microelectronic device (100) according to any one of the preceding claims, wherein the stack of dielectric layers (1) further comprises a third dielectric layer (42) and a fourth dielectric layer (52) above the third dielectric layer (42), superimposed with the first dielectric layer (41) and the second dielectric layer (51) along the z direction.

9. A method of manufacturing a microelectronic device (100) according to the preceding claim, wherein each line of the set of metal interconnection lines (2) further comprises a via (32) extending through the third dielectric layer (42) in the z direction, and a second metal interconnection (M2) extending laterally in the fourth dielectric layer (52) in the y direction, said via (32) being in contact with an upper face of the first metal interconnection (M1) and a lower face of the second metal interconnection (M2).

10. Method of manufacturing a microelectronic device (100) according to any one of the preceding claims, in which the first contacts (31) of the set of interconnection lines (2) are in the form of pillars.

11. A method of manufacturing a microelectronic device (100) according to any one of the preceding claims, wherein the microelectronic device (100) further comprises at least one second transistor (11b) adjacent to the first transistor (11a) in the x direction, comprising a second channel (12b) surmounted by a second grid (15b) extending laterally in the y direction, a second source (13b) and a second drain (14b).

12. Microelectronic device (100), comprising: • a substrate (S) and an active layer (10) above the substrate (S), • at least one first transistor (11a), comprising a first channel (12a) surmounted by a first gate (15a), a first source (13a) and a first drain (14a), the first channel (12a), the first source (13a) and the first drain (14a) being in the active layer (10), the first gate (15a) extending laterally in the y direction above the active layer (10), the first transistor (11a) and the active layer (10) forming an active zone, • a cover (3) of the active zone comprising at least one mechanical stress layer (70) covering the active layer (10) and the first grid (15a), • a set of at least two interconnection lines (2) passing along the z direction through the cover (3) of the active zone up to, respectively, the first source (13a) and the first drain (13b) so as to form an electrical contact, respectively, with the first source (13a) and the first drain (14a), each line of said set of interconnection lines (2) comprising at least a first contact (31) extending along the z direction, and a first metal interconnection (M1) extending laterally along the y direction, said first contact (31) being in contact with a lower face of the first metal interconnection (M1) and with an upper face, respectively, of the first source (13a) and the first drain (14a), • a passivation layer (60) covering the set of interconnection lines (2), • a first barrier layer (80) overlying the passivation layer (60), the first barrier layer (80) being based on one of the following materials: AI2O3, AIN and SiN x rich in Si, and • a cavity (20) above the active zone, the device (100) being characterized in that the cavity (20) extends laterally in the direction x so as to expose walls of all the interconnection lines (2) opposite the first transistor (11a), and along the z direction so as to expose an upper face of the cover (3) of the active zone.

13. Microelectronic device (100) according to the preceding claim, wherein the width of the first metal interconnections (M1) extends laterally in the x direction beyond the width of the first contacts (31), and the cavity (20) further exposes at least the portion of the lower face of the first metal interconnections (M1) extending beyond the width of the first contacts (31).

14. Microelectronic device (100) according to any one of claims 12 and 13, wherein the cavity (20) is filled with air or a gas having a dielectric permittivity of less than 2.

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