A semiconductor device and a method of manufacturing a semiconductor device

Abstract

The present invention relates to a semiconductor device (100) that prevents sidewall profile damages during etch, preferably a deep reactive ion etching, of a through silicon via, TSV, (150) through a Si layer (110) of a stack in the semiconductor device (100). This is achieved by, in a via-last process, using a first conductive material (130, 130', 130'') embedded in an insulating layer (120) of the stack as an etch stop. The even TSV sidewall profile thus obtained simplifies subsequent metallization of the TSV using physical vapor deposition, PVD. The present invention further includes a method of manufacturing such a semiconductor device (100). The improved, more reliable, metallization obtained using the inventive semiconductor device (100) leads to improved conductivity of the TSV (150), as well as a less costly and complex manufacturing process with improved yield.

Description

[0001] A SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A

[0002] SEMICONDUCTOR DEVICE

[0003] TECHNICAL FIELD

[0004] The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.

[0005] Specifically, the present invention relates to a semiconductor device and a method of manufacturing a semiconductor device in a manner that facilitates providing the semiconductor device with a through- silicon via (TSV) using a via-last process.

[0006] BACKGROUND

[0007] Packaging of high-density integrated circuits (ICs) is a challenging task, particularly considering the need for electrical connections able to reduce the distance that the signal needs to travel, while not impacting the chip footprint. One solution to this issue is to have vertical electrical interconnects that passes though the IC Silicon (Si) substrate, or Si layer. Such a vertical electrical interconnect is commonly referred to as a Through Silicon Via (TSV). In the semiconductor industry, through silicon vias (TSVs) are required in a broad range of application, such as three-dimensional (3D) and Micro Electromechanical Systems (MEMS) device packaging or stacking. The use of a combination of IC and MEMS processing, including TSVs, hence enables dies to be 3D stacked and removes the need for additional lateral space for traditional wire bond interconnections.

[0008] TSVs can be formed by various techniques, such as wet etching, plasma etching, drilling, electrical discharge machining, powder blasting, laser processing, etc. One common process for forming TSVs is deep reactive ion etching (DRIE). DRIE is a process that is a corner stone in the Micro Electromechanical System (MEMS) manufacturing industry where it is mainly used to etch deep, high aspect ratio features in silicon bulk wafers. The process involves the use of an etch gas, typically sulfur hexafluoride (SF6), that is introduced into a vacuum chamber containing the substrate to be etched. The gas is ionized using radio frequency power source which creates a plasma containing reactive ion species that can effectively etch Silicon (Si). To etch deep trenches in the silicon, a high bias is applied between the plasma and the substrate chuck (on which the substrate, or wafer, is mounted during processing), which accelerates the reactive ions towards the surface of the substrate material, in this case the Si. A photolithography mask or the like protects the areas on the substrate where etch is unwanted. A truly anisotropic etch with well-defined vertical Si walls can be achieved by a repeated cycle of etch and sidewall passivation steps, a method known as a “Bosch process”.

[0009] The building of ICs starts with manufacturing the actual components such as transistors, capacitors, resistors, MEMS structures etc. This is called the front-end- of-line (FEOL). After, and on top of that, all interconnections with wiring are built in multiple metal routing layers, a process named back-end-of-line (BEOL). The TSVs today are often done after the BEOL, which is called a “via-last” procedure.

[0010] The via-last procedure is drastically simplified if the DRIE can avoid reaching through the whole thickness of the wafers since processing becomes very difficult for wafers with through holes. One of the most challenging steps of etching deep holes, especially high aspect ratio holes such as TSVs, with the Bosch process or other forms of DRIE is the last step of the sequence, i.e. stopping the etch. In a standard complementary metal-oxide-semiconductor (CMOS) stack, the first material to be reached by the DRIE after the Si layer is an insulator, or insulating layer, comprising some type of oxide, e.g., but not limited to phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS) etc. The insulating layer thereby acts as an etch stop layer, preventing the etch from reaching through the entire thickness of the CMOS stack.

[0011] However, when a DRIE stops on an insulating layer a certain amount of over etch is required to compensate for etch variations across the wafer. During this over etch, the insulating etch stop layer is exposed to, and bombarded with, the positively charged ions that are present in the DRIE plasma. Since an insulator has poor electric charge transport ability, excess charges are accumulated in the insulating layer. This will subsequently lead to a buildup of a local electric field that will strongly distort the trajectories of further incoming etch ions from the plasma, i.e. will distort the etch profile. The trajectories of the ions will be deflected outward towards the Si sidewall which then has a different electric potential relative to the positively charged insulating layer. This results in an unwanted etching and roughening of the Si sidewalls of the hole or TSV, also referred to as notching of the Si sidewalls.

[0012] An uneven TSV profile means that it will be more difficult to achieve an even metallization using physical vapor deposition (PVD) techniques such as metal sputtering" Metallization with unsatisfactory coverage of course in turn leads to inferior conductivity properties of the resulting TSV. For an uneven TSV profile, more expensive metallization techniques such as atomic layer deposition (ALD) with a conductive layer such as platinum (Pt) must instead be used. Besides being a more expensive solution, ALD further suffers from other problems such as deficient adhesion to the underlying oxide, making the subsequent metallization and resulting conductivity result unreliable.

[0013] The problem of notching during plasma etching of Si is for example explained in the document “Charging effect simulation model used in simulations of plasma etching of silicon” by V. Ishchuk et al., Journal of Applied Physics (2012), 112(8).

[0014] Hence, there is a need for an improved solution for providing an IC with a TSV using a via-last process, compared to existing solutions.

[0015] SUMMARY

[0016] The object of the invention is to provide a solution for the identified problems. This is achieved by a semiconductor device and a method of manufacturing a semiconductor device, according to the appended independent claims.

[0017] A solution is hence described for how to prevent silicon (Si) sidewall profile damages during a deep reactive ion etching (DRIE) of a through silicon via (TSV) through the Si layer of a stack in a semiconductor device, in a via-last process, using a conductive material embedded in an insulating layer of the stack as an etch stop. The even TSV sidewall profile thus obtained simplifies subsequent metallization of the TSV by physical vapor deposition (PVD). The improved, more reliable, metallization results lead to improved conductivity of TSVs, and improved yield for the semiconductor devices obtained according to embodiments described herein.

[0018] In a first aspect of the invention, there is provided a method of manufacturing a semiconductor device. The method comprises providing a stack comprising a silicon, Si, layer, and an insulating layer. The Si layer has a front side and a back side. The insulating layer has a front side that is in contact with the back side of the Si layer, and a back side. The stack further comprises a first electrically conductive layer embedded in the insulating layer, wherein the first electrically conductive layer extends to and is in electrical contact with the back side of the Si layer and is arranged to act as a first etch-stop layer for a deep reactive ion etching, DRIE, process from the front side of the Si layer. The method further comprises etching a through silicon via, TSV, from the front side of the Si layer to the first electrically conductive layer. Thereafter, the method comprises insulating the TSV from the Si layer and providing electrical contact between the TSV and an electrically conductive layer in the stack that is arranged to act as a routing layer.

[0019] Thereby, a semiconductor device with a TSV is provided. Since the layers are stacked before the TSV is etched, the method described is a via last process. Using known standard CMOS stacks or the like, the first material in the insulating layer that would be reached by the DRIE would be an insulator, for example some type of oxide such as PSG, TEOS, etc. Suitably, by having the first electrically conductive layer embedded in the insulating layer, and being arranged to act as an etch stop layer that stops the etching before DRIE reaches the insulating material of the insulating layer, the charge accumulation in the insulating material that would otherwise be the result of over etching before the etch process is stopped is avoided. Suitably, by using an electrically conductive layer, herein the first electrically conductive layer, as the stop layer when etching the TSV, problems with notching and other etch induced damaging or distortion of the Si sidewalls, i.e. the inner side walls of the TSV, are thereby greatly reduced or even completely eliminated. Hence, the resulting TSV will have very even and straight inner side walls, i.e. a straight and even profile. This in turn leads to the advantage that the TSV is much easier to metallize compared to an uneven profile, e.g. a profile affected by notching. For example, when using metal deposition, such as PVD, the seed layer coverage will be improved because the profile of the TSV is more even, which in turn allows for electroplating of the whole TSV, all the way to the chosen connecting metal (or other electrically conductive material) in the stack. The improved metallization of the TSV provides more reliable electrical contact, which contributes to increased semiconductor device manufacturing yield. Furthermore, the inventive method provides the advantage that the etch process is simplified and faster when the over etch becomes non-critical, since it eliminates the need for using a 2-step DRIE processes with timed soft-landing step to reduce notching. Such 2-step DRIE often requires time consuming and destructive inspections of one or several pilot wafers to perfectly time the etch and adjust for etch variations in the DRIE tool that may vary over time depending on the specific chamber condition. Using the inventive method however, over etching no longer poses a problem, since the DRIE never reaches the insulating material of the insulating layer. The stack may further comprise a second electrically conductive layer embedded in the insulating layer, wherein the second electrically conductive layer is arranged to act as a routing layer. The second electrically conductive layer hence enables electrical connection to the TSV and / or between different electrical components and / or power sources when the semiconductor device is used.

[0020] The stack may comprise at least one semiconductor component or micro electromechanical systems (MEMS) component, comprised in the Si layer and / or the insulating layer and / or in another additional layer of the stack and / or attached or electrically connected to the semiconductor device. At least one of the at least one semiconductor component or MEMS component may be in electrical contact with the TSV.

[0021] The method step of providing electrical contact between the TSV and an electrically conductive layer in the stack that is arranged to act as a routing layer may comprise providing electrical contact between the TSV and the first electrically conductive layer. Alternatively, it may comprise providing electrical contact between the TSV and the second electrically conductive layer.

[0022] In a first embodiment of the first aspect, the electrically conductive layer in the stack arranged to act as a routing layer is the second electrically conductive layer. In this embodiment, the first electrically conductive layer extends outside a bottom circumference of the etched TSV and the second electrically conductive layer is at least partially inside the bottom circumference of the etched TSV. In this embodiment, insulating the TSV from the Si layer comprises dry etching and / or wet etching at the bottom of the TSV, such that the TSV is extended to the insulating layer and thereafter passivating a set of inner walls of the TSV. The set of inner walls of the TSV comprises the inner surfaces of the vertical side walls and the bottom (horizontal bottom) of the TSV. Providing electrical contact between the TSV and the electrically conductive layer in the stack arranged to act as a routing layer then comprises etching at the bottom of the TSV to the second electrically conductive layer, thereby extending the TSV to the second electrically conductive layer. Thereafter, the method comprises metallizing the set of inner walls, i.e. the inner surfaces of the vertical side walls and the bottom, of the resulting TSV.

[0023] Suitably, a semiconductor device with a notch-free TSV that does not go through the entire thickness of the wafer is thereby obtained, by a via-last process. In a second embodiment of the first aspect, the electrically conductive layer in the stack arranged to act as a routing layer is the first electrically conductive layer. In this embodiment, the first electrically conductive layer comprises at least a first and a second separate section, wherein the first section is comprised within and does not contact the bottom circumference of the etched TSV, while the second section is outside and is electrically isolated from the bottom circumference of the etched TSV. The first section and the second section are in electrical contact with each other via another conductive layer or element comprised in the insulating layer or being attached or connected tothe insulating layer. In this second embodiment, insulating the TSV from the Si layer comprises passivating the set of inner walls (the inner surfaces of the vertical side walls and the bottom of the TSV) of the TSV, and then cutting the electrical path, by breaking the electrical connection between the first section and the second section of the first electrically conductive layer. In this second embodiment, providing electrical contact between the TSV and the electrically conductive layer in the stack arranged to act as a routing layer comprises etching at the bottom of the TSV to the first section of the first electrically conductive layer, thereby extending the TSV to the first section of the first electrically conductive layer, and then metallizing the set of inner walls of the resulting TSV.

[0024] Suitably, a semiconductor device with a notch-free TSV that does not go through the entire thickness of the wafer is thereby obtained, by a via-last process.

[0025] One such conductive layer or element may be a top electrode comprise on the back side of the insulating layer, wherein the first section and the second section are in electrical contact with each other via the top electrode. Cutting the electrical path between the first section and the second section of the first electrically conductive layer may then comprise dry etching and / or wet etching through the top electrode at a location between the connection of the top electrode to the first section of the first electrically conductive layer and the connection of the top electrode to the second section of the first electrically conductive layer.

[0026] In a third embodiment of the first aspect, the electrically conductive layer in the stack arranged to act as a routing layer is the first electrically conductive layer. In this embodiment, the first electrically conductive layer comprises at least one of a first section and a second section, wherein the first section is comprised within and does not contact the bottom circumference of the etched TSV, while the second section is outside and is electrically isolated from the bottom circumference of the etched TSV. In this third embodiment, each of the at least one first section and / or second section is connected to an external power supply or external electrical connection. In the third embodiment, insulating the TSV from the Si layer comprises passivating the inner walls of the TSV, and then cutting the electrical path by breaking the electrical connection to each of the at least one first section and / or second section. Providing electrical contact between the TSV and the electrically conductive layer in the stack arranged to act as a routing layer in this embodiment comprises etching at the bottom of the TSV until the first section of the first electrically conductive layer is reached, thereby extending the TSV to the first section of the first electrically conductive layer, and thereafter metallizing the set of inner walls of the resulting TSV.

[0027] Suitably, a semiconductor device with a notch-free TSV that does not go through the entire thickness of the wafer is thereby obtained, by a via-last process.

[0028] In the third embodiment, breaking the electrical connection to each of the at least one first section and / or second section of the first electrically conductive layer may comprise breaking the connection between each of the at least one first section and / or second section and the external power supply, or respective external power supply, to which it is connected.

[0029] In a fourth embodiment of the first aspect, the electrically conductive layer in the stack arranged to act as a routing layer is the first electrically conductive layer. In this embodiment, the first electrically conductive layer is at least partially inside a bottom circumference of the etched TSV and also extends outside the bottom circumference of the etched TSV. In the fourth embodiment, insulating the TSV from the Si layer comprises selectively removing part of the first electrically conductive layer to divide the first electrically conductive layer into a first section and a second section, wherein the first section is comprised within and does not contact the bottom circumference of the etched TSV, and wherein the second section is outside and is electrically isolated from the bottom circumference of the etched TSV. Insulating the TSV from the Si layer then comprises passivating a set of inner walls of the TSV. Providing electrical contact between the TSV and the electrically conductive layer in the stack arranged to act as a routing layer in this embodiment comprises etching at the bottom of the TSV to the first electrically conductive layer, thereby extending the TSV to the first electrically conductive layer, and thereafter metallizing a set of inner walls of the resulting TSV. Suitably, a semiconductor device with a notch-free TSV that does not go through the entire thickness of the wafer is thereby obtained, by a via-last process.

[0030] In a fifth embodiment of the first aspect, the electrically conductive layer in the stack arranged to act as a routing layer is the first electrically conductive layer. In this embodiment, the first electrically conductive layer extends outside a bottom circumference of the etched TSV. The first electrically conductive layer in this embodiment comprises a first electrically conductive material facing the Si layer and a second electrically conductive material, different from the first electrically conductive material, that is in electrical contact with the first electrically conductive material. The first electrically conductive material is at least partially inside a bottom circumference of the etched TSV and also extends outside the bottom circumference of the etched TSV and the second electrically conductive material comprises at least a first section that is comprised within and does not contact the bottom circumference of the etched TSV, as seen from a top view. In this embodiment, insulating the TSV from the Si layer comprises selectively etching the first electrically conductive material against the second electrically conductive material from the front side of the Si layer, thereby extending the TSV to the second electrically conductive material of the first electrically conductive layer, and thereafter passivating a set of inner walls of the TSV. Providing electrical contact between the TSV and the electrically conductive layer in the stack arranged to act as a routing layer in this embodiment comprises etching at the bottom of the TSV to the first electrically conductive layer, thereby extending the TSV to the first electrically conductive material of the first electrically conductive layer, and finally metallizing a set of inner walls of the resulting TSV.

[0031] Suitably, a semiconductor device with a notch-free TSV that does not go through the entire thickness of the wafer is thereby obtained, by a via-last process.

[0032] In a sixth embodiment of the first aspect, the electrically conductive layer in the stack arranged to act as a routing layer is the first electrically conductive layer. In this embodiment, the first electrically conductive layer extends outside a bottom circumference of the etched TSV and comprises a continuous first electrically conductive material and a second electrically conductive material, different from the first electrically conductive material, that is in electrical contact with the first electrically conductive material. In this embodiment, the second electrically conductive material faces the Si layer. The first electrically conductive material is at least partially inside a bottom circumference of the etched TSV and also extends outside the bottom circumference of the etched TSV. The second electrically conductive material comprises at least a first section that is comprised within and does not contact the bottom circumference of the etched TSV and a second section that is outside the bottom circumference of the etched TSV, all as seen in a top view. In this embodiment, insulating the TSV from the Si layer comprises selectively etching the first electrically conductive material against the second electrically conductive material from the front side of the Si layer, thereby dividing the first electrically conductive layer into a first section and a second section separated from the first section, and thereafter passivating a set of inner walls of the TSV. Providing electrical contact between the TSV and the electrically conductive layer in the stack arranged to act as a routing layer in this embodiment comprises etching at the bottom of the TSV to the first electrically conductive layer, thereby extending the TSV to the first electrically conductive material of the first electrically conductive layer, and finally metallizing a set of inner walls of the resulting TSV.

[0033] Suitably, a semiconductor device with a notch-free TSV that does not go through the entire thickness of the wafer is thereby obtained, by a via-last process.

[0034] In a seventh embodiment of the first aspect, the electrically conductive layer in the stack arranged to act as a routing layer is the first electrically conductive layer. In this embodiment, the first electrically conductive layer extends outside a bottom circumference of the etched TSV, and the semiconductor device further comprises an additional insulating layer embedded in the insulating layer. The additional insulating layer partially overlaps with the first electrically conductive layer, is arranged between a part of the first electrically conductive layer and the Si layer and extends from the outer periphery of said part of the first electrically conductive layer to inside the bottom circumference of the etched TSV. In this embodiment, insulating the TSV from the Si layer comprises selectively removing part of the first electrically conductive layer to divide the first electrically conductive layer into a first section and a second section. The first section is partly comprised within the bottom circumference of the etched TSV and further comprises the part of the first electrically conductive layer that overlaps the additional insulating layer, and the second section is outside and is electrically isolated from the bottom circumference of the etched TSV. The second section is further electrically isolated from the first section. Insulating the TSV from the Si layer further comprises passivating a set of inner walls of the TSV. Providing electrical contact between the TSV and the electrically conductive layer in the stack arranged to act as a routing layer in this embodiment comprises etching at the bottom of the TSV to the first electrically conductive layer, thereby extending the TSV to the first electrically conductive layer, and thereafter metallizing a set of inner walls of the resulting TSV.

[0035] Suitably, a semiconductor device with a notch-free TSV that does not go through the entire thickness of the wafer is thereby obtained, by a via-last process.

[0036] In a second aspect of the invention, there is provided a semiconductor device comprising a stack of a silicon, Si, layer having a front side and a back side, and an insulating layer having a front side that is in contact with the back side of the Si layer, and a back side. The semiconductor device further comprises a first electrically conductive layer embedded in the insulating layer, wherein the first electrically conductive layer extends to and is in electrical contact with the back side of the Si layer and is arranged to act as a first etch-stop layer for a deep reactive ion etching, DRIE, process from the front side of the Si layer.

[0037] Suitably, a semiconductor device start wafer is provided, that can be processed to obtain a notch-free TSV that does not go through the entire thickness of the wafer, using a via-last process.

[0038] In some embodiments of the second aspect, the semiconductor device further comprises a second electrically conductive layer embedded in the insulating layer, wherein the second electrically conductive layer is arranged to act as a routing layer.

[0039] In a first embodiment of the second aspect, wherein the semiconductor device comprises the second electrically conductive layer embedded in the insulating layer, the first electrically conductive layer extends outside a bottom circumference of the etched TSV, wherein the second electrically conductive layer is electrically isolated from the first electrically conductive layer and from the Si layer, and the second electrically conductive layer is arranged to act as a second etch-stop layer for an etch process from the front side of the Si layer. A semiconductor device start wafer is thus provided, that can be processed to obtain a notch-free TSV that does not go through the entire thickness of the wafer, using a via-last process, according to a process that suitably only requires processing steps from the front side of the semiconductor device.

[0040] In a second embodiment of the second aspect, the first electrically conductive layer comprises at least a first section and a second section, wherein the first section is comprised within and does not contact the bottom circumference of the etched TSV, and the second section is outside and is electrically isolated from the bottom circumference of the etched TSV. The first section and the second section are in electrical contact with each other via another conductive layer or element that is comprised in the insulating layer or attached or connected to the insulating layer. Thereby, a semiconductor device start wafer is provided that can be processed to obtain a notch-free TSV that does not go through the entire thickness of the wafer, using a via-last process, according to a process that advantageously does not require removing the first electrically conductive layer.

[0041] The other conductive layer or element semiconductor device may in this second embodiment comprise at least one top electrode on the back side of the insulating layer, wherein the first section and the second section are in electrical contact with each other via the at least one top electrode.

[0042] In a third embodiment of the second aspect, the semiconductor device comprises a first top electrode and a second top electrode on the back side of the insulating layer. In this embodiment, the first electrically conductive layer comprises at least a first section and a second section, wherein the first section is comprised within and does not contact the bottom circumference of the etched TSV, and wherein the second section is outside and is electrically isolated from the bottom circumference of the etched TSV. Each of the first and second sections of the electrically conductive layer is further electrically connected to a respective one of the first and second top electrodes. Thereby, a semiconductor device start wafer is provided that can be processed to obtain a notch-free TSV that does not go through the entire thickness of the wafer, using a via-last process, according to a process that suitably only requires processing steps from the front side of the semiconductor device and that advantageously does not require removing the first electrically conductive layer.

[0043] In a fourth embodiment of the second aspect, the first electrically conductive layer extends outside a bottom circumference of the etched TSV. Thereby, a semiconductor device start wafer is provided that can be processed to obtain a notch-free TSV that does not go through the entire thickness of the wafer, using a via-last process, according to a process that suitably only requires processing steps from the front side of the semiconductor device and that advantageously does not require removing the first electrically conductive layer. In a fifth embodiment of the second aspect, the first electrically conductive layer extends outside a bottom circumference of the etched TSV. The first electrically conductive layer in this embodiment comprises a first electrically conductive material facing the Si layer and a second electrically conductive material, different from the first electrically conductive material, that is in electrical contact with the first electrically conductive material. The first electrically conductive material is at least partially inside a bottom circumference of the etched TSV and also extends outside the bottom circumference of the etched TSV, as seen in a top view. The second electrically conductive material comprises at least a first section that is comprised within and does not contact the bottom circumference of the etched TSV and a second section that is outside the bottom circumference of the etched TSV, as seen in the top view. Thereby, a semiconductor device start wafer is provided that can be processed to obtain a notch-free TSV that does not go through the entire thickness of the wafer, using a via-last process, according to a process that suitably only requires processing steps from the front side of the semiconductor device and that advantageously enables selectively etching the first electrically conductive material against the second electrically conductive material to obtain a division of the first electrically conductive layer into a first section and a second section that are separated from each other.

[0044] In a sixth embodiment of the second aspect, the first electrically conductive layer extends outside a bottom circumference of the etched TSV. The first electrically conductive layer in this embodiment comprises a first electrically conductive material and a second electrically conductive material that is different from the first electrically conductive material and that is in electrical contact with the first electrically conductive material. The second electrically conductive material faces the Si layer. The first electrically conductive material is at least partially inside a bottom circumference of the etched TSV and also extends outside the bottom circumference of the etched TSV, as seen in the top view, and the second electrically conductive material comprises at least a first section that is comprised within and does not contact the bottom circumference of the etched TSV and a second section that is outside the bottom circumference of the etched TSV, as seen in the top view. Thereby, a semiconductor device start wafer is provided that can be processed to obtain a notch-free TSV that does not go through the entire thickness of the wafer, using a via-last process, according to a process that suitably only requires processing steps from the front side of the semiconductor device and that advantageously enables selectively etching the first electrically conductive material against the second electrically conductive material to obtain a division of the first electrically conductive layer into a first section and a second section that are separated from each other.

[0045] In a seventh embodiment of the second aspect, the first electrically conductive layer extends outside a bottom circumference of the etched TSV. The semiconductor device in this embodiment further comprises an additional insulating layer embedded in the insulating layer, wherein the additional insulating layer partially overlaps with the first electrically conductive layer. The additional insulating layer is arranged between a part of the first electrically conductive layer and the Si layer and extends from the outer periphery of said part of the first electrically conductive layer to inside the bottom circumference of the etched TSV. Thereby, a semiconductor device start wafer is provided that can be processed to obtain a notch-free TSV that does not go through the entire thickness of the wafer, using a via-last process, according to a process that suitably only requires processing steps from the front side of the semiconductor device and that advantageously does not require removing more than a small section of the first electrically conductive layer.

[0046] The semiconductor device according to any embodiment may further comprise at least one semiconductor component or MEMS component that is comprised in the Si layer and that is in electrical contact with at least one semiconductor component or MEMS component comprised in the Si layer, or comprised in another layer of the stack, or attached or electrically connected to the semiconductor device.

[0047] The invention also includes a semiconductor device resulting from the method of manufacturing a semiconductor device according to any described embodiment herein, that is the description, the claims, and the drawings.

[0048] For any embodiment of the first or second aspect, each of the first electrically conductive layer and the second electrically conductive layer may comprise or consist of a metal material. Preferably, the metal material may comprise the same material as any metal used in the FOEL material stack for simpler integration, for example tungsten, W, or aluminium, Al.

[0049] For any embodiment of the first or second aspect, the semiconductor device may be is a CMOS device. Any advantage described in connection with the first aspect of the invention, i.e. the manufacturing method, is equally applicable to corresponding embodiments of the second aspect of the invention, i.e. the semiconductor device, and vice versa.

[0050] Many additional benefits and advantages of the present invention will be readily understood by the skilled person in view of the detailed description below.

[0051] DRAWINGS

[0052] The invention will now be described in more detail with reference to the appended drawings, wherein:

[0053] Fig. 1 illustrates problems of etching a TSV in a semiconductor device using prior art technique;

[0054] Fig. 2 schematically discloses layers and elements of a semiconductor device according to the invention;

[0055] Fig. 3 is a flow chart showing a method for manufacturing a semiconductor device with a TSV according to one or more embodiments of the invention;

[0056] Figs. 4a-f schematically illustrate a first embodiment of a semiconductor device according to the invention, and a process sequence of a first embodiment of a manufacturing method according to the invention;

[0057] Figs. 5a-c schematically discloses a top view of some alternative designs of the first electrically conductive layer, i.e. the first etch stop layer, of a semiconductor device according to the first embodiment;

[0058] Fig. 6 schematically discloses an example of a design of electrodes, for the first semiconductor device embodiment, that matches the surrounding metal pattern density;

[0059] Figs. 7a-f schematically illustrate a second embodiment of a semiconductor device according to the invention, and a process sequence of a second embodiment of a manufacturing method according to the invention;

[0060] Figs. 8a-c schematically discloses a top view of some alternative designs of the first electrically conductive layer, i.e. the first etch stop layer, of a semiconductor device according to the second embodiment; Fig. 9 schematically discloses an example of a design of electrodes, for the second semiconductor device embodiment, that matches the surrounding metal pattern density;

[0061] Figs. lOa-f schematically illustrate a third embodiment of a semiconductor device according to the invention, and a process sequence of a third embodiment of a manufacturing method according to the invention;

[0062] Figs. 1 la-h schematically discloses a top view of some alternative designs of the first electrically conductive layer, i.e. the first etch stop layer, of a semiconductor device according to the third embodiment;

[0063] Fig. 12 is a flow chart detailing some of the steps of Fig. 3 according to a first embodiment of the inventive method;

[0064] Fig. 13 is a flow chart detailing some of the steps of Fig. 3 according to a second embodiment of the method;

[0065] Figs. 14 a-f schematically illustrate a fourth embodiment of a semiconductor device according to the invention, and a process sequence of a fourth embodiment of a manufacturing method according to the invention;

[0066] Figs. 15a-c schematically discloses a top view of some alternative designs of the first electrically conductive layer, i.e. the first etch stop layer, of a semiconductor device according to the fifth or sixth embodiment;

[0067] Figs. 16 a-f schematically illustrate a fifth embodiment of a semiconductor device according to the invention, and a process sequence of a fifth embodiment of a manufacturing method according to the invention;

[0068] Figs. 17 a-f schematically illustrate a sixth embodiment of a semiconductor device according to the invention, and a process sequence of a sixth embodiment of a manufacturing method according to the invention;

[0069] Figs. 18 a-f schematically illustrate a seventh embodiment of a semiconductor device according to the invention, and a process sequence of a seventh embodiment of a manufacturing method according to the invention;

[0070] Figs. 19a-b schematically discloses a top view of some alternative designs of the first electrically conductive layer, i.e. the first etch stop layer, of a semiconductor device according to the seventh embodiment; and Fig. 20 is a flow chart detailing some of the steps of Fig. 3 according to fourth, fifth, sixth and seventh embodiments of the method;

[0071] All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary in order to elucidate the respective embodiments, whereas other parts may be omitted or merely suggested. Any reference number appearing in multiple drawings refers to the same object or feature throughout the drawings, unless otherwise indicated.

[0072] DETAILED DESCRIPTION

[0073] The problem with notching is schematically illustrated in Fig. 1, which shows a prior art CMOS stack and DRIE of a TSV in the CMOS stack. Fig. 1 shows a stack with a Si layer (Si bulk) 1, and an insulating layer 3. An etch mask 4 is applied on the Si layer 1 and a DRIE is performed to form a TSV 2. The insulating layer 3 thereby acts as an etch stop layer, preventing the etch from reaching through the entire thickness of the CMOS stack. In Fig. 1, positively charged ions 6 in the DRIE plasma are shown, having a direction vertically downwards in the figure, towards the insulating layer 3. As explained herein, when a DRIE stops on an insulating layer a certain amount of over etch is required to compensate for etch variations across the wafer. During this over etch, the insulating etch stop layer 3 is exposed to, and bombarded with, the positively charged ions 6 that are present in the DRIE plasma, whereby excess charges are accumulated in the insulating layer 3. This will subsequently lead to a buildup of a local electric field that will strongly distort the trajectories of further incoming etch ions from the plasma, as shown in the figure by the curved direction of the positively charged ions 6 that are approaching the insulating layer 3. This in turn distorts the etch profile, as the etching is also performed on the lower parts of the sidewalls of the TSV 2 resulting in an unwanted etching and roughening of the Si sidewalls of TSV 2. As illustrated in Fig. 1, it is often most severe right next to the insulating layer 3 where it can create notching 5 of the Si sidewalls. This is a well- known problem for etching high-aspect ratio features such as metal interconnects through a Si wafer.

[0074] This invention discloses a solution for preventing notching using an IC stack having an embedded electrically conductive layer that is in contact with the DRIE plasma and the Si layer / Si bulk at the same time, during the DRIE process. It is previously known in the art that using a conductive material as a DRIE etch stop layer mitigates the effects of notching in an Si wafer during an over etch process. This is e.g. explained in the document “Simultaneous Through-Silicon Via and Large Cavity Formation Using Deep Reactive Ion Etching and Aluminum Etch-Stop Layer” by J. Tian et al., Electronic Components and Technology Conference, 2008, ECTC 2008, 58th. The document discloses DRIE through a Si wafer using a conductive material, in this case aluminum (Al), as an etch stop layer. For this purpose, a conductive etch-stop layer is deposited onto the backside of the Si wafer before DRIE is carried out. Thereafter, as a final step, the etch-stop layer is removed. The resulting product is an Si wafer with a TSV having an even inner wall profile, without notching, and extending though the entire wafer thickness, i.e. the entire thickness of the semiconductor device. As described herein, a wafer with a hole through its entire thickness is hard to further process for obvious reasons. All deposited material, whether it is standard spin-on lithography resist, oxide deposition or metal deposition etc., it will leak through the wafers and contaminate chucks in standard IC and MEMS manufacturing tools. Any dry plasma etch such as DRIE or oxide etch will damage chucks at exposed areas. These tools also often use vacuum to clamp the wafers and such vacuum is not possible to maintain with holes through the wafers.

[0075] The inventors have realized that by embedding an electrically conductive layer into an insulating layer of an IC, e.g. a CMOS stack, and arranging the electrically conductive layer (or layers, which may also include electrically conductive routings between layers) such that it is simultaneously in contact with the DRIE plasma and the Si layer during the DRIE process, a semiconductor device in the form of an IC with a notch-free TSV that does not go through the entire thickness of the stack can be obtained. Integrating, or embedding, electrically conductive one or more electrically conductive layer in, i.e. as part of, the IC, arranged to act as an etch stop layer, is what enables the present invention. If the etch process is a DRIE etch process, the electrically conductive etch stopping layer is selected to have a high etch selectivity to DRIE Si etching. The electrically conductive layer(s) is / are embedded in the IC, specifically an insulating layer of the IC, during FEOL or BEOL. Advantageously, this means that the benefits of both the even profile TSV and a resulting semiconductor device that has a reliable electrically conductive through connection and that is easy to handle and process are achieved.

[0076] An electrically conductive layer in any embodiment herein may comprise a continuous conductive material in one part, having at least two separate sections, or being a patterned material, e.g. a pattern metal. A layer may cover a small part of the horizontal cross-section area of the stacked semiconductor device, e.g. being in the form of a conductive pad or the like, cover a large part of it, or cover the entire horizontal cross-section area of the stacked semiconductor device.

[0077] Anytime we refer to a set of inner walls of the TSV herein, this includes the (inner surfaces of the) inner (substantially vertical) side walls and (substantially horizontal) bottom of the TSV in its present form, i.e. the TSV according to the step of the process that is currently being described, regardless of whether the DRIE has just been performed, if the TSV has been extended by one or more further etch process, or whether the TSV has been passivated and / or metallized, etc.

[0078] The at least one semiconductor component or MEMS component referred to herein may comprise transistors, capacitors, resistors, MEMS structures etc. Such semiconductor and / or MEMS components may be embedded in the Si layer, and may have been manufactured from, or placed in, the Si layer during the FEOL process. Alternatively, or additionally, such semiconductor components or MEMS components may be embedded in or placed on the insulating layer of the stack.

[0079] As is evident to a person skilled in the art, it is very hard, often impossible, to achieve perfect shapes in MEMS manufacturing. Therefore, when it is stated herein that a component, layer, section of layer, etch area or the like has a certain size or form, the defined size or form includes the exact shape or form as well as the substantially same shape or form, within manufacturing tolerances, especially in embodiments wherein MEMS technology is applied.

[0080] In insulating layer referred to herein comprises an insulating material, an insulator, i.e. a material with low electrical conduction. The insulating material may be or comprise an oxide, e.g. but not limited to PSG or TEOS. If the semiconductor device described is a CMOS device, comprising a CMOS stack, the insulating layer is typically a CMOS oxide layer.

[0081] The term embedded as used herein may also be referred to as enclosed in, or completely integrated into.

[0082] In a first aspect of the invention, a method of manufacturing a semiconductor device 100 will first be described with reference to Figs. 3, 12, 13 and 14, and also referring to Figs. 2 and 4a-l lh. Fig. 3 is a flow chart showing a method for manufacturing a semiconductor device with a TSV. The method comprises:

[0083] In a step 310: providing a stack comprising a silicon, Si, layer 110 and an insulating layer 120.

[0084] The Si layer 110 has a front side 111 and a back side 112.

[0085] The front side 111 of the Si layer 110 is also the front side of the semiconductor device 100 unless additional layers have been provided on top of the Si layer 110.

[0086] The insulating layer 120 has a front side 121 that is in contact with the back side 112 of the Si layer, and a back side 122. The insulating layer 120 comprises a first electrically conductive layer 130, 130’ embedded in the insulating layer 120, wherein the first electrically conductive layer 130, 130’ extends to and is in electrical contact with the back side 112 of the Si layer, and is thereby arranged to act as a first etchstop layer for a deep reactive ion etching, DRIE, process from the front side 111 of the Si layer 110.

[0087] The back side 122 of the insulating layer 120 is also the back side of the semiconductor device 100 unless additional layers have been attached to the back side 122 of the insulating layer 120.

[0088] Thereby, there is provided an IC stack having an embedded electrically conductive layer that is in contact with the DRIE plasma and the Si layer / Si bulk at the same time, during the DRIE process.

[0089] In a step 320: etching a TSV 150 from the front side 111 of the Si layer 110 to the first electrically conductive layer 130, 130’.

[0090] That the first electrically conductive layer 130, 130’ extends to and thus is in electric contact with the back side 112 of the Si layer 110 may also be expressed as the first electrically conductive layer 130, 130’ extending to the front side 121 of the insulating layer 120. Due to this embedded arrangement of the first electrically conductive layer 130, 130’ in the insulating layer 120, an etching process, e.g. a DRIE process, from the front side 111 of the Si layer 110, will after etching through the Si layer 110 reach the first electrically conductive layer 130, 130’. Thereby, the first electrically conductive layer 130, 130’ is arranged to act as an etch stop layer, and any charge accumulation that is the result of over etch into an insulating layer is avoided. Hence, the TSV obtained by step 320 advantageously has an even etch profile. Of course, the etch area for the intended TSV must be at least partially overlapping in the horizonal plane, i.e. as seen in a top view, with the embedded first electrically conductive layer 130, 130’. The placement of the first electrically conductive layer 130, 130’ in the insulating layer 120 may therefore differ depending on the application for which it is to be used.

[0091] In a step 330: insulating the TSV 150 from the Si layer 110.

[0092] Insulating the TSV 150 from the Si layer 110 may also be expressed as breaking the electrical contact between the TSV 150 and the Si layer 110.

[0093] In a step 340: providing electrical contact between the TSV 150 and an electrically conductive layer in the stack that is arranged to act as a routing layer.

[0094] In some embodiments, the electrically conductive layer in the stack that is arranged to act as a routing layer. In these embodiments, providing electrical contact between the TSV 150 and an electrically conductive layer in the stack that is arranged to act as a routing layer comprises providing electrical contact between the TSV 150 and the first electrically conductive layer 130, 130’.

[0095] In some embodiments, the semiconductor device 100 further comprises a second electrically conductive layer 140, 140’, 140” embedded in the insulating layer 120, wherein the second electrically conductive layer 140, 140’, 140” is arranged to act as a routing layer. There may be more than one second electrical layer 140. Additionally, or alternatively, at least one second electrical layer 140 may comprise more than one separate section. In these embodiments, providing electrical contact between the TSV 150 and an electrically conductive layer in the stack that is arranged to act as a routing layer may comprise providing electrical contact between the TSV 150 and a second electrically conductive layer 140, 140’, 140”.

[0096] Insulating the TSV 150 from the Si layer 110 and providing an electrical contact between the TSV 150 and the second conductive layer 140, 140’, 140”, corresponding to the steps 330 and 340 in the figures, may be performed in parallel or in sequence. If they are performed in sequence, the order of the steps may vary depending on what is preferable for different applications.

[0097] Thereby, a semiconductor device 100 with a TSV 150 is provided, using a via last process. The TSV does not go through the entire thickness of the semiconductor device, meaning that it is easy to handle and process further, as it does not suffer from the disadvantages of a semiconductor device with holes through the entire thickness of the device. Suitably, by using an electrically conductive layer, herein the first electrically conductive layer, as the stop layer when etching the TSV, the resulting TSV will have very even and straight inner side walls, i.e. a straight and even profile.

[0098] For embodiments wherein the providing electrical contact between the TSV 150 and the second electrically conductive layer 140, 140’, 140” comprises metallizing the inner walls (side walls and bottom) of the TSV 150, the even, notch-free, etch profile of the TSV 150 achieved by the present invention leads to the advantage that the TSV 150 is much easier to metallize in a subsequent processing step. This is especially true when using metal deposition techniques such as PVD, or metal sputtering. Thereby, the even etch profile of the TSV 150 enables the use of such metallization techniques, in contrast to having to use e.g. the more expensive metallization technique of ALD with a conductive layer of e.g. Pt, which besides from being comparatively much more expensive also suffers from problems such as poor or unreliable adhesion to the underlying oxide. An improved metallization of the TSV, using the PVD technique, provides more reliable electrical contact, which contributes to increased semiconductor device manufacturing yield. It further eliminates the need for using a pilot wafer, saving both time, material, and money in the manufacturing process.

[0099] The following section describes seven embodiments of the manufacturing method, or process flow, and corresponding embodiments of the resulting semiconductor device 100, in connection with Figs. 12, 13 and 20. In the embodiments of Figs. 12, 13 and 20the semiconductor device 100 is a CMOS device, or CMOS wafer. In the stacked CMOS device, the first and second electrically conductive layers are numbered following the order of the CMOS stack, where the first electrically conductive layer 130 and in some cases the sections 130’, 130” of the first electrically conductive layer are closer to the Si layer, or Si substrate, than the second conductive layer, or layers, 140, 140’, 140”. If there are more than one second conductive layers, these are arranged at different distances from the Si layer. The electrically conductive layers may consist of or comprise any electrically conductive material used in FEOL and / or BEOL that is selective in DRIE Si etching. Although the seven exemplary, nonlimiting, embodiments of Figs. 12, 13 and 20 all relate to CMOS wafers, the semiconductor device 100 could alternatively be generic bulk silicon that needs an electrical path through the wafer, having conductive materials stacked in a similar way as an IC architecture. The designs shown in the embodiments herein are of course only illustrational, and many other alternative arrangements are possible within the scope of the invention, i.e. within the scope of the appended independent claims.

[0100] A first method embodiment is illustrated by the process flow of Fig. 3 in combination with Fig. 12. In this first embodiment of the manufacturing method, the first electrically conductive layer 130 extends both inside and outside a bottom circumference 153 of the etched TSV 150. Thereby, the first electrically conductive layer 130 will be part of the TSV 150, i.e. form or be part of the bottom 151 of the TSV 150, and still be in contact with the Si layer 110 after the TSV 150 has been etched. The semiconductor device 100 in this embodiment further comprises a second electrically conductive layer 140, 140', 140" that is at least partially inside the bottom circumference 153 of the etched TSV 150.

[0101] The first method embodiment is thus performed on a start wafer corresponding to the first embodiment of the semiconductor device 100, e.g. as schematically illustrated in Fig. 4a. In this first method embodiment, and the corresponding start wafer of the first embodiment of the semiconductor device 100, there are different options for the shape, size, and arrangement of the first electrically conductive, etchstopping, layer 130. Three non-limiting options are illustrated in Figs. 5a to 5c.

[0102] The first electrically conductive layer 130 may before etching in step 320 cover the entire area intended for etching and an area surrounding the intended for etching, as seen from a top view. An example of this is shown in Fig. 5a, wherein the etch area for the TSV 150 is indicated by the outline 153 and the first electrically conductive layer 130 covers the whole etch area inside the outline 153 and continues outside the etch area on all sides. The outline 153 of the etch area is also referred to herein as the bottom circumference 153 of the TSV 150 that is obtained by the etching. The etch area and first electrically conductive layer 130 are in this embodiment shown as circular (substantially circular, within manufacturing tolerances) and concentrical when viewed from a top view. Other shapes of the first electrically conductive layer 130, and possibly also the TSV 150, as well as non- concentric arrangement of the first electrically conductive layer 130 in relation to the TSV 150 are of course also possible within the scope of this first method embodiment.

[0103] Alternatively, the first electrically conductive layer 130 may before etching cover the entire area intended for etching and an area surrounding the intended for etching, as seen from a top view, except for a cut-out area. An example is illustrated in Fig. 5b. This alternative design for the first embodiment will work as long as the first electrically conductive layer 130 is continuous (either as a continuous material or a patterned material extending in a continuous area enabling electrical contact in the continuous area) and partly extends both inside the etch area for the TSV 150, indicated by the outline 153 (i.e. the bottom circumference 153 of the TSV 150), and outside the same area.

[0104] Alternatively, the first electrically conductive layer 130 may before etching cover only part of the area intended for etching and part of the area surrounding it, as illustrated in Fig. 5c. Also in this case, this alternative design will work for the first embodiment as long as the first electrically conductive layer 130 is continuous (either as a continuous material or a patterned material extending in a continuous area enabling electrical contact in the continuous area) and partly extends both inside the etch area for the TSV 150, indicated by the outline 153, and outside the same area.

[0105] Fig. 6 schematically discloses an example of a design of electrodes for the first semiconductor device embodiment, that matches the surrounding metal pattern density, e.g. FEOL metal, as seen in a cross-sectional top view. In Fig. 6, the electrodes are exemplified as non-continuous sections of electrically conductive material evenly distributed along the bottom circumference 153 of the TSV 150. The sections of electrically conductive material together form the first electrically conductive layer 130 in this example.

[0106] Looking at the device 100, or a cross-section thereof, from the top view is herein to be understood as looking towards the device or cross-section along an axis perpendicular to the front side 111 of the Si layer 110 (assuming that the front side 111 is planar).

[0107] As is readily apparent to someone skilled in the art, the extension of a layer in a stack of layers refers to the extension of the layer in the plane of the layer, said plane having a normal that is parallel to the axis perpendicular to the front side 111 of the Si layer 110.

[0108] Turning again to Fig. 12, step 330 of insulating the TSV 150 from the Si layer 110, by breaking the electrical contact between the TSV 150 and the Si layer 110, according to this first method embodiment comprises two sub-steps 331 and 332, comprising: In a step 331: dry etching and / or wet etching at the bottom 151 of the TSV 150 such that the TSV 150 is extended to the insulating layer 120.

[0109] Etching in step 331 may be performed using any suitable method known in the art. In a non-limiting example a standard dry oxide etch that is directional and non- isotropic may be used.

[0110] Suitably, if an etch selective to the material being etched, here the material of the first electrically conductive layer 130, is applied, the inner vertical walls 152 of the TSV 150 do not need to be passivated before etching.

[0111] In a step 332: passivating a set of inner walls 151, 152 of the TSV 150.

[0112] In some embodiments, insulating the TSV 150 from the Si layer includes adding a passivating layer 125, as illustrated in Figs. 4d, 7c and lOd, to the set of inner walls 151, 152 of the TSV, in any suitable manner known in the art. In a non-limiting example, the passivation is achieved by depositing the passivation layer 125 on the set of inner walls 151, 152. The insulating layer or passivation layer 125 may comprise the same type of insulating material as the insulating layer 120, but it is not limited thereto. In some embodiments, the passivation layer 125 comprises an oxide.

[0113] As further shown in Fig. 12, step 340 of providing electrical contact between the TSV 150 and the electrically conductive layer in the stack that is arranged to act as the routing layer, in this embodiment the second electrically conductive layer 140, 140’ comprises two sub-steps 341 and 343, comprising:

[0114] In step 341: etching at the bottom 151 of the TSV 150 to the second electrically conductive layer 140’, thereby extending the TSV 150 to the second electrically conductive layer 140’.

[0115] In other words, step 341 comprises etching through the passivation added in step 332, e.g. the passivation layer 125, and the insulating layer 120, until the second electrically conductive layer 140’ is reached.

[0116] Preferably, the etch of step 341 is directional, vertically into the TSV from the front side 111 of the Si layer 110. Thereby the etching only removes passivation, such as the passivation layer 125, on planar horizontal surfaces like the bottom 151 of the TSV 150. In embodiments wherein the passivation layer 125 as well as the insulation layer comprise an oxide, the etching may suitably comprise standard directional plasma etching. Thereby, the second electrically conductive layer 140’ is arranged to act as an etch stop.

[0117] Alternatively, or additionally, the etching in step 341 may comprise dry etching and / or wet etching, or any other etch process suitable to the material to be etched.

[0118] In step 343: metallizing a set of inner walls 151, 152 of the resulting TSV 150.

[0119] The metallization may be performed in any suitable manner. However, due to the straight and even TSV profile achieved using embodiments presented herein improved metallization by metal sputter deposition, such as PVD, is facilitated. Metal sputtering, or sputter deposition, is cheaper, faster, and provides a more reliable metallization than e.g. ALD, as described herein.

[0120] For the second to seventh embodiments of the manufacturing method, only features that differ from the first embodiments will be described in detail. The same method step reference number in different embodiment refers to a method step that is performed in a similar manner for the different embodiments.

[0121] A second method embodiment is illustrated by the process flow of Fig. 3 in combination with Fig. 13. In this second embodiment of the manufacturing method, the first electrically conductive layer 130 comprises at least a first section 130’ and a second section 130”. The first section 130’ is comprised within and does not contact the bottom circumference 153 of the etched TSV 150. The second section 130” is outside and is electrically isolated from the bottom circumference 153 of the etched TSV 150. Thereby, the first section 130’ and the second section 130” of the first electrically conductive layer 130 are separated from each other in the plane of extension of the first electrically conductive layer 130, since the first section 130’ is part of the bottom 151 of the TSV 150 and is not in contact with the Si layer 110 after the TSV 150 has been etched, while the second part 130” is in contact with the Si layer 110 both before and after the TSV 150 has been etched, but does not extend to and is not in contact with the bottom 151 of the etched TSV 150.

[0122] The first section 130’ and the second section 130” are in this embodiment in electrical contact with each other via another conductive layer or element comprised in the insulating layer 120 or being attached or connected to the insulating layer 120. In other words, the second method embodiment is performed on a start wafer corresponding to the second embodiment of the semiconductor device 100, e.g. as schematically illustrated in Fig. 7a.

[0123] In some embodiments, the semiconductor device comprises a top electrode 170 on the back side 122 of the insulating layer 120, wherein top electrode 170 is the other conductive layer or element, and the first section 130’ and the second section 130” are in electrical contact with each other via the top electrode 170.

[0124] As shown in Fig. 13, step 330 of insulating the TSV 150 from the Si layer 110, by breaking the electrical contact between the TSV 150 and the Si layer 110, according to this second method embodiment comprises two sub-steps 332 and 333. Step 332 correspond to the passivating step 332 described in connection with Fig. 12. The method of Fig. 13 then comprises:

[0125] In sub-step 333: cutting the electrical path.

[0126] In this second embodiment, cutting the electrical path comprises breaking the electrical connection between the first section 130’ and the second section 130” of the first electrically conductive layer 130.

[0127] If a top electrode 170 is used to connect the first and second sections 130’, 130” of the first electrically conductive layer 130, sub-step 333 of cutting the electrical path between the first section 130’ and the second section 130” of the first electrically conductive layer 130 may comprise dry etching and / or wet etching, or using any other suitable separation method described herein or known in the art, through the top electrode 170 at a location between the connection of the top electrode 170 to the first section 130’ of the first electrically conductive layer 130 and the connection of the top electrode 170 to the second section 130” of the first electrically conductive layer 130.

[0128] In this second embodiment, step 340 of providing electrical contact between the TSV 150 and the electrically conductive layer in the stack that is arranged to act as the routing layer, in this embodiment the first electrically conductive layer 130, 130’, comprises the two sub-steps 342 and 343, comprising:

[0129] In sub-step 342: etching through the passivation layer 125 at the bottom of the TSV 150, from the front side 111 of the Si layer. In this embodiment, step 342 comprises etching at the bottom of the TSV 150 to the first section 130’ of the first electrically conductive layer 130, thereby extending the TSV 150 to the first section 130’ of the first electrically conductive layer 130.

[0130] Preferably, the etch of step 342 is directional, vertically into the TSV from the front side 111 of the Si layer 110. Thereby the etching only removes passivation, such as the passivation layer 125, on planar horizontal surfaces like the bottom 151 of the TSV 150.

[0131] In embodiments wherein the passivation layer 125 comprises an oxide, the etching may suitably comprise standard directional plasma etching. Alternatively, or additionally, the etching in step 341 may comprise dry etching and / or wet etching, or any other etch process suitable to the material to be etched.

[0132] Sub-step 343 is then performed according to any embodiment described in connection with Fig. 12.

[0133] In the second embodiment, there are many different options for the shape, size, and arrangement of the first electrically conductive, etch- stopping, layer 130. Three nonlimiting options are illustrated in Figs. 8a to 8c.

[0134] As shown in Fig. 8a, the bottom circumference 153 of the TSV 150 and the first section 130’ of the first electrically conductive layer 130 are in this example shown as circular and the second section 130” of the first electrically conductive layer 130 is shown as being circular with a circular mid-section cut-out as seen from a top view. The sections 130’, 130” and the bottom circumference 153, of the TSV 150, which may also be referred to herein as the bottom etch area, are in the example of Fig. 8a all concentrical. Other shapes of the first and second sections 130’, 130”, and possibly also the TSV 150, as well as non- concentric arrangement of the first section 130’ and / or the second section 130” in relation to the bottom circumference 153 of the TSV 150 are of course also possible within the scope of this second embodiment. What must be fulfilled in this second embodiment is that the first section 130’ is comprised within and does not contact the bottom circumference 153 of the etched TSV 150, while the second section 130” is outside and does not contact the bottom circumference 153 of the etched TSV 150.

[0135] Another alternative design under the second embodiment that fulfills this requirement is shown in Fig. 8b. The design of Fig. 8b is similar to that of Fig. 8a, except that the first section 130’ comprises a cut-out. Yet another alternative design under the second embodiment that fulfills the requirement is shown in Fig. 8c. In the example if Fig. 8c, the first section 130’ covers only part of the area intended for etching / the bottom circumference 153, and the second section 130” covers only a part of the area surrounding the bottom circumference 153.

[0136] In Figs. 8a-c the first and second sections 130’, 130” of the first electrically conductive layer 130 are illustrated as a concentric sections. The first and second sections 130’, 130” may be, but are not limited to being, in the shape of circles or circle sections.

[0137] Fig. 9 schematically discloses an example of a design of electrodes for any of the second or third semiconductor device embodiment, that matches the surrounding metal pattern density, e.g. FEOL metal, as seen in a cross-sectional top view. In Fig. 9, the electrodes are exemplified as non- continuous sections of electrically conductive material evenly distributed along the bottom circumference 153 of the TSV 150. The sections of electrically conductive material inside the bottom circumference 153 of the TSV 150 together form the first section 130’ of the first electrically conductive layer 130 in this example, while the sections of electrically conductive material outside the bottom circumference 153 of the TSV 150 together form the second section 130” of the first electrically conductive layer 130.

[0138] A third method embodiment is now described, also in connection with the process flow of Fig. 3 in combination with Fig. 13. In this third embodiment of the manufacturing method, the first electrically conductive layer 130 comprises at least one of a first section 130’ and / or a second section 130”. The first section 130’ is comprised within and does not contact the bottom circumference 153 of the etched TSV 150. The second section 130” is outside and is electrically isolated from the bottom circumference 153 of the etched TSV 150. Thereby, similar to in the second embodiment, if both a the first section 130’ and the second section 130” of the first electrically conductive layer 130 are present, they are separated from each other in the plane of extension of the first electrically conductive layer 130, since the first section 130’ is part of the bottom 151 of the TSV 150 and is not in contact with the Si layer 110 after the TSV 150 has been etched, while the second part 130" is in contact with the Si layer 110 both before and after the TSV 150 has been etched, but does not extend to and is not in contact with the bottom 151 of the etched TSV 150. That the second section 130” of the first electrically conductive layer 130 is electrically isolated from the first section 130’ of the same, in the second and third embodiments, may also be described as the second section 130” being free from electric contact with the bottom circumference 153. In the examples shown in figures 8a-c and l la-c, the second section 130” is separated from the bottom circumference 153 of the etched TSV 150 by a section of the non-conductive material (of the insulating layer 120) in which the second section 130” is embedded. The non- conductive material may be or comprise an oxide, as described herein.

[0139] In a first example of the third embodiment, illustrated in Figs. lOa-f and l la-c, the first section 130’ is connected to a first external power supply or electrical connection 180’, and the second section 130” is connected to a second external power supply or electrical connection 180”. In other words, the third method embodiment is performed on a start wafer corresponding to the third embodiment of the semiconductor device 100, e.g. as schematically illustrated in Fig. 10a. Each of the external power supplies or electrical connections 180’, 180” may be a ground connection, ground potential, or a negative or positive potential bias.

[0140] In this first example of the third embodiment, step 330 of insulating the TSV 150 from the Si layer 110, by breaking the electrical contact between the TSV 150 and the Si layer 110, comprises the previously described two sub-steps 332 and 333 of passivating the set of inner walls 151, 152 of the TSV and then cutting the electrical path. Cutting the electrical path herein comprises breaking the electrical connection between any first section 130’ and the external power supply or electrical connection 180, and breaking the electrical connection between any second section 130” and the external power supply or electrical connection 180, if each of the at least one first section and / or second section 130’, 130” is connected to the same external power source. Alternatively, cutting the electrical path in step 333 may comprise breaking the electrical connection between each of the at least one first and / or second section 130’, 130” and the respective external power supply or electrical connection 180’, 180” to which each section is connected, as illustrated in Fig. 10c. Cutting the electrical path may in this embodiment include removing the top electrode 170 or top electrodes 170’, 170”, if such are included, in any suitable manner, e.g. using etching such as dry and / or wet etching, mechanical methods such as grinding or scraping, electrically using fusing, etc. In a second example of the third embodiment, as illustrated in Figs, l ld-e, the first electrically conductive layer 130 comprises a second section 130” that is outside and is electrically isolated from the bottom circumference 153 of the etched TSV 150. Cutting the electrical path herein comprises breaking the electrical connection between the second section 130” and the external power supply or electrical connection 180 connected thereto.

[0141] In a third example of the third embodiment, as illustrated in Figs, l lf-h, the first electrically conductive layer 130 comprises a first section 130’ that is comprised within and does not contact the bottom circumference 153 of the etched TSV 150. Cutting the electrical path herein comprises breaking the electrical connection between the first section 130’ and the external power supply or electrical connection 180 connected thereto.

[0142] Step 340 of providing electrical contact between the TSV 150 and electrically conductive layer in the stack that is arranged to act as the routing layer, in this embodiment the first electrically conductive layer 130, 130’, , comprises the two substeps 342 and 343 as previously described.

[0143] In this third embodiment, there are many different options for the shape, size, and arrangement of the first electrically conductive layer 130. Some non-limiting options are illustrated in Figs. I la to l lh.

[0144] A non-limiting design of the first electrically conductive layer 130 according to the third embodiment is shown in Figs. 1 la-c. In Fig. I la the bottom circumference 153 of the TSV 150 and the first section 130’ of the first electrically conductive layer 130 are in this example shown as circular and the second section 130” of the first electrically conductive layer 130 is shown as being circular with a circular midsection cut-out as seen from a top view. The sections 130’, 130” and the bottom circumference 153 of the TSV 150 are in the example of Fig. l la-h concentric. Other shapes of the first and second sections 130’, 130”, and possibly also the TSV 150, as well as non- concentric arrangement of the first section 130’ and / or the second section 130” in relation to the bottom circumference 153 of the TSV 150 are of course also possible within the scope of the third embodiment. What must be fulfilled in the third embodiment, in likeness with the second embodiment, is that the first section 130’ is comprised within and does not contact the bottom circumference 153 of the etched TSV 150, while the second section 130” is outside and does not contact the bottom circumference 153 of the etched TSV 150. As described herein, each of the first and second sections 130’, 130” may be connected to a respective, or a common, external power source or electrical connection. Fig. 1 la illustrates the example where the first section 130’ is connected to a first power source or electrical connection 180’, and the second section 130” is connected to a second power source or electrical connection 180”. In Figs, l la-c, each of the electrical connections 180’, 180” are illustrated as a ground connection.

[0145] Another alternative design under the second embodiment that fulfills the requirement is shown in Fig. 1 lb. The design of Fig. 1 lb is similar to that of Fig. I la, except that the first section 130’ comprises a cut-out, in this example a circular cut-out in the middle of the first section 130’. Fig. 1 lb illustrates the example where the first section 130’ is connected to the first power source or electrical connection 180’, and the second section 130” is connected to the second power source or electrical connection 180”.

[0146] Yet another alternative design under the second embodiment that fulfills the requirement is shown in Fig. 11c. In the example of Fig. 11c, the first section 130’ covers only part of the area intended for etching / the bottom circumference 153, and the second section 130” covers only a part of the area surrounding the bottom circumference 153. Fig. 11c illustrates the example where the first section 130’ is connected to the first power source or electrical connection 180’, and the second section 130” is connected to the second power source or electrical connection 180”.

[0147] Figs, l ld-e illustrate an alternative embodiment showing the second section 130” of the respective designs of Figs, l la-c, wherein the second section 130” is connected to an external power source or electrical connection 180. The external power source or electrical connection 180 is in these embodiment configured to apply an external electrical field, or potential, on the Si wafer (the Si layer 110) that the second section 130” is in electrical contact with, to thereby counteract the effect of the charge accumulation in, or on the surface of, the insulating layer 120 during etching of the TSV 150. In this embodiment, the external power source or electrical connection 180 is not a ground connection, but an electrical source of voltage. The first section 130’ is optional in these embodiments, whereby this section is not shown in the figures.

[0148] Figs, l lf-h illustrate an alternative embodiment showing the first section 130’ of the respective designs of Figs, l la-c, wherein the first section 130’ is connected to an external power source or electrical connection 180. The external power source or electrical connection 180 is in these embodiment configured to act as a current sink, thereby counteracting build-up of charge at the bottom of the TSV 150, i.e. in, or on the surface of, the insulating layer 120, during etching of the TSV 150. Thereby, notching is prevented. In this embodiment, the external power source or electrical connection 180 is not a ground connection, but an electrical source of voltage. The second section 130” is optional in these embodiments, whereby this section is not shown in the figures.

[0149] In Figs, l la-h the first and second sections 130’, 130” of the first electrically conductive layer 130 are illustrated as a concentric sections. The first and second sections 130’, 130” may be, but are not limited to being, in the shape of circles or circle sections.

[0150] A fourth method embodiment is now described, in connection with the process flow of Fig. 3 in combination with Fig. 20.

[0151] In this fourth embodiment of the manufacturing method, the first electrically conductive layer 130 is at least partially inside a bottom circumference 153 of the etched TSV 150 and also extends outside the bottom circumference 153 of the etched TSV 150. Thereby, the first electrically conductive layer 130 will be part of the TSV 150, i.e. form or be part of the bottom 151 of the TSV 150, and still be in contact with the Si layer 110 after the TSV 150 has been etched.

[0152] The fourth method embodiment is thus performed on a start wafer corresponding to the fourth embodiment of the semiconductor device 100, e.g. as schematically illustrated in Fig. 14a. In this fourth method embodiment, and the corresponding start wafer of the fourth embodiment of the semiconductor device 100, there are different options for the shape, size, and arrangement of the first electrically conductive, etch- stopping, layer 130. The three non-limiting options illustrated in Figs. 5a to 5c, and the variations thereof previously described in connection with the first embodiment, are applicable also to the fourth embodiment.

[0153] As shown in Fig. 20, step 330 of insulating the TSV 150 from the Si layer 110, by breaking the electrical contact between the TSV 150 and the Si layer 110, according to this fourth method embodiment comprises two sub-steps 334 and 332. Step 332 correspond to the passivating step 332 described in connection with Fig. 12. Prior to the passivating step 332, the method of Fig. 20 comprises:

[0154] In sub-step 334: selectively removing part of the first electrically conductive layer 130 to divide the first electrically conductive layer 130 into a first section 130’ and a second section 130”, such that the first section 130’ is comprised within and does not contact the bottom circumference 153 of the etched TSV 150, and such that the second section 130” is outside and is electrically isolated from the bottom circumference 153 of the etched TSV 150.

[0155] The selective removal of part of the first electrically conductive layer 130 to obtain the division into the first and second section 130’, 130” may be achieved in any suitable manner, for example using masked etching, using mechanical removal methods such as cleaving or laser cutting, or by fusing.

[0156] Step 340 of providing electrical contact between the TSV 150 and the electrically conductive layer in the stack that is arranged to act as the routing layer, in this fourth embodiment being the first electrically conductive layer 130, 130’, comprises the two sub-steps 342 and 343 as previously described.

[0157] A fifth method embodiment is now described, also in connection with the process flow of Fig. 3 in combination with Fig. 20.

[0158] In this fifth embodiment of the manufacturing method, the first electrically conductive layer 130 extends inside and outside a bottom circumference 153 of the etched TSV 150. Thereby, the first electrically conductive layer 130 will be part of the TSV 150, i.e. form or be part of the bottom 151 of the TSV 150, and still be in contact with the Si layer 110 after the TSV 150 has been etched. The first electrically conductive layer 130 comprises a first electrically conductive material 131 facing the Si layer 110 and a second electrically conductive material 132, different from the first electrically conductive material 131, that is in electrical contact with the first electrically conductive material 131. The first electrically conductive material 131 is at least partially inside a bottom circumference 153 of the etched TSV 150 and also extends outside the bottom circumference 153 of the etched TSV 150, and the second electrically conductive material 132 comprises at least a first section that is comprised within and does not contact the bottom circumference 153 of the etched TSV 150.

[0159] The fifth method embodiment is thus performed on a start wafer corresponding to the fifth embodiment of the semiconductor device 100, e.g. as schematically illustrated in Fig. 16a. In the fifth method embodiment, and the corresponding start wafer of the fifth embodiment of the semiconductor device 100, there are different options for the shape, size, and arrangement of the first electrically conductive, etchstopping, layer 130.

[0160] Similarly to in the fourth embodiment, the first electrically conductive layer 130 may in the fifth as well as in the sixth embodiment before etching in step 320 cover the entire area intended for etching and an area surrounding the intended for etching, as seen from a top view, as exemplified in Fig. 15a, wherein the etch area for the TSV 150 is indicated by the outline 153 and the first electrically conductive layer 130 covers the whole etch area inside the outline 153 and continues outside the etch area on all sides. Of course, the first and second conductive materials 131, 132 comprised in the first electrically conductive layer 130 in the fifth and sixth embodiments need not cover exactly the same area as seen in a top view, whereby one of the first and second conductive material 131, 132 may extend beyond the other at any point. This is not shown in the non-limiting example of Fig. 15a. What needs to be fulfilled for the fifth embodiment is that the first electrically conductive material 131 is at least partially inside a bottom circumference 153 of the etched TSV 150 and also extends outside the bottom circumference 153 of the etched TSV 150, and that the second electrically conductive material 132 comprises at least a first section that is comprised within and does not contact the bottom circumference 153 of the etched TSV 150 and a second section that is outside the bottom circumference 153 of the etched TSV 150, as seen in a top view. Since the first electrically conductive material 131 is facing the Si layer 110 in this fifth embodiment, the second electrically conductive material 132 is behind the first electrically conductive material 131 and thus not visible in the top view representation of Fig. 15a. The etch area and first electrically conductive layer 130 are in this embodiment shown as circular (substantially circular, within manufacturing tolerances) and concentrical when viewed from a top view. Other shapes of the first electrically conductive layer 130, and possibly also the TSV 150, as well as non-concentric arrangement of the first electrically conductive layer 130 in relation to the TSV 150 are of course also possible within the scope of this fifth method embodiment.

[0161] Alternatively, or additionally, the first electrically conductive material 131 of the first electrically conductive layer 130 may before etching cover the entire area intended for etching and an area surrounding the intended for etching, as seen from a top view, except for a cut-out area. An example is illustrated in Fig. 15b. This alternative design for the fifth embodiment will work as long as the first electrically conductive layer 130 is continuous (either as a continuous material or a patterned material extending in a continuous area) and partly extends both inside the etch area for the TSV 150, indicated by the outline 153 (i.e. the bottom circumference 153 of the TSV 150), and outside the same area. In the example of Fig. 15b, this is enabled by the bridge connecting the section of the first electrically conductive material 131 that is outside the cut-out area to the section of the first electrically conductive material 131 that is inside the cut-out area.

[0162] As shown in Fig. 20, step 330 of insulating the TSV 150 from the Si layer 110, by breaking the electrical contact between the TSV 150 and the Si layer 110, according to this fifth method embodiment, in likeness with the fourth embodiment, comprises the previously described two sub-steps 334 and 332. However, the sub-step 334 of selectively removing part of the first electrically conductive layer to divide it into a first and a second section 130’, 130” for the fifth embodiment comprises selectively etching the first electrically conductive material 131 against the second electrically conductive material 132 from the front side 111 of the Si layer 110, thereby extending the TSV 150 to the second electrically conductive material 132 of the first electrically conductive layer 130, 130’ and dividing the first electrically conductive layer 130 into a first section 130’ and a second section 130”. Suitably, by using two different materials to form the first electrically conductive layer 130, selective etching and other selective removal methods of parts of the first electrically conductive layer 130 to form the separate first and second sections 130’, 130” are facilitated.

[0163] Step 340 comprises the two sub-steps 342 and 343 as previously described.

[0164] A sixth method embodiment is now described, also in connection with the process flow of Fig. 3 in combination with Fig. 20.

[0165] In this sixth embodiment of the manufacturing method, the first electrically conductive layer 130 extends inside and outside a bottom circumference 153 of the etched TSV 150. In likeness with the fifth embodiment, the first electrically conductive layer 130 comprises a first electrically conductive material 131 and a second electrically conductive material 132, different from the first electrically conductive material 131, that is in electrical contact with the first electrically conductive material 131. In contrast to the fifth embodiment however, it is the second electrically conductive material 132 that faces the Si layer 110 in this sixth embodiment. The first electrically conductive material 131 is at least partially inside a bottom circumference 153 of the etched TSV 150 and also extends outside the bottom circumference 153 of the etched TSV 150. The second electrically conductive material 132 comprises at least a first section that is comprised within and does not contact the bottom circumference 153 of the etched TSV 150 and a second section that is outside the bottom circumference 153 of the etched TSV 150, as seen in a top view.

[0166] Step 330 of insulating the TSV 150 from the Si layer 110, by breaking the electrical contact between the TSV 150 and the Si layer 110, according to this sixth method embodiment, comprises the sub-step 334 previously described in connection with the fifth embodiment of selectively etching the first electrically conductive material 131 against the second electrically conductive material 132 from the front side 111 of the Si layer 110. However, for the sixth embodiment, because it is the second electrically conductive material 132 that faces the Si layer 110, only the parts of the first electrically conductive material 131 that are between the sections of the second electrically conductive material 132, as seen from a top view, are reached and etched away. Thereby, the selective etching divides the first electrically conductive layer 130 into a first section 130’ and a second section 130” in an alternative manner. Suitably, in likeness with the fifth embodiment, by using two different materials to form the first electrically conductive layer 130, selective etching and other selective removal methods of parts of the first electrically conductive layer 130 to form the separate first and second sections 130’, 130” are facilitated. Step 330 further comprises substep 332 as previously described herein. Step 340 comprises the two sub-steps 342 and 343 as previously described.

[0167] The sixth method embodiment is thus performed on a start wafer corresponding to the sixth embodiment of the semiconductor device 100, e.g. as schematically illustrated in Fig. 17a. In the sixth method embodiment, and the corresponding start wafer of the sixth embodiment of the semiconductor device 100, there are different options for the shape, size, and arrangement of the first electrically conductive, etchstopping, layer 130.

[0168] Similarly to the fifth embodiment, the first electrically conductive layer 130 comprises a first and second conductive material 131, 132. In the sixth embodiment, before etching, the second electrically conductive material 132 of the first electrically conductive layer 130 is facing the Si layer 110 and covers a first section 130’ of the first electrically conductive layer 130 and a second section 130” of the first electrically conductive layer 130, as seen in a top view, and these two sections 130’ and 130” are separated from each other and from the bottom circumference 153 of the TSV 150. This is shown in the top view in Fig. 15c by the first electrically conductive material 131 being visible through the second electrically conductive material 132 in the area around the bottom circumference 153 of the TSV 150. Of course, the first and second conductive materials 131, 132 comprised in the first electrically conductive layer 130 in the fifth and sixth embodiments need not cover exactly the same area as seen in a top view, whereby one of the first and second conductive material 131, 132 may extend beyond the other at any point. This is not shown in the non-limiting example of Fig. 15c. What needs to be fulfilled for the sixth embodiment is that the second electrically conductive material 132 faces the Si layer 110, wherein the first electrically conductive material 131 is at least partially inside a bottom circumference 153 of the etched TSV 50) and also extends outside the bottom circumference 153 of the etched TSV 150, and wherein the second electrically conductive material 132 comprises at least a first section that is comprised within and does not contact the bottom circumference 153 of the etched TSV 150 and a second section that is outside the bottom circumference 153 of the etched TSV 150, as seen in a top view. The etch area and first electrically conductive layer 130 are in this embodiment shown as circular (substantially circular, within manufacturing tolerances) and concentrical when viewed from a top view. Other shapes of the first electrically conductive layer 130, and possibly also the TSV 150, as well as non- concentric arrangement of the first electrically conductive layer 130 in relation to the TSV 150 are of course also possible within the scope of this sixth method embodiment.

[0169] A seventh method embodiment is now described, also in connection with the process flow of Fig. 3 in combination with Fig. 20. In this seventh embodiment of the manufacturing method, the first electrically conductive layer 130 extends inside and outside a bottom circumference 153 of the etched TSV 150. The semiconductor device further comprises an additional insulating layer 115 embedded in the insulating layer 120, the additional insulating layer 115 partially overlapping with the first electrically conductive layer 130, being arranged between a part of the first electrically conductive layer 130 and the Si layer 110 and extending from the outer periphery of said part of the first electrically conductive layer 130 to inside the bottom circumference 153 of the etched TSV 150.

[0170] The seventh method embodiment is thus performed on a start wafer corresponding to the seventh embodiment of the semiconductor device 100, e.g. as schematically illustrated in Fig. 18a. In the seventh method embodiment, and the corresponding start wafer of the seventh embodiment of the semiconductor device 100, there are different options for the shape, size, and arrangement of the first electrically conductive, etch-stopping, layer 130.

[0171] The seventh embodiment is similar to the fourth embodiment, except in that the seventh embodiment includes an additional insulating layer 115 embedded in the insulating layer 120, the additional insulating layer 115 partially overlapping with the first electrically conductive layer 130 and being arranged between a part of the first electrically conductive layer 130 and the Si layer 110. The additional insulating layer 115 further extends from the outer periphery of said part of the first electrically conductive layer 130 to inside the bottom circumference 153 of the etched TSV 150. A non-limiting example is shown in the top view in Fig. 19a, comprising a cut-out that provides a narrow bridge between the inner section and the outer section of the first electrically conductive layer 130. By this design, only the bridge needs to be removed to divide the first electrically conductive layer 130 into a first section 130’ and a second section 130”, as shown in Fig. 19b that does not comprise such a bridge, after the TSV 150 has been etched. The etch area and first electrically conductive layer 130 are in this embodiment shown as circular (substantially circular, within manufacturing tolerances) and concentrical when viewed from a top view. Other shapes of the first electrically conductive layer 130, and possibly also the TSV 150, as well as non-concentric arrangement of the first electrically conductive layer 130 in relation to the TSV 150 are of course also possible within the scope of this sixth method embodiment.

[0172] Step 330 of insulating the TSV 150 from the Si layer 110, by breaking the electrical contact between the TSV 150 and the Si layer 110, according to this seventh method embodiment, comprises the sub-step 334 previously described in connection with the fifth embodiment. However, sub-step 334 of selectively removing part of the first electrically conductive layer to divide it into a first and a second section 130’, 130” for the seventh embodiment comprises selectively removing part of the first electrically conductive layer 130 to divide the first electrically conductive layer 130 into a first section 130’ and a second section 130”, wherein the first section 130’ is partly comprised within the bottom circumference 153 of the etched TSV 150 and further comprises the part of the first electrically conductive layer 130 that overlaps the additional insulating layer 115, wherein the second section 130” is outside and is electrically isolated from the bottom circumference 153 of the etched TSV 150 and from the first section 130’. Suitably, the overlapping part of the first electrically conductive layer 130 is thereby after the division electrically isolated from the bottom circumference 153 of the etched TSV 150.

[0173] Step 330 further comprises sub-step 332 as previously described herein. Step 340 comprises the two sub-steps 342 and 343 as previously described.

[0174] For any method embodiment described herein, the semiconductor device 100 may further comprise at least one semiconductor component or MEMS component 160, comprised in the Si layer or in the insulating layer, or comprised in another layer of the stack, or attached or electrically connected to the semiconductor device 100. At least one of the at least one semiconductor component or MEMS component 160 may further be in electrical contact with the TSV 150, directly or via routings.

[0175] Each of the first and second section 130’, 130” of the first electrically conductive layer 130, according to the second and third embodiments, may in turn comprise one part, or several parts. Each of the first and second sections 130’, 130” according to any embodiment described herein, as well as any parts or sections thereof, may be in the form of a continuous layer of electrically conductive material, or a patterned electrically conductive material extending in a continuous area enabling electrical contact in the continuous area, e.g. a metal pattern as described herein.

[0176] In a second aspect of the invention, a semiconductor device 100 will now be described in connection with Fig. 2, and also referring to Figs. 4a-f, 7a-f, lOa-f, 14a-f, 16a-f, 17a-f and 18a-f.

[0177] Fig. 2 schematically discloses a semiconductor device 100 comprising a stack of a silicon, Si, layer 110 and an insulating layer 120. The Si layer has a front side 111 and a back side 112. The insulating layer 120 has a front side 121 that is in contact with the back side 112 of the Si layer, and a back side 122. The semiconductor device 100 further comprises a first electrically conductive layer 130 embedded in the insulating layer 120, wherein the first electrically conductive layer 130 extends to and is in electric contact with the back side 112 of the Si layer 110 and is arranged to act as a first etch-stop layer for a deep reactive ion etching, DRIE, process from the front side 111 of the Si layer 110.

[0178] The semiconductor device 100 may further comprise a second electrically conductive layer 140 embedded in the insulating layer 120, wherein the second electrically conductive layer 140 is arranged to act as a routing layer and is in electrical contact with at least one semiconductor component or MEMS component 160 comprised in the Si layer 110.

[0179] Fig. 2 discloses the semiconductor device 100 in the form of a start wafer that enables processing to obtain the advantageous straight profile TSV 150, according to embodiments herein.

[0180] Figs. 4a-f, 7a-f, lOa-f, 14a-f, 16a-f, 17a-fand 18a-f disclose seven examples of process flows where embodiments of the semiconductor device 100 is processed to be provided with a notch-free TSV 150. The seven process flows are use case examples of the seven method embodiments described in connection with Figs. 12 and 13 herein. In the examples of Figs. 4a-f, 7a-f, lOa-f 14a-f, 16a-f, 17a-f and 18a-f the semiconductor devices 100 are all illustrated as CMOS wafers. As described herein, other types of stacked semiconductor devices may be used within the scope of the invention, e.g. generic bulk Si that requires an electrical path through the wafer with optional conductive materials stacked in a similar way as an IC architecture. The conductive layers are numbered following the order of the CMOS stack, where the first electrically conductive layer 130, 130’, 130” is closest to the Si layer 110 (Si substrate), and the at least one second electrically conductive layer 140, 140’, 140” is further from the Si layer 110 compared to the first electrically conductive layer 130, 130’, 130”. It is noted that the electrically conductive layers may consist of or comprise any electrically conductive material used in FEOL and / or BEOL that is selective in DRIE Si etching.

[0181] Any effect or advantage described in connection with a process step for one of the embodiments is applicable to corresponding process steps, achieving similar results, according to any of the other embodiments.

[0182] Figs. 4a-f schematically illustrate a first via-last process sequence of providing a semiconductor device 100 according to a first embodiment, having a TSV 150 that does not go through the entire thickness of the semiconductor device 100.

[0183] Turning first to Fig. 4a, a first embodiment of a semiconductor device 100 is schematically illustrated. In this first embodiment, the first electrically conductive layer 130 extends inside and outside a bottom circumference 153 of the etched TSV 150, and the second electrically conductive layer 140, if there is one, is electrically isolated from the first electrically conductive layer 130 as well as from the Si layer 110. The second electrically conductive layer 140 is then arranged to act as a second etch-stop layer for an etch process from the front side 111 of the Si layer 110. In Fig. 4b, etching, here DRIE, through the Si layer 110 is performed from the front side 111 of the Si layer 110 down to the etch stopping first electrically conductive layer 130. As illustrated in Fig. 4b the first electrically conductive layer 130 extends horizontally outside the etch area 153 (the bottom circumference 151 of the TSV 150 after etching) and is thus in electric contact with the Si layer 110 during the etching. Thereby, the first electrically conductive layer 130 suitably hinders any charge accumulation in the insulating layer 120, which means that there is no notching caused by over-etch. The profile of the inner side walls 152 of the etched TSV 150 is thereby straight and even. As shown in Fig. 4b, the bottom 151 of the TSV 150 now coincides with the front side of the first electrically conductive layer 130.

[0184] In Fig. 4c, etching through the first conductive layer 110 is performed, from the front side 111 of the Si layer 110 down to the insulating layer 120 that is reached after etching through the first conductive layer 130. As shown in Fig. 4c, the sections 130” (which could be opposite sides of one continuous section 130” surrounding the TSV 150) of the first conductive layer 130 are outside the etch area 153 and thus are not removed by the directional and non-isotropic etching. Thereby, these sections 130” remain and are still in contact with the Si layer 110. Alternatively, the entire first conductive layer 130 may be removed, if a different etch method is selected. After this step, the TSV 150 has been extended to, and the bottom 151 of the TSV 150 now coincides with, the insulating layer 120 below the first electrically conductive layer 130.

[0185] Fig. 4d shows passivation of the Si layer 110 and any remaining sections 130” of the first electrically conductive layer 130. In this use case example, passivation is done by applying a passivating layer 125 on the set of inner walls, i.e. the bottom 151 and vertical inner side walls 152 of the TSV 150. The passivation may be achieved by depositing the passivation layer 125 on the set of inner walls 151, 152. The insulating layer or passivation layer 125 may comprise the same type of insulating material as the insulating layer 120, here an oxide since the semiconductor device 100 is a CMOS device in this use case example. After passivation, the bottom 151 of the TSV 150 now coincides with the horizontal front side of the passivating layer 125.

[0186] Fig. 4e shows etching through the passivation layer 125 from the front side 111 of the Si layer 110 down to the second electrically conductive layer 140’, which is thus arranged to act as a second etch stopping layer. Etching through the passivation layer 125 may be performed in any suitable manner described herein, for example but not limited to directional etching. As shown in Fig. 4e, the TSV 150 is extended to and the bottom 151 of the TSV 150 now coincides with the front side of the second electrically conductive layer 140’. The TSV 150 is still electrically insulated from the Si layer 110 and any remaining sections 130” of the first electrically conductive layer 130 by the passivation layer 125 and the insulating layer 120.

[0187] Finally, as shown in Fig. 4f, electrical contact is provided between the resulting TSV 150 and the second electrically conductive layer 140’, by metallizing the TSV 150. In this use case example, the metallization comprises deposition, e.g. PVD, of a seed layer 190 of metal and subsequently growing a metal layer 191 on the seed layer 190. Furthermore, if at least one semiconductor component or MEMS component 160 is comprised in the Si layer 110 and electrically connected to the second electrically conductive layer 140’, electrical contact between the TSV 150 and the at least one semiconductor component or MEMS component 160 is achieved.

[0188] In the first embodiment of the semiconductor device 100, and the corresponding first embodiment of the manufacturing method, the etch area for the intended TSV are at least partially overlapping in the horizonal plane, i.e. as seen in a top view, with each of the first and the second electrically conductive layers 130, 130’, 140, 140’, 140”, so that they are arranged to act as etch stopping layers. The placement of the first and the second electrically conductive layers 130, 130’, 140, 140’, 140” in the insulating layer 120 may therefore differ depending on the application for which it is to be used.

[0189] Figs. 7a-f schematically illustrate a second via-last process sequence of providing a semiconductor device 100 according to a second embodiment, having a TSV 150 that does not go through the entire thickness of the semiconductor device 100.

[0190] Turning first to Fig. 7a, a second embodiment of a semiconductor device 100 is schematically illustrated. In this second embodiment, the first electrically conductive layer 130 comprises at least a first section 130’ and a second section 130”, wherein the first section 130’ is comprised within and does not contact the bottom circumference 153 of the etched TSV 150, while the second section 130” is outside and is electrically isolated from the bottom circumference 153 of the etched TSV 150. The first section 130’ and the second section 130” are in electrical contact with each other via another conductive layer or element comprised in the insulating layer 120 or being attached or connected to the insulating layer 120. In the example shown in Fig. 7a, the other conductive layer or element comprises a top electrode 170 on the back side 122 of the insulating layer 120, whereby the first section 130’ and the second section 130” are in electrical contact with each other via the top electrode 170.

[0191] The electrical connections may comprise routing via additional conductive elements, in this example the illustrated second electrically conductive layer 140” and any connecting intermediate elements, provided in manners known in the art. In other words, there is one or more conductive electrode, here in the form of the first section 130’ of the first electrically conductive layer 130, that is in electrical contact with the DRIE plasma during etching, but that does not extend all the way out to the Si bulk of the Si layer 110. At the same time, other separate electrode or electrodes, here in the form of the second section 130” of the first electrically conductive layer 130, is / are in electrical contact with the surrounding bulk Si of the Si layer 110, but does not extend to the bottom circumference 153 of the TSV 150. The first and second sections 130’, 130” of the first electrically conductive layer 130 are further in electrical contact with each other in a different layer than the first DRIE stopping layer.

[0192] In Fig. 7b, etching, here DRIE, through the Si layer 110 is performed from the front side 111 of the Si layer 110 down to the etch stopping first section 130’ of the first electrically conductive layer 130. Since the second section 130” is in electric contact with the Si layer 110 and the first and second sections 130’, 130” of the first electrically conductive layer 130 are in electric contact with each other during the etching, the first electrically conductive layer 130 also in this embodiment suitably hinders any charge accumulation in the insulating layer 120, which means that there is no notching caused by over-etch. The profile of the inner side walls 152 of the etched TSV 150 is thereby straight and even. As shown in Fig. 7b, the bottom 151 of the TSV 150 now coincides with the front side of the first electrically conductive layer 130, 130’, 130”.

[0193] Since the first section 130’ is comprised within and does not contact the bottom circumference 153 of the etched TSV 150, while the second section 130” is outside and is electrically isolated from the bottom circumference 153 of the etched TSV 150, electrical isolation between the Si bulk and the TSV 150 can be obtained in an alternative manner compared to in the first embodiment, suitably without needing to etch through any part of the first electrically conductive layer 130. This is also advantageous if it is desirable to keep the first electrically conductive layer 130, e.g. for later routing purposes.

[0194] As shown in Fig. 7c, passivation of the Si layer 110 and the first section 130’ of the first electrically conductive layer 130 is performed. In this use case example, passivation is done by applying a passivating layer 125 on the set of inner walls, i.e. the bottom 151 and vertical inner side walls 152 of the TSV 150. The passivation may be achieved by depositing the passivation layer 125 on the set of inner walls 151, 152. The insulating layer or passivation layer 125 may comprise the same type of insulating material as the insulating layer 120, here an oxide since the semiconductor device 100 is a CMOS device in this use case example. After passivation, the bottom 151 of the TSV 150 now coincides with the horizontal front side of the passivating layer 125.

[0195] Fig. 7d then shows etching through the passivation layer 125 from the front side 111 of the Si layer 110 down to the first section 130’ of the first electrically conductive layer 130, which again acts as an etch stopping layer. Etching through the passivation layer 125 may be performed in any suitable manner described herein. The profile of the inner side walls 152 of the etched TSV 150 is thereby still straight and even. As shown in Fig. 7d, the TSV 150 is now again extended to and the bottom 151 of the TSV 150 again coincides with the front side of the first electrically conductive layer 130, 130’ , 130”.

[0196] As shown in Fig. 7e, electrical contact is then provided between the resulting TSV 150 and the first section 130’ of the first electrically conductive layer 130, by metallizing the TSV 150. In this use case example, the metallization comprises deposition, e.g. PVD, of a seed layer 190 of metal and subsequently if required growing a thicker metal layer 191 on the seed layer 190 using electroplating. Thereby, an electrical through connection between the TSV 150 and the first section 130’ of the first electrically conductive layer 130, and further to the back side 122 of the insulating layer 120, or to a component embedded in the stack, via routings, is achieved.

[0197] Finally, as shown in Fig. 7f, insulation, or electrical isolation, between the TSV 150 and the Si layer 110 is achieved by cutting the electrical path between the first section 130’ and the second section 130” of the first electrically conductive layer 130. In this use case, cutting the electrical path comprises etching, e.g. using dry or wet directional and non-iso tropic etching, through the top electrode 170 from the back side 122 of the insulating layer 120, at a location 175 between the connection of the top electrode 170 to the first section 130’ of the first electrically conductive layer 130 and the connection of the top electrode 170 to the second section 130” of the first electrically conductive layer 130. As illustrated in Fig. 7f, the top electrode 170 is thereby divided into two non- contacting, electrically isolated, parts 170’, 170”. The TSV 150 is now suitably insulated, or electrically isolated, from the Si layer 110 and the second section 130” of the first electrically conductive layer 130 by the passivation layer 125 and the insulating layer 120.

[0198] Figs. lOa-f schematically illustrate a third via-last process sequence of providing a semiconductor device 100 according to a third embodiment, having a TSV 150 that does not go through the entire thickness of the semiconductor device 100.

[0199] Turning first to Fig. 10a, a third embodiment of a semiconductor device 100 is schematically illustrated. Similarly to the semiconductor device 100 of the second embodiment, the first electrically conductive layer 130 comprises at least a first section 130’ and a second section 130”, wherein the first section 130’ is comprised within and does not contact the bottom circumference 153 of the etched TSV 150, while the second section 130” is outside and is electrically isolated from the bottom circumference 153 of the etched TSV 150. In this third embodiment, the first section 130’ and the second section 130” of the first electrically conductive layer 130 are not in contact with each other. Instead, the first and second sections 130’, 130” are each connected to an external power supply or electrical connection 180, which may be a common external power supply or electrical connection 180 or, as illustrated in Fig. 10a, a respective external power supply or electrical connection 180’, 180”. Advantageously, an external bias control is thereby provided, since each of the first and second sections 130’, 130” of the first electrically conductive layer 130 is in electrical contact with an external power supply or electrical connection 180, 180’, 180” during the DRIE process, so that the electric field can be manipulated and controlled throughout the etch, manually or automatically. Alternatively, the external power supply or electrical connection 180, or external power supplies or electrical connections 180’, 180”, may provide ground electric potential.

[0200] The semiconductor device 100 may further comprise a first top electrode 170’ and a second top electrode 170” on the back side 122 of the insulating layer 120. In this case, the first section 130’ of the first electrically conductive layer 130 is connected to the external power supply or electrical connection 180, 180’ via the first top electrode 170’ and the second section 130” of the first electrically conductive layer 130 is connected to the external power supply or electrical connection 180, 180” via the second top electrode 170”.

[0201] In Fig. 10b, etching, here DRIE etching, through the Si layer 110 is performed from the front side 111 of the Si layer 110 down to the etch stopping first section 130’ of the first electrically conductive layer 130. The external power supplies or electrical connections 180’, 180” will now be used to avoid an electric field build up, due to charge built up, in the first section 130’ of the first electrically conductive layer 130, which is in contact to the plasma etch. To achieve this the first section 130’ of the electrically conductive layer 130 in contact with the plasma of the DRIE can either be put to ground potential, or negative or positive potential bias. Alternatively, or in combination, a similar bias as is applied to the first section 130’ of the first electrically conductive layer 130 can be applied to the second section 130” of the first electrically conductive layer 130, which is in contact with the Si layer 110, to minimize the electric field created between the first section 130’ of the first electrically conductive layer 130, which is in contact with the plasma etch and the second section 130” of the first electrically conductive layer 130. Thereby, no notching will occur during over-etch. The profile of the inner side walls 152 of the etched TSV 150 is thereby straight and even. As shown in Fig. 10b, the bottom 151 of the TSV 150 now coincides with the front side of the first electrically conductive layer 130, 130’, 130”.

[0202] Since the first section 130’ is comprised within and does not contact the bottom circumference 153 of the etched TSV 150, while the second section 130” is outside and is electrically isolated from the bottom circumference 153 of the etched TSV 150, electrical isolation between the Si bulk and the TSV 150 can be obtained in an alternative manner compared to in the first embodiment, suitably without needing to etch through any part of the first electrically conductive layer 130. This is also advantageous if it is desirable to keep the first electrically conductive layer 130, e.g. for later routing purposes. In this third embodiment, as shown in Fig. 10c, cutting the electrical path between the first section 130’ and the second section 130” of the first electrically conductive layer 130 comprises breaking the connection between each of the first section 130’ and the second section 130”, and the external power supply or electrical connection 180, or respective external power supply or electrical connection 180’, 180”, to which it is connected. If first and second top electrodes 170’, 170” were used, this process step suitably includes removing the top electrodes 170’, 170”, by e.g. dry and / or wet etching, using mechanical removal methods such as grinding, dicing, cleaving, laser cutting or scraping, or by fusing, or using an integrated gate or switch configured to connect and disconnect the first and second sections 130’, 130”.

[0203] The steps shown in Figs. 10c- lOf must be performed after the etch step in Fig. 10b, but the step shown in Fig. 10c may be performed at any time before, between or after the steps of Figs. lOd-lOf.

[0204] As shown in Fig. lOd, passivation of the Si layer 110 and the first section 130’ of the first electrically conductive layer 130 is performed. In this use case example, passivation is done by applying a passivating layer 125 on the set of inner walls, i.e. the bottom 151 and vertical inner side walls 152 of the TSV 150. The passivation may be achieved by depositing the passivation layer 125 on the set of inner walls 151, 152. The insulating layer or passivation layer 125 may comprise the same type of insulating material as the insulating layer 120, here an oxide since the semiconductor device 100 is a CMOS device in this use case example. After passivation, the bottom 151 of the TSV 150 now coincides with the horizontal front side of the passivating layer 125.

[0205] Fig. lOe shows subsequent etching through the passivation layer 125 from the front side 111 of the Si layer 110 down to the first section 130’ of the first electrically conductive layer 130, which again acts as an etch stopping layer. Etching through the passivation layer 125 may be performed in any suitable manner described herein. The profile of the inner side walls 152 of the etched TSV 150 is thereby still straight and even. As shown in Fig. lOe, the TSV 150 is now again extended to and the bottom 151 of the TSV 150 again coincides with the front side of the first electrically conductive layer 130, 130’ , 130”.

[0206] Finally, in Fig. lOf, electrical contact is provided between the resulting TSV 150 and the first section 130’ of the first electrically conductive layer 130, by metallizing the TSV 150. In this use case example, the metallization comprises deposition, e.g. PVD, of a seed layer 190 of metal and subsequently growing a metal layer 191 on the seed layer 190. Thereby, an electrical through connection between the TSV 150 and the first section 130’ of the first electrically conductive layer 130, and further to the back side 122 of the insulating layer 120, or to a component embedded in the stack, via routings, is achieved. The TSV 150 is now suitably electrically insulated from the Si layer 110 and the second section 130” of the first electrically conductive layer 130 by the passivation layer 125 and the insulating layer 120, and at the same time electrically connected to the first section 130’ of the first electrically conductive layer 130 and any elements electrically connected thereto.

[0207] Figs. 14a-f schematically illustrate a fourth via-last process sequence of providing a semiconductor device 100 according to a fourth embodiment, having a TSV 150 that does not go through the entire thickness of the semiconductor device 100.

[0208] Turning first to Fig. 14a, a fourth embodiment of a semiconductor device 100 similar to the semiconductor device or starting wafer of Fig. 4a, wherein the first electrically conductive layer 130 extends inside and outside a bottom circumference 153 of the etched TSV 150, is schematically illustrated. However, in this fourth embodiment, there is no second electrically conductive layer. Such layer or layers may optionally be included but are not necessary in this embodiment.

[0209] In the process step of Fig. 14b, etching of aTSV 150 is performed in the same manner as described in connection with Fig. 4b.

[0210] In the process step of Fig. 14c, the first electrically conductive layer 130 is divided into a first section 130’ and a second section 130”, corresponding to the first and second sections 130’, 130” described for other embodiments herein, wherein the first section 130’ is comprised within and does not contact the bottom circumference 153 of the etched TSV 150, while the second section 130” is outside and is electrically isolated from the bottom circumference 153 of the etched TSV 150. The division into the first and second section 130’, 130” may be achieved in any suitable manner, for example using masked etching, using mechanical removal methods such as cleaving or laser cutting, or by fusing.

[0211] Fig. 14d shows passivation of the TSV 150, performed in any manner described for other embodiments herein.

[0212] Fig. 14e shows etching through the passivation layer 125 from the front side 111 of the Si layer 110 down to the first section 130’ of the first electrically conductive layer 130, which again acts as an etch stopping layer. Etching through the passivation layer 125 may be performed in any suitable manner described herein. As shown in Fig. 14e, a residue 126 may remain after etching. Such a residue is shown in some of the figures, and left out in others that illustrate a similar etching step. This residue may differ in size, possibly not even being visible. Since the residue 126 is convex, in contrast to the concave hollowing caused by notching, the residue 126 does not affect the quality of the subsequent metallization process.

[0213] In Fig. 14f, an electrical connection 127 between the first electrically conductive layer 130’ and the back side 122 of the insulating layer 120 is shown. The electrical connection 127 may be obtained in any suitable manner known in the art, for example but not limited to obtaining an opening that may be used for connecting a wire connection, an opening that may have metallized walls or be filled with an electrically conductive material, providing routings via one or more additional electrically conductive layer (complete layer, patterned layer, contact pad, or the like) comprised in the insulating layer 120 or on the back side 122 of insulating layer, etc. Although not shown in the Figs. 14a-e, the electrical connection 127, in any suitable form, may be added at any point of the process after the step of Fig. 14b. Fig 14f also shows that the TSV 150 is metallized, in any manner described in connection with other embodiments herein.

[0214] Figs. 16a-f schematically illustrate a fifth via-last process sequence of providing a semiconductor device 100 according to a fifth embodiment, having a TSV 150 that does not go through the entire thickness of the semiconductor device 100.

[0215] Fig. 16a shows a semiconductor device or start wafer similar to that of Fig. 14a. The start wafer of Fig. 16a differs from that of Fig. 14a in that the first electrically conductive layer 130 comprises, or is formed by, two different electrically conductive materials 131, 132, which are not separated by an insulator but are in electrical contact with each other. In the fifth embodiment, the first electrically conductive material 131 is facing the Si layer 110. The first electrically conductive material 131 is at least partially inside a bottom circumference 153 of the etched TSV 150 and also extends outside the bottom circumference 153 of the etched TSV 150, as seen in a top view. The second electrically conductive material 132 is divided into sections, wherein one section is comprised within and does not contact the bottom circumference 153 of the etched TSV 150, while the second section 130” is outside the bottom circumference 153 of the etched TSV 150, as seen in the top view. Suitably, the second section of the second material 132 is at this point not electrically isolated from the bottom circumference 153 of the etched TSV 150 since the first electrically conductive material 131 in contact with the Si layer 110 extends both within and outside the bottom circumference 153 of the etched TSV 150. In the process step of Fig. 16b, etching of aTSV 150 is performed in the same manner as described in connection with Fig. 4b.

[0216] In the process step of Fig. 16c, the first electrically conductive material 131 is etched selectively against the second electrically conductive material 132, such that the TSV 150 is extended to the second electrically conductive material 132. Thereby, the first electrically conductive layer 130 is divided into a first section 130’ and a second section 130”, corresponding to the first and second sections 130’, 130” described for other embodiments herein, wherein the first section 130’ is comprised within and does not contact the bottom circumference 153 of the etched TSV 150, while the second section 130” is outside and is electrically isolated from the bottom circumference 153 of the etched TSV 150.

[0217] Suitably, compared to the corresponding process step of Fig. 14c in the fourth embodiment, no etch masked needs to be used. Thereby, the process is simplified.

[0218] The process steps of Figs. 16d-f are performed in the same manner as the corresponding process steps of Figs. 14d-f.

[0219] Figs. 17a-f schematically illustrate a sixth via-last process sequence of providing a semiconductor device 100 according to a sixth embodiment, having a TSV 150 that does not go through the entire thickness of the semiconductor device 100.

[0220] As shown in Fig. 17a, the sixth embodiment is similar to the fifth embodiment, but the order of the first material 131 and the second material 132 of the first electrically conductive layer 130 are reversed, such that the second material 132 is facing the Si layer 110.

[0221] In other words, in the sixth embodiment the first electrically conductive layer 130 extends inside and outside a bottom circumference 153 of the etched TSV 150, wherein the first electrically conductive layer 130 comprises a first electrically conductive material 131 and a second electrically conductive material 132 that is different from the first electrically conductive material 131. The second electrically conductive material 132 is in electrical contact with the first electrically conductive material 131. In this sixth embodiment, the second electrically conductive material 132 faces the Si layer 110. The first electrically conductive material 131 is at least partially inside a bottom circumference 153 of the etched TSV 150 and also extends outside the bottom circumference 153 of the etched TSV 150, while the second electrically conductive material 132 comprises at least a first section that is comprised within and does not contact the bottom circumference 153 of the etched TSV 150 and a second section that is outside the bottom circumference 153 of the etched TSV 150, as seen in a top view.

[0222] In the process step of Fig. 17b, etching of a TSV 150 is performed in the same manner as described in connection with Fig. 4b.

[0223] In the process step of Fig. 17c, the first electrically conductive material 131 is etched selectively against the second electrically conductive material 132, similar to the process step of Fig. 16c. However, since the sectioned second electrically conductive material 132 is the one facing the TSV 150, only the parts of the first electrically conductive material 131 that is located between the sections of the second electrically conductive material 132 can be reached and thus removed by the selective etching. Thereby, in a manner alternative to that of the fifth embodiment, the first electrically conductive layer 130 is divided into a first section 130’ and a second section 130”, corresponding to the first and second sections 130’, 130” described for other embodiments herein, wherein the first section 130’ is comprised within and does not contact the bottom circumference 153 of the etched TSV 150, while the second section 130” is outside and is electrically isolated from the bottom circumference 153 of the etched TSV 150.

[0224] Suitably, compared to if an etching method is used in the corresponding process step of Fig. 14c in the fourth embodiment, no etch mask needs to be used. Thereby, the process is simplified.

[0225] The process steps of Figs. 17d-f are performed in the same manner as the corresponding process steps of Figs. 14d-f.

[0226] A layer, in any embodiment herein, may comprise a continuous material or a patterned material e.g. extending in a continuous area enabling electrical contact in the continuous area, covering at least part of the top view cross-section of the stack, that has been applied during stacking. A layer further does not have to be flat in the horizontal direction, but may have different depths along its extension, since it may for instance have been applied, during production of the stack, on top of a patterned layer or a continuous layer that did not cover the entire area of the top view crosssection. This is for example shown for the first electrically conductive layer 130 in Figs. 18a-f. Figs. 18a-f schematically illustrate a seventh via-last process sequence of providing a semiconductor device 100 according to a seventh embodiment, having a TSV 150 that does not go through the entire thickness of the semiconductor device 100.

[0227] Turning first to Fig. 18a, a seventh embodiment of a semiconductor device 100 similar to the semiconductor device or starting wafer of Fig. 14a, wherein the first electrically conductive layer 130 extends inside and outside a bottom circumference 153 of the etched TSV 150, is schematically illustrated. However, in difference to the fourth embodiment, an additional insulating layer 115 is comprised in the stack of the semiconductor device 100. The additional insulating layer 115 partially overlaps with the first electrically conductive layer 130, as seen in a top view, and the additional insulating layer 115 is arranged between a part of the first electrically conductive layer 130 and the Si layer 110 and extends from the outer periphery of said part of the first electrically conductive layer 130 to inside the bottom circumference 153 of the etched TSV 150. Thereby, it separates the first electrically conductive layer 130 from a section of the Si layer 110. The stack of this embodiment is or has been achieved by applying the additional insulating layer 115 on the Si layer 110 before applying the first conductive layer 130 and the subsequent insulating layer 120, during production of the stack. The additional insulating layer 115 causes the subsequently applied first electrically conductive layer 130 to have a non-flat depth profile, illustrated by the curved first electrically conductive layer 130, following the edge of the additional insulating layer 115 in the side view shown of Figs. 18a-f. Thereby, a first part of the continuous first electrically conductive layer 130 is in direct contact with the Si layer 110 while a second part of the continuous first electrically conductive layer 130 is separated from the Si layer 110 by the additional insulating layer 115. The additional insulating layer 115 may comprise the same material as the insulating layer 120 or a different insulating material.

[0228] In the process step of Fig. 18b, etching of a TSV 150 is performed in the same manner as described in connection with Fig. 4b.

[0229] In the process step of Fig. 18c, the first electrically conductive layer 130 is divided into a first section 130’ and a second section 130”. In likeness with the other embodiments having a first and a second section 130', the second section 130” is outside and is electrically isolated from the bottom circumference 153 of the etched TSV 150. However, the in difference to these other embodiments, the first section 130’ in this embodiment is comprised within the bottom circumference 153 of the etched TSV 150, but also extends outside the bottom circumference 153, as seen in a top view. However, the first section 130’ is separated from the Si layer and the bottom circumference 153 of the TSV 150 by the additional insulating layer 115, whereby the first section 130’ is electrically isolated from the Si layer. The division into the first and second section 130’, 130” may be achieved in any suitable manner, for example using masked etching, using mechanical removal methods such as cleaving or laser cutting, or by fusing.

[0230] The process steps of Figs. 18d-f are performed in the same manner as the corresponding process steps of Figs. 14d-f.

[0231] As illustrated in Fig. 18f, by the use of an additional insulating layer 115 the electrical connection 127 from the TSV 150 to the back side 122 of the semiconductor device 100, or to a component embedded in the stack, now suitably does not have to be centered, aligned, or even overlapping with the TSV 150, as seen in a top view. Thereby, more options for routing, arrangement of components and design of the semiconductor device are available.

[0232] Of course, for embodiments wherein providing electrical contact between the TSV 150 and an electrically conductive layer in the stack comprises providing electrical contact between the TSV 150 and the first electrically conductive layer 130, 130’, electrical contact may additionally be provided between the TSV 150 and a second electrically conductive layer 140, 140’, 140”, via a respective separate routing.

[0233] Depending on the design chosen for a particular application, the dedicated DRIE etch stopping layer can be etched away and / or passivated if needed after the DRIE is completed. The resulting TSV 150 can be grounded to the Si layer 110 or passivated, so that the TSV 150 becomes electrically isolated to the Si layer 110. The use case examples herein simply illustrate a few, non-limiting, design options and process sequences. Regardless of which solution is chosen, the subsequent metallization will be drastically simplified using embodiments of the invention, since the improved seed layer coverage of PVD metal, or the like, allows for electroplating of the entire TSV 150, all the way down to the chosen connecting conductive routing layer, e.g. the first or any of the second electrically conductive layers 130, 130’, 130”, 140, 140’, 140” embedded in the insulating layer 120.

[0234] The semiconductor device 100 according to any embodiment herein may further comprise at least one semiconductor component or MEMS component 160 comprised in the Si layer, or comprised in another layer of the stack, or attached or electrically connected to the semiconductor device 100.

[0235] Of course, the electrical connections described herein may comprise connection routing between layers and / or components. Such routings, achieved using any suitable known technique, are standard in the art and are as such not described further herein. The routings are not illustrated, or only schematically illustrated, in the figures.

[0236] It is noted that the figures only show features relevant for the description of the specific figure. For example, the process sequences of Figs. 4a-f, 7a-f, lOa-f, 14a-f, 16a-f, 17a-f and 18a-f serve to illustrate the process of obtaining a TSV 150 in a semiconductor device. As such, any semiconductor components and / or MEMS components 160 that may be comprised in the semiconductor device 100, which do not play an active part in the making of a TSV 150, are not shown in the figures. Similarly, the stack of the semiconductor device 100 according to any embodiment herein may comprise additional layers, not shown in the figures, if this is suitable to a certain application.

[0237] The invention also includes a semiconductor device 100 resulting from the method of manufacturing a semiconductor device according to any described embodiment herein, that is the description, the claims, and the drawings, specifically in connection with Figs. 3, 12, 13 and 20.

[0238] For any embodiment of the semiconductor device 100 or the manufacturing method described herein, each of the first electrically conductive layer and the optional second electrically conductive layer may comprise or consist of a metal material. Preferably, the metal material may comprise tungsten, W, or aluminium, Al.

[0239] For any embodiment of the semiconductor device 100 or the manufacturing method described herein, the semiconductor device may be a CMOS device.

[0240] It is noted that, for any embodiment of providing electrical contact between the TSV 150 and an electrically conductive layer 130, 130’, 140, 140’ herein, if an etch or other removal of insulation to provide the electrical contact is performed on an area smaller than and not touching the bottom circumference 153 of the etched TSV 150, any electrically conductive layer 130, 130’, 130”, 140, 140’ defined herein as not contacting the bottom circumference 153 of the etched TSV 150 may in fact do so as long as it does not contact the circumference of the etch area of the etch removing the insulation.

[0241] Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

[0242] The term “comprises / comprising” when used in this specification is taken to specify the presence of stated features, integers, steps, or components. The term does not preclude the presence or addition of one or more additional elements, features, integers, steps or components or groups thereof. The indefinite article "a" or "an" does not exclude a plurality. In the claims, the word “or” is not to be interpreted as an exclusive or (sometimes referred to as “XOR”). On the contrary, expressions such as “A or B” covers all the cases “A and not B”, “B and not A” and “A and B”, unless otherwise indicated. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

[0243] It is also to be noted that features from the various embodiments described herein may freely be combined, unless it is explicitly stated that such a combination would be unsuitable.

[0244] The invention is not restricted to the described embodiments in the figures but may be varied freely within the scope of the claims.

Claims

CLAIMS1. A method of manufacturing an integrated circuit, IC, (100) with a through silicon via, TSV, (150) that does not go through the entire thickness of the IC (100), the method comprising: providing a stack comprising:- a silicon, Si, layer (110) having a front side (111) and a back side (112);- an insulating layer (120) having a front side (121) that is in contact with the back side (112) of the Si layer, and a back side (122); and- a first electrically conductive layer (130, 130’) embedded in the insulating layer (120) that is arranged to act as a routing layer, wherein the first electrically conductive layer (130, 130’) extends to and is in electrical contact with the back side (112) of the Si layer (110) and is arranged to act as a first etch-stop layer for a deep reactive ion etching, DRIE, process from the front side (111) of the Si layer (110); etching a TSV (150) from the front side (111) of the Si layer (110) to the first electrically conductive layer (130, 130’); breaking the electrical contact between the TSV (150) and the Si layer (110) and passivating a set of inner walls (151, 152) of the TSV (150); and providing electrical contact between the TSV (150) and the first electrically conductive layer (130, 130’).

2. A method of manufacturing an integrated circuit, IC, (100) with a TSV (150) that does not go through the entire thickness of the IC (100), the method comprising: providing a stack comprising: a silicon, Si, layer (110) having a front side (111) and a back side (112);- an insulating layer (120) having a front side (121) that is in contact with the back side (112) of the Si layer, and a back side (122);- a first electrically conductive layer (130, 130’) embedded in the insulating layer (120), wherein the first electrically conductive layer (130, 130’) extends to and is in electrical contact with the back side (112) of the Si layer (110) and is arranged to act as a first etch-stop layer for a deep reactive ion etching, DRIE, process from the front side (111) of the Si layer (110); and- a second electrically conductive layer (140, 140’, 140”) embedded in the insulating layer (120) that is arranged to act as a routing layer, wherein the second electrically conductive layer (140, 140’, 140”) is electrically isolated from the first electrically conductive layer (130, 130’) as well as from the Si layer (110); etching a through silicon via, TSV, (150) from the front side (111) of the Si layer (110) to the first electrically conductive layer (130, 130’); breaking the electrical contact between the TSV (150) and the Si layer (110) and passivating a set of inner walls (151, 152) of the TSV (150); and providing electrical contact between the TSV (150) and the second electrically conductive layer (140, 140’, 140”).

3. The method of claim 2, wherein the first electrically conductive layer (130) extends outside a bottom circumference (153) of the etched TSV (150) and the second electrically conductive layer (140, 140', 140") is at least partially inside the bottom circumference (153) of the etched TSV (150), wherein breaking the electrical contact between the TSV (150) and the Si layer (110) and passivating the set of inner walls (151, 152) of the TSV (150) comprises: first dry etching or wet etching at the bottom (151) of the TSV (150) such that the TSV (150) is extended to the insulating layer (120); and then passivating the set of inner walls (151, 152) of the TSV (150),wherein providing electrical contact between the TSV (150) and the electrically conductive layer in the stack that is arranged to act as the routing layer comprises: etching at the bottom (151) of the TSV (150) to the second electrically conductive layer (140, 140’, 140”), thereby extending the TSV (150) to the second electrically conductive layer (140, 140’, 140”); and metallizing a set of inner walls (151, 152) of the resulting TSV (150).

4. The method of claim 1, wherein the first electrically conductive layer (130) comprises at least a first section (130’) and a second section (130”), wherein the first section (130’) is comprised within and does not contact the bottom circumference (153) of the etched TSV (150), wherein the second section (130”) is outside and is electrically isolated from the bottom circumference (153) of the etched TSV (150), wherein the first section (130’) and the second section (130”) are in electrical contact with each other via another conductive layer or element comprised in the insulating layer (120) or being attached or connected to the insulating layer (120), wherein breaking the electrical contact between the TSV (150) and the Si layer (110) cutting the electrical path, by breaking the electrical connection between the first section (130’) and the second section (130”) of the first electrically conductive layer (130), wherein providing electrical contact between the TSV (150) and the electrically conductive layer in the stack that is arranged to act as the routing layer comprises: etching at the bottom (151) of the TSV (150) to the first section (130’) of the first electrically conductive layer ( 130) , thereby extending the TSV (150) to the first section (130’) of the first electrically conductive layer (130); and metallizing the set of inner walls of the resulting TSV (150).

5. The method of claim 4, wherein the IC (100) comprises a top electrode (170) on the back side (122) of the insulating layer (120), wherein the first section(130’) and the second section (130”) are in electrical contact with each other via the top electrode (170).

6. The method of claim 5, wherein cutting the electrical path between the first section (130’) and the second section (130”) of the first electrically conductive layer (130) comprises dry etching or wet etching through the top electrode (170) at a location (175) between the connection of the top electrode (170) to the first section (130’) of the first electrically conductive layer (130) and the connection of the top electrode (170) to the second section (130”) of the first electrically conductive layer (130).

7. The method of claim 1, wherein the first electrically conductive layer (130) comprises at least one of a first section (130’) and a second section (130”), wherein the first section (130’) is comprised within and does not contact the bottom circumference (153) of the etched TSV (150), wherein the second section (130”) is outside and is electrically isolated from the bottom circumference (153) of the etched TSV (150), wherein each of the at least one first section (130’) and / or second section (130”) is connected to an external power supply or external electrical connection (180, 180’, 180”), wherein breaking the electrical contact between the TSV (150) and the Si layer (110) comprises cutting the electrical path by breaking the electrical connection to each of the at least one first section (130’) and / or second section (130”), wherein providing electrical contact between the TSV (150) and the electrically conductive layer in the stack that is arranged to act as the routing layer comprises: etching at the bottom (151) of the TSV (150) to the first section (130’) of the first electrically conductive layer ( 130) , thereby extending the TSV (150) to the first section (130’) of the first electrically conductive layer (130); and metallizing the set of inner walls (151, 152) of the resulting TSV (150).

8. The method of claim 7, wherein breaking the electrical connection to each of the at least one first section (130’) and / or second section (130”) comprises breaking the connection between each of the at least one first section (130’) and / or second section (130”) and the respective external power supply or electrical connection (180, 180’, 180”), to which it is connected.

9. The method of claim 1, wherein the first electrically conductive layer (130) is at least partially inside a bottom circumference (153) of the etched TSV (150) and also extends outside the bottom circumference ( 153) of the etched TSV (150), wherein breaking the electrical contact between the TSV ( 150) and the Si layer (110) and passivating the set of inner walls (151, 152) of the TSV (150) comprises: first selectively removing part of the first electrically conductive layer (130) to divide the first electrically conductive layer 130 into a first section (130’) and a second section (130”), wherein the first section (130’) is comprised within and does not contact the bottom circumference (153) of the etched TSV (150), wherein the second section (130”) is outside and is electrically isolated from the bottom circumference (153) of the etched TSV (150); and then passivating the set of inner walls (151, 152) of the TSV (150), wherein providing electrical contact between the TSV (150) and the electrically conductive layer in the stack that is arranged to act as the routing layer comprises: etching at the bottom (151) of the TSV (150) to the first electrically conductive layer (130, 130’), thereby extending the TSV (150) to the first electrically conductive layer (130, 130’); and metallizing a set of inner walls (151, 152) of the resulting TSV (150).

10. The method of claim 1, wherein the first electrically conductive layer (130) extends outside a bottom circumference (153) of the etched TSV (150), wherein the first electrically conductive layer (130) comprises a first electrically conductive material (131) facing the Si layer (110) and a second electrically conductive material (132), different from the first electricallyconductive material (131), that is in electrical contact with the first electrically conductive material (131), wherein the first electrically conductive material (131) is at least partially inside a bottom circumference (153) of the etched TSV (150) and also extends outside the bottom circumference (153) of the etched TSV (150); wherein the second electrically conductive material (132) comprises at least a first section that is comprised within and does not contact the bottom circumference (153) of the etched TSV (150), wherein breaking the electrical contact between the TSV ( 150) and the Si layer (110) and passivating the set of inner walls (151, 152) of the TSV (150) comprises: first selectively etching the first electrically conductive material (131) against the second electrically conductive material (132) from the front side (111) of the Si layer (110), thereby extending the TSV (150) to the second electrically conductive material (132) of the first electrically conductive layer (130, 130’) and dividing the first electrically conductive layer (130) into a first section (130’) and a second section (130”); and then passivating the set of inner walls (151, 152) of the TSV (150), wherein providing electrical contact between the TSV (150) and the electrically conductive layer in the stack that is arranged to act as the routing layer comprises: etching at the bottom (151) of the TSV (150) to the first electrically conductive layer (130, 130’), thereby extending the TSV (150) to the second electrically conductive material (132) of the first electrically conductive layer (130, 130’); and metallizing a set of inner walls (151, 152) of the resulting TSV (150). l.The method of claim 1, wherein the first electrically conductive layer (130) extends outside a bottom circumference (153) of the etched TSV (150), wherein the first electrically conductive layer (130) comprises a first electrically conductive material (131) and a second electrically conductive material (132), different from the first electrically conductive material (131),that is in electrical contact with the first electrically conductive material (131), wherein the second electrically conductive material (132) faces the Si layer (110), wherein the first electrically conductive material (131) is at least partially inside a bottom circumference (153) of the etched TSV (150) and also extends outside the bottom circumference (153) of the etched TSV (150); wherein the second electrically conductive material (132) comprises at least a first section that is comprised within and does not contact the bottom circumference (153) of the etched TSV (150) and a second section that is outside the bottom circumference (153) of the etched TSV (150), as seen in a top view, wherein breaking the electrical contact between the TSV (150) and the Si layer (110) and passivating the set of inner walls (151, 152) of the TSV (150) comprises: first selectively etching the first electrically conductive material (131) against the second electrically conductive material (132) from the front side (111) of the Si layer (110); and then passivating the set of inner walls (151, 152) of the TSV (150), wherein providing electrical contact between the TSV (150) and the electrically conductive layer in the stack that is arranged to act as the routing layer comprises: etching at the bottom (151) of the TSV (150) to the first electrically conductive layer (130, 130’), thereby dividing the first electrically conductive layer (130) into a first section (130’) and a second section (130”); and metallizing a set of inner walls (151, 152) of the resulting TSV (150).

12. The method of claim 1, wherein the first electrically conductive layer (130) extends outside a bottom circumference (153) of the etched TSV (150), wherein the IC (100) further comprises an additional insulating layer (115) embedded in the insulating layer (120), the additional insulating layer (115) partially overlapping with the first electrically conductive layer (130), being arranged between a part of the first electrically conductive layer (130) andthe Si layer (110) and extending from the outer periphery of said part of the first electrically conductive layer (130) to inside the bottom circumference (153) of the etched TSV (150); wherein breaking the electrical contact between the TSV (150) and the Si layer (110) and passivating the set of inner walls (151, 152) of the TSV (150) comprises: first selectively removing part of the first electrically conductive layer (130) to divide the first electrically conductive layer (130) into a first section (130’) and a second section (130”), wherein the first section (130’) is partly comprised within the bottom circumference (153) of the etched TSV ( 150) and further comprises the part of the first electrically conductive layer (130) that overlaps the additional insulating layer (115), wherein the second section (130”) is outside and is electrically isolated from the bottom circumference (153) of the etched TSV (150) and from the first section (130’); and then passivating the set of inner walls (151, 152) of the TSV (150), wherein providing electrical contact between the TSV (150) and the electrically conductive layer in the stack that is arranged to act as the routing layer comprises: etching at the bottom (151) of the TSV (150) to the first electrically conductive layer (130, 130’), thereby extending the TSV (150) to the first electrically conductive layer (130, 130’); and metallizing a set of inner walls (151, 152) of the resulting TSV (150).

13. The method of any one of the preceding claims, wherein the IC (100) further comprises at least one semiconductor component or micro electromechanical systems (MEMS) component (160), comprised in the Si layer or in the insulating layer, or comprised in another layer of the stack, or attached or electrically connected to the IC (100).

14. The method of claim 13, wherein at least one of the at least one semiconductor component or micro electro-mechanical systems (MEMS) component (160) is in electrical contact with the TSV (150).

15. An integrated circuit, IC, (100), comprising:a stack of a silicon, Si, layer (110) having a front side (111) and a back side (112), and an insulating layer (120) having a front side (121) that is in contact with the back side (112) of the Si layer, and a back side (122); and a first electrically conductive layer (130, 130’) embedded in the insulating layer (120), wherein the first electrically conductive layer (130, 130’) extends to and is in electric contact with the back side (112) of the Si layer (110), wherein an etch area for an intended TSV at least partially overlaps in the horizonal plane with the embedded first electrically conductive layer (130, 130’), so that the first electrically conductive layer (130, 130’) is arranged to act as a first etch-stop layer for a deep reactive ion etching, DRIE, process from the front side (111) of the Si layer (110).

16. The IC (100) of claim 15, further comprising a second electrically conductive layer (140, 140’, 140”) embedded in the insulating layer (120), the second electrically conductive layer (140, 140’, 140”) being arranged to act as a routing layer.

17. The IC (100) of claim 16, wherein the first electrically conductive layer (130) extends outside a bottom circumference (153) of the etched TSV (150), wherein the second electrically conductive layer (140, 140’, 140”) is electrically isolated from the first electrically conductive layer (130) and from the Si layer (110), wherein the etch area for the intended TSV at least partially overlaps in the horizonal plane also with the embedded second electrically conductive layer (140, 140’, 140”) so that second electrically conductive layer (140, 140’, 140”) is arranged to act as a second etch- stop layer for an etch process from the front side (111) of the Si layer (110).

18. The IC (100) of claim 15, wherein the first electrically conductive layer (130) comprises at least a first section (130’) and a second section (130”), wherein the first section (130’) is comprised within and does not contact the bottom circumference (153) of the etched TSV (150), wherein the second section (130”) is outside and is electrically isolated from the bottom circumference (153) of the etched TSV (150), wherein the first section (130’) and the second section (130”) are in electrical contact with each other via another conductivelayer or element comprised in the insulating layer (120) or being attached or connected to the insulating layer (120).

19. The IC (100) of claim 18, further comprising a top electrode (170) on the back side (122) of the insulating layer (120), wherein the first section (130’) and the second section (130”) are in electrical contact with each other via the top electrode (170).

20. The IC (100) of claim 15, further comprising a first top electrode (170’) and a second top electrode (170”) on the back side (122) of the insulating layer (120), wherein the first electrically conductive layer (130) comprises at least a first section (130’) and a second section (130”), wherein the first section (130’) is comprised within and does not contact the bottom circumference (153) of the etched TSV (150), wherein the second section (130”) is outside and is electrically isolated from the bottom circumference (153) of the etched TSV (150), and wherein each of the first and second sections (130’, 130”) of the first electrically conductive layer (130) is electrically connected to a respective one of the first and second top electrodes (170’, 170”).

21. The IC (100) of claim 15, wherein the first electrically conductive layer (130) extends outside a bottom circumference (153) of the etched TSV (150).

22. The IC (100) of claim 15, wherein the first electrically conductive layer (130) extends outside a bottom circumference (153) of the etched TSV (150), wherein the first electrically conductive layer (130) comprises a first electrically conductive material (131) facing the Si layer (110) and a second electrically conductive material (132), different from the first electrically conductive material (131), that is in electrical contact with the first electrically conductive material (131), wherein the first electrically conductive material (131) is at least partially inside a bottom circumference (153) of the etched TSV (150) and also extends outside the bottom circumference (153) of the etched TSV ( 150) , and wherein the second electrically conductive material (132) comprises at least a first section that is comprised within and does not contact the bottom circumference (153) of the etched TSV (150) and a second section that is outside the bottom circumference ( 153) of the etched TSV (150), as seen in a top view.

23. The IC (100) of claim 15, wherein the first electrically conductive layer (130) extends outside a bottom circumference (153) of the etched TSV (150),wherein the first electrically conductive layer (130) comprises a first electrically conductive material (131) and a second electrically conductive material (132), different from the first electrically conductive material (131), that is in electrical contact with the first electrically conductive material (131), wherein the second electrically conductive material (132) faces the Si layer (110), wherein the first electrically conductive material (131) is at least partially inside a bottom circumference (153) of the etched TSV (150) and also extends outside the bottom circumference (153) of the etched TSV (150), and wherein the second electrically conductive material (132) comprises at least a first section that is comprised within and does not contact the bottom circumference (153) of the etched TSV (150) and a second section that is outside the bottom circumference (153) of the etched TSV (150), as seen in a top view.

24. The IC (100) of claim 15, wherein the first electrically conductive layer (130) extends outside a bottom circumference (153) of the etched TSV (150), and wherein the IC (100) further comprises an additional insulating layer (115) embedded in the insulating layer (120), wherein the additional insulating layer (115) partially overlaps with the first electrically conductive layer (130), wherein the additional insulating layer (115) is arranged between a part of the first electrically conductive layer (130) and the Si layer (110) and extends from the outer periphery of said part of the first electrically conductive layer (130) to inside the bottom circumference (153) of the etched TSV (150).

25. The IC (100) of anyone of the claims 15 to 24, further comprising at least one semiconductor component or MEMS component (160) comprised in the Si layer (110), or comprised in another layer of the stack, or attached or electrically connected to the IC (100).

26. The method of any one of the claims 1-14 or the IC (100) of any one of the claims 15 to 25, wherein each of the first electrically conductive layer (130) and the second electrically conductive layer (140) comprises or consists of a metal material.

27. The method or IC (100) of claim 26, wherein the metal material comprises tungsten, W, or aluminum, Al.

8. The method of any one of the claims 1-14 or 26-27, or the IC (100) of any one of the claims 15 to 27, wherein the IC (100) is a complementary metal-oxide- semiconductor, CMOS, device.

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