Quantum circuit conversion program, quantum circuit conversion method, and information processing device

Abstract

The present invention reduces the number of gate operations for an arbitrary rotation.　A quantum circuit (2) includes rotation gates (2a, 2b) that represent gate operations for arbitrary rotation for rotating, around an axis different from the coordinate axes, the state of a qubit to be manipulated. An information processing device (10) converts the rotation gates (2a, 2b) for the arbitrary rotation into partial circuits (4a, 4b) that perform rotation gate operations for causing a rotation that is insufficient, relative to the arbitrary rotation, by a prescribed angle around the Z axis. The information processing device (10) then changes, in the quantum circuit (2), the gate operation of one or more quantum gates following the rotation gates (2a, 2b) for the qubit to be manipulated into a gate operation for causing a rotation that is in excess by the prescribed angle around the Z axis.

Description

Quantum circuit conversion program, quantum circuit conversion method, and information processing device

[0001] The present invention relates to a quantum circuit conversion program, a quantum circuit conversion method, and an information processing device.

[0002] Currently available quantum computers are of the type known as NISQ (Noisy Intermediate-Scale Quantum Computer), which use superconducting or ion-trapped quantum bits. These quantum devices have an error rate of around 1% and a quantum bit count of around 10-1000. Such small-scale quantum computers cannot completely correct errors. Therefore, when performing quantum computations on a quantum computer, it is important to use quantum circuits that can reduce errors as much as possible.

[0003] Quantum computers also implement one-qubit gates and two-qubit gates as quantum gates for manipulating qubits. These quantum gates are called native gates. Which two-qubit gates are supported as native gates depends on the quantum device type used in the quantum computer.

[0004] As a technology for creating quantum circuits, for example, a shortened quantum circuit has been proposed that can obtain the same calculation results as a quantum algorithm that requires a large number of quantum gate operations on an NISQ device. A quantum computer has also been proposed that reduces the total number of gate operations compared to the normal number of gate operations when using the imaginary time evolution method. Various other methods for optimizing the design of quantum circuits have also been proposed.

[0005] Japanese Patent Publication No. 2022-180189 International Publication No. 2021 / 177031 U.S. Patent Application Publication No. 2020 / 0074035 U.S. Patent Application Publication No. 2020 / 0104747

[0006] One type of gate operation for a single quantum bit is an arbitrary rotation gate operation, which rotates the bit by an arbitrary angle in an arbitrary direction. An arbitrary rotation gate operation is executed by decomposing it into native gates. However, if the number of gate operations after decomposition into native gates is large, the execution time of the quantum circuit will be extended. If the execution time of the quantum circuit is long, the execution time may exceed the coherent time, making it impossible to obtain the correct result. Therefore, it is desirable to realize an arbitrary rotation gate operation with as few gate operations as possible.

[0007] In one aspect, the present invention aims to reduce the number of gate operations for an arbitrary rotation.

[0008] One proposal provides a quantum circuit conversion program that causes a computer to execute the following process: The computer converts a first rotation gate, which is included in a quantum circuit and indicates a gate operation of an arbitrary rotation that rotates the state of a quantum bit to be operated about an axis different from the coordinate axes, into a partial circuit that performs a rotation gate operation that is insufficient in rotation by a predetermined angle around the Z axis relative to the arbitrary rotation. The computer then changes the gate operation of one or more quantum gates in the quantum circuit that follow the first rotation gate for the quantum bit to be operated about, to a gate operation that performs an additional rotation by the predetermined angle around the Z axis.

[0009] According to one aspect, the number of gate operations required for any rotation can be reduced. The above and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings illustrating preferred embodiments of the present invention by way of example.

[0010] 1 is a diagram showing an example of a quantum circuit conversion method according to a first embodiment; FIG. 2 is a diagram showing an example of the configuration of a quantum computing system; FIG. 3 is a diagram showing an example of the hardware configuration of a quantum computer device; FIG. 4 is a diagram showing an example of the hardware configuration of a classical computer device; FIG. 5 is a diagram showing an example of a quantum circuit including gate operations of arbitrary rotation; FIG. 6 is a diagram showing an example of a method of decomposing gate operations to perform arbitrary rotation with a small number of gate operations; FIG. 7 is a diagram showing an example of functions possessed by a classical computer device; FIG. 8 is a flowchart showing an example of a quantum computing procedure; FIG. 9 is a flowchart (1 / 2) showing an example of a procedure for conversion to native gates; FIG. 10 is a diagram showing an example of conversion from a ZXZXZ circuit to a native gate of an ion trap quantum device; XX 1 is a diagram showing an example of a correspondence relationship with a gate. XX 1 is a diagram illustrating an example of a conversion process for a partial circuit including a gate. XX FIG. 1 is a diagram showing an example of conversion processing of a partial circuit including a gate. FIG. 2 is a first diagram showing an example of conversion of a quantum gate of arbitrary rotation to a native gate. FIG. 3 is a diagram showing an example of conversion of the final gate operation of an arbitrary rotation to a native gate. FIG. 4 is a third diagram showing an example of conversion of a quantum gate of arbitrary rotation to a native gate. FIG. 5 is a flowchart (2 / 2) showing an example of the procedure of conversion processing to a native gate.

[0011] The present embodiment will be described below with reference to the drawings. Note that each embodiment can be implemented by combining multiple embodiments within a consistent range. [First Embodiment] The first embodiment is a quantum circuit conversion method that can reduce the number of quantum gates used for gate operation of arbitrary rotation.

[0012] Fig. 1 is a diagram illustrating an example of a quantum circuit conversion method according to a first embodiment. Fig. 1 shows an information processing device 10 for implementing the quantum circuit conversion method. The information processing device 10 can implement the quantum circuit conversion method by, for example, executing a quantum circuit conversion program.

[0013] The information processing device 10 includes a storage unit 11 and a processing unit 12. The storage unit 11 is, for example, a memory or a storage device included in the information processing device 10. The processing unit 12 is, for example, a processor or an arithmetic circuit included in the information processing device 10.

[0014] The storage unit 11 stores a quantum circuit 2 that indicates a procedure for quantum computation using the quantum computer device 1. The quantum circuit 2 includes rotation gates 2a and 2b (first rotation gates) that indicate an arbitrary rotation gate operation that rotates the state of the quantum bit to be manipulated around an axis different from the coordinate axes. The rotation axis different from the coordinate axes is an arbitrary rotation axis other than the X-axis, Y-axis, and Z-axis of the Bloch sphere. The arbitrary rotation axis is represented, for example, by a three-dimensional axis vector.

[0015] For example, in quantum circuit 2, a rotation gate 2a with a rotation angle of "α" around a rotation axis "n" (n is a three-dimensional axis vector) is arranged at the first quantum bit "q". In quantum circuit 2, a rotation gate 2b with a rotation angle of "α" around a rotation axis "n" (n is a three-dimensional axis vector) is arranged at the second quantum bit "q".

[0016] Next to the rotation gates 2a and 2b for the two quantum bits "q0, q1", respectively, there is an MS (Mollmer-Sorenson (the o next to M and S is marked with a slash)) gate 2c with an angle parameter of (0, 0). The gate operation by the MS gate 2c with an angle parameter of (0, 0) is XX This is the same as the (π / 2) gate. For quantum bit "q0", a rotation gate 2d (sixth rotation gate) with arbitrary rotation is placed next to the MS gate 2c. For quantum bit "q1", a rotation gate 2e (sixth rotation gate) with arbitrary rotation is placed next to the MS gate 2c.

[0017] The processing unit 12 converts the quantum circuit 2 into a quantum circuit 3 that uses native gates of the quantum computer device 1. For example, the native gates of one quantum bit of the quantum computer device 1 are defined as a "1Q1 gate" and a "1Q2 gate."

[0018] The 1Q1 gate is a rotation gate that changes the state of a quantum bit to a state after rotation around the Z axis and rotation around the X axis in a single gate operation. The state after the change is, for example, the state of the quantum bit when it is rotated by twice the angle specified by the angle parameter in the opposite direction to the specified rotation direction around the Z axis and then rotated 180 degrees around the X axis. The gate operation for the 180-degree rotation around the X axis is the same as the gate operation of an X gate.

[0019] The 1Q2 gate is a rotation gate that transitions the state of a quantum bit to a state after rotation around the Z axis, rotation around the X axis, and rotation around the Z axis in a single gate operation. The transition state is, for example, a state obtained by rotating the quantum bit state in the opposite direction to the specified rotation direction around the Z axis by an angle specified by an angle parameter, rotating 90 degrees around the X axis, and then rotating by a specified angle in the specified rotation direction around the Z axis. The gate operation for a 90-degree rotation around the X axis is the same as the gate operation of an SX gate. The two-qubit native gate of the quantum computer device 1 is, for example, an MS gate.

[0020] For example, the processing unit 12 converts into partial circuits 4a and 4b each of the rotation gates 2a and 2b, which are included in the quantum circuit 2 and perform arbitrary rotation and rotate the state of the quantum bit to be operated about an axis different from the coordinate axis. The partial circuits 4a and 4b are quantum circuits that perform a rotation operation in which the rotation about the Z axis is insufficient by a predetermined angle with respect to the arbitrary rotation of the corresponding rotation gates 2a and 2b.

[0021] For example, the rotary gate 2a for the quantum bit "q0" is converted into a partial circuit 4a including a rotary gate 3a (second rotary gate) and a rotary gate 3c (third rotary gate). Also, the rotary gate 2b for the quantum bit "q1" is converted into a partial circuit 4b including a rotary gate 3b (second rotary gate) and a rotary gate 3d (third rotary gate).

[0022] The rotation gates 3a and 3b and the rotation gates 3c and 3d are all 1Q2 gates. In this case, an arbitrary rotation "R" to the quantum bit "q" is n0 (α0)" is "R n0 (α0) = 1Q2 (φ'0) - 1Q2 (θ'0) - RZ The rotation angle parameters "φ'0, θ'0, λ'0" are real numbers. An arbitrary rotation "R n1 (α1)" is "R n1 (α1) = 1Q2 (φ'1) - 1Q2 (θ'1) - R Z (λ'1)). The rotation angle parameters "φ'1, θ'1, λ'1" are all real numbers. Consecutive quantum gates connected by "-" indicate that the gate operations of the connected quantum gates are executed in order from left to right.

[0023] In this case, "λ'0" and "λ'1" indicate the predetermined angles of the shortage of rotation around the Z axis of each quantum bit after implementing the partial circuits 4a and 4b. In other words, simply adding rotation gate 3a and rotation gate 3c to quantum circuit 3 results in a shortage of rotation around the Z axis by "λ'0" for the desired arbitrary rotation in quantum bit "q0". Similarly, simply adding rotation gate 3b and rotation gate 3d to quantum circuit 3 results in a shortage of rotation around the Z axis by "λ'1" for the desired arbitrary rotation in quantum bit "q1".

[0024] Therefore, the processing unit 12 changes the gate operation of one or more quantum gates subsequent to the rotation gates 2a and 2b for the quantum bit to be operated in the quantum circuit 2 to a gate operation that rotates the quantum bit by an additional predetermined angle around the Z axis to compensate for the shortage in the converted partial circuits 4a and 4b. Z (λ'0) and R Z The gate operation of rotation with respect to (λ'1) is implemented by the quantum gates subsequent to the rotation gates 2a and 2b.

[0025] 1, an MS gate 2c is placed next to the rotary gates 2a and 2b in the quantum circuit 2. In this case, the processing unit 12 adds a value obtained by reversing the sign of a predetermined angle to the angle parameter of the MS gate 2c next to the rotary gates 2a and 2b. After the angle parameter update, the MS gate 3e is placed next to the rotary gates 3c and 3d in the quantum circuit 3.

[0026] Furthermore, the processing unit 12 adds a predetermined angle to the rotation angles around the Z axis of the rotation gates 2d and 2e that are next to the MS gate 2c. Rotation gates 3f and 3g, which are obtained by changing the rotation angles of the rotation gates 2d and 2e, are placed next to the MS gate 3e in the quantum circuit 3.

[0027] In this way, the arbitrary rotation of each of the rotation gates 2a and 2b is implemented using two native gates. That is, the rotation gates 2a and 2b are converted into partial circuits 4a and 4b that exhibit rotation gate operation with insufficient rotation in the Z-axis direction. If the insufficient rotation in the Z-axis direction is acceptable, the partial circuits 4a and 4b can be simplified compared to an equivalent circuit that accurately implements the arbitrary rotation. As a result, the number of quantum gates used for gate operation of the arbitrary rotation is reduced.

[0028] For example, any rotation of the rotary gate 2a can be decomposed into rotations around the coordinate axes. The decomposition of any rotation of the rotary gate 2a into rotations around the Z axis and rotations around the X axis (ZX decomposition) is expressed as "R n0 (α0) = R Z (φ0)-R x (θ0)-R Z (λ0)" where "φ0, θ0, λ0" are real numbers that indicate Euler rotation angle parameters. The ZX decomposition of an arbitrary rotation of the rotation gate 2b is "R n1 (α1) = R Z (φ1)-R x (θ1)-R Z (λ1)" where "φ1, θ1, λ1" are real numbers that indicate Euler rotation angle parameters.

[0029] When an arbitrary rotation is ZX decomposed in this way, the values ​​of the angle parameters of rotation gates 3a and 3b and rotation gates 3c and 3d can be determined based on the Euler rotation angle parameters obtained by the decomposition. For example, the value of the angle parameter "φ'0" of rotation gate 3a (1Q2(φ'0)) is "φ'0 = -φ0". The value of the angle parameter "φ'1" of rotation gate 3b (1Q2(φ'1)) is "φ'1 = -φ1". The value of the angle parameter "θ'0" of rotation gate 3c (1Q2(θ'0)) is "θ'0 = -(φ0 + θ0)". The value of the angle parameter "θ'1" of rotation gate 3d (1Q2(θ'1)) is "θ'1 = -(φ1 + θ1)".

[0030] In this case, the predetermined angle "λ'0" which is the insufficient rotation around the Z axis for the quantum bit "q0" is "λ'0 = φ0 + θ0 + λ0". The predetermined angle "λ'1" which is the insufficient rotation around the Z axis for the quantum bit "q1" is "λ'1 = φ1 + θ1 + λ1".

[0031] The value obtained by subtracting the insufficient angle of rotation around the Z axis for each of the quantum bit "q0" and the quantum bit "q1" becomes the angle parameter (-λ'0, -λ'1) of the MS gate 3e. Furthermore, the rotation gate 2d next to the MS gate 2c in the quantum circuit 2 becomes the rotation gate 3f in the quantum circuit 3. The gate operation of the rotation gate 2d is called "R n2 (α2)" and the gate operation of the rotary gate 3f is "R n4 (α4)" is "R n4 (α4) = R Z (λ'0)-R n2 (α2)".

[0032] The rotation gate 2e next to the MS gate 2c in the quantum circuit 2 becomes the gate 3g in the quantum circuit 3. The gate operation of the rotation gate 2e is called "R n3 (α3)" and the gate operation of the rotary gate 3g is "R n5 (α5)" is "R n5 (α5) = R Z (λ'1)-R n3 (α3)".

[0033] In this way, the rotation operation around the Z axis (R Z (λ'0), R Z (λ'1)) is summarized into an MS gate 3e and rotation gates 3f and 3g. In the example of Figure 1, the rotation gates 3f and 3g are also rotation gates of arbitrary rotation. If the rotation gates 3f and 3g are followed by quantum gates such as MS gates, the rotation gates 3f and 3g can also be converted into native gates, just like the rotation gates 2a and 2b.

[0034] In the example of Figure 1, quantum gates follow after the rotation gates 2a and 2b with arbitrary rotation, but the rotation gates 2a and 2b with arbitrary rotation may be the last quantum gate. In that case, the missing rotation around the Z axis when converted to rotation gates 3a to 3d cannot be combined with other quantum gates.

[0035] In such a case, the processing unit 12 implements the missing rotation operation around the Z axis using native gates after the rotation gates 3c and 3d in the partial circuits 4a and 4b. For example, the processing unit 12 adds a 1Q1 gate (fourth gate) with an angle parameter set to "-λ' / 2" and a 1Q1 gate (fifth gate) with an angle parameter set to "0" after the rotation gates 3c and 3d, respectively. The 1Q1 gate with an angle parameter set to "-λ' / 2" changes the state of the quantum bit to a state obtained after rotating λ' around the Z axis and rotating 180° around the X axis in a single gate operation. The gate operation of the 1Q1 gate with an angle parameter set to "0" is the same as the gate operation of the X gate.

[0036] For example, if the rotation gate 2a for arbitrary rotation of the quantum bit "q0" is the last quantum gate, then a 1Q1 gate with an angle parameter set to "-λ'0 / 2" is placed next to the rotation gate 3c, and then a 1Q1 gate with an angle parameter set to "0" is placed after that. Similarly, if the rotation gate 2b for arbitrary rotation of the quantum bit "q1" is the last quantum gate, then a 1Q1 gate with an angle parameter set to "-λ'1 / 2" is placed after the rotation gate 3d, and then a 1Q1 gate with an angle parameter set to "0" is placed after that.

[0037] As a result, the final arbitrary rotation rotary gate of the quantum circuit 2 can also be converted into a native gate in the quantum computer device 1. In the example of FIG. 1 , an MS gate 2c is located after the arbitrary rotation rotary gates 2a and 2b, but there may also be another rotary gate after the first rotary gates 2a and 2b. In this case, when the other rotary gate is decomposed, the leading quantum gate after decomposition becomes a rotary gate around the Z axis (the seventh rotary gate). In this case, the processing unit 12 adds a predetermined angle, which is the missing rotation angle around the Z axis in the partial circuits 4a and 4b, to the rotation angle of the rotary gate indicating the next rotation around the Z axis after the arbitrary rotation rotary gates 2a and 2b. As a result, the missing rotation operation around the Z axis in the converted rotary gates 3a to 3d is integrated into the next rotary gate.

[0038] In the quantum circuit 2, there may be a series of multiple one-qubit gates operating on a first qubit. In this case, the processing unit 12 converts the multiple consecutive one-qubit gates into a single one-qubit gate with an arbitrary rotation. This allows the gate operations of a large number of consecutive rotation gates to be replaced with, for example, two native gates.

[0039] Note that when the arbitrary rotation rotary gates 2a and 2b are converted into native gates, 3a to 3d, the subsequent quantum gates are modified. Therefore, the processing unit 12 identifies the arbitrary rotation rotary gates in order from the beginning of the quantum circuit 2. Then, each time the processing unit 12 identifies an arbitrary rotation rotary gate, it performs a process of converting the identified rotary gate into a subcircuit using native gates and a process of changing the gate operation of one or more subsequent quantum gates. In this way, by proceeding with the conversion process in order from the beginning of the quantum circuit 2, the quantum circuit 3 using native gates can be efficiently generated.

[0040] Second Embodiment The second embodiment is a quantum computer system that reduces the number of gate operations required for arbitrary rotation of a trapped ion quantum bit.

[0041] FIG. 2 is a diagram illustrating an example of the configuration of a quantum computing system. The quantum computing system 300 is a computer system using, for example, an ion trap quantum device. The quantum computing system 300 includes a classical computer device 100 and a quantum computer device 200. Terminal devices 401, 402, ... are connected to the classical computer device 100 via a network 20. The terminal devices 401, 402, ... are computers used by users who request quantum computing by the quantum computing system 300. The classical computer device 100 accepts quantum circuits from the terminal devices 401, 402, .... A quantum circuit indicates the order of operations on quantum bits by the arrangement of elements such as gates. A quantum bit is a bit that can represent a superposition of a "0" state and a "1" state.

[0042] The classical computer device 100 instructs the quantum computer device 200 to control quantum bits in accordance with the quantum circuits received from the terminal devices 401, 402, .... The classical computer device 100 also acquires measurement results of each quantum bit from the quantum computer device 200.

[0043] The quantum computer device 200 has a plurality of quantum bits and devices for manipulating each of the quantum bits. The quantum bits of the quantum computer device 200 are realized by, for example, an ion trap method.

[0044] 3 is a diagram showing an example of the hardware configuration of a quantum computer device 200. The quantum computer device 200 includes a group of ion trap quantum bits 201, a plurality of laser light source devices 202 and 203, a diffractive optical element (DOE) 204, a lens 205, an acousto-optic modulator (AOM) 206, and a detector 207.

[0045] The ion trap quantum bit group 201 is a group of quantum bits whose states are represented using ion traps. One laser light source device 202 outputs a global address beam to be irradiated onto the plurality of quantum bits. The other laser light source device 203 outputs laser light that becomes individual address beams. The laser light output by the laser light source device 203 is incident on a lens 205 via a DOE 204, becoming multiple parallel laser beams that then enter an AOM 206. The AOM 206 modulates the frequency and amplitude of these laser beams according to the gate operation to be performed. The laser light modulated by the AOM 206 is irradiated onto the plurality of quantum bits as individual address beams. This allows a gate operation to be performed on any quantum bit. The detector 207 detects photons output from the quantum bit to be measured. The state of the quantum bit is measured based on the amount of photons detected by the detector 207.

[0046] The classical computing device 100 controls such a quantum computing device 200 to cause the quantum computing device 200 to perform gate operations using the AOM 206 or measure states using the detector 207 .

[0047] FIG. 4 illustrates an example hardware configuration of a classical computer device. The classical computer device 100 is entirely controlled by a central processing unit (CPU) 101. The CPU 101 is a processor that executes program instructions. The CPU 101 may include multiple processor cores. The CPU 101 may also be multiple processors, such as a microprocessing unit (MPU) or a digital signal processor (DSP). At least some of the functions realized by the CPU 101 executing a program may be realized by electronic circuits such as an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). A random access memory (RAM) 102 and multiple peripheral devices are connected to the CPU 101 via a bus 100a.

[0048] The RAM 102 is the main storage device of the classical computer device 100. The RAM 102 temporarily stores at least a portion of the OS (Operating System) programs and application programs executed by the CPU 101. The RAM 102 also stores various data used in processing by the CPU 101. The classical computer device 100 may be provided with a type of memory other than RAM, or may be provided with multiple memories.

[0049] The peripheral devices connected to the bus 100 a include a hard disk drive (HDD) 103 , a graphics processing unit (GPU) 104 , an input interface 105 , an optical drive device 106 , device connection interfaces 107 and 108 , and a network interface 109 .

[0050] The HDD 103 is an auxiliary storage device of the classical computer device 100. The HDD 103 magnetically writes and reads data to and from a built-in magnetic disk. The HDD 103 stores the OS program, application programs, and various data. The classical computer device 100 may also be equipped with other types of auxiliary storage devices, such as flash memory or a solid-state drive (SSD), or may be equipped with multiple auxiliary storage devices.

[0051] A monitor 21 is connected to the GPU 104. The GPU 104 displays an image on the screen of the monitor 21 in accordance with an instruction from the CPU 101. The monitor 21 may be a display device using an organic EL (Electro Luminescence) display device or a liquid crystal display device.

[0052] The input interface 105 is connected to a keyboard 22 and a mouse 23. The input interface 105 transmits signals sent from the keyboard 22 and the mouse 23 to the CPU 101. The mouse 23 is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

[0053] The optical drive device 106 uses laser light or the like to read data recorded on an optical disc 24. The optical disc 24 is a portable recording medium on which data is recorded so that it can be read by reflected light. The optical disc 24 includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (Rewritable), etc.

[0054] The device connection interface 107 is a communication interface for connecting peripheral devices to the classical computer device 100. For example, a memory device 25 or a memory reader / writer 26 can be connected to the device connection interface 107. The memory device 25 is a recording medium equipped with a function for communicating with the device connection interface 107. The memory reader / writer 26 is a device for writing data to a memory card 27 or reading data from the memory card 27. The memory card 27 is a card-type recording medium.

[0055] The device connection interface 108 is a communication interface for connecting the quantum computer device 200 to the classical computer device 100. The classical computer device 100 transmits instructions for controlling quantum bits to the quantum computer device 200 via the device connection interface 108.

[0056] The network interface 109 is connected to the network 20. The network interface 109 transmits and receives data to and from other computers or communication devices via the network 20.

[0057] The classical computer device 100 can realize the processing functions of the second embodiment with the hardware configuration described above. The information processing device 10 shown in the first embodiment can also be realized with hardware similar to that of the classical computer device 100 shown in Fig. 4. The CPU 101 is an example of the processing unit 12 shown in the first embodiment.

[0058] The classical computer device 100 realizes the processing functions of the second embodiment by executing a program recorded on, for example, a computer-readable recording medium. The program describing the processing to be executed by the classical computer device 100 can be recorded on various recording media. For example, the program to be executed by the classical computer device 100 can be stored on the HDD 103. The CPU 101 loads at least a portion of the program from the HDD 103 into the RAM 102 and executes the program. The program to be executed by the classical computer device 100 can also be recorded on a portable recording medium such as the optical disk 24, memory device 25, or memory card 27. The program stored on the portable recording medium becomes executable after being installed on the HDD 103 under the control of, for example, the CPU 101. The CPU 101 can also read and execute the program directly from the portable recording medium.

[0059] In the system described above, the classical computer device 100 acquires quantum circuits describing procedures for gate operations of qubits for quantum computation from the terminal devices 401, 402, etc. The quantum circuits acquired from the terminal devices 401, 402, etc. include gate operations of three or more qubit gates. On the other hand, the gate operations in the quantum computer device 200 are limited to gate operations of one qubit gate or two qubit gates.

[0060] Therefore, the classical computer device 100 converts three or more quantum gates included in the quantum circuit to be subjected to quantum computation into an equivalent circuit using one or two quantum bit gates that can be executed by the quantum computer device 200. Then, the classical computer device 100 instructs the quantum computing system 300 to perform quantum computation using the converted quantum circuit.

[0061] Quantum computation based on a quantum circuit specified by a user is performed by such a quantum computing system 300. For example, the classical computing device 100 generates a quantum circuit according to a problem to be solved, and instructs the quantum computing device 200 to execute the quantum circuit.

[0062] Depending on the problem to be solved, a gate operation for an arbitrary rotation of one quantum bit may be required. The gate operation for an arbitrary rotation can be decomposed into multiple one-qubit gates using three Euler rotation angle parameters (θ, φ, λ) (θ, φ, λ are real numbers). The values ​​of the Euler rotation angle parameters are determined according to the rotation axis and rotation angle.

[0063] For example, when the gate operation of an arbitrary rotation is decomposed into ZX, an equivalent circuit "R" is obtained by combining a rotation gate around the X axis (X rotation gate) and a rotation gate around the Z axis (Z rotation gate). Z (φ)-R X (θ)-R Z (λ)" can be realized as "(R Z (λ) R X (θ) R Z (φ)) (where φ is the tensor product).

[0064] If the quantum device is a superconducting device, the Z rotation gate can be virtually realized by a computational transformation, and there is no need to perform an actual gate operation on the qubit. Note that in NISQ devices, even rotation operations around a rotation axis that can be implemented as a native gate may have limitations on the angle of rotation. For example, in superconducting devices, a Z rotation gate can be implemented at any rotation angle, but X rotation is often limited to 90°. A 90° X rotation gate is an SX gate. Therefore, in order to implement a one-qubit gate with any rotation, R Z -SX-R Z -SX-R Z For example, "R Z (φ)-R X (90)-R Z (θ)-R X (90)-R Z (λ)" allows gate operation with arbitrary rotation.

[0065] In this way, if the quantum device is a superconducting device, arbitrary rotation gate operation is possible by essentially operating the SX gate twice. In contrast, in the case of a trapped ion quantum device, the SX gate is not included in the native gate. For example, the following gates are examples of native gates for one-qubit gates of trapped ion quantum devices.

[0066]

[0067]

[0068] 1Q1(φ) is "R Z This is equivalent to the gate operation of (-2φ)-X. The formula is "1Q1(φ) = X R Z (-2φ)" (· is the tensor product). 1Q2(φ) is expressed as "R Z (-φ)-SX-R Z (φ)" gate operation. The formula is "1Q2(φ) = R Z (φ) SX R Z (-φ)" (· is the tensor product). In this way, the native gate of the one-qubit gate of the ion trap quantum device can be expressed as a Z rotation gate of any angle and an RX (90) or R X This is a gate operation that combines (180).

[0069] An example of a native gate for a two-qubit gate of an ion trap quantum device is the MS gate shown in formula (3).

[0070]

[0071] When the values ​​of the angle parameters φ1 and φ2 of the MS gate are both "0", R XX (π / 2) gate (MS(0,0) = R XX (π / 2)). Here, we consider the case where an arbitrary rotation gate operation is performed in an ion trap type quantum device. For example, an arbitrary rotation gate operation "R Z (φ)-SX-R Z (θ)-SX-R Z (λ) can be converted into gate operations that can be performed on the trapped ion quantum device by the following equation: 1Q2(φ')-1Q2(θ')-1Q1(λ')-1Q1(0) = [R Z (-φ')-SX-R Z (φ′)]−[R Z (-θ')-SX-R Z (θ′)][R Z (-2λ')-X]-[X] =R Z (-φ')-SX-R Z (φ'-θ')-SX-R Z (θ'-2λ') Here, "φ'=-φ", "θ'=-(φ+θ)", and "λ'=-(φ+θ+λ) / 2".

[0072] FIG. 5 is a diagram showing an example of a quantum circuit including an arbitrary rotation gate operation. For example, after performing an arbitrary rotation gate operation on each of two quantum bits, an XX interaction gate operation “R XX The Euler rotation angle parameter for the first qubit is (θ 00 , φ 00 , λ 00 ), and the Euler rotation angle parameter for the second qubit is (θ 10 , φ 10 , λ10 )

[0073] In the quantum circuit 31 after the gate operation of the arbitrary rotation is ZXZXZ converted, the gate operation “R Z (φ 00 )-SX-R Z (θ 00 )-SX-R Z (λ 00 ) is performed on the second quantum bit. Z (φ 10 )-SX-R Z (θ 10 )-SX-R Z (λ 10 ) is performed. Then, the two qubits are assigned "R XX " gate operation is carried out.

[0074] In the quantum circuit 32 converted for the ion trap type quantum device, the gate operation “1Q2(φ′ 00 ) -1Q2(θ' 00 )-1Q1(λ' 00 )-1Q1(0)" is performed. Also, for the second quantum bit, the gate operation "1Q2(φ' 10 ) -1Q2(θ' 10 )-1Q1(λ' 10 )-1Q1(0)" is performed. Then, the gate operation "MS(0,0)" is performed on the two quantum bits.

[0075] Thereafter, the gate operations of the arbitrary rotation are converted into native gates in sequence. Note that when the order of execution of the gate operations of the arbitrary rotation is i (i=0, 1, 2, . . . ) and the quantum bit number is k (k=0, 1, 2, . . . ), "φ' ik =-φ ik ", "θ' ik = - (φ ik +θ ik ) and "λ' ik = - (φ ik +θ ik +λ ik ) / 2".

[0076] In this way, in the case of an ion trap type quantum device, if an arbitrary rotation is realized by the gate operation "1Q2(φ')-1Q2(θ')-1Q1(λ')-1Q1(0)", four gate operations are performed. This is the same as the gate operation "R Z (φ)-SX-R Z (θ)-SX-R Z Compared with "(λ)" (two SX gate operations), the number of gate operations is doubled.

[0077] Quantum devices have a limited time, called coherent time, during which the quantum state of a qubit can be maintained. Therefore, it is desirable to implement a gate circuit that achieves the same quantum computation with as few gate operations as possible. There are two types of coherent time: T1: The time during which the excited state of the qubit can be maintained. T2: The time during which the qubit can maintain a superposition state. If the time required for gate operations according to the quantum circuit exceeds the coherent time, the correct computation result cannot be obtained. Furthermore, as the number of gate operations increases, the noise of the qubit increases and the fidelity decreases. Therefore, it is desirable to minimize the number of gate operations when performing quantum computation.

[0078] For example, in a quantum computer using superconducting quantum devices, arbitrary rotation gate operations can be realized using a relatively simple equivalent circuit by combining an X-rotation gate and a Z-rotation gate. However, in the case of ion trap quantum devices, arbitrary rotation cannot be performed using an equivalent circuit combining an X-rotation gate and a Z-rotation gate. This requires combining more native gates, which increases the number of gate operations. If the number of gate operations increases too much, the time required to perform gate operations according to the quantum circuit may exceed the coherent time. If the execution time of the quantum circuit exceeds the coherent time, the correct result cannot be obtained.

[0079] Therefore, in order to realize an arbitrary rotation gate operation with a small number of gate operations, the classical computer device 100 implements the final Z rotation gate operation when the arbitrary rotation gate operation is separated into multiple gate operations as a single gate operation.

[0080] FIG. 6 is a diagram showing an example of a method for decomposing gate operations that perform arbitrary rotation with a small number of gate operations. The classical computer device 100 decomposes the gate operation of an arbitrary rotation into a native gate of an ion trap quantum device that corresponds to a gate operation of rotation with a predetermined amount of Z rotation remaining, and gate operations of less than Z rotation. The correspondence between the gate operations after decomposition and the gate operations after ZXZXZ transformation is as follows: "1Q2(φ')-1Q2(θ')-R Z (λ′)=R Z (-φ')-SX-R Z (φ'-θ')-SX-R Z (θ'+λ')" where "φ' = -φ", "θ' = -(φ+θ)", and "λ' = φ+θ+λ". Arbitrary rotation gate operation "1Q2(φ')-1Q2(θ')-R Z (λ')" the last Z rotation gate operation "R Z In many cases, the gate operation "R (λ')" can be integrated into the subsequent gate operation. For example, as shown in FIG. 5, there is a case where an MS gate is executed after an arbitrary rotation. In this case, by changing the angle parameter of the MS gate, the gate operation of the arbitrary rotation can be decomposed into the final Z rotation gate operation "R Z (λ')) can be combined into a subsequent MS gate.

[0081] 7 is a diagram illustrating an example of functions of a classical computer device. The classical computer device 100 includes a computation request receiving unit 110, a quantum circuit generation unit 120, and a quantum computation control unit 130.

[0082] The computation request receiving unit 110 receives quantum computation requests from the terminal devices 401, 402, .... The computation request receiving unit 110 requests the quantum circuit generation unit 120 to generate a quantum circuit corresponding to the specified quantum computation. Furthermore, upon receiving a computation result from the quantum computation control unit 130, the computation request receiving unit 110 transmits the computation result to the terminal device that sent the computation request.

[0083] The quantum circuit generation unit 120 generates a quantum circuit for executing a quantum computation specified by the computation request receiving unit 110. For example, the quantum circuit generation unit 120 generates a quantum circuit by allowing the use of quantum gates other than the native gates of the ion trap quantum device. The quantum circuit generation unit 120 then converts the generated quantum circuit into a quantum circuit that uses the native gates of the ion trap quantum device. The quantum circuit generation unit 120 transmits the converted quantum circuit to the quantum computation control unit 130.

[0084] The quantum computing control unit 130 instructs the quantum computer device 200 to perform quantum bit gate operations in accordance with each of the multiple quantum circuits acquired from the quantum circuit generation unit 120. Each time a gate operation in accordance with a quantum circuit is completed, the quantum computing control unit 130 receives a measurement result of the quantum bit state from the quantum computer device 200. The measurement result is a probability distribution of the quantum bit state (bit string). The quantum computing control unit 130 calculates a solution to the problem to be solved from the measurement results obtained from each of the multiple quantum circuits, and transmits the calculation result to the calculation request receiving unit 110.

[0085] The functions of each element shown in Fig. 7 can be realized, for example, by having a computer execute a program module corresponding to that element. Fig. 8 is a flowchart showing an example of a quantum computing procedure. The process shown in Fig. 8 will be explained below in order of step number.

[0086] [Step S101] The computation request receiving unit 110 receives a quantum computation request from one of the terminal devices. The computation request receiving unit 110 then instructs the quantum circuit generation unit 120 to generate a quantum circuit. In response to the instruction, the quantum circuit generation unit 120 generates a quantum circuit corresponding to the problem to be solved. The quantum circuit generated at this time includes quantum gates other than the native gate of the ion trap quantum device.

[0087] [Step S102] The quantum circuit generation unit 120 converts the generated quantum circuit into native gates. The details of the conversion process into native gates will be described later (see FIGS. 9 and 18).

[0088] [Step S103] The quantum computing control unit 130 instructs the quantum computing device 200 to perform quantum computing based on a quantum circuit configured with native gates. The quantum computing device 200 then executes quantum computing according to the quantum circuit. The quantum computing device 200 transmits the result of the measurement performed at the end of the quantum computing to the quantum computing control unit 130.

[0089] [Step S104] The quantum computing control unit 130 acquires the measurement results from the quantum computer device 200. The quantum computing control unit 130 calculates a solution to the problem to be solved based on the acquired measurement results, and transmits the calculation results to the computation request receiving unit 110. The computation request receiving unit 110 transmits the calculation results to the terminal device that sent the computation request.

[0090] Next, the conversion process to native gates will be described in detail. Figure 9 is a flowchart (1 / 2) showing an example of the procedure for the conversion process to native gates. Below, the process shown in Figure 9 will be described in order of step number.

[0091] [Step S201] The quantum circuit generation unit 120 generates a two-qubit gate using R XX [Step S202] The quantum circuit generation unit 120 combines consecutive 1-qubit gates. For example, combining an X rotation gate, a Y rotation gate, and a Z rotation gate results in a single 1-qubit gate with arbitrary rotation.

[0092] [Step S203] The quantum circuit generation unit 120 converts the coupled 1-qubit gates into a ZXZXZ circuit. The quantum circuit generation unit 120 then proceeds to step S211 (see FIG. 18 ).

[0093] In this way, consecutive 1-qubit gates are first converted into ZXZXZ circuits, and then the ZXZXZ circuits are converted into native gates of the trapped ion quantum device.

[0094] FIG. 10 is a diagram showing an example of converting a ZXZXZ circuit into a native gate of an ion trap quantum device. A quantum circuit 33 is a quantum circuit after converting an arbitrary rotation gate operation into a ZXZXZ circuit. In the quantum circuit 33, "Z", "S", "T", and "R" are Z " is a Z rotation gate. A Z rotation gate marked "Z" is a Z gate (180° rotation around the Z axis). "S" is an S gate (90° rotation around the Z axis). "T" is a T gate (45° rotation around the Z axis). "R Z " is a rotation gate around the Z axis with a rotation angle other than 180°, 90°, or 45°. The two-qubit gate shown in quantum circuit 33 is R XX (π / 2) gate. XX (π / 2) gate simply by R XX It is also called a gate.

[0095] In the quantum circuit 33, after "Z rotation gate - SX gate - Z rotation gate - SX gate - Z rotation gate" is arranged for each of the 0th and 1st quantum bits, R XX Next, a "Z rotation gate - SX gate - Z rotation gate - SX gate - Z rotation gate" is placed on the first and sixth quantum bits, respectively, and then the R XX Furthermore, after "Z rotation gate - SX gate - Z rotation gate - SX gate - Z rotation gate" is placed on each of the 0th and 6th quantum bits, R that operates the 0th and 6th quantum bits is placed. XX Gates are placed.

[0096] Quantum circuit 34 is a quantum circuit after converting the ion trap quantum device into a native gate. The one-qubit gate denoted as "1Q2" in quantum circuit 34 is the 1Q2 gate shown in formula (2). The two-qubit gate shown in quantum circuit 34 is the MS gate shown in formula (3).

[0097] In quantum circuit 34, a "1Q2 gate-1Q2 gate" is placed for each of the 0th and 1st quantum bits, followed by an MS gate that operates on the 0th and 1st quantum bits. Next, a "1Q2 gate-1Q2 gate" is placed for each of the 1st and 6th quantum bits, followed by an MS gate that operates on the 1st and 6th quantum bits. Furthermore, a "1Q2 gate-1Q2 gate" is placed for each of the 0th and 6th quantum bits, followed by an MS gate that operates on the 0th and 6th quantum bits.

[0098] In this way, the ZXZXZ circuit and R XX The quantum circuit in which two 1Q2 gates and an MS gate are alternately arranged is converted into a quantum circuit in which two 1Q2 gates and an MS gate are alternately arranged. At this time, the angle parameters between the 1Q2 gate and the MS gate are XX It is calculated based on the angle parameters with the gate.

[0099] FIG. 11 shows the MS gate and R XX 1 is a diagram showing an example of a correspondence relationship with a gate. An MS gate 41 to which arbitrary angle parameters “φ0, φ1” are set can be represented by an equivalent circuit 42.

[0100] The equivalent circuit 42 has Z rotation gates 42a and 42b for two quantum bits, and R XX The Z rotation gate 42a has a rotation angle of "-φ0". The Z rotation gate 42b has a rotation angle of "-φ1". R XX The rotation angle of the gate 42c is "π / 2", and the R XXGate 42c operates in the same manner as an MS gate with both angle parameters set to 0. Z rotation gate 42d has a rotation angle of φ0. Z rotation gate 42e has a rotation angle of φ1.

[0101] As shown in FIG. 11, the MS gate 41 is xx The equivalent circuit 42 can be replaced with an equivalent circuit 42 that uses a gate 42c and a plurality of Z rotation gates 42a, 42b, 42d, and 42e. In other words, if a quantum circuit can be converted to generate a partial circuit that corresponds to the equivalent circuit 42, the partial circuit can be replaced with the MS gate 41.

[0102] FIG. 12 shows the R XX 1 is a diagram showing an example of a conversion process of a partial circuit including a gate. The partial circuit 43 includes Z rotation gates 43a and 43b for two quantum bits, and R XX The Z rotation gate 43a has a rotation angle of "λ'0". The Z rotation gate 43b has a rotation angle of "λ'1". R XX The rotation angle of gate 43c is "π / 2", the rotation angle of Z rotation gate 43d is "λ2", and the rotation angle of Z rotation gate 43e is "λ3".

[0103] The Z rotation gates 43a and 43b are, for example, R XX The "1Q2-1Q2-R" generated by converting the 1-qubit gate of any rotation just before gate 43c z " is a quantum gate that indicates the final Z rotation of the circuit. Each of the Z rotation gates 43d and 43e is, for example, R XX This is a quantum gate showing the first Z rotation of the ZXZXZ circuit generated by converting the next arbitrary rotation 1-qubit gate of gate 43c.

[0104] By dividing Z rotation gates 43d and 43e, partial circuit 43 is transformed into partial circuit 43-1. Z rotation gate 43d is replaced with Z rotation gate 43f with a rotation angle of "-λ'0" and Z rotation gate 43g with a rotation angle of "λ'0 + λ2". Z rotation gate 43e is replaced with Z rotation gate 43h with a rotation angle of "-λ'1" and Z rotation gate 43i with a rotation angle of "λ'1 + λ3".

[0105] In this way, R XX After gate 43c, Z rotation gates 43f and 43h corresponding to Z rotation gates 42d and 42e in the equivalent circuit 42 shown in Fig. 11 are inserted. By inserting Z rotation gates 43f and 43h, an extra Z rotation is performed. Therefore, Z rotation gates 43d and 43e before conversion are converted into Z rotation gates 43g and 43i, which are rotated in the opposite direction by the rotation angle of Z rotation gates 43f and 43h.

[0106] Z rotation gates 43a, 43b, and R in the partial circuit 43-1 XX The gate 43c and the Z rotation gates 43f and 43h have the same configuration as the equivalent circuit 42 shown in Fig. 11. Therefore, the partial circuit 43-1 includes the Z rotation gates 43a and 43b, the R XX The gate 43c and the Z rotation gates 43f and 43h can be converted into a partial circuit 43-2 in which an MS gate 43j is converted. The angle parameters of the MS gate 43j are (-λ0, -λ1).

[0107] In this way, R XX The partial circuit 43 including the gate 43c can be transformed into a partial circuit 43-2 using the MS gate 43j. The example shown in FIG. 12 shows the R XX It is assumed that the gate 43c is sandwiched between two arbitrary rotation gate operations. XX If the gates are not pinched, a series of Z rotary gates can be replaced by a single Z rotary gate.

[0108] FIG. 13 shows the R XX1 is a diagram showing an example of a conversion process of a partial circuit including gates. A partial circuit 44 has Z rotation gates 44a and 44c that are continuous with a first quantum bit, and Z rotation gates 44b and 44d that are continuous with a second quantum bit. The rotation angle of Z rotation gate 44a is "λ'0". The rotation angle of Z rotation gate 44b is "λ'1". The rotation angle of Z rotation gate 44c is "λ2". The rotation angle of Z rotation gate 44d is "λ3".

[0109] Each of the Z rotation gates 44a and 44b is a "1Q2-1Q2-R" generated by converting a one-qubit gate of an arbitrary rotation, for example. z Each of the Z rotation gates 44c and 44d is a quantum gate that indicates the first Z rotation of the ZXZXZ circuit generated by converting the following 1-qubit gate of an arbitrary rotation:

[0110] Consecutive Z rotation gates in partial circuit 44 can be replaced with a single Z rotation gate. For example, in partial circuit 44-1, consecutive Z rotation gates 44a and 44c are replaced with a single Z rotation gate 44e, and consecutive Z rotation gates 44c and 44d are replaced with a single Z rotation gate 44f. The rotation angle of Z rotation gate 44e is "λ'0 + λ2". The rotation angle of Z rotation gate 44f is "λ'1 + λ3".

[0111] The quantum circuit generation unit 120 converts the partial circuits as shown in Figures 12 and 13, and implements the last Z rotation gate of the "1Q2-1Q2-Z" circuit after converting the gate operation of the arbitrary rotation for the ion trap quantum device together with the next quantum gate. The quantum circuit generation unit 120 performs such circuit conversion in order from the beginning of the quantum circuit.

[0112] 14 is a first diagram showing an example of converting an arbitrary rotation quantum gate into a native gate. A quantum circuit 50 shows gate operations on three quantum bits. In the quantum circuit 50, after an arbitrary rotation gate operation on each of the three quantum bits, R is applied to the first and second quantum bits. XX A gate operation is performed on the gate, and then an arbitrary rotation gate operation is performed on each of the three quantum bits.

[0113] The Euler rotation angle parameter of the first arbitrary rotation of the first qubit is (φ 00 , θ 00 , λ 00 ) The Euler rotation angle parameter of the first arbitrary rotation of the second qubit is (φ 10 , θ 10 , λ 10 The Euler rotation angle parameter of the first arbitrary rotation of the third qubit is (φ 20 , θ 20 , λ 20 The Euler rotation angle parameter of the second arbitrary rotation of the first qubit is (φ 01 , θ 01 , λ 01 The Euler rotation angle parameter of the second arbitrary rotation of the second qubit is (φ 11 , θ 11 , λ 11 The Euler rotation angle parameter of the second arbitrary rotation of the third qubit is (φ 21 , θ 21 , λ 21 )

[0114] The quantum circuit 50 shows the state after converting the gate operation of an arbitrary rotation into a ZXZXZ circuit. The subcircuit 51 included in the quantum circuit 50 is a ZXZXZ circuit showing the gate operation of an arbitrary rotation and an R XX The subcircuit 51 is converted into the subcircuit 52 by converting the ZXZXZ circuit into a "1Q2-1Q2-Z" circuit and combining the final Z rotation gate with the subsequent quantum gate as shown in FIG.

[0115] In the partial circuit 52, the rotation angle "φ' 00 " 1Q2 gate and rotation angle "θ' 00 " and a 1Q2 gate with a rotation angle of "φ' 10 " 1Q2 gate and rotation angle "θ' 10 " and a 1Q2 gate with a rotation angle of "φ' 20 " 1Q2 gate and rotation angle "θ' 20" and the 1Q2 gate are placed. Then, the angle parameter "-λ' 00 , -λ' 10 " is placed in the MS gate. At this time, the final angle "λ'" after conversion to the "1Q2-1Q2-Z" circuit is 00 ", "λ' 10 ", "λ' 20 The Z rotation of each qubit in is absorbed by an MS gate followed by a Z rotation gate.

[0116] The angle parameter “φ′” of the quantum gate for the i-th (i=0, 1, 2) quantum bit in the partial circuit 52 i0 , θ' i0 , λ' i0 " has the following value: φ' i0 =-φ i0 θ' i0 = - (φ i0 +θ i0 ) λ' i0 =φ i0 +θ i0 +λ i0 "φ i1 Each Z rotation gate of "" has a rotation angle of "λ' i0 +φ i1 Such a conversion process is performed in order from the beginning of the quantum circuit 50.

[0117] 15 is a second diagram showing an example of converting an arbitrary rotation quantum gate into a native gate. This diagram shows a quantum circuit 50b after the second and subsequent arbitrary rotation gate operations have also been converted into native gates.

[0118] The Euler rotation angle parameter of the k-th arbitrary rotation gate operation for the i-th quantum bit is (φ ik , θ ik , λ ik ) In this case, the converted angle parameter "φ' ik , θ' ik , λ' ik " has the following value: φ' ik = - (φ ik +λ' ik-1 ) = -(φ ik +φ ik-1+θ ik-1 +λ ik-1 ) θ' ik = - (φ ik +λ' ik-1 +θ ik ) = -(φ ik +φ ik-1 +θ ik-1 +λ ik-1 +θ ik ) λ' ik =φ ik +λ' ik-1 +θ ik +λ ik =φ ik +φ ik-1 +θ ik-1 +λ ik-1 +θ ik +λ ik Here, the initial value of the Euler rotation angle parameter (k = -1) is "φ ik = θ ik = λ ik =0".

[0119] The final gate operation of any rotation of a quantum circuit does not have a subsequent quantum gate that combines the gate operations of the final Z rotation gate. Therefore, the quantum circuit generation unit 120 converts the Z rotation gate into a corresponding native gate.

[0120] 16 is a diagram showing an example of converting the final gate operation of an arbitrary rotation into a native gate. For example, in a quantum circuit 50 after converting an arbitrary rotation into a ZXZXZ circuit, the gate operation of the nth (n is a natural number) arbitrary rotation is assumed to be the final gate operation.

[0121] The partial circuit 53 showing the n-th gate operation is "R Z (φ in )-SX-R Z (θ in )-SX-R Z (λ in This partial circuit 53 can be expressed as "1Q2(φ')-1Q2(θ')-R Z (λ')" can be converted. Z (λ') is "R Z (λ')=1Q1(λ”)−1Q1(0)=[R z (-2λ”)-X]-[X]=R Z(-2λ"), where λ" = -λ' / 2.

[0122] FIG. 17 is a third diagram showing an example of converting an arbitrary rotation quantum gate into a native gate. FIG. 17 shows the final arbitrary rotation gate operation in the quantum circuit 50b. The partial circuit 53 shown in FIG. 16 is a circuit for converting "1Q2(φ' in ) -1Q2(θ' in )-1Q1(λ" in )-1Q1(0)" and the converted angle parameter "φ'" for the gate operation of the nth arbitrary rotation. in , θ' in , λ” in " has the following value: φ' in = - (φ in +λ' in-1 ) = -(φ in +φ in-1 +θ in-1 +λ in-1 ) θ' in = - (φ in +λ' in-1 +θ in ) = -(φ in +φ in-1 +θ in-1 +λ in-1 +θ in ) λ” in = - (φ in +λ' in-1 +θ in +λ in ) / 2 = -(φ in +φ in-1 +θ in-1 +λ in-1 +θ in +λ in ) / 2 Thus, the final gate operation of arbitrary rotation is implemented by four native gates.

[0123] 18 is a flowchart (2 / 2) showing an example of the procedure for the conversion process to native gates. The process shown in FIG. 18 will be explained below in order of step number. [Step S211] The quantum circuit generation unit 120 converts the residual R Z The gate rotation angle data is initialized to "0".

[0124] [Step S212] The quantum circuit generation unit 120 selects ZXZXZ circuits that indicate arbitrary rotation gate operations, starting from the top of the quantum circuit. [Step S213] The quantum circuit generation unit 120 determines whether the selected ZXZXZ circuit is the last arbitrary rotation gate operation in the quantum circuit. If it is the last arbitrary rotation gate operation, the quantum circuit generation unit 120 proceeds to step S219. If it is not the last arbitrary rotation gate operation, the quantum circuit generation unit 120 proceeds to step S214.

[0125] [Step S214] The quantum circuit generation unit 120 calculates the residual R Z [Step S215] The quantum circuit generation unit 120 reads the gate rotation angle data. XX The quantum circuit generation unit 120 determines whether the next XX If it is a gate, the process proceeds to step S216. XX If it is not a gate, the process proceeds to step S217.

[0126] [Step S216] The quantum circuit generation unit 120 calculates the next R XX Gate and its R XX R for each of the two quantum bits that are the targets of gate operation XX The quantum circuit generator 120 converts the ZXZXZ circuit immediately before the gate into a native gate. XX Instead of the ZXZX circuits for each of the two quantum bits to be operated by the gate, a 1Q2 gate + 1Q2 gate is implemented, and R XX The rotation angle of each quantum gate is the current residual R Z Gate rotation angle data (λ' ik-1 ) is used for the calculation. After that, the quantum circuit generation unit 120 proceeds to step S218.

[0127] [Step S217] The quantum circuit generation unit 120 implements a 1Q2 gate + 1Q2 gate in place of the selected ZXZXZ circuit. [Step S218] The quantum circuit generation unit 120 implements a residual R Z Gate rotation angle (λ'ik ) to the residual R Z The quantum circuit generation unit 120 then proceeds to step S212.

[0128] [Step S219] The quantum circuit generation unit 120 calculates the current residual R Z Gate rotation angle data (λ' ik-1 [Step S220] For each quantum bit to be operated on by the quantum circuit, the quantum circuit generation unit 120 implements a 1Q2+1Q2+1Q1+1Q1 gate instead of the final ZXZXZ circuit.

[0129] In this way, each quantum gate in the quantum circuit is converted into a native gate of the trapped ion quantum device. Moreover, each arbitrary rotation gate operation except for the last arbitrary rotation gate operation is implemented with two one-qubit gates. This improves the efficiency of quantum computation and makes it easier to perform calculations within coherent time. Furthermore, the reduction in the number of quantum gates reduces noise due to gate operations, improving fidelity.

[0130] [Other Embodiments] In the second embodiment, an example using an ion trap quantum device is shown, but the present invention can also be applied to quantum computer systems using quantum devices other than ion trap quantum devices, as long as gate operations of the MS gate, 1Q1 gate, and 1Q2 gate are possible.

[0131] The foregoing merely illustrates the principles of the present invention. Further, since numerous modifications and changes will be apparent to those skilled in the art, the present invention is not limited to the exact construction and application shown and described above, and all corresponding modifications and equivalents are deemed to be within the scope of the present invention as defined by the appended claims and their equivalents.

[0132] REFERENCE SIGNS LIST 1 quantum computer device 2, 3 quantum circuit 2a, 2b, 2d, 2e, 3a to 3d, 3f, 3g rotation gate 2c, 3e MS gate 4a, 4b partial circuit 10 information processing device 11 storage unit 12 processing unit

Claims

1. A quantum circuit conversion program that causes a computer to execute a process of converting a first rotation gate included in a quantum circuit, which indicates a gate operation of an arbitrary rotation that rotates the state of a quantum bit to be operated on around an axis different from the coordinate axis, into a partial circuit that performs a rotation gate operation that is insufficient in rotation by a specified angle around the Z axis compared to the arbitrary rotation, and changing the gate operation of one or more quantum gates after the first rotation gate in the quantum circuit for the quantum bit to be operated on, to a gate operation that rotates the quantum bit to an additional amount around the Z axis by the specified angle.

2. The quantum circuit conversion program according to claim 1, wherein the process of converting into the partial circuit converts into the partial circuit using a second rotation gate that changes the state of the quantum bit to be operated on by rotating it around the Z axis by an angle -φ' (φ' is a real number), rotating it 90 degrees around the X axis, and rotating it around the Z axis by the angle φ' in a single gate operation, and a third rotation gate that changes the state of the quantum bit to be operated on by rotating it around the Z axis by an angle -θ' (θ' is a real number), rotating it 90 degrees around the X axis, and rotating it around the Z axis by the angle θ' in a single gate operation.

3. The quantum circuit conversion program according to claim 2, wherein in the process of converting into the partial circuit, the arbitrary rotation is decomposed into a rotation around the Z axis by an angle φ (φ is a real number), a rotation around the X axis by an angle θ (θ is a real number), and a rotation around the Z axis by an angle λ (λ is a real number), and the rotation angles of the second rotation gate and the third rotation gate are set as φ' = -φ and θ' = -(φ + θ), and in the process of changing the gate operation of the one or more quantum gates from the next onwards, the gate operation of the one or more quantum gates from the next onwards is changed to a gate operation of rotating around the Z axis by the predetermined angle λ' obtained by λ' = φ + θ + λ (λ' is a real number).

4. The quantum circuit conversion program according to claim 2, wherein in the process of converting into the partial circuit, when the one-qubit gate is the last quantum gate in the quantum circuit, a fourth rotation gate that changes the state of the quantum bit to be operated on by a single gate operation to a state after rotating the quantum bit by the specified angle around the Z axis and rotating 180 degrees around the X axis is added next to the third rotation gate in the partial circuit, and a fifth rotation gate that rotates the state of the quantum bit to be operated on by 180 degrees around the X axis.

5. The quantum circuit conversion program according to claim 1, wherein in the process of changing the gate operation of the one or more quantum gates from the next onwards, a value with the sign of the specified angle reversed is set as the angle parameter of an MS (Molmer-Sorenson (the o after M and S is marked with a slash)) gate next to the first rotation gate, and the specified angle is added to the rotation angle around the Z axis of a sixth rotation gate next to the MS gate.

6. The quantum circuit conversion program according to claim 1, wherein in the process of changing the gate operation of the one or more quantum gates from the next onwards, the predetermined angle is added to the rotation angle of a seventh rotation gate indicating the next rotation around the Z axis of the first rotation gate.

7. The quantum circuit conversion program according to claim 1, further causing a computer to execute the process of: converting, when multiple one-qubit gates are consecutive in the quantum circuit with a first quantum bit as an operation target, the consecutive multiple one-qubit gates into one one-qubit gate of the arbitrary rotation.

8. The quantum circuit conversion program according to claim 1, further comprising: identifying the first rotation gates indicating the gate operation of the arbitrary rotation in order from the beginning of the quantum circuit; and each time a first rotation gate is identified, a process of converting the identified first rotation gate into the partial circuit and a process of changing the gate operation of the one or more quantum gates from the next onwards are executed for the identified first rotation gate.

9. A quantum circuit conversion method in which a computer executes the process of converting a first rotation gate included in a quantum circuit, which indicates a gate operation of an arbitrary rotation that rotates the state of a quantum bit to be operated around an axis different from the coordinate axis, into a partial circuit that performs a rotation gate operation that is insufficient in rotation by a predetermined angle around the Z axis compared to the arbitrary rotation, and changing the gate operation of one or more quantum gates after the first rotation gate in the quantum circuit for the quantum bit to be operated on, to a gate operation that rotates the quantum bit to an additional amount around the Z axis by the predetermined angle.

10. An information processing device having a processing unit that converts a first rotation gate included in a quantum circuit, which indicates a gate operation of an arbitrary rotation that rotates the state of a quantum bit to be operated around an axis different from a coordinate axis, into a partial circuit that performs a rotation gate operation that is insufficient in rotation by a predetermined angle around the Z axis compared to the arbitrary rotation, and changes the gate operation of one or more quantum gates after the first rotation gate in the quantum circuit for the quantum bit to be operated on to a gate operation that rotates the quantum bit to an additional amount around the Z axis by the predetermined angle.

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