Semiconductor device

Abstract

A semiconductor device according to an embodiment comprises: a first conductor which is exposed at a first surface of a package; first and second transistors, drains of which are connected to the first conductor; an insulation substrate; a second conductor and a third conductor which are exposed at a second surface of the package and which are provided on a third surface of the insulation substrate; a first wiring layer which is embedded in the insulation substrate and which is connected to the second conductor; a fourth conductor which is connected to the third conductor and to a source of the first transistor; a fifth conductor which is connected to the third conductor and to a source of the second transistor; a sixth conductor which is connected to the second conductor and to a gate of the first transistor; and a seventh conductor which is provided on a fourth surface of the insulation substrate and which is connected to the first wiring layer and to a gate of the second transistor.

Description

Semiconductor Devices

[0001] FIELD An embodiment of the present invention relates to a semiconductor device.

[0002] A power module is known as a semiconductor device that achieves high output. A power module is configured as a single package in which a plurality of power semiconductors are integrated.

[0003] Japanese Patent Application Publication No. 2022-165445

[0004] One embodiment of the present invention provides a semiconductor device capable of suppressing oscillation within the device.

[0005] a first wiring layer embedded in the insulating substrate and connected to the second conductor; a fourth wiring layer provided on a fourth surface of the insulating substrate opposite the third surface and connected to the source of the first transistor and the third conductor; a fifth wiring layer provided on the fourth surface of the insulating substrate and connected to the source of the second transistor and the third conductor; a sixth wiring layer provided on the fourth surface of the insulating substrate and connected to the gate of the first transistor and the second conductor;

[0006] 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor device according to an embodiment; 2 is a plan view of the upper surface of a package of a semiconductor device according to an embodiment; 3 is a plan view of the lower surface of a package of a semiconductor device according to an embodiment; 4 is a cross-sectional view of a semiconductor device taken along line A1-A2 in FIGS. 2 and 3; 5 is a plan view of the upper surface of a package of a semiconductor device according to a first modified example of an embodiment; 6 is a circuit diagram showing a circuit configuration of a semiconductor device according to a second modified example of an embodiment; 7 is a cross-sectional view of a semiconductor device according to a third modified example of an embodiment; 8 is a cross-sectional view of a semiconductor device according to a fourth modified example of an embodiment; Embodiment

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned the same reference numeral. Furthermore, when multiple components having the same reference numeral are to be distinguished from one another, a subscript will be added to the common reference numeral. Furthermore, when no particular distinction is required between multiple components, the multiple components will be assigned only the common reference numeral, without a subscript. Here, subscripts are not limited to subscripts and superscripts, but also include, for example, lowercase letters added to the end of a reference numeral, and indexes indicating an array.

[0008] A semiconductor device according to one embodiment is a power module, and is applied to, for example, a power conversion device for a railway vehicle, or industrial equipment for a renewable energy power generation system.

[0009] 1. Circuit Configuration of Semiconductor Device First, an example of the circuit configuration of a semiconductor device 1 will be described with reference to Fig. 1. Fig. 1 is a circuit diagram showing an example of the circuit configuration of the semiconductor device 1.

[0010] 1, the semiconductor device 1 includes a plurality of transistors Tr connected in parallel. In the example shown in Fig. 1, the semiconductor device 1 includes two transistors Tr1 and Tr2 connected in parallel. Note that the number of transistors Tr connected in parallel may be three or more.

[0011] The transistors Tr1 and Tr2 are, for example, n-channel MOS (Metal Oxide Semiconductor) transistors. The substrate on which the transistors Tr are formed may be a Si substrate or a SiC substrate. The following describes the case where the substrate is SiC.

[0012] The drains of the transistors Tr1 and Tr2 are commonly connected to a drain terminal D. For example, a positive voltage is applied to the drain terminal D from the outside.

[0013] The gates of the transistors Tr1 and Tr2 are commonly connected to a gate terminal G. A gate signal (voltage) that controls the transistors Tr1 and Tr2 is applied to the gate terminal G. A parasitic inductance (also referred to as "gate inductance") occurs in the gate wiring that connects the gate of the transistor Tr1 and the gate of the transistor Tr2.

[0014] The sources of the transistors Tr1 and Tr2 are commonly connected to a source terminal S. For example, a voltage lower than that applied to the drain terminal D is applied to the source terminal S. A parasitic inductance (also referred to as "source inductance") occurs in the source wiring connecting the source of the transistor Tr1 and the source of the transistor Tr2.

[0015] 2. Configuration of Semiconductor Device 2.1 Planar Configuration of Semiconductor Device First, an example of the planar configuration of the semiconductor device 1 will be described with reference to FIGS. 2 and 3. FIG. 2 is a plan view of the package top surface P1 of the semiconductor device 1. FIG. 3 is a plan view of the package bottom surface P2 of the semiconductor device 1. In the following description, when the semiconductor device 1 is surface-mounted on, for example, a printed circuit board, the mounting surface that is joined to the printed circuit board will be referred to as the "package bottom surface P2." Furthermore, the surface of the semiconductor device 1 that faces the package bottom surface P2 will be referred to as the "package top surface P1." In the examples of FIGS. 2 and 3, the plane along the package top surface P1 and the package bottom surface P2 will be referred to as the XY plane. The direction intersecting the XY plane will be referred to as the Z direction.

[0016] As shown in FIGS. 2 and 3, the molding resin 10 and the conductors 22, 23, and 30 are exposed on the surface of the package of the semiconductor device 1.

[0017] The mold resin 10 seals the semiconductor device 1. The mold resin 10 stably maintains the insulation and arrangement between the semiconductor chip (not shown) and the conductors 22, 23, and 30 within the semiconductor device 1. The mold resin 10 may be, for example, an epoxy resin. The mold resin 10 may contain a filler such as silicon oxide.

[0018] The conductors 22, 23, and 30 are made of a conductive material, such as copper (Cu). The surface of each conductor exposed from the molded resin 10 (hereinafter referred to as the "exposed surface") may or may not be covered with tin (Sn), solder, or the like. The exposed surfaces of the conductors 22, 23, and 30 may function as heat sinks for the semiconductor device 1. While FIGS. 2 and 3 illustrate a structure in which each conductor (lead terminal) does not protrude from the molded resin 10 (i.e., the package), such as DFN (Dual Flatpack Non-leaded), this is not limiting. Each conductor may protrude from the molded resin 10. The shape of each conductor is also arbitrary.

[0019] The conductors 22 and 23 are exposed on the upper surface P1 of the package. For example, the conductor 22 functions as a source terminal S. The conductor 23 functions as a gate terminal G. The exposed surfaces of the conductors 22 and 23 are electrically connected to a printed circuit board or the like via solder or the like.

[0020] The conductor 30 is exposed on the package bottom surface P2. For example, the conductor 30 functions as a drain terminal D. For example, the exposed surface of the conductor 30 is electrically connected to a printed circuit board or the like via solder or the like.

[0021] 2.2 Cross-sectional Configuration of Semiconductor Device Next, an example of the cross-sectional configuration of the semiconductor device 1 will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view of the semiconductor device 1 taken along line A1-A2 in Fig. 2 and Fig. 3. In the following description, the direction in which two semiconductor chips 40 are arranged side by side on the XY plane is referred to as the X direction. The direction intersecting the X direction is referred to as the Y direction.

[0022] As shown in FIG. 4, the semiconductor device 1 includes a molding resin 10, a wiring substrate 20, a conductor 30, two semiconductor chips 40, and mounting materials 50d, 50g, and 50s.

[0023] The lower surface of the conductor 30 is exposed at the package lower surface P2. The conductor 30 functions as a drain terminal D. Two semiconductor chips 40 are bonded to the upper surface of the conductor 30 via a mounting material 50g. That is, the two semiconductor chips 40 are provided in the package (mold resin 10).

[0024] The two semiconductor chips 40 are the transistors Tr1 and Tr2 described with reference to Fig. 1. The semiconductor chip 40 includes a SiC substrate 41, an epitaxial layer 42, a gate insulating layer 46, a gate electrode 47, a source electrode 48, and a passivation film 49.

[0025] The SiC substrate 41 is ＋ The SiC substrate 41 functions as a drain region. The lower surface of the SiC substrate 41 is bonded to the upper surface of the conductor 30 by a mounting material 50g. That is, the lower surface of the SiC substrate 41 is electrically connected to the conductor 30 (drain terminal D) as a drain electrode. Note that a separate drain electrode may be provided so as to contact the lower surface of the SiC substrate 41. In the example shown in FIG. 4 , two semiconductor chips 40 arranged side by side in the X direction are bonded to the upper surface of the conductor 30 by a mounting material 50g.

[0026] An epitaxial layer 42 is provided on the upper surface of the SiC substrate 41. The epitaxial layer 42 contains n － a p-type drift region 43, a p-type body region 44, and an n ＋ A source region 45 is provided.

[0027] The drift region 43 is provided on the SiC substrate 41, that is, on the upper surface of the drain region.

[0028] Two p-type body regions 44 are provided near the surface (upper surface) of the drift region 43 .

[0029] A source region 45 is provided near the surface of the p-type body region 44. The source region 45 is surrounded by the p-type body region 44.

[0030] The gate insulating layer 46 is provided on the upper surface of the epitaxial layer 42. The lower surface of the gate insulating layer 46 contacts parts of the two source regions 45, parts of the two p-type body regions 44, and the drift region 43 between the two p-type body regions 44. For example, between the two source regions 45, a channel of the transistor Tr is formed near the surface of the p-type body region 44 that contacts the gate insulating layer 46. The gate insulating layer 46 is made of an insulating material.

[0031] The gate electrode 47 is provided on the upper surface of the gate insulating layer 46. The gate electrode 47 is made of a conductive material.

[0032] A source electrode 48 is provided on each of the two p-type body regions. More specifically, the source electrode 48 is provided on the upper surface of a part of the source region 45 and a part of the p-type body region 44. The source electrode 48 is made of a conductive material. For example, a gate electrode 47 is provided between the two source electrodes 48 in the X direction.

[0033] The passivation film 49 is provided to surround the gate electrode 47 and the source electrode 48. The passivation film 49 physically and electrically separates the gate electrode 47 from the source electrode 48. The passivation film 49 is made of, for example, a resin material such as polyimide.

[0034] The wiring substrate 20 is provided above the semiconductor chip 40. That is, the semiconductor chip 40 is provided between the conductor 30 and the wiring substrate 20.

[0035] The gate electrode 47 is electrically connected to the wiring substrate 20 via a mounting material 50g. The source electrode 48 is electrically connected to the wiring substrate 20 via a mounting material 50s.

[0036] The mounting materials 50d, 50g, and 50s are made of a conductive material. For example, solder is used for the mounting materials 50d, 50g, and 50s. Instead of solder, a sintered material that is difficult to melt (e.g., copper, silver, lead, a tin-copper compound, a tin-silver compound, or a tin-nickel compound) may be used. In this case, a pressure-sintered material with excellent pressure resistance may be used.

[0037] Next, the internal structure of the wiring substrate 20 will be described. The wiring substrate 20 is a multilayer wiring substrate having a plurality of conductors (wiring layers) provided on both sides and inside. The wiring substrate 20 includes an insulating substrate 21, a conductor 22, a conductor 23, conductors 24a to 24d, conductors 25a and 25b, a gate wiring 26, and contact plugs 27a to 27g. The conductor 22, the conductor 23, the conductors 24a to 24d, the conductors 25a and 25b, the gate wiring 26, and the contact plugs 27a to 27g are made of a conductive material, including, for example, copper.

[0038] The insulating substrate 21 is made of an insulating material and may be made of, for example, ceramic or may contain a thermosetting resin.

[0039] The conductor 22 is provided on the upper surface S1 of the insulating substrate 21. The upper surface of the conductor 22 is exposed at the upper surface P1 of the package and functions as a source wiring and a source terminal S.

[0040] The conductor 23 is provided on the upper surface S1 of the insulating substrate 21 and spaced apart from the conductor 22. The upper surface of the conductor 23 is exposed at the upper surface P1 of the package and functions as a gate terminal G.

[0041] The conductors 24 a to 24 d and the conductors 25 a and 25 b are provided on the lower surface S 2 of the insulating substrate 21 .

[0042] Each of the conductors 24a to 24d is connected to the source electrode 48 of the semiconductor chip 40 via a mounting material 50s. For example, the conductors 24a and 24b are connected to the two source electrodes 48 of the semiconductor chip 40 (transistor Tr1), respectively. The conductors 24c and 24d are connected to the two source electrodes 48 of the semiconductor chip 40 (transistor Tr2), respectively.

[0043] Each of the conductors 25a and 25b is connected to the gate electrode 47 of the semiconductor chip 40 via a mounting material 50g. For example, the conductor 25a is connected to the gate electrode 47 of the semiconductor chip 40 (transistor Tr1). The conductor 25b is connected to the gate electrode 47 of the semiconductor chip 40 (transistor Tr2).

[0044] The gate wiring 26 is embedded in the insulating substrate 21. The gate wiring 26 is disposed between the upper surface S1 and the lower surface S2 of the insulating substrate 21 in the Z direction. The gate wiring 26 extends on the XY plane. The wiring width, wiring thickness, and wiring length (wiring layout) of the gate wiring 26 can be set arbitrarily. The gate inductance of the gate wiring 26 can be adjusted by adjusting the wiring width, wiring thickness, and wiring length of the gate wiring 26.

[0045] The gate wiring 26 is arranged parallel to the conductor 22 in the Z direction.

[0046] Contact plugs 27a to 27g are provided in the insulating substrate 21. The contact plugs 27a to 27g extend in the Z direction. One end of the contact plug 27a is connected to the conductor 22, and the other end is connected to the conductor 24a. One end of the contact plug 27b is connected to the conductor 23, and the other end is connected to the conductor 25a. One end of the contact plug 27c is connected to the conductor 23, and the other end is connected to the gate wiring 26. One end of the contact plug 27d is connected to the conductor 22, and the other end is connected to the conductor 24b. One end of the contact plug 27e is connected to the conductor 22, and the other end is connected to the conductor 24c. One end of the contact plug 27f is connected to the gate wiring 26, and the other end is connected to the conductor 25b. One end of the contact plug 27g is connected to the conductor 22, and the other end is connected to the conductor 24d.

[0047] Let Ig be the current flowing through the gate wiring 26, and Is be the current flowing through the conductor 22 (i.e., the source wiring). In this embodiment, the conductor 22 and the gate wiring 26 are laid out so that the currents Ig and Is flow in opposite directions. That is, the layout is such that the gate signal flowing through the gate wiring 26 and the source signal flowing through the conductor 22 are in opposite phase to each other. As a result, the gate inductance is in the opposite phase to the source inductance. Therefore, the gate inductance is canceled out by the mutual inductance between the gate inductance and the source inductance.

[0048] The configuration according to this embodiment can provide a semiconductor device 1 that can suppress oscillation within the device.

[0049] For example, in a loop between parallel-connected transistors, if the length of the source wiring increases, the source inductance between the transistors increases, making oscillation more likely to occur during switching. Increasing the gate inductance between the transistors is an effective countermeasure against oscillation. However, if the gate inductance increases, the performance of the semiconductor device will deteriorate due to substrate variations in transistor switching and a decrease in switching speed.

[0050] In contrast, with the configuration according to this embodiment, the semiconductor device 1 can use the wiring substrate 20 to connect the semiconductor chip 40 to the gate terminal G and the source terminal S. By using the wiring substrate 20, the current paths (wiring layout) of the gate wiring and source wiring can be optimized. That is, the gate inductance and source inductance between the semiconductor chips 40 can be adjusted. This makes it possible to increase the gate inductance. Furthermore, by shortening the current path of the source wiring and increasing the wiring area, the source inductance can be reduced.

[0051] Furthermore, with the configuration according to this embodiment, the semiconductor device 1 can lay out the conductor 22 (i.e., the source wiring) and the gate wiring 26 on the wiring substrate 20 so that the gate current Ig and the source current Is flow in opposite directions. This allows the gate inductance to be in opposite phase to the source inductance. Therefore, the gate inductance can be canceled out by the mutual inductance with the source inductance. This makes it possible to suppress a decrease in switching speed due to the gate inductance.

[0052] Furthermore, with the configuration according to this embodiment, the semiconductor device 1 can expose the conductors 22 and 23 provided on the upper surface S1 of the wiring substrate 20 from the upper surface P1 of the package. Also, the semiconductor device 1 can expose the conductor 30 from the lower surface P2 of the package. This allows the semiconductor device 1 to expose conductors (metal materials) with excellent thermal conductivity from both sides of the package. In other words, the semiconductor device 1 can dissipate heat from both sides of the package. Therefore, the heat dissipation performance of the semiconductor device 1 can be improved.

[0053] 3. Modifications, etc. Note that various modifications are possible, not limited to the above-described embodiment. Three modifications will be described below. Note that the following modifications will be described focusing on the differences from the embodiment.

[0054] 3.1 First Modification A first modification will be described with reference to Fig. 5. Fig. 5 is a plan view of the package upper surface P1 of the semiconductor device 1.

[0055] As shown in FIG. 5, the insulating substrate 21 may be exposed on the package upper surface P1 of the semiconductor device 1.

[0056] 3.2 Second Modification A second modification will be described with reference to Fig. 6. Fig. 6 is a circuit diagram showing the circuit configuration of the semiconductor device 1. The semiconductor device 1 may have the circuit configuration shown in Fig. 6.

[0057] 6, for example, the semiconductor device 1 includes an upper arm portion UA ​​including a plurality of transistors connected in parallel, and a lower arm portion LA including a plurality of transistors connected in parallel. The upper arm portion UA ​​and the lower arm portion LA are connected in series. Each arm portion corresponds to the circuit configuration described with reference to FIG.

[0058] The upper arm portion UA ​​includes transistors Tr1 and Tr2, which are connected in parallel.

[0059] The lower arm portion LA includes transistors Tr3 and Tr4, which are connected in parallel.

[0060] The transistors Tr1, Tr2, Tr3, and Tr4 are, for example, n-channel MOS transistors.

[0061] The drains of transistors Tr1 and Tr2 are commonly connected to a positive terminal P. A positive voltage is applied to the positive terminal P from the outside. The gates of transistors Tr1 and Tr2 are commonly connected to an upper gate terminal HG via an upper gate wiring. The sources of transistors Tr1 and Tr2 are commonly connected to an upper source sense terminal HSS via an upper source sense wiring. The upper source sense terminal HSS is used to sense (monitor) the source voltages of transistors Tr1 and Tr2. The sources of transistors Tr1 and Tr2 are commonly connected to an output terminal AC and the drains of transistors Tr3 and Tr4.

[0062] The gates of the transistors Tr3 and Tr4 are commonly connected to a lower gate terminal LG via a lower gate wiring. The sources of the transistors Tr3 and Tr4 are commonly connected to a lower source sense terminal LSS via a lower source sense wiring. The lower source sense terminal LSS is used to sense (monitor) the source voltages of the transistors Tr3 and Tr4. The sources of the transistors Tr3 and Tr4 are also commonly connected to a negative terminal N. A voltage lower than that applied to the positive terminal P is applied to the negative terminal N.

[0063] 3.3 Third Modification A third modification will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view of the semiconductor device 1.

[0064] 7, the wiring substrate 20 may further include a source wiring 28 embedded in the insulating substrate 21. For example, the source wiring 28 is disposed between the upper surface S1 of the insulating substrate 21 and the upper surface of the gate wiring 26 in the Z direction. The source wiring 28 extends on the XY plane. The source wiring 28 is disposed parallel to the gate wiring 26 in the Z direction. The source wiring 28 is connected to the conductor 22 via a contact plug 27h.

[0065] 3.4 Fourth Modification A fourth modification will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view of the semiconductor device 1.

[0066] 8, a wiring substrate 60 may be provided between the semiconductor chip 40 and the conductor 30. The wiring substrate 60 is a wiring substrate having a plurality of conductors provided on both sides. The wiring substrate 60 includes an insulating substrate 61, a conductor 62, and a conductor 63. The insulating substrate 61 is made of an insulating material. The conductors 62 and 63 are made of a conductive material, including copper, for example.

[0067] The conductor 62 is provided on the upper surface of the insulating substrate 61 and is connected to the SiC substrate (drain region) of the semiconductor chip 40. The conductor 63 is provided on the lower surface of the insulating substrate 61 and is connected to the conductor 30 via the mounting material 50d. The conductors 62 and 63 are electrically connected by a contact plug (not shown).

[0068] In the above embodiment, "connection" also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0069] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

Claims

a first conductor exposed on a first surface of a package; a first transistor provided in the package, the drain of the first conductor connected to the first conductor; a second transistor provided in the package, the drain of the second transistor connected to the first conductor; an insulating substrate; a second conductor exposed from a second surface of the package opposite the first surface and provided on a third surface of the insulating substrate; a third conductor exposed from the second surface of the package and provided on the third surface of the insulating substrate at a distance from the second conductor; a first wiring layer embedded in the insulating substrate and connected to the second conductor; a fourth conductor provided on a fourth surface of the insulating substrate opposite the third surface and connected to a source of the first transistor and the third conductor; a fifth conductor provided on the fourth surface of the insulating substrate and connected to a source of the second transistor and the third conductor; a seventh conductor provided on the fourth surface of the insulating substrate and connected to the gate of the second transistor and the first wiring layer.

2. The semiconductor device according to claim 1, wherein the third conductor and the first wiring layer are arranged in parallel.

3. The semiconductor device according to claim 1, wherein the first signal applied to the third conductor and the second signal applied to the first wiring layer are in opposite phase to each other.

4. The semiconductor device according to claim 1, wherein the first transistor and the second transistor are disposed between the first conductor and the insulating substrate.

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