Solid-state imaging element, imaging device, and method for controlling solid-state imaging element

Abstract

This solid-state imaging element, which performs analog to digital (AD) conversion, shortens an AD conversion time while suppressing an increase in power consumption.　The solid-state imaging element comprises a constant current source, a control transistor, and a body bias control unit. In this solid-state imaging element, the constant current source is connected to a vertical signal line. Further, in the solid-state imaging element, the control transistor lowers the potential of the vertical signal line in accordance with a prescribed control signal. The body bias control unit controls the body bias of the control transistor.

Description

Solid-state imaging device, imaging apparatus, and method for controlling solid-state imaging device

[0001] The present technology relates to a solid-state imaging element, and more particularly to a solid-state imaging element having vertical signal lines, an imaging device, and a method for controlling the solid-state imaging element.

[0002] In recent years, there has been a trend toward a demand for solid-state imaging devices with high frame rates that can smoothly represent the movement of a subject. To meet this demand, for example, a solid-state imaging device has been proposed in which a control transistor that reduces the potential of a vertical signal line when transferring charges within a pixel is added to each column (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2008-022259

[0004] The above-described conventional technology attempts to shorten the AD (Analog to Digital) conversion time by lowering the potential of the vertical signal line during charge transfer. However, in the above-described conventional technology, the settling time until the potential of the vertical signal line converges can vary due to PVT (Process, Voltage, Temperature) variations. Therefore, it is necessary to provide a sufficient margin in the pulse width of the pulse signal to the control transistor to account for the settling time fluctuations. As a result, it becomes difficult to further shorten the AD (Analog to Digital) conversion time. While the margin can be reduced by increasing the accuracy of the pulse width adjustment, this requires a highly accurate clock signal, which increases power consumption. Furthermore, the settling time can be shortened by increasing the current value of the constant current source connected to the vertical signal line, but this also increases power consumption. As such, it is difficult to shorten the AD conversion time while suppressing increases in power consumption in the above-described solid-state imaging device.

[0005] The present technology was developed in view of such circumstances, and aims to reduce the AD conversion time while suppressing an increase in power consumption in a solid-state imaging device that performs AD conversion.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof relates to a solid-state imaging device including a constant current source connected to a vertical signal line, a control transistor that reduces the potential of the vertical signal line in accordance with a predetermined control signal, and a body bias control unit that controls the body bias of the control transistor, and a control method thereof, which has the effect of shortening the AD conversion time.

[0007] In addition, in this first aspect, the control transistor may further include a replica transistor having the same characteristics as the control transistor, and the body bias control unit may include a current monitor unit that measures a value of a current flowing through the replica transistor as a measurement value, a comparator unit that compares the measurement value with a predetermined reference current value and outputs the comparison result, and a body bias generation unit that generates the body bias based on the comparison result, thereby suppressing fluctuations in settling time due to PVT variations.

[0008] In the first aspect, the body bias control unit may include a register that stores a predetermined set value, and a body bias generation unit that generates the body bias based on the set value, thereby suppressing fluctuations in settling time due to process variations.

[0009] In the first aspect, the semiconductor substrate on which the control transistor is formed may be an SOI (Silicon On Insulator) substrate, thereby providing an effect of expanding the adjustment range of the body bias.

[0010] In this first aspect, the constant current source may be formed in a first well of a semiconductor substrate, and the control transistor may be formed in a second well of the semiconductor substrate, thereby providing the effect of isolating the wells.

[0011] In this first aspect, the body bias control unit may further control the body bias of the constant current source, thereby suppressing fluctuations in the current value of the constant current source due to PVT variations.

[0012] In addition, in this first aspect, the body bias control unit may control the body biases of the constant current source and the control transistor to the same potential, and the constant current source and the control transistor may be formed in a predetermined well of a semiconductor substrate, thereby reducing the mounting area of ​​the constant current source and the control transistor.

[0013] In addition, in this first aspect, the pixel may further include a photoelectric conversion element, a transfer transistor for transferring charges from the photoelectric conversion element to a floating diffusion layer in accordance with a predetermined transfer signal, a reset transistor for initializing the floating diffusion layer in accordance with a predetermined reset signal, a selection transistor for opening and closing a path between a power supply voltage and the vertical signal line in accordance with a predetermined selection signal, and an amplification transistor for amplifying the potential of the floating diffusion layer and supplying the amplified potential to the vertical signal line, thereby producing the effect of generating image data.

[0014] A second aspect of the present technology is an image pickup device including a constant current source connected to a vertical signal line, a control transistor that reduces a potential of the vertical signal line in accordance with a predetermined control signal, a body bias control unit that controls a body bias of the control transistor, and a signal processing unit that processes a pixel signal of the potential, thereby shortening an AD conversion time of the image pickup device.

[0015] 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment of the present technology. FIG. 2 is a block diagram showing a configuration example of a solid-state imaging element according to the first embodiment of the present technology. FIG. 3 is a circuit diagram showing a configuration example of a pixel and a load MOS circuit according to the first embodiment of the present technology. FIG. 4 is a block diagram showing a configuration example of a body bias control unit according to the first embodiment of the present technology. FIG. 5 is a block diagram showing a configuration example of a column signal processing unit according to the first embodiment of the present technology. FIG. 6 is a timing chart showing an example of a method for driving a pixel according to the first embodiment of the present technology. FIG. 7 is a graph showing an example of input characteristics of a control transistor according to the first embodiment of the present technology. FIG. 8 is a timing chart showing potential fluctuations when the charge extraction capability of a control transistor in a comparative example is low. FIG. 9 is a timing chart showing potential fluctuations when the charge extraction capability of a control transistor in a comparative example is high. FIG. 10 is an example of a timing chart showing potential fluctuations in the comparative example and the first embodiment of the present technology. FIG. 11 is a cross-sectional view showing a configuration example of a semiconductor substrate according to the first embodiment of the present technology. FIG. 12 is a cross-sectional view showing a configuration example of a semiconductor substrate according to a second embodiment of the present technology. FIG. 13 is a circuit diagram showing a configuration example of a load MOS circuit according to a third embodiment of the present technology. FIG. 14 is a cross-sectional view showing a configuration example of a semiconductor substrate according to the third embodiment of the present technology. It is a block diagram showing an example of a configuration of a body bias control unit according to a fourth embodiment of the present technology.It is a block diagram showing an example of a schematic configuration of a vehicle control system.It is an explanatory diagram showing an example of an installation position of an imaging unit.

[0016] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be given in the following order: 1. First embodiment (an example of controlling the body bias of a control transistor) 2. Second embodiment (an example of controlling the body bias of a control transistor and forming an insulating film under the channel) 3. Third embodiment (an example of controlling the body bias of a control transistor and a constant current source) 4. Fourth embodiment (an example of controlling the body bias of a control transistor according to a set value of a register) 5. Application example to a mobile object

[0017] 1 is a block diagram showing an example of the configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device for capturing image data, and includes an optical unit 110, a solid-state imaging element 200, and a DSP (Digital Signal Processing) circuit 120. The imaging device 100 further includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. The imaging device 100 may be a digital camera or an electronic device with an imaging function (such as a smartphone or a personal computer).

[0018] The optical unit 110 collects light from a subject and guides it to the solid-state image sensor 200. The solid-state image sensor 200 generates image data through photoelectric conversion. The solid-state image sensor 200 generates the image data and supplies it to the DSP circuit 120 via a signal line 209.

[0019] The DSP circuit 120 performs predetermined signal processing on the image data, and outputs the processed image data to a frame memory 160 or the like via a bus 150.

[0020] The display unit 130 displays image data. For example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed as the display unit 130. The operation unit 140 generates an operation signal in accordance with a user's operation.

[0021] The bus 150 is a common path for the optical unit 110, solid-state image sensor 200, DSP circuit 120, display unit 130, operation unit 140, frame memory 160, storage unit 170, and power supply unit 180 to exchange data with one another.

[0022] The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the solid-state imaging device 200, the DSP circuit 120, the display unit 130, etc.

[0023] 2 is a block diagram showing a configuration example of a solid-state imaging element 200 according to the first embodiment of the present technology. The solid-state imaging element 200 includes a vertical drive circuit 210, a timing control unit 220, a DAC (Digital to Analog Converter) 230, and a pixel array unit 240. The solid-state imaging element 200 further includes a load MOS (Metal-Oxide-Semiconductor) circuit 260, a column signal processing unit 280, a horizontal scanning circuit 290, and a body bias control unit 300. In the pixel array unit 240, a plurality of pixels 250 are arranged in a two-dimensional lattice pattern.

[0024] The circuits and elements in the solid-state imaging device 200 are arranged, for example, on a single semiconductor substrate. Note that the circuits and elements in the solid-state imaging device 200 may also be distributed and arranged on multiple stacked semiconductor substrates.

[0025] The vertical drive circuit 210 sequentially selects and drives rows in the pixel array section 240 .

[0026] The timing control section 220 controls the operation timing of the vertical drive circuit 210, the DAC 230, the load MOS circuit 260, the column signal processing section 280, and the horizontal scanning circuit 290 in synchronization with the vertical synchronization signal VSYNC.

[0027] The DAC 230 generates a sawtooth ramp signal and supplies it to the column signal processing unit 280 .

[0028] The pixels 250 generate analog signals as pixel signals by photoelectric conversion under the control of the vertical drive circuit 210. The pixels 250 in each column output pixel signals to the column signal processing unit 280 via vertical signal lines.

[0029] In the load MOS circuit 260, a constant current source (not shown) is arranged for each vertical signal line.

[0030] The column signal processing unit 280 performs AD conversion and CDS (Correlated Double Sampling) processing on pixel signals for each column of the pixels 250. The column signal processing unit 280 outputs the processed digital signals to the DSP circuit 120 under the control of the horizontal scanning circuit 290. The column signal processing unit 280 is an example of a signal processing unit described in the claims.

[0031] The horizontal scanning circuit 290 controls the column signal processing unit 280 to output digital signals in sequence.

[0032] The body bias control unit 300 controls the body bias of the transistors in the load MOS circuit 260 .

[0033] 3 is a circuit diagram showing a configuration example of a pixel 250 and a load MOS circuit 260 according to the first embodiment of the present technology. In the pixel array section 240, a vertical signal line 259 is wired for each column of pixels 250. The pixel 250 includes a photoelectric conversion element 251, a transfer transistor 252, a reset transistor 253, a floating diffusion layer 254, a selection transistor 255, and an amplification transistor 256. Each transistor in the pixel 250 is, for example, an nMOS (n-channel MOS) transistor.

[0034] The photoelectric conversion element 251 photoelectrically converts incident light to generate electric charges. The transfer transistor 252 transfers electric charges from the photoelectric conversion element 251 to the floating diffusion layer 254 in accordance with a transfer signal TG from the vertical drive circuit 210. The reset transistor 253 initializes the floating diffusion layer 254 in accordance with a reset signal RST from the vertical drive circuit 210. The floating diffusion layer 254 generates an electric potential according to the amount of electric charges accumulated therein.

[0035] The selection transistor 255 opens and closes a path between the power supply voltage VDD and a vertical signal line 259 in accordance with a selection signal VSEL from the vertical drive circuit 210. The amplification transistor 256 amplifies the potential of the floating diffusion layer 254 and supplies it as a pixel signal to the vertical signal line 259. Note that the circuit configuration of the pixel 250 is not limited to that illustrated in the figure, as long as it is capable of generating a pixel signal.

[0036] The load MOS circuit 260 includes a plurality of constant current sources 261, a plurality of control transistors 262, and a replica circuit 270. The constant current sources 261 and the control transistors 262 are arranged for each column. For example, nMOS transistors are used as the control transistors.

[0037] The constant current source 261 supplies a constant current. This constant current source 261 is connected to the vertical signal line 259 of the corresponding column. A connection node between the constant current source 261 and the vertical signal line 259 is connected to the column signal processing unit 280. A signal of the potential of this connection node is supplied to the column signal processing unit 280 as the pixel signal Vin. As the constant current source 261, for example, a MOS transistor (such as an nMOS transistor) having a constant bias voltage applied to its gate is used.

[0038] The control transistor 262 lowers the potential of the vertical signal line 259 in accordance with an enable signal PDEN from the timing control unit 220. For example, the enable signal PDEN is set to a high level to enable the function of lowering the potential, and to a low level to disable it. The control transistor 262 and the constant current source 261 are connected in parallel between the vertical signal line 259 and a ground node. The enable signal PDEN is input to the gate of the control transistor 262. The body bias control unit 300 described above also generates a body bias VB, which is a bias for a semiconductor substrate on which the control transistor 262 is formed, and supplies the body bias VB to the substrate. The enable signal PDEN is an example of a control signal recited in the claims.

[0039] The replica circuit 270 includes a resistor 271 and a replica transistor 272. The value of the resistor 271 is set to, for example, the resistance value of the pixel 250 when it receives incident light of a predetermined brightness. The replica transistor 272 is a transistor having various characteristics (such as input characteristics) that are the same as those of the control transistor 262. The body bias control unit 300 also supplies a body bias VB to the replica transistor 272.

[0040] 4 is a block diagram showing an example of the configuration of the body bias control unit 300 according to the first embodiment of the present technology. The body bias control unit 300 includes a current monitor circuit 310, a comparison circuit 320, and a body bias generation unit 330.

[0041] The current monitor circuit 310 measures the value of the current flowing through the resistor 271 and the replica transistor 272. The current monitor circuit 310 measures the current when the enable signal PDEN is at a high level (i.e., enabled), and supplies the value to the comparison circuit 320 as a measurement value Im.

[0042] The comparison circuit 320 compares the measured value Im with a reference value Iref, which is a predetermined reference current value, and supplies the comparison result to the body bias generation section 330.

[0043] The body bias generating section 330 generates a body bias VB based on the comparison result of the comparison circuit 320. The body bias generating section 330 is realized by a charge pump circuit or the like.

[0044] When the measured value Im is greater than the reference value Iref, the body bias generation unit 330 generates a body bias VB greater than 0 volts (V). On the other hand, when the measured value Im is less than the reference value Iref, the body bias generation unit 330 generates a body bias VB less than 0 volts (V). When the measured value Im is equal to the reference value Iref, the body bias generation unit 330 generates a body bias VB of 0 volts (V). Furthermore, the greater the difference between the measured value Im and the reference value Iref, the greater the absolute value of the body bias VB the body bias generation unit 330 increases. This control of the body bias VB causes the threshold voltage of the control transistor 262 to fluctuate. This phenomenon is called the substrate bias effect. Due to the substrate bias effect, the current flowing through the replica transistor 272 increases or decreases, and the measured value Im is adjusted to the reference value Iref.

[0045] The generated body bias VB is supplied to the substrates (in other words, back gates) of the control transistors 262 and replica transistors 272 of each column.

[0046] As described above, by controlling the body bias VB based on the result of comparison between the measured value Im and the reference value Iref, it is possible to suppress fluctuations in the characteristics of the control transistor 262 due to PVT variations.

[0047] The body bias control unit 300 can measure the current and adjust the body bias at any timing. For example, the body bias is periodically adjusted while the solid-state imaging device 200 is in operation. The body bias is also adjusted while the imaging operation of the solid-state imaging device 200 is stopped. By adjusting the body bias while the imaging operation is stopped, it is possible to suppress fluctuations in the characteristics of the control transistor 262 due to process variations. Furthermore, by adjusting the body bias during operation, it is possible to suppress fluctuations in the characteristics of the control transistor 262 due to variations in temperature and power supply voltage.

[0048] 5 is a block diagram showing an example of the configuration of the column signal processing unit 280 according to the first embodiment of the present technology. The column signal processing unit 280 includes an ADC 281 and a latch circuit 284 for each column.

[0049] The ADC 281 converts the analog pixel signal Ain into a digital signal Dout. The ADC 281 includes a comparator 282 and a counter 283. Such an ADC is called a single-slope ADC. Note that instead of a single-slope ADC, a SAR ADC (Successive Approximation Register ADC) or the like can also be used as the ADC 281.

[0050] The comparator 282 compares the pixel signal Ain with the ramp signal RMP from the DAC 230. The comparator 282 supplies the comparison result CMP to the counter 283.

[0051] The counter 283 counts the count value over a period until the comparison result CMP is inverted. The counter 283 supplies a digital signal Dout indicating the count value to the latch circuit 284.

[0052] The timing control unit 220 controls the counter 283 to count down when the reset level is converted and count up when the signal level is converted. Here, the reset level is the level of the pixel signal Vin when the floating diffusion layer in the pixel is initialized, and the signal level is the level of the pixel signal Vin when charge is transferred to the floating diffusion layer. By controlling the counter 283 to count down when the reset level is converted and count up when the signal level is converted, CDS processing can be realized to determine the difference between the reset level and the signal level. Note that it is also possible for the ADC 281 to only perform up-counting, and for a subsequent circuit to perform CDS processing.

[0053] The latch circuit 284 holds the digital signal Dout and supplies it to the DSP circuit 120 under the control of the horizontal scanning circuit 290 .

[0054] 6 is a timing chart showing an example of a method for driving the pixel 250 according to the first embodiment of the present technology. The vertical drive circuit 210 sequentially selects rows and performs AD conversion on the pixel signals Vin.

[0055] When a predetermined row is selected, the vertical drive circuit 210 supplies a high-level selection signal VSEL to the row from timing T0 to T4. This period is called the AD conversion time dT ＡＤＣ Let's say.

[0056] The vertical drive circuit 210 supplies a high-level reset signal RST to the selected row over a pulse period from timing T1 immediately after timing T0. This causes the potential of the pixel signal Vin (in other words, the potential of the vertical signal line) to drop to the reset level. The settling time from when the potential starts to drop until it converges to the reset level is defined as dT. ｓｅｔ１ This dT ｓｅｔ１ The reset level is sampled from the time when the reset level is sampled until timing T2. This period is called the sampling period dT of the reset level. ｓｍｐ１ Let's say.

[0057] The vertical drive circuit 210 then supplies a high-level transfer signal TG to the selected row over a pulse period from timing T2, and then supplies a high-level enable signal PDEN over a pulse period from timing T3 immediately thereafter. This causes the potential of the pixel signal Vin (the potential of the vertical signal line) to drop according to the amount of charge accumulation and become the signal level. The settling time from when the potential starts to drop until it converges to the signal level varies depending on the brightness, but the value obtained by adding a margin for the variation to the shortest settling time is defined as dT. ｓｅｔ２ This dT ｓｅｔ２ The signal level is sampled from the time when the signal level is sampled until timing T4. This period is called the signal level sampling period dT. ｓｍｐ２ Let's say.

[0058] As described above, the AD conversion time dT ＡＤＣ is dT ｓｅｔ１ , dT ｓｍｐ１ , dT ｓｅｔ２ and dTｓｍｐ２ Includes:

[0059] Here, the vertical signal lines are connected with amplifying transistors corresponding to the number of rows, and thus have parasitic capacitance. Therefore, a non-negligible settling time is required from the time the transfer signal TG is supplied until the potential of the vertical signal lines converges to the signal level. The length of this signal level settling time strongly depends on the total parasitic capacitance present on the vertical signal lines and the current value flowing from the constant current source 261.

[0060] In the above-described configuration, the greater the number of pixels, the greater the parasitic capacitance of the vertical signal line, resulting in a longer settling time. Therefore, as shown in the figure, the vertical drive circuit 210 turns on the control transistor 262 using the enable signal PDEN immediately after transfer. This control allows charges to be extracted from the parasitic capacitance, shortening the settling time of the signal level.

[0061] However, the settling time of the signal level varies not only with brightness but also with PVT variations. If the body bias VB were kept constant regardless of PVT variations, the settling time would vary due to PVT variations in addition to brightness. As a comparative example, a configuration in which the body bias VB is kept constant without being controlled in accordance with PVT variations is assumed.

[0062] In the comparative example, dT is set to a value including a sufficiently long margin in consideration of fluctuations in settling time due to PVT variations. ｓｅｔ２ As a result, dT ｓｅｔ２ becomes longer, and the AD conversion time dT ＡＤＣ becomes longer.

[0063] In contrast to this, in the first embodiment, the body bias VB is controlled based on the comparison result between the measured value Im and the reference value Iref, so that the fluctuation of the settling time due to the PVT variation can be suppressed. ｓｅｔ２ By reducing the margin within ＡＤＣ can be made shorter than that in the comparative example.

[0064] As will be described later, the margin can also be reduced by adjusting the pulse width of the enable signal PDEN with high precision. However, increasing the precision of the pulse width adjustment requires a high-speed clock signal, which increases power consumption, and is therefore not desirable.

[0065] Furthermore, although the timing control section 220 supplies the pulse of the enable signal PDEN immediately after the pulse of the transfer signal TG, it is also possible to supply the pulse of the enable signal PDEN simultaneously with the pulse of the transfer signal TG.

[0066] Furthermore, when the body bias control unit 300 generates the body bias VB using a charge pump circuit, it is preferable to stop the clock signal to the charge pump circuit within the AD conversion time. While the clock signal is stopped, the body bias VB is sampled and held in the parasitic capacitance of the semiconductor substrate, etc. This control can suppress noise from the charge pump circuit to analog circuits (such as pixels).

[0067] 7 is a graph showing an example of the input characteristics of the control transistor 262 according to the first embodiment of the present technology. The vertical axis of the graph represents the drain current Id of the control transistor 262, and the horizontal axis represents the gate-source voltage Vgs.

[0068] The dashed line indicates the reference input characteristic. The solid line indicates the input characteristic when the ability to extract charge from the parasitic capacitance is high compared to the reference. The rough dashed line indicates the input characteristic when the ability to extract charge from the parasitic capacitance is low compared to the reference. In the reference input characteristic, the enable signal PDEN is at a high level V ＥＮ The drain current Id at this time is set as a reference value Iref.

[0069] The input characteristics of the control transistor 262 fluctuate due to variations in PVT. ＥＮ The measured value Im of the drain current Id at this time also fluctuates due to PVT variations.

[0070] The body bias control unit 300 increases the body bias VB above 0 volts (V) when the measured value Im is greater than the reference value Iref, in other words, when the charge extraction capability is high (e.g., the input characteristics indicated by the solid line). On the other hand, when the measured value Im is smaller than the reference value Iref, in other words, when the charge extraction capability is low (e.g., the input characteristics indicated by the roughly dashed line), the body bias control unit 300 decreases the body bias VB below 0 volts (V). Furthermore, when the measured value Im is equal to the reference value Iref (i.e., the input characteristics indicated by the dashed-dotted line), the body bias control unit 300 decreases the body bias VB to 0 volts (V). Furthermore, the greater the difference between the measured value Im and the reference value Iref, the greater the absolute value of the body bias VB the body bias control unit 300 increases. This control can suppress fluctuations in settling time due to PVT variations.

[0071] 8 is a timing chart showing potential fluctuations when the charge extraction capability of the control transistor 262 in the comparative example is low. The timing chart "a" in the figure shows a case where the charge extraction capability of the control transistor 262 is low and the incident light is dark. The timing chart "b" in the figure shows a case where the charge extraction capability of the control transistor 262 is low and the incident light is bright.

[0072] As illustrated in FIG. 1A, the vertical drive circuit 210 supplies a high-level transfer signal TG to a selected row for a pulse period starting from timing T10, and then supplies a high-level enable signal PDEN for a pulse period starting from timing T11 immediately thereafter. This causes the potential of the pixel signal Vin (the potential of the vertical signal line) to drop in accordance with the amount of charge accumulation and reach the signal level. The time from timing T11, when the potential starts to drop, to timing T12, when the potential converges to the signal level, corresponds to the settling time.

[0073] Furthermore, as shown in Fig. 1B, when the incident light is bright, the potential of the vertical signal line converges to the signal level at timing T13 after timing T12. In other words, when the incident light is bright, the settling time is longer than when the incident light is dark.

[0074] As shown in a and b in the figure, if the charge extraction capability of the control transistor 262 is low, the settling time when it is bright becomes longer than when it is dark. Therefore, in order to match the settling time when it is bright, the dT ｓｅｔ２ is set.

[0075] 9 is a timing chart showing potential fluctuations when the charge extraction capability of the control transistor 262 in the comparative example is high. The timing chart a in the figure shows a case where the charge extraction capability of the control transistor 262 is high and the incident light is dark. The timing chart b in the figure shows a case where the charge extraction capability of the control transistor 262 is high and the incident light is bright.

[0076] As shown in the example of a in the figure, when the incident light is dark, the potential of the pixel signal Vin (the potential of the vertical signal line) converges to the signal level at timing T13.

[0077] On the other hand, as illustrated in FIG. 1B, when the incident light is bright, the potential of the vertical signal line converges to the signal level at timing T12, which is before timing T13.

[0078] As shown in a and b in the figure, if the control transistor 262 has a high ability to extract electric charges, the settling time in the dark will be longer than in the bright state. ｓｅｔ２ is set.

[0079] 8a and 8b and 9a and 9b, in the comparative example in which the body bias VB is not controlled, the charge extraction capability of the control transistor 262 varies due to PVT variations, and therefore the settling time varies due to brightness and PVT variations.

[0080] 10 is an example of a timing chart showing potential fluctuations in a comparative example and the first embodiment of the present technology, where "a" in the figure shows the timing chart of the comparative example, and "b" in the figure shows the timing chart of the first embodiment.

[0081] As mentioned above, in the comparative example, the settling time varies due to brightness and PVT variations. Therefore, as shown in FIG. 1A, a pulse width including a sufficiently long margin dTm is set for the enable signal PDEN. The solid line indicates the potential fluctuations at the longest settling time, and the dashed-dotted line indicates the potential fluctuations at the shortest settling time. Because the pulse width is thus longer, the AD conversion time is longer in the comparative example.

[0082] The margin can be reduced by adjusting the pulse width of the enable signal PDEN with high precision. However, improving the accuracy of the pulse width adjustment requires a high-speed clock signal, which increases power consumption.

[0083] In contrast, in the first embodiment, the body bias control unit 300 controls the body bias VB, thereby suppressing fluctuations in settling time due to PVT variations. Therefore, as illustrated in FIG. 1B, the margin dTm can be reduced compared to the comparative example. This allows for a shorter AD conversion time. Furthermore, since there is no need to adjust the pulse width with high precision, an increase in power consumption can be suppressed.

[0084] 11 is a cross-sectional view showing a configuration example of a semiconductor substrate 400 according to the first embodiment of the present technology. On this semiconductor substrate 400, circuits and elements in the solid-state imaging device 200 shown in FIG.

[0085] 11, in a semiconductor substrate 400, a deep N-well 402 is formed in a P-substrate 401. ＋ Layer 404, P － Layer 405, P － Layer 407 is formed. ＋ Layer 404 is connected to a power supply voltage VDD, which is higher than the body bias VB.

[0086] P － Layer 405 contains P ＋ layer 406 and N ＋ The source 412 and drain 413 of the P ＋The layer 406 is grounded. A gate 411 is formed between the source 412 and the drain 413. The gate 411, the source 412, and the drain 413 function as the constant current source 261 described above. A constant bias voltage Vb is applied to the gate 411.

[0087] Also, P － Layer 407 contains P ＋ layer 408 and N ＋ The source 422 and drain 423 of the layer are formed. ＋ A body bias VB is applied to the layer 408. A gate 421 is formed between a source 422 and a drain 423. The gate 421, source 422, and drain 423 function as the above-mentioned control transistor 262. An enable signal PDEN is input to the gate 421.

[0088] Also, adjacent N ＋ Layer and P ＋ An insulating layer 403 is formed between the layers. As illustrated in the figure, a P － layer 407 and a P well in which the constant current source 261 is formed. － It is separated from the layer 405. Also, no insulating film is formed directly below the channel of the MOS transistor (the control transistor 262 and the constant current source 261), and this structure is called a bulk structure.

[0089] In addition, P － Layer 405 is an example of a first well as defined in the claims. － Layer 407 is an example of a claimed second well.

[0090] As described above, according to the first embodiment of the present technology, it is possible to suppress fluctuations in settling time due to PVT variations because the body bias control unit 300 controls the body bias of the control transistor 262. This makes it possible to reduce the AD conversion time while suppressing an increase in power consumption.

[0091] 2. Second Embodiment In the first embodiment described above, the control transistor 262 and the constant current source 261 are formed on the semiconductor substrate 400 having a bulk structure, but this structure may result in an insufficient adjustment range for the body bias. The solid-state imaging device 200 in this second embodiment differs from the first embodiment in that it uses an SOI structure instead of a bulk structure.

[0092] 12 is a cross-sectional view showing a configuration example of a semiconductor substrate 400 according to the second embodiment of the present technology. The semiconductor substrate 400 according to the second embodiment differs from the first embodiment in that it further includes BOX (Burried Oxide) films 431 and 432.

[0093] The BOX film 431 is formed with the gate side facing up, directly below the channel between the source 412 and the drain 413. The BOX film 432 is formed directly below the channel between the source 422 and the drain 423. A structure in which an insulating film such as a BOX film is inserted directly below the channel in this manner is called an SOI structure, and a semiconductor substrate with an SOI structure is also called an SOI substrate.

[0094] By using the SOI structure semiconductor substrate 400, the parasitic capacitance is reduced, and the amount of change in threshold voltage when the body bias VB is changed by a unit voltage is smaller than in the case of a bulk structure, which allows the adjustment range of the body bias VB of the control transistor 262 to be expanded.

[0095] As described above, according to the second embodiment of the present technology, the semiconductor substrate 400 having an SOI structure is used, so that the adjustment range of the body bias VB of the control transistor 262 can be expanded.

[0096] 3. Third Embodiment In the second embodiment described above, the body bias control unit 300 supplies the body bias VB only to the control transistor 262. However, the dynamic range of the current of the constant current source 261 may also fluctuate due to PVT variations. This body bias control unit 300 differs from the second embodiment in that it further controls the body bias of the constant current source 261.

[0097] 13 is a circuit diagram showing a configuration example of a load MOS circuit 260 according to the third embodiment of the present technology. A body bias control unit 300 according to the third embodiment supplies a body bias VB of the same potential to both the constant current source 261 and the control transistor 262 of each column, and controls the bias.

[0098] The body bias control unit 300 further controls the body bias of the constant current source 261, thereby making it possible to suppress fluctuations in the dynamic range of the current value of the constant current source 261 due to PVT variations.

[0099] 14 is a cross-sectional view showing a configuration example of a semiconductor substrate 400 according to the third embodiment of the present technology. － Of the layers 405 and 407, P ＋ Layer 405 is reduced. － Layer 407 contains P ＋ A layer 408, a gate 411, a source 412 and a drain 413 that constitute the constant current source 261, and a gate 421, a source 422 and a drain 423 that constitute the control transistor 262 are formed.

[0100] 13, the body bias control unit 300 controls the body bias of the constant current source 261 and the control transistor 262 to the same potential. With this configuration, the wells are not separated as in the second embodiment, and the constant current source 261 and the control transistor 262 are connected to the same well (P － The structure in which the wells are not separated can reduce the mounting area of ​​the constant current source 261 and the control transistor 262 compared to the case in which they are separated.

[0101] The body bias control unit 300 can also control the body bias of the constant current source 261 and the body bias of the control transistor 262 to different potentials. In this case, separation of the wells is required.

[0102] In addition, in the figure, the semiconductor substrate 400 has an SOI structure, but it can also have a bulk structure.

[0103] As described above, according to the third embodiment of the present technology, the body bias control unit 300 further controls the body bias of the constant current source 261, thereby suppressing fluctuations in the dynamic range of the current value of the constant current source 261 due to PVT variations. Furthermore, by controlling the body biases of the constant current source 261 and the control transistor 262 to the same potential, separation of wells is not required, and the mounting area can be reduced.

[0104] 4. Fourth Embodiment In the first embodiment described above, the body bias VB is controlled based on the comparison result between the measured value Im of the current flowing through the replica transistor 272 and the reference value Iref. However, there are cases where the influence of variations in the power supply voltage and temperature among the PVT factors is relatively small. The solid-state imaging device 200 in this fourth embodiment differs from the first embodiment in that the body bias VB is generated based on a setting value of a register.

[0105] 15 is a block diagram showing a configuration example of a body bias control unit 300 and a load MOS circuit 260 according to a fourth embodiment of the present technology. The body bias control unit 300 according to the fourth embodiment differs from the first embodiment in that it includes a one-time programmable (OTP) memory 341 and a register 342 instead of a current monitor circuit 310 and a comparison circuit 320. Furthermore, the replica circuit 270 is not arranged in the load MOS circuit 260 according to the fourth embodiment.

[0106] A test circuit (not shown) external to the solid-state imaging device 200 measures the current flowing through the control transistor 262 in a predetermined test environment, calculates a set value based on the comparison result between the measured value Im and the reference value Iref, and stores the set value in the OTP memory 341. This set value indicates the control content of the body bias VB. Note that the set value can also be stored in a type of nonvolatile invention memory other than the OTP memory 341.

[0107] The register 342 holds the setting value read from the OTP memory 341. The register 342 supplies the setting value to the body bias generation section 330. The body bias generation section 330 generates a body bias VB in accordance with the setting value.

[0108] When the influence of variations in power supply voltage and temperature is relatively small, fluctuations in settling time due to process variations can be suppressed by generating the body bias VB according to the setting value of the register 342. With this configuration, the replica circuit 270, the current monitor circuit 310, and the comparison circuit 320 can be eliminated.

[0109] The second or third embodiment can be applied to the fourth embodiment.

[0110] Thus, according to the fourth embodiment of the present technology, the body bias control unit 300 generates the body bias VB according to the set value of the register 342, so that the replica circuit 270, the current monitor circuit 310, and the comparison circuit 320 can be reduced.

[0111] 5. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0112] FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0113] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 16, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0114] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0115] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0116] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0117] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0118] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0119] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0120] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0121] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0122] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 16, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0123] FIG. 17 is a diagram showing an example of the installation position of the imaging unit 12031.

[0124] In FIG. 17, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0125] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0126] 17 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0127] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0128] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0129] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0130] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0131] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the image capture unit 12031 of the above-described configuration. Specifically, the image capture device 100 of FIG. 1 can be applied to the image capture unit 12031. By applying the technology according to the present disclosure to the image capture unit 12031, it is possible to reduce the AD conversion time while suppressing an increase in power consumption, thereby increasing the frame rate.

[0132] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0133] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0134] The present technology may also be configured as follows: (1) A solid-state imaging device comprising: a constant current source connected to a vertical signal line; a control transistor that lowers the potential of the vertical signal line in accordance with a predetermined control signal; and a body bias control unit that controls the body bias of the control transistor. (2) The solid-state imaging device according to (1), further comprising: a replica transistor having the same characteristics as the control transistor, wherein the body bias control unit comprises: a current monitor unit that measures a value of a current flowing through the replica transistor as a measurement value; a comparator that compares the measurement value with a predetermined reference current value and outputs a comparison result; and a body bias generation unit that generates the body bias based on the comparison result. (3) The solid-state imaging device according to (1), wherein the body bias control unit comprises: a register that holds a predetermined setting value; and a body bias generation unit that generates the body bias based on the setting value. (4) The solid-state imaging device according to any of (1) to (3), wherein the semiconductor substrate on which the control transistor is formed is an SOI substrate. (5) The solid-state imaging device according to any one of (1) to (4), wherein the constant current source is formed in a first well of a semiconductor substrate, and the control transistor is formed in a second well of the semiconductor substrate. (6) The solid-state imaging device according to any one of (1) to (5), wherein the body bias control unit further controls the body bias of the constant current source. (7) The solid-state imaging device according to (6), wherein the body bias control unit controls the body bias of the constant current source and the control transistor to the same potential, and the constant current source and the control transistor are formed in a predetermined well of a semiconductor substrate. (8) The solid-state imaging device according to (1), further comprising: a photoelectric conversion element; a transfer transistor that transfers charges from the photoelectric conversion element to a floating diffusion layer in accordance with a predetermined transfer signal; a reset transistor that initializes the floating diffusion layer in accordance with a predetermined reset signal; a selection transistor that opens and closes a path between a power supply voltage and the vertical signal line in accordance with a predetermined selection signal; and an amplifier transistor that amplifies the potential of the floating diffusion layer and supplies the amplified potential to the vertical signal line.(9) An imaging device comprising: a constant current source connected to a vertical signal line; a control transistor for lowering a potential of the vertical signal line in accordance with a predetermined control signal; a body bias control unit for controlling a body bias of the control transistor; and a signal processing unit for processing a pixel signal of the potential. (10) A control method for a solid-state imaging element comprising: a procedure in which the control transistor lowers a potential of the vertical signal line to which the constant current source is connected in accordance with a predetermined control signal; and a procedure in which the body bias control unit controls the body bias of the control transistor.

[0135] 100 Imaging device 110 Optical unit 120 DSP circuit 130 Display unit 140 Operation unit 150 Bus 160 Frame memory 170 Storage unit 180 Power supply unit 200 Solid-state imaging element 210 Vertical drive circuit 220 Timing control unit 230 DAC 240 Pixel array unit 250 Pixel 251 Photoelectric conversion element 252 Transfer transistor 253 Reset transistor 254 Floating diffusion layer 255 Selection transistor 256 Amplification transistor 260 Load MOS circuit 261 Constant current source 262 Control transistor 270 Replica circuit 271 Resistor 272 Replica transistor 280 Column signal processing unit 281 ADC 282 Comparator 283 Counter 284 Latch circuit 290 Horizontal scanning circuit 300 Body bias control unit 310 Current monitor circuit 320 Comparison circuit 330 Body bias generation unit 341 OTP memory 342 Register 400 Semiconductor substrate 401 P substrate 402 Deep N well 403 Insulation layer 404 N ＋ Layer 405, 407 P － Layer 406, 408 P ＋ Layers 411, 421 Gate 422, 422 Source 423, 423 Drain 431, 432 BOX (Burried Oxide) film 12031 Imaging section

Claims

1. A solid-state imaging element comprising: a constant current source connected to a vertical signal line; a control transistor that lowers the potential of the vertical signal line in accordance with a predetermined control signal; and a body bias control unit that controls the body bias of the control transistor.

2. A solid-state imaging element as described in claim 1, further comprising a replica transistor having the same characteristics as the control transistor, wherein the body bias control unit comprises: a current monitor unit which measures the value of a current flowing through the replica transistor as a measurement value; a comparison unit which compares the measurement value with a predetermined reference current value and outputs a comparison result; and a body bias generation unit which generates the body bias based on the comparison result.

3. A solid-state imaging element according to claim 1, wherein the body bias control unit comprises: a register for holding a predetermined set value; and a body bias generation unit for generating the body bias based on the set value.

4. The solid-state imaging device according to claim 1, wherein the semiconductor substrate on which the control transistor is formed is an SOI (Silicon On Insulator) substrate.

5. The solid-state imaging device according to claim 1, wherein the constant current source is formed in a first well of a semiconductor substrate, and the control transistor is formed in a second well of the semiconductor substrate.

6. The solid-state imaging device according to claim 1, wherein the body bias control section further controls the body bias of the constant current source.

7. A solid-state imaging device according to claim 6, wherein the body bias control unit controls the body bias of the constant current source and the control transistor to the same potential, and the constant current source and the control transistor are formed in a predetermined well of a semiconductor substrate.

8. A solid-state imaging device as described in claim 1, further comprising: a photoelectric conversion element; a transfer transistor for transferring charges from the photoelectric conversion element to a floating diffusion layer in accordance with a predetermined transfer signal; a reset transistor for initializing the floating diffusion layer in accordance with a predetermined reset signal; a selection transistor for opening and closing a path between a power supply voltage and the vertical signal line in accordance with a predetermined selection signal; and an amplification transistor for amplifying the potential of the floating diffusion layer and supplying it to the vertical signal line.

9. An imaging device comprising: a constant current source connected to a vertical signal line; a control transistor that lowers the potential of the vertical signal line in accordance with a predetermined control signal; a body bias control unit that controls the body bias of the control transistor; and a signal processing unit that processes a pixel signal of the potential.

10. A method for controlling a solid-state imaging element, comprising: a step of a control transistor lowering the potential of a vertical signal line to which a constant current source is connected in accordance with a predetermined control signal; and a step of a body bias control unit controlling the body bias of the control transistor.

Images