Chip-scale packaging-based optical module and manufacturing method therefor

Abstract

An optical module is disclosed. The optical module comprises: a core substrate including an element arrangement hole, a via and an alignment mark; an electronic element and an optical element arranged in the element arrangement hole; an epoxy molding compound molded between the electronic element and the optical element; a metal rewiring layer for electrically connecting the via, a pad of the electronic element, and a pad of the optical element; an insulating layer arranged on the metal rewiring layer, the electronic element and the optical element; and an opening which is formed on the insulating layer arranged on the optical element, and which serves as a signal path of light that is input into or output from the optical element.

Description

Chip-scale packaging-based optical module and its manufacturing method

[0001] The present invention relates to an optical module, and more particularly, to an optical module based on chip-scale packaging.

[0002] An optical module is a module that converts electrical signals into optical signals or vice versa. It provides optical connectivity for high-speed signal transmission in applications such as data centers and high-performance computing. An optical module comprises optical and electronic components. Optical modules can be implemented by packaging optical and electronic components into a confined space.

[0003] Recently, active research has been conducted on technologies that connect optical and electronic components by placing high-speed optical components close to the input / output of electronic components. In particular, as the data transmission speeds of optical modules used in data centers increase to 51 Tbps and 102 Tbps or more, it becomes necessary to place optical components as close as possible to electronic components on the same package substrate. However, structures that mount optical and electronic components on the same package substrate face physical limitations in achieving the closest possible placement of optical and electronic components.

[0004] The present invention, which aims to solve the above-described problems, is directed to providing an optical module based on chip-scale packaging and a method for manufacturing the same, which is designed to place optical elements and electronic elements as closely as possible using wafer-level packaging (WLP) technology as another novel approach.

[0005] In order to achieve the above-described object, a method for manufacturing an optical module based on chip-scale packaging according to one aspect of the present invention comprises: a first step of forming a device placement hole, a via, and an alignment mark in a core substrate; a second step of arranging an electronic device and an optical device on the temporary substrate exposed upward by the device placement hole after arranging the core substrate on a temporary substrate, with reference to the alignment mark; a third step of forming a metal redistribution layer electrically connecting the via, the pad formed on the electronic device, and the pad formed on the optical device, which are exposed by the separation of the temporary substrate after separating the temporary substrate from the core substrate; a fourth step of forming an insulating layer on the metal redistribution layer, the electronic device, and the optical device; a fifth step of forming an opening that serves as an optical signal path through which light is input or output to the optical device by removing the insulating layer formed on the optical device; and a sixth step of defining an individual chip including the via, the electronic device, the optical device, and the opening as one optical module and separating the optical module from the core substrate.

[0006] According to another aspect of the present invention, an optical module based on chip-scale packaging comprises: a core substrate including a device placement hole, a via, and an alignment mark; an electronic device and an optical device placed in the device placement hole; an epoxy molding compound molded between the electronic device and the optical device; a metal redistribution layer electrically connecting the via, a pad of the electronic device, and a pad of the optical device; an insulating layer disposed over the metal redistribution layer, the electronic device, and the optical device; and an opening formed on the insulating layer disposed over the optical device and serving as a signal path for light input to or output from the optical device.

[0007] In an embodiment, the optical module further includes an optical fiber block positioned on the opening using an alignment mark for optical coupling formed on the core substrate.

[0008] In an embodiment, the alignment mark for optical coupling is formed between the element placement hole and the via.

[0009] In an embodiment, the alignment mark is a structure in which a conductive material is filled in a hole penetrating the core substrate.

[0010] According to the present invention, by manufacturing an optical module using a wafer-level packaging (WLP) process, a highly integrated optical module having miniaturization, high signal integrity, reduced packaging cost, and high mass production yield can be realized.

[0011] Figure 1 is a configuration diagram of an optical module according to an embodiment of the present invention.

[0012] FIGS. 2 and 3 are plan views and cross-sectional views for explaining a core substrate manufacturing process among the manufacturing processes of an optical module according to an embodiment of the present invention.

[0013] FIGS. 4 and 5 are plan views and cross-sectional views for explaining a process performed after the core substrate manufacturing process of FIGS. 2 and 3 among the manufacturing processes of an optical module according to an embodiment of the present invention.

[0014] FIGS. 6 and 7 are plan views and cross-sectional views for explaining a process performed after the element arrangement process of FIGS. 4 and 5 among the manufacturing processes of an optical module according to an embodiment of the present invention.

[0015] FIGS. 8 and 9 are plan views and cross-sectional views for explaining a process performed after the epoxy molding and back-grinding processes of FIGS. 6 and 7 among the manufacturing processes of an optical module according to an embodiment of the present invention.

[0016] FIG. 10 is a drawing for explaining a process performed after forming the redistribution layer of FIGS. 8 and 9 among the manufacturing processes of an optical module according to an embodiment of the present invention.

[0017] FIG. 11 is a drawing for explaining in detail a core substrate according to an embodiment of the present invention.

[0018] FIG. 12 is a drawing for explaining an optical fiber block mounted on an optical module according to an embodiment of the present invention.

[0019] FIG. 13 is a flowchart illustrating a method for manufacturing an optical module based on chip-scale packaging according to an embodiment of the present invention.

[0020] Hereinafter, with reference to the attached drawings, preferred embodiments of the present invention will be described in more detail. In order to facilitate an overall understanding in describing the present invention, identical reference numerals will be used for identical components in the drawings, and redundant descriptions of identical components will be omitted.

[0021] The terminology used herein is merely used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0022]

[0023] Figure 1 is a configuration diagram of an optical module according to an embodiment of the present invention.

[0024] Referring to FIG. 1, an optical module (100) includes an electronic component (10), an optical component (20), and an optical fiber block (30). The electronic component (10) and the optical component (20) can be implemented in the form of a chip. The electronic component (10) includes an electronic component (12) for optical transmission and an electronic component (14) for optical reception. The optical component (20) includes an optical transmission component (22) and an optical reception component (24).

[0025] The optical module (100) can be used as an optical transmission module or an optical reception module. An electronic component for optical transmission (12), an optical transmission component (22), and an optical fiber block (30) can be used as an optical transmission module, and an electronic component for optical reception (14), an optical reception component (24), and an optical fiber block (30) can be used as an optical reception module.

[0026] An optical transmission electronic component (12) used as an optical transmission module applies a bias current to an optical transmission component (22) used as an optical transmission module. To apply the bias current, the optical transmission electronic component (12) may include a driver IC (Integrated Circuit). In addition, the optical transmission electronic component (12) may be configured to further include a CDR (Clock and Data Recovery) block, a DSP (Digital Signal Processor), and the like. The optical transmission electronic component (12) configured to include a driver IC, a CDR block, a DSP, and the like may be implemented in a chip form.

[0027] The optical transmission element (22) modulates and converts an electrical signal into an optical signal according to a bias current applied from the optical transmission electronic element (12). To this end, the optical transmission element (22) may be configured to include, for example, a VCSEL (Vertical-Cavity Surface-Emitting Laser) driven according to the bias current. Such a VCSEL may be implemented in a chip form.

[0028] An optical fiber block (30) used as an optical transmission module may be configured to include a multi-channel or single optical fiber that transmits an optical signal from an optical transmission element (22). In this case, the optical fiber block (30) may also be used as an optical reception module. The optical fiber block (30) may be, for example, an 'optical waveguide' including an optical fiber.

[0029] The optical receiving element (24) used as the optical receiving module converts the optical signal transmitted from the optical fiber block (30) used as the optical receiving module into an electrical signal (current signal or photocurrent). For this purpose, the optical receiving element (24) may include, for example, a photodiode (PD). Here, the photodiode may be configured to have a structure in which the optical signal is incident vertically onto the photodiode.

[0030] The optical receiving electronic component (14) used as the optical receiving module converts and amplifies the electrical signal output from the optical receiving component (24) into a corresponding current signal (e.g., photocurrent). To this end, the optical receiving electronic component (14) may include a TIA (Transimpedance amplifier). In addition, the optical receiving electronic component (14) may be configured to further include a CDR block, a DSP, etc. The optical transmitting electronic component (12) configured to include a TIA, a CDR block, a DSP, etc. may be implemented in a chip form.

[0031]

[0032] FIGS. 2 and 3 are plan views and cross-sectional views for explaining a core substrate manufacturing process among the manufacturing processes of an optical module according to an embodiment of the present invention.

[0033] Referring to FIGS. 2 and 3, first, a wafer-level core substrate (110) is prepared. At this time, the core substrate (110) may be a circular wafer or a square panel. In this specification, the core substrate (110) is assumed to be a circular wafer for explanation as an example. In this case, the core substrate may be, for example, a silicon wafer or a glass wafer. A component placement hole (111), a via (vertical interconnect access) (112), and an alignment mark (113) are formed on the prepared core substrate (110).

[0034] The element placement hole (111) is a hole penetrating the core substrate (110). The element placement hole (111) is used as a space for placing electronic elements (120 in FIGS. 4 and 5) and optical elements (130 in FIGS. 4 and 5). The element placement hole (111) is formed on the outer side of the core substrate (110). The element placement hole (111) can be formed by, for example, a process such as wet etching, dry etching, or laser ablation.

[0035] A via (112) is, for example, a structure in which a conductive material (e.g., a metal material, etc.) is filled in a hole penetrating the core substrate (110), and may be configured in multiple numbers surrounding the element placement hole (111). The hole for forming the via (112) may be formed by a process such as wet etching, dry etching, or laser ablation, for example. The via (112) serves to electrically connect any structure disposed on the upper surface of the core substrate (110) and any structure disposed on the lower surface of the core substrate (110). In this specification, the upper surface and the lower surface are defined by pads (121, 122, and 131 of FIG. 9) described below. That is, the surface on which the pads (121, 122, and 131 of FIG. 9) are visible is defined as the lower surface, and the opposite surface is defined as the upper surface.

[0036] The alignment mark (113) is, for example, a structure in which a conductive material (e.g., a metal material, etc.) is filled in a hole penetrating the core substrate (110), and is utilized as an identification mark required in device placement and wafer processing. The hole for forming the alignment mark (113) can be formed by, for example, a process such as wet etching, dry etching, or laser ablation.

[0037] As described above, since the alignment mark (113) is a structure in which a conductive material is filled in a hole penetrating the core substrate (110), the alignment mark (113) is continuously exposed even if the surface of the core substrate (110) is removed through an etching process such as the planarization process (backgrinding process) described below. Therefore, there is an advantage in that an additional process of forming the alignment mark (113) again after the planarization process of the core substrate (110) is unnecessary.

[0038]

[0039] FIGS. 4 and 5 are plan views and cross-sectional views for explaining a process performed after the core substrate manufacturing process of FIGS. 2 and 3 among the manufacturing processes of an optical module according to an embodiment of the present invention.

[0040] Referring to FIGS. 4 and 5, a core substrate (110) is placed on a temporary wafer (150) using a pick and place device. During this placement process, the core substrate (110) is bonded to the surface of the temporary substrate (150) by an adhesive layer (140) formed on the surface of the temporary substrate (150).

[0041] Next, based on the alignment mark (113) visible on the upper surface of the core substrate (110), the electronic element (120) and the optical element (130) are placed on the surface of the temporary substrate (150) exposed upward by the element placement hole (111). At this time, the electronic element (120) and the optical element (130) are bonded on the surface of the temporary substrate (150) by the adhesive layer (140). The electronic element (120) and the optical element (130) correspond to the electronic element (10) and the optical element (20) of FIG. 1, respectively.

[0042]

[0043] FIGS. 6 and 7 are plan views and cross-sectional views for explaining a process performed after the element arrangement process of FIGS. 4 and 5 among the manufacturing processes of an optical module according to an embodiment of the present invention.

[0044] Referring to FIGS. 6 and 7, in order to physically protect the electronic element (120) and the optical element (130) placed in the element placement hole (111) of the core substrate (110) from the external environment, the surface of the core substrate (110), the electronic element (120), and the optical element (130) are molded with an epoxy molding compound (EMC) (160) through an epoxy molding process. At this time, the EMC (160) is also filled in the empty space between the side surface of the electronic element (120) and the inner wall of the element placement hole (111), the empty space between the side surface of the optical element (130) and the inner wall of the element placement hole (111), and the empty space between the side surface of the electronic element (120) and the side surface of the optical element (130).

[0045] Next, the EMC (160) is cured under high temperature and high pressure conditions through a curing process, and when the EMC (160) is completely cured by this curing process, the surface of the core substrate (110), the electronic element (120), and the optical element (130) are completely blocked from the external environment by the cured EMC (160). In the present invention, since the empty space between the core substrate (110), the electronic element (120), and the optical element (130) is filled with the cured EMC (160), the electronic element (120) and the optical element (130) can be stably fixed inside the element placement hole of the core substrate (110). If the EMC (160) has high thermal conductivity and the core substrate (110) with high thermal conductivity is used, there is an advantage of improving the package heat dissipation performance.

[0046] Next, through a backgrinding process, the upper surface of the core substrate (110) and the upper surface of the via (112) are planarized and the core substrate (110) and EMC (160) are removed to form a chip scale thickness.

[0047] Next, when the entire height of the core substrate (110) reaches a certain height while the upper surface of the electronic element (120) and the upper surface of the optical element (130) are exposed or the upper surface of the electronic element (120) and the upper surface of the optical element (130) are not exposed, a metal pattern (70) that serves as an electrical ground and heat dissipation is formed on the exposed upper surface of the electronic element (120) and the upper surface of the optical element (130) with reference to the exposed alignment mark, or when the upper surface of the electronic element (120) and the upper surface of the optical element (130) are not exposed, a metal pattern (70) that serves as a heat dissipation is formed on the EMC (160) formed on the upper surface of the electronic element (120) and the upper surface of the optical element (130).

[0048] Additionally, a pad (71) such as a land or ball for signal input / output of an electronic element (120) and an optical element (130) is formed on the upper surface of the exposed via (112).

[0049]

[0050] FIGS. 8 and 9 are plan views and cross-sectional views for explaining a process performed after the epoxy molding and back-grinding processes of FIGS. 6 and 7 among the manufacturing processes of an optical module according to an embodiment of the present invention.

[0051]

[0052] *Referring to FIGS. 8 and 9, a temporary substrate (150) is separated from the lower surface of the core substrate (110). The separation process may be performed, for example, through a process of heating the temporary substrate (150) and the adhesive layer (140) to a predetermined separation temperature or irradiating them with UV.

[0053] Next, through a cleaning process, impurities remaining on the lower surface of the core substrate (110), the lower surface of the via (112), the lower surface of the electronic element (120), and the lower surface of the optical element (130) are cleanly removed. The cleaning process includes, for example, chemical cleaning that removes impurities using a chemical solution or gas, and a washing and drying process that washes with an appropriate solvent or DI (Deionized) water.

[0054] Next, a first insulating layer (e.g., polymer material, etc.) for electrical insulation is formed over the entire lower surface of the core substrate (110) through a deposition process such as spin coating. For simplicity of the drawing, the first insulating layer is omitted in FIG. 9.

[0055] Next, in order to expose the pad (122) of the electronic component (120) and the pad (131) of the optical component (130) with reference to the alignment mark (113), the first insulating layer (not shown) is partially removed. To partially remove the first insulating layer (not shown), a first photolithography process can be used. The first insulating layer is made of a transparent material so that the alignment mark (113) can be confirmed with the naked eye. Therefore, the pad (122) of the electronic component (120) and the pad (131) of the optical component (130) can be opened with reference to the alignment mark (113). In this way, in the present invention, the pad (122) of the electronic component (120) and the pad (131) of the optical component (130) are opened with reference to the alignment mark (113). If the accuracy of the pick-and-place equipment is high, the chip pad can be opened within several micrometers, which has the advantage of alleviating chip pad size constraints.

[0056] Next, a first metal redistribution layer (171) that electrically connects the lower surface of the via (112) and the pad (121) of the electronic device (120) and a second metal redistribution layer (172) that electrically connects the pad (122) of the electronic device (120) and the pad (131) of the optical device (130) are formed through a deposition process. The metal redistribution layer (metal RDL) may be, for example, a material having excellent electrical conductivity, such as copper, gold, aluminum, or a composite thereof.

[0057] Next, through a deposition process such as spin coating, a second insulating layer (e.g., polymer material) (180) is formed over the entire lower surface of the core substrate (110), and then an opening (OP) is formed to expose the lower surface of the optical element (130) to the second insulating layer (180) with reference to the alignment mark (113). The opening (OP) can be formed by a photolithography process (hereinafter, referred to as the “second photolithography process”). The opening (OP) serves as an optical signal path through which light is input to or output from the optical element (130).

[0058]

[0059] FIG. 10 is a drawing for explaining a process performed after forming the redistribution layer of FIGS. 8 and 9 among the manufacturing processes of an optical module according to an embodiment of the present invention.

[0060] Referring to FIG. 10, when the formation of the redistribution layers (171, 172, and 180) at the wafer level is completed, a core substrate (110) at the wafer level is cut along a dicing line (DL, Dicing Line) using a die-cutting device in a dicing process, and a modularization process is performed to separate the optical module (100) as an individual chip from the core substrate (110).

[0061]

[0062] FIG. 11 is a drawing for explaining in detail a core substrate according to an embodiment of the present invention.

[0063] Referring to FIG. 11, reference symbol A is a plan view of the core substrate (110) as viewed from above, reference symbol B is a three-dimensional view of the core substrate (110) as viewed from above, and reference symbol C is a three-dimensional view of the core substrate (110) as viewed from below. In addition, D is an enlarged view of a portion indicated by a circle in the three-dimensional view C of the core substrate (110) as viewed from below.

[0064] As shown in Fig. 11, a plurality of element placement holes (111) penetrating the core substrate (110) are arranged in a matrix form.

[0065] In addition, a plurality of vias (112) surrounding each element placement hole (111) are formed in the core substrate (110), and each via (112) can be configured as a structure in which a conductive material is filled in a hole penetrating the core substrate (110).

[0066] In addition, cross (+)-shaped alignment marks (113) are formed on the core substrate (110) around a plurality of element placement holes (111) to accurately place and align electronic elements (120) and optical elements (130) in the element placement holes (111). Each alignment mark (113) may be formed of a structure in which a conductive material is filled in a hole through which the core substrate (110) passes.

[0067] In Fig. 11, it is assumed that the inside of the hole for forming a via (112) and the hole for forming an alignment mark (113) are empty.

[0068] Meanwhile, as can be seen in the enlarged view D of FIG. 11, an alignment mark (114) for optical coupling may be further formed between the element placement hole (111) and the via (112) on the lower surface of the core substrate (110). This alignment mark (114) for optical coupling serves as an identification mark for coupling the optical fiber block (30 of FIG. 1) and the optical element (130).

[0069]

[0070] FIG. 12 is a drawing for explaining an optical fiber block mounted on an optical module according to an embodiment of the present invention.

[0071] As illustrated in Fig. 12, a highly integrated optical module is implemented by mounting an optical fiber block (30) on an optical module (100) separated as an individual chip from a core substrate (110). The optical fiber block (30) includes an optical fiber (32). In addition, the optical fiber block (30) may be configured to further include a lens, although not illustrated, in order to increase optical coupling efficiency with the optical module (100) and reduce optical alignment errors. The optical fiber block (30) may be a type of optical waveguide.

[0072] In the process of mounting the optical fiber block (30) on the optical module (100), an alignment mark (114) for optical coupling formed on the lower surface of the core substrate (110) of FIG. 11 and another alignment mark (34) for optical coupling formed on the lower surface of the optical fiber block (30) can be used.

[0073] In an embodiment, the end of the optical fiber block (30) is placed on an opening (OP) formed in a second insulating layer (180) of the optical module (100), and an optical coupling alignment mark (114) formed on a core substrate (110) and another optical coupling alignment mark (34) formed on a lower surface of the end of the optical fiber block (30) are aligned in a vertical direction, and then the optical fiber block (30) is mounted on the optical module (100). By doing so, a highly integrated optical module in which the optical fiber block (30) and the optical module (100) are combined is completed.

[0074]

[0075] FIG. 13 is a flowchart illustrating a method for manufacturing an optical module based on chip-scale packaging according to an embodiment of the present invention.

[0076] Referring to FIG. 13, in S110, a first process is performed to form a device placement hole (111), a via (112), and an alignment mark (113) in a core substrate (110) through an etching process.

[0077] Next, at S120, a second process is performed in which the core substrate (110) is placed on a temporary substrate (150) through a pick and place device, and then the electronic element (120) and the optical element (130) are placed on the temporary substrate (150) exposed upward by the element placement hole (111) with reference to the alignment mark (113).

[0078] Next, in S130, the core substrate (110) is irradiated with UV to separate the temporary substrate (150) from the core substrate (110), and then a third process is performed to form metal redistribution layers (171 and 172) that electrically connect the via (112) exposed by separation of the temporary substrate (150), the pad formed on the electronic element (120), and the pad formed on the optical element (130) through a deposition process.

[0079] Next, in S140, a fourth process is performed to form an insulating layer (180) on the metal redistribution layer (171 and 172), the electronic element (120), and the optical element (130) through a deposition process.

[0080] Next, at S150, the insulating layer (180) formed on the optical element (130) is removed through an etching process to form an opening that serves as a signal path for light input or output to the optical element (130). At S160, a sixth process of dicing the core substrate is performed to obtain an optical module in a chip unit including the via, the electronic element, the optical element, and the opening.

[0081] In an embodiment, the core substrate (110) may be a silicon wafer or a glass wafer.

[0082] In an embodiment, the first process includes a process of forming a plurality of holes penetrating the core substrate (110) on the outer surface of the core substrate (110) and a process of forming the alignment mark by filling the plurality of holes with a conductive material.

[0083] In an embodiment, the first process includes a process of forming a plurality of holes surrounding the element placement hole (111) and a process of filling the plurality of holes with a conductive material to form the via (112).

[0084] In an embodiment, between the second process and the third process, a process of molding the electronic element (120) and the optical element (130) with EMC (160), a process of removing the EMC (160) until the upper surfaces of the electronic element (120) and the optical element (130) are exposed, and a process of forming a metal pattern (70 in FIG. 7) that serves as an electrical ground and heat dissipation on the upper surfaces of the electronic element (120) and the optical element (130) exposed by the removal of the EMC (160).

[0085] In the embodiment, the process further includes forming a pad (71 in FIG. 7) including a land or ball in the via exposed by removal of the EMC (160).

[0086] In the embodiment, after the sixth process, a process of mounting an optical fiber block (30) on the optical module (100) using a first optical coupling alignment mark (114 in FIG. 11) formed on the core substrate (110) is further included.

[0087] In an embodiment, the first optical coupling alignment mark (114 in FIG. 11) may be formed between the element placement hole (111) and the via (112).

[0088] In an embodiment, the mounting process further includes a process of placing an end portion of the optical fiber block (30) over the opening (OP), a process of vertically aligning the first optical coupling alignment mark (114) and the second optical coupling alignment mark (34 in FIG. 12) formed on the lower surface of the end portion, and a process of mounting the optical fiber block (30) over the optical module (100) while aligning the first optical coupling alignment mark (114) and the second optical coupling alignment mark (34 in FIG. 12).

[0089]

[0090] Although the present invention has been described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

[0091] It can be used to manufacture optical modules based on chip-scale packaging.

Claims

1. A first step of forming element placement holes, vias and alignment marks on a core substrate; A second step of placing the core substrate on a temporary substrate, and then placing electronic elements and optical elements on the temporary substrate exposed upward by the element placement hole with reference to the alignment mark; A third step of forming a metal rewiring layer that electrically connects the via, the pad formed on the electronic element, and the pad formed on the optical element exposed by separating the temporary substrate from the core substrate; A fourth step of forming an insulating layer on the metal rewiring layer, the electronic element, and the optical element; A fifth step of removing the insulating layer formed on the optical element to form an opening that serves as a signal path for light input or output to the optical element; and Step 6 of dicing the above core substrate A method for manufacturing an optical module based on chip-scale packaging comprising:

2. In paragraph 1, A method for manufacturing an optical module based on chip-scale packaging, wherein the core substrate is a silicon wafer, a glass wafer or a panel.

3. In paragraph 1, The above first step is, A step of forming a plurality of holes penetrating the core substrate on the outer surface of the core substrate; and A step of forming the alignment mark by filling the plurality of holes with a conductive material. A method for manufacturing an optical module based on chip-scale packaging comprising:

4. In paragraph 1, The above first step is, A step of forming a plurality of holes surrounding the above-mentioned element arrangement hole; and A step of forming the via by filling the plurality of holes with a conductive material. A method for manufacturing an optical module based on chip-scale packaging comprising:

5. In paragraph 1, Between the second and third steps, A step of molding the electronic element and the optical element with an epoxy molding compound; A step of removing the epoxy molding compound until the upper surface of the electronic element and the optical element is exposed; and A step of forming a metal pattern that serves as an electrical ground and heat dissipation on the upper surface of the electronic element and the optical element exposed by removing the epoxy molding compound. A method for manufacturing an optical module based on chip-scale packaging, the method further comprising:

6. In paragraph 5, A step of forming a pad including a land or ball in the via exposed by removing the epoxy molding compound. A method for manufacturing an optical module based on chip-scale packaging, the method further comprising:

7. In paragraph 1, After the above 6th step, a step of mounting an optical fiber block on the optical module using the first optical coupling alignment mark formed on the core substrate. A method for manufacturing an optical module based on chip-scale packaging, the method further comprising:

8. In paragraph 7, The above first optical coupling alignment mark is, A method for manufacturing an optical module based on chip-scale packaging formed between the above-mentioned element placement hole and the above-mentioned via.

9. In paragraph 7, The above implementation steps are: A step of placing the end of the optical fiber block over the opening; A step of vertically aligning the first optical coupling alignment mark and the second optical coupling alignment mark formed on the lower surface of the end portion; and A step of mounting the optical fiber block on the optical module while aligning the first optical coupling alignment mark and the second optical coupling alignment mark. A method for manufacturing an optical module based on chip-scale packaging, the method further comprising:

10. Core substrate including component placement holes, vias and alignment marks; Electronic elements and optical elements arranged in the above element arrangement holes; An epoxy molding compound molded between the electronic element and the optical element; A metal redistribution layer electrically connecting the above via, the pad of the electronic element, and the pad of the optical element; an insulating layer disposed on the metal rewiring layer, the electronic element, and the optical element; and An opening formed on an insulating layer disposed on the optical element and serving as a signal path for light input or output to the optical element An optical module including:

11. In paragraph 10, An optical module further comprising an optical fiber block arranged on the opening using an alignment mark for optical coupling formed on the core substrate.

12. In paragraph 11, The alignment mark for the above optical coupling is, An optical module formed between the above-mentioned element placement hole and the above-mentioned via.

13. In paragraph 10, The above alignment marks are, An optical module having a structure in which a conductive material is filled in a hole penetrating the core substrate.

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