In-SITU patterning for ETCH process

Abstract

A method of transferring a pattern from a patterned mask to an etch layer is provided, wherein the patterned mask defines wider mask features and narrower mask features, where the wider mask features are wider than the narrower mask features. Features are etched into the etch layer through the patterned mask to form narrower features and wider features, wherein the wider features are wider than the narrower features. A deposition is deposited over the narrower features and wider features, wherein the deposition closes the narrower features and does not close the wider features. The wider features are over etched, wherein the over etching does not etch the narrower features.

Description

IN-SITU PATTERNING FOR ETCH PROCESSCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of U.S. Application No. 63 / 582,932, filed September 15, 2023, which is incorporated herein by reference for all purposes.BACKGROUND

[0002] One process frequently employed during the fabrication of semiconductor devices is the formation of a recessed feature in a stack below a mask. The stack may be altemating / repeating layers or a thick film of a single layer of material into which the recessed feature is formed. One example context where such a process may occur is memory applications such as dynamic random access memory (DRAM) and not and devices (NAND). In the manufacturing of some semiconductor devices, metal or other materials may be etched below a carbon containing mask. As the semiconductor industry advances and device dimensions become smaller, such recessed features become increasingly harder to etch in a uniform manner.

[0003] In some etch processes, a CD shrink may be used to provide a mask with a reduced CD, compared to an original mask CD. The original mask may have wider features and narrower features. In a CD shrink process, the CD of the narrower features may be shrunk more than the CD of the wider features.

[0004] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0005] To achieve the foregoing and in accordance with the purpose of the present disclosure, a method of transferring a pattern from a patterned mask to an etch layer is provided, wherein the patterned mask defines wider mask features and narrower mask features, where the wider mask features are wider than the narrower mask features. Features are etched into the etch layer through the patterned mask to form narrower features and wider features, wherein the wider features are wider than the narrower features. A deposition is deposited over the narrower features and wider features, wherein the deposition closes the narrower features and does not close the wider features. The wider features are over etched, wherein the over etching does not etch the narrower features.

[0006] In another manifestation, an apparatus for processing a plurality of stacks isprovided. A substrate support supports a substrate inside a processing chamber. An RF power source provides RF power in the processing chamber. A gas source comprises an etch gas source and a deposition gas source. A controller is controllably connected to the RF power source and the gas source and is configured to cause a substrate to be loaded on the substrate support, cause an etch gas to be provided from the etch gas source, cause a plasma to be generated from the etch gas in order to etch narrower features and wider features in an etch layer on the substrate, cause a deposition gas to be provided from the deposition gas source, cause a plasma to be generated from the deposition gas in order to deposit a deposition over the etch layer, wherein the deposition closes the narrower features but does not close the wider features, cause an over etch gas to be provided from the etch gas source, cause a plasma to be generated from the over etch gas to reduce a taper of the wider features without reducing a taper of the narrower features, and cause the substrate to be removed from the substrate support.

[0007] These and other features of the present disclosure will be described in more detail below in the detailed description and in conjunction with the following figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0009] FIG. 1 depicts a flow chart describing a method used in some embodiments.

[0010] FIGS. 2A-2F are schematic cross-sectional illustrations of a stack processed according to some embodiments.

[0011] FIG. 3 shows a semiconductor processing system that may be used in some embodiments.

[0012] FIG. 4 illustrates a computer system for implementing a controller used in some embodiments.

[0013] In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale.DETAILED DESCRIPTION

[0014] The present disclosure will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without some or all of these specific details. In other instances, wellknown process steps and / or structures have not been described in detail in order to not unnecessarily obscure the present disclosure.

[0015] Fabrication of certain semiconductor devices involves etching features into a stack of materials. In various embodiments herein, the stack of materials includes one or more layers of one or more materials below a carbon containing mask. In some embodiments, at least one layer of the stack contains at least one of silicon, germanium, and metal. Silicon containing layers may contain at least one of silicon nitride, silicon oxide, silicon carbide, silicon oxy-nitride, silicon oxy-carbide, polysilicon, and silicon germanium. In some embodiments, the stack includes alternating layers of silicon oxide and polysilicon. In some embodiments, the stack comprises alternating silicon oxide films with silicon nitride films, or a single silicon oxide layer, or a single silicon layer. In some embodiments, the stack may be a conductive or dielectric layer that may be a metal or silicon containing layer below a carbon containing mask. In some embodiments, the carbon containing mask is a carbon containing at least one of a photoresist, a doped carbon, and an amorphous carbon mask.

[0016] In the formation of semiconductor devices, a CD shrink process may be used in order to provide features with a reduced CD. Some embodiments provide semiconductor devices with a reduced CD by providing a CD shrink process. In some embodiments, a CD shrink process transfers a pattern to a lower layer while shrinking the CD. In some embodiments, the lower layer is used as a mask for etching another layer.

[0017] To facilitate understanding, FIG. 1 is a high level flow chart of a method that may be used in some embodiments. A stack with a patterned mask over an etch layer is provided in a process chamber (step 104). FIG. 2 A is a schematic cross-sectional view of a stack 200 that may be processed according to some embodiments. In some embodiments, the stack 200 comprises an etch layer 204 under a patterned mask 212. In some embodiments, the etch layer 204 may be formed over an under layer 208, that is over another under layer 216. In some embodiments, one or more additional under layers 216 may be between the under layer 208 and a substrate. In some embodiments, one or more layers may be between the etch layer and the mask 212.

[0018] In some embodiments, the mask 212 and the etch layer 204 are different materials. For example, in some embodiments, the mask 212 is a carbon containing material, such as at least one of photoresist, carbon polymer, and amorphous carbon, and the etch layer 204 is a silicon or germanium containing material, such as at least one of silicon oxide, silicon, silicon nitride, silicon carbide, and silicon germanium. The mask 212 defines mask features with wider mask features 220 and narrower mask features 224. In some embodiments, the wider mask features 220 have a first width (Wl), and the narrower mask features 224 have a second width (W2),where the wider mask features 220 are wider than the narrower mask features 224 so that W 1 is greater than W2. In some embodiments, W1>1.5(W2). In some embodiments W1>2(W2).

[0019] In the process chamber, features are etched into the etch layer 204 using the mask 212 as a mask. The etch recipe depends on the material forming the etch layer 204 and the material forming the mask 212. If the mask 212 is a carbon containing mask and the etch layer 204 is formed from a silicon containing material, such as silicon oxide, in some embodiments, a halogen containing etch gas is formed into a plasma in order to etch features into the etch layer 204. FIG. 2B is a schematic cross-sectional view of a stack 200 after the etch process has been completed. In some embodiments, wider features 228 are etched through the wider mask features 220, and narrower features 232 are etched through the narrower mask features 224. In some embodiments, the widest part of the wider features 228 is as wide as the width of the wider mask features 220, and the widest part of the narrower features 232 is as wide as the width of the narrower mask features 224. As a result, the widest part of the wider features 228 is greater than the widest part of the narrower features 232. In some embodiments, the widest part of the wider features 228 is at least one and a half times the widest part of the narrower features 232. In some embodiments, the widest part of the wider features 228 is at least twice the widest part of the narrower features 232.

[0020] In some embodiments, the wider features 228 and the narrower features 232 are tapered. In some embodiments, the wider features 228 have about the same taper as the narrower features 232, so that the slope of the sidewalls of the wider features 228 is about equal to the slope of the sidewalls of the narrower features 232. In some embodiments, a CD bias loading causes the narrower features 232 to have less taper than the wider features 228 so that the slope of the sidewalls of the wider features 228 is less than the slope of the sidewalls of the narrower features 232. As a result, the sidewalls of the narrower features 232 are closer to vertical than the sidewalls of the wider features 228, as shown. In some embodiments, during the etch more etch byproducts may deposit on the wider features, or the wider features may be more reagent limited causing the wider features to be more tapered. The amount of taper is process driven. A process may allow the taper of the wider features to be closer to the taper of the narrower features. However, such processes may affect other characteristics of the etch, like the reduction of CD control, making such processes less desirable. In some embodiments, the widths of the narrowest parts of the wider features 228 and the narrower features 232 depend on the amount of taper of the wider features 228 and the narrower features 232. In some embodiments, the under layer 208 provides an etch stop for the etch process.

[0021] After the features are etched (step 108), the narrower features are closed (step 112) bydepositing a deposition on tops of or over the narrower features 232 and wider features 228 without closing the wider features 228. The recipe for the deposition depends on the material forming the mask 212 and the material forming the etch layer 204. In some embodiments, the deposition is able to be selectively removed with respect to the etch layer 204. In some embodiments, with a carbon containing mask 212 and a silicon containing etch layer 204, the deposition is a carbon containing deposition. An example recipe to provide a carbon containing deposition would use a deposition gas comprising at least one of a hydrocarbon, such as methane (CH4), a fluorocarbon, and a hydrofluorocarbon. In some embodiments, the deposition gas is oxygen free. In some embodiments, the deposition gas further comprises a hydrogen containing component. FIG. 2C is a schematic cross-sectional view of a stack 200 after a deposition 236 has been deposited over the mask 212 and etch layer 204. The deposition 236 closes narrower features 232 without closing wider features 228.

[0022] Next, an over etch of the wider features 228 is provided through the openings in the deposition 236 above the wider features 228 (step 116). The over etch recipe depends on the material forming the etch layer 204 and the material forming the deposition 236. If the deposition 236 is a carbon containing deposition and the etch layer 204 is formed from a silicon containing material, in some embodiments, a halogen containing over etch gas is formed into a plasma in order to over etch the wider features 228. FIG. 2D is a schematic cross-sectional view of a stack 200 after an over etch reduces the taper of the wider features 228, without changing the taper of the narrower features 232. The deposition 236 prevents the over etch from changing the taper of the narrower features 232, while the over etch reduces the taper of the wider features 228.

[0023] If any deposition 236 or mask 212 remains after the over etch, the deposition 236 and / or mask may be removed in an optional deposition and / or mask removal process (step 120). The recipe for the deposition 236 and / or mask 212 removal process depends on the material forming the deposition 236, mask 212, and etch layer 204. For example, if the deposition 236 and / or mask 212 are carbon based and the etch layer 204 is silicon based, the removal recipe may use an oxygen based removal gas that is formed into a plasma in order to ash the deposition 236 and the mask 212. FIG. 2E is a schematic cross-sectional view of a stack 200 after the deposition 236 and mask 212 (shown in FIG. 2D) have been removed. In some embodiments, the deposition removal does not remove or etch any of the etch layer 204. Some embodiments do not have a deposition 236 and / or mask 212 removal process (step 120). In some embodiments, the deposition 236 and / or mask 212 are removed during the over etch (step 116) or during the subsequent pattern transfer (step 124).

[0024] In some embodiments, an optional additional pattern transfer to one or more lower layers is provided (step 124). The optional pattern transfer recipe depends on the material forming the etch layer (204) and the material forming the one or more under layers 208, 216. FIG. 2F is a schematic cross-sectional view of a stack 200 after the wider features 228 and narrower features 232 are further etched through the one or more under layers 208, 216. Other additional processes may be performed in the process chamber in some embodiments.

[0025] After the processing of the stack is completed in the process chamber, the stack is removed from the process chamber (step 128) so that other stacks may be processed. An advantage that is provided by some embodiments is that the etching the features (step 108), closing the narrower features (step 1 12), over etching the wider features (step 1 16), removing the deposition and / or mask (step 120), and transferring the pattern to one or more under layers (step 124) are performed in-situ in a process chamber on a substrate support. Since all of the steps are performed in-situ, the stack 200 does not need to be transferred between chambers or moved from one substrate support to another, increasing processing speed. In addition, performing the steps in-situ also reduces manufacturing costs and reduces contamination.

[0026] In some embodiments, after over etching, the wider features 228 have a taper so that the sidewalls of the wider features 228 are closer to vertical than the sidewalls of the narrower features 232 so that the slope of the narrower features 232 is less than the slope of the wider features 228. For example, the slope of the sidewalls of the wider features 228 is within 5° from the vertical and the slope of the sidewalls of the narrower features 232 is more than 5° from the vertical. In some embodiments, the slope of the sidewalls of the narrower features 232 is about equal to the slope of the sidewall of the wider features 228 after the over etch. For example, the slope of the sidewalls of the narrower features 232 is within 5° of the slope of the sidewalls of the wider features 228. By providing features where the sidewalls of the wider features 228 have about the same slope as the sidewalls of the narrower features 232, the wider features 228 and the narrower features 232 have about equal CD shrink. As a result, the CD shrink for wider features 232 is comparable to the CD shrink for narrower features 228. This allows for providing a CD shrink process that is independent of feature width making the process using CD shrink simpler since such a process does not need to account for different feature widths.

[0027] Some embodiments allow for the taper of the wider features 228 to be selectively reduced, without reducing the taper of the narrower features 232. The selective reduction of tapering provides an improved controlled CD shrink process by providing independent control of the taper of wider features 228 with respect to narrower features 232. Some embodiments use the CD shrink process in multi-pattern applications. In some embodiments, the CD shrink offeatures below the narrower features is about the same as the CD shrink of features below the wider features, providing a CD shrink process that is independent of feature width. In some embodiments, the CD shrink of features below the narrower features has more CD shrink than the features below the wider features.

[0028] In some embodiments, the wider features 228 and narrower features 232 have at least one of circular or oval cross-sections. For features with circular cross-sections, the diameters of the features are the width of the features. For features with an oval cross-section, the minor axes of the oval cross-sections are the widths of the features. In some embodiments, the features have a linear cross-section, where the width of the linear cross-section is the width of the feature. In some embodiments, the mask 212 may be formed from other materials instead of carbon. For example, the mask 212 may comprise silicon. In some embodiments, the etch layer 204 may be formed from other materials. For example, the etch layer 204 may be a carbon based etch layer 204.APPARATUS

[0029] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, 300 mm, or 450 mm. The above detailed description assumes the embodiments are implemented on a wafer. However, the embodiments are not so limited. The workpiece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0030] Unless otherwise defined for a particular parameter, the terms “about” and “approximately” as used herein are intended to mean ±10% with respect to a relevant value.

[0031] FIG. 3 is a schematic view of a plasma processing chamber 300 for plasma processing substrates, in an embodiment. In one or more embodiments, the plasma processing chamber 300 comprises a gas distribution plate 306 providing a gas inlet and an electrostatic chuck (ESC) 316, within a process chamber 304, enclosed by a chamber wall 350. Within the process chamber 304, the substrate 308 is positioned on top of the ESC 316 so that the ESC 316 acts as a substrate support. A bias power may be provided to the ESC 316 from an ESC power source348. A gas source 310 is connected to the process chamber 304 through the gas distribution plate306. In some embodiments, the gas source 310 comprises an etch gas source 312, a removal gas source 314, and a deposition gas source 318. An ESC temperature controller 351 is connected to the ESC 316 and provides temperature control of the ESC 316. A radio frequency (RF) power source 330 provides RF power to the ESC 316 and an upper electrode. In this embodiment, the upper electrode is the gas distribution plate 306. In a preferred embodiment, 400 kilohertz (kHz), 13.56 megahertz (MHz), 1 MHz, 2 MHz, 60 MHz, and / or optionally, 27 MHz power sources make up the RF power source 330 and the ESC power source 348 to provide RF power at RF frequencies. A controller 335 is controllably connected to the RF power source 330, the ESC power source 348, an exhaust pump 320, and the gas source 310. A high flow liner 360 is a liner within the process chamber 304, which confines gas from the gas source and has slots 362. The slots 362 maintain a controlled flow of gas to pass from the gas source 310 to the exhaust pump 320. An example of such a plasma processing chamber is the Flex® etch system manufactured by Lam Research Corporation of Fremont, CA. The process chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0032] FIG. 4 is a high level block diagram illustrating a computer system 400 for implementing the controller 335 used in embodiments of the present inventions. The computer system may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge supercomputer. The computer system 400 may include one or more processors 402 and further can include an electronic display device 404 (for displaying graphics, text, and other data), a main memory 406 (e.g., random access memory (RAM)), storage device 408 (e.g., hard disk drive), removable storage device 410 (e.g., optical disk drive), user interface devices 412 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and / or a communication interface 414 (e.g., wireless network interface). The communication interface 414 may allow software and / or data to be transferred between the computer system 400 and external devices via a link. The system may also include a communications infrastructure 416 (e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices / modules may be connected.

[0033] Information transferred via communications interface 414 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 414, via a communication link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and / or other communication channels. With such a communications interface, it is contemplated that the one or more processors 402 might receive information from a network or might output information to the network in the course of performing the above-describedmethod steps. Furthermore, method embodiments may execute solely upon the processors or may execute over a network such as the Internet in conjunction with remote processors that share a portion of the processing.

[0034] The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM, and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.

[0035] In some embodiments, the controller is configured to etch features into the etch layer to form wider features and narrower features in the etch layer, depositing a deposition over the narrower features and wider features where the deposition closes the narrower features and does not close the wider features, and over etching the wider features but not the narrower features. In some embodiments, the controller is further configured to remove the deposition and to transfer the pattern to layers below the etch layer.CONCLUSION

[0036] While this disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents, which fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure. As used herein, the phrase “A, B, or C” should be construed to mean a logical (“A OR B OR C”), using a non-exclusive logical “OR,” and should not be construed to mean “only one of A or B or C. Each step within a process may be an optional step and is not required. Different embodiments may have one or more steps removed or may provide steps in a different order. In addition, various embodiments may provide different steps simultaneously instead of sequentially.

Claims

CLAIMSWhat is claimed is:

1. A method of transferring a pattern from a patterned mask to an etch layer, wherein the patterned mask defines wider mask features and narrower mask features, where the wider mask features are wider than the narrower mask features, comprising: a) etching features into the etch layer through the patterned mask to form narrower features and wider features, wherein the wider features are wider than the narrower features; b) depositing a deposition over the narrower features and wider features, wherein the deposition closes the narrower features and does not close the wider features; and c) over etching the wider features, wherein the over etching does not etch the narrower features.

2. The method of claim 1 , wherein the over etching of the wider features reduces a taper of the wider features.

3. The method of claim 1, wherein the wider mask features are at least 50% wider than the narrower mask features.

4. The method of claim 1 , wherein the wider mask features have a width that is at least two times a width of the narrower mask features.

5. The method of claim 1, wherein the etching of the features into the etch layer etches the narrower features and wider features to an etch stop layer below the etch layer.

6. The method of claim 1, further comprising removing the deposition.

7. The method of claim 1, further comprising etching a layer below the etch layer transferring a pattern from the etch layer to the layer below the etch layer.

8. The method of claim 7, wherein the transferring the pattern from the etch layer to the layer below the etch layer has a controlled CD shrink, where a CD shrink of wider features is independently controlled with respect to a CD shrink of narrower features.

9. The method of claim 1 , wherein steps b and c are repeated at least once.

10. The method of claim 1, wherein step a is stopped before step b is started.

11. The method of claim 1 , wherein steps b and c overlap.

12. The method of claim 1, wherein the deposition is a carbon containing deposition.

13. The method of claim 12, wherein the etch layer is a silicon containing etch layer.

14. The method of claim 1, wherein steps a, b, and c are performed in-situ in a process chamber on a substrate support.

15. An apparatus for processing a plurality of stacks, comprising: a process chamber;a substrate support for supporting a substrate inside the processing chamber; an RF power source for providing RF power in the processing chamber; a gas source, comprising an etch gas source; and a deposition gas source; and a controller, controllably connected to the RF power source and the gas source, configured to: a) cause a substrate to be loaded on the substrate support; b) cause an etch gas to be provided from the etch gas source; c) cause a plasma to be generated from the etch gas in order to etch narrower features and wider features in an etch layer on the substrate; d) cause a deposition gas to be provided from the deposition gas source; e) cause a plasma to be generated from the deposition gas in order to deposit a deposition over the etch layer, wherein the deposition closes the narrower features but does not close the wider features; f) cause an over etch gas to be provided from the etch gas source; g) cause a plasma to be generated from the over etch gas to reduce a taper of the wider features without reducing a taper of the narrower features; and h) cause the substrate to be removed from the substrate support.

16. The apparatus of claim 15, wherein the gas source further comprises a removal gas source and wherein the controller is further configured to: cause a removal gas to be provided from the removal gas source after step g and before step h; and cause a plasma to be generated from the removal gas to remove the deposition.

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