System unit, system, and control method

Abstract

The present application relates to the technical field of storage, and discloses a system unit, a system, and a control method. The system comprises a system unit and a storage system. The system unit sends an identifier for indicating a peak power capability supported by the system unit to a storage controller of the storage system by configuring a first interface. After receiving the identifier by means of a second interface, the storage controller determines a peak power management strategy on the basis of the identifier, and processes an I / O request on the basis of the determined peak power management strategy. By using the present application, the storage controller of the storage system can sense the peak power capability supported by the system unit, and then can determine the peak power management strategy on the basis of the sensed peak power capability, so that the storage performance of the storage system can be fully exerted.

Description

Host, system and control method Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a host, a system, and a control method. Background Art

[0002] The hardware systems of some devices (such as mobile phones and tablets) may include a host and a storage system. The host can power the storage system, and the maximum power it can supply is called peak power.

[0003] To ensure the normal operation of the power management unit and the storage system, it is generally required that the operating power of the storage system does not exceed the peak power supported by the host.

[0004] However, the peak power supported by hosts on the market is not uniform, so storage manufacturers generally limit the operating power of storage systems so that the storage systems they provide can adapt to more hosts on the market.

[0005] Summary of the Invention

[0006] The present invention provides a host, system, and control method. The system includes a storage system that can sense the peak power capability supported by the host and determine an appropriate peak power management strategy based on the sensed peak power capability, thereby fully utilizing the storage performance of the storage system. The technical solution is as follows:

[0007] In a first aspect, a system is provided, including a host and a storage system, wherein the host is configured with a first interface, the storage system includes a storage controller, and the storage controller is configured with a second interface, and the host and the storage system are coupled through the first interface and the second interface to implement information exchange.

[0008] The host is configured to send an identifier indicating the peak power capability supported by the host through a first interface, and the storage controller is configured to receive the identifier through a second interface and determine a peak power management policy according to the received identifier.

[0009] Optionally, the host includes a power management unit, which is used to supply power to the storage system. The above identifier is used to indicate the peak power capability supported by the power management unit.

[0010] Optionally, the above identifier is used to indicate the magnitude of the current that the power management unit can provide to the storage system according to the supported peak power capability.

[0011] Optionally, the current that the power management unit can provide to the storage system according to the supported peak power capability includes Icc and / or Iccq.

[0012] Optionally, a default peak power management policy is set in the storage controller. The storage controller is configured to replace the default peak power management policy with the determined peak power management policy after determining the peak power management policy.

[0013] Optionally, the peak power management policy includes parameters for controlling the operation of the storage system.

[0014] Optionally, the parameters in the peak power management policy include at least one of a clock frequency, a parallelism of the flash memory NAND, and an operation delay of an I / O request.

[0015] Optionally, the storage system is a universal flash storage UFS storage system, and the first interface and the second interface are UFS interfaces.

[0016] Optionally, the above identifier is carried in an extension field of a UFS data packet.

[0017] Optionally, the power management unit is a power management chip PMIC.

[0018] Optionally, the storage controller is further configured to send a response message through the second interface after receiving the identifier, the response message being used to indicate that the storage controller has received the identifier. The host is further configured to receive the response message through the first interface.

[0019] Optionally, the host is further configured to send an I / O request through the first interface. The storage controller is further configured to receive the I / O request through the second interface and control the memory to process the I / O request according to the determined peak power management policy.

[0020] In a second aspect, a host is provided. The host is configured with a first interface. The host is coupled to a second interface of a storage controller in a storage system through the first interface to implement information exchange.

[0021] The host is configured to send an identifier to the second interface of the storage controller through the first interface, where the identifier is used to indicate the peak power capability supported by the host, and receive a response message sent by the storage controller through the first interface, where the response message is used to indicate that the storage controller has received the identifier.

[0022] Optionally, the host includes a power management unit, which is used to supply power to the storage system. The above identifier is used to indicate the peak power capability supported by the power management unit.

[0023] Optionally, the above identifier is used to indicate the magnitude of the current that the power management unit can provide to the storage system according to the supported peak power capability.

[0024] Optionally, the current that the power management unit can provide to the storage system according to the supported peak power capability includes Icc and / or Iccq.

[0025] Optionally, the host is further configured to send an I / O request to the second interface of the storage controller through the first interface.

[0026] Optionally, the storage system is a universal flash storage UFS storage system, the first interface is a UFS interface, and the identifier is carried in an extension field of the UFS data packet.

[0027] Optionally, the power management unit is a power management chip PMIC.

[0028] In a third aspect, a storage system is provided. The storage system includes a storage controller and a memory. The storage controller is configured with a second interface. The storage controller is coupled to the first interface of the host through the second interface to realize information interaction.

[0029] The storage controller is configured to receive, through the second interface, an identifier sent by the host through the first interface and used to indicate the peak power capability supported by the host, and determine a peak power management policy according to the identifier.

[0030] The memory controller is configured to control the memory to process I / O requests according to the determined peak power management policy.

[0031] Optionally, a default peak power management policy is set in the storage controller. The storage controller is configured to replace the default peak power management policy with the determined peak power management policy after determining the peak power management policy.

[0032] Optionally, the peak power management policy includes parameters for controlling the operation of the storage system.

[0033] Optionally, the parameter includes at least one of a clock frequency, a parallelism of the flash memory NAND, and an operation delay of an I / O request.

[0034] Optionally, the storage system is a universal flash storage UFS storage system, the second interface is a UFS interface, and the identifier is carried in an extension field of the UFS data packet.

[0035] Optionally, the storage controller is further configured to send a response message through the second interface after receiving the above identifier, where the response message is used to indicate that the storage controller has received the identifier.

[0036] In a fourth aspect, a system control method is provided. The system includes a host and a storage system, wherein the host is configured with a first interface, and the storage system includes a storage controller configured with a second interface. The host and the storage system are coupled and exchange information via the first interface and the second interface. The control method includes: the host sends an identifier indicating the peak power capability supported by the host via the first interface. The storage controller receives the identifier via the second interface, and determines, based on the identifier, a peak power management policy that matches the peak power capability.

[0037] Optionally, the host includes a power management unit, which is used to supply power to the storage system, and the identifier is used to indicate a peak power capability supported by the power management unit.

[0038] Optionally, the identifier is used to indicate the magnitude of current that the power management unit can provide to the storage system according to the supported peak power capability.

[0039] Optionally, the current that the power management unit can provide to the storage system according to the supported peak power capability includes Icc and / or Iccq.

[0040] Optionally, a default peak power management policy is set in the storage controller. The control method further includes: after determining the peak power management policy, the storage controller replaces the default peak power management policy with the determined peak power management policy.

[0041] Optionally, the peak power management policy includes parameters for controlling the operation of the storage system.

[0042] Optionally, the parameter includes at least one of a clock frequency, a parallelism of the flash memory NAND, and an operation delay of an I / O request.

[0043] Optionally, the storage system is a universal flash storage UFS storage system, and the first interface and the second interface are UFS interfaces.

[0044] Optionally, the identifier is carried in an extension field of the UFS data packet.

[0045] Optionally, the power management unit is a power management chip PMIC.

[0046] Optionally, the control method further includes: after receiving the identifier, the storage controller sends a response message through the second interface, the response message being used to indicate that the storage controller has received the identifier, and the host receives the response message through the first interface.

[0047] Optionally, the control method further includes: the host sending an I / O request through the first interface, the storage controller receiving the I / O request through the second interface, and controlling the memory to process the I / O request according to the determined peak power management policy.

[0048] The beneficial effects of the technical solution provided by the embodiments of the present application are:

[0049] In an embodiment of the present application, after the host and the storage controller of the storage system establish information exchange through an interface, the host can send an identifier corresponding to the supported peak power capability to the storage controller. Based on the received identifier, the storage controller can determine a peak power management policy that matches the peak power capability of the host, and then process I / O requests based on the determined peak power management policy. In this way, the storage controller can adjust the peak power management policy based on the peak power capability of the host, eliminating the need to limit the storage system's storage performance in advance, and enabling the storage system's performance to be fully utilized. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0051] FIG1 is a schematic diagram of an exemplary system provided in an embodiment of the present application;

[0052] FIG2 is a diagram of an exemplary memory card provided in an embodiment of the present application;

[0053] FIG3 is a schematic diagram of an exemplary solid-state drive provided in an embodiment of the present application;

[0054] FIG4 is a schematic diagram of an exemplary system provided in an embodiment of the present application;

[0055] FIG5 is a flow chart of a control method of an exemplary system provided in an embodiment of the present application;

[0056] FIG6 is a flow chart of a control method of an exemplary system provided in an embodiment of the present application;

[0057] FIG7 is a schematic diagram of the structure of an exemplary memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0059] FIG1 shows a block diagram of an exemplary system 100 with a storage system according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. As shown in FIG1 , the system 100 may include a host 108 and a storage system 102, the storage system 102 having one or more memories 104 and a storage controller 106. The host 108 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 can be configured to send data to the memory 104 or receive data from the memory 104.

[0060] The memory 104 may be any memory device disclosed in the present disclosure. Optionally, the memory 104 is a NAND flash memory device, such as a three-dimensional (3D) NAND flash memory device.

[0061] In some embodiments, the storage controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The storage controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the storage controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the storage controller 106 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The storage controller 106 can be configured to control the operations of the memory 104, such as read, erase, and program processes. The storage controller 106 can also be configured to manage various functions related to the data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the storage controller 106 is further configured to process error correction codes (ECC) on data read from or written to the memory 104. The storage controller 106 may also perform any other suitable functions, such as formatting the memory 104. The storage controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the storage controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer miniature interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0062] The storage controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the storage system 102 can be implemented and packaged into different types of terminal electronic products. In one example, as shown in FIG2 , the storage controller 106 and a single memory 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG1 ). In another example, as shown in FIG3 , the storage controller 106 and multiple memories 104 can be integrated into an SSD 306. SSD 306 may also include an SSD connector 308 that couples SSD 306 to a host (eg, host 108 in FIG. 1 ). In some implementations, SSD 306 has a greater storage capacity and / or operating speed than memory card 202.

[0063] In system 100, host 108 can provide power to storage system 102. In one example, as shown in FIG4 , host 108 may include a PMU (Power Management Unit) 402. PMU 402 can provide power to memory 104 and storage controller 106, respectively. PMU 402 provides a voltage of Vcc and a current of Icc to memory 104, and a voltage of Vccq and a current of Iccq to storage controller 106. The maximum power supplied by PMU 402 to memory 104 is referred to as peak power. During operation, storage system 102 must ensure that the power it requires does not exceed the peak power supported by the host (or PMU).

[0064] In some embodiments, the peak power supported by hosts 108 provided by different host manufacturers is not uniform. Therefore, to improve the adaptability of storage system 102, storage manufacturers generally limit the operating power of storage system 102 to below the peak power supported by most hosts 108 on the market. In one example, peak power can be represented by the corresponding peak current. If the peak power supported by hosts 108 on the market may include 800mA, 1A, and 1.2A, the storage manufacturer may limit the operating power of storage system 102 to below 800mA.

[0065] The operating power of the storage system 102 is directly related to the storage performance of the storage system 102. Limiting the operating power is also achieved by limiting the storage performance of the storage system 102. For example, limiting the read and write rates of the storage system 102 can be used to limit the operating power of the storage system 102. This improves the adaptability of the storage system 102. However, if the host 108 in the system 100 can support a higher peak power, the storage system 102 may not be able to fully demonstrate its storage performance.

[0066] An embodiment of the present application provides a system control method, which may be system 100 shown in FIG1 , including a host and a storage system. In this system, the storage system can sense the peak power of the host and then adjust the peak power management policy based on the sensed peak power to maximize the storage performance of the storage system.

[0067] Figures 5 and 6 are flow charts of a control method for a system provided in an embodiment of the present application. As shown in Figure 5 or 6, in the system provided in an embodiment of the present application, the host is configured with a first interface, and the storage controller of the storage system is configured with a second interface. The host and the storage system can be coupled through the first interface and the second interface to realize information interaction.

[0068] Referring to FIG5 , a system control method provided in an embodiment of the present application includes:

[0069] Step 501: The host sends an identifier indicating the peak power capability supported by the host through a first interface.

[0070] In an implementation, the host may store an identifier indicating the supported peak power capability, and the host may send the identifier to the second interface of the storage controller through the configured first interface.

[0071] Step 502: The storage controller receives an identifier through the second interface.

[0072] Step 503: The storage controller determines a peak power management policy that matches the peak power capability according to the identifier.

[0073] The peak power management policy can be used to control the operating power of the storage system. In one example, the peak power management policy is used to limit the write rate of the memory to achieve the effect of controlling the operating power of the storage system.

[0074] In implementation, after receiving the identifier sent by the host, the second interface configured by the storage controller can determine the peak power management policy corresponding to the received identifier in the correspondence between the stored identifier and the peak power management policy, and then the determined peak power management policy can be used as the peak power management policy adopted during the operation of the storage system.

[0075] In the above correspondence, the peak power management policy corresponding to an identifier matches the peak power capability indicated by the identifier. For example, if the identifier "1h" indicates that the host supports a peak power of 650mA, then when the storage system applies the peak power management policy corresponding to "1h", the peak current generated can be less than and close to (or equal to) 650mA. If the identifier "2h" indicates that the host supports a peak power of 800mA, then when the storage system applies the peak power management policy corresponding to "2h", the peak current generated can be less than and close to (or equal to) 800mA.

[0076] In the control method of the system provided in the embodiments of the present application, a host can send the peak power capabilities supported by the host to the storage system. The storage controller in the storage system can dynamically match and apply the appropriate peak power management policy based on the peak power capabilities supported by the host. This embodiment of the present application avoids the storage system setting a peak power management policy with lower storage performance to match the majority of hosts, and enables the storage system to fully utilize storage performance when working with a variety of hosts.

[0077] As shown in Figure 6, after power-on, the host in the system can send an initialization instruction to the second interface of the storage controller through the first interface. After receiving the initialization instruction, the storage controller can perform initialization operations and send an RSP (response message) to the host through the second interface. After the host initially receives the RSP of the storage system through the first interface, it can again send an identifier indicating the peak power capability supported by the host to the storage controller through the first interface. After the storage controller receives the identifier indicating the peak power capability supported by the host through the second interface, it can determine and apply the peak power management policy corresponding to the received identifier based on the stored correspondence. After receiving the identifier, the storage controller can also send an RSP to the host again through the second interface. The RSP sent again is used to indicate the identifier sent by the host received by the storage controller.

[0078] Continuing to refer to Figure 6, after the host receives the RSP sent by the storage controller for the second time through the first interface, and when there is an I / O (Input / Output) request to be processed in the host, the host can send an I / O request to the storage controller through the first interface. After the storage controller receives the I / O request through the second interface, it can control the memory to process the I / O request according to the determined peak power management policy. In this way, the storage system can process the I / O request according to the peak power management policy that matches the peak power capability of the host, and can fully exert the storage performance under the premise that the operating power of the storage system does not exceed the peak power of the host. And because the storage system can flexibly adjust the matching peak power management policy according to the peak power of the host, the storage system provided in the embodiment of the present application has higher adaptability than some implementation methods.

[0079] In the system shown in FIG4 , the host can supply power to the storage system through the PMU. The PMU can be a control chip integrated in the host controller of the host, or a control chip independent of the host controller. In one example, the PMU can be a power management integrated circuit (PMIC) independent of the host controller. Accordingly, the identifier used to indicate the peak power capability supported by the host in the above embodiment can be used to indicate the peak power capability supported by the PMU. Since the operating voltage provided by the PMU to the storage controller and memory is relatively stable during the operation of the storage system, the current provided by the PMU to the storage controller and memory can reflect the peak power capability of the PMU. Therefore, the identifier indicating the peak power capability of the PMU can also be used to indicate the amount of current that the PMU can provide to the storage system according to the supported peak power capability.

[0080] In one example, the peak power management strategy includes controlling at least one parameter for storage system operation. This at least one parameter can be used to control the write rate of the memory in the storage system, thereby controlling the operating power of the storage system so that the operating power of the storage system is less than and close to (or equal to) the peak power supported by the host. Table 1 shows the relationship between the peak power capability supported by the host and the write rate of the memory, where the memory cells in the memory can be triple-level cells (TLC).

[0081] Table 1

[0082] As shown in Table 1, when the host supports a peak power capacity of 800 mA, the parameters in the peak power management policy can be used to control the memory write rate to 650 MB / s, thereby ensuring that the operating power of the storage system does not exceed the peak power supported by the host.

[0083] In one example, at least one parameter included in the peak power management strategy may be the clock frequency of the storage system, the parallelism of the flash memory NAND, the operation delay of the I / O request, etc. Among them, the clock frequency refers to the clock frequency used by the storage system during operation. Generally, the higher the clock frequency, the higher the write rate, and the corresponding storage system's operating power consumption is greater. The parallelism of NAND refers to the number of NAND cells performing write operations at the same time. Generally, the higher the parallelism, the higher the write rate, and the corresponding storage system's operating power consumption is greater. The operation delay of the I / O request refers to the time interval for the storage controller to process adjacent I / O requests. Generally, the shorter the operation delay, the higher the write rate, and the corresponding storage system's operating power consumption is higher.

[0084] In the aforementioned correspondence between identifiers and peak power management policies, the specific values ​​of the parameters included in the peak power management policy corresponding to each identifier can be configured by a technician. For example, the write rate required to meet the peak power capability can be used as input to the configuration algorithm, which then outputs the specific values ​​of the aforementioned parameters. The specific processing of the configuration algorithm is known in the art and will not be described in detail in the present embodiments.

[0085] In practice, upon receiving an identifier indicating peak power capability from a host, the storage controller can determine the peak power management policy corresponding to the received identifier from a pre-stored correspondence, and then set the values ​​of the storage system's operating parameters to those included in the peak power management policy. This allows the memory's write rate to be adjusted based on the host's supported peak power capability, thereby fully utilizing the memory's storage performance while ensuring the storage system's operating power does not exceed the host's supported peak power.

[0086] Since the memory consumes a lot of power when performing a write operation, controlling the write rate can be used to control the operating power of the storage system. However, in the embodiments of the present application, controlling the operating power of the storage system is not limited to controlling the write rate alone. Similarly, in the embodiments of the present application, the erase rate and read rate of the memory can be controlled by adjusting the above parameters, thereby further controlling the operating power of the storage system.

[0087] In one example, the storage system provided in an embodiment of the present application may be a UFS storage system. The host and the storage system may communicate according to the UFS protocol. Accordingly, the first interface of the host and the second interface of the storage controller may both be UFS interfaces.

[0088] In the embodiments of the present application, the memory in the UFS storage system may be referred to as a UFS memory, and the storage controller in the UFS storage system may be referred to as a UFS storage controller. The PMU may power the UFS memory and the UFS storage controller separately. The voltage Vcc and current Icc provided by the PMU to the UFS memory, and the voltage Vccq and current Iccq provided by the PMU to the UFS storage controller, respectively. Because the Vcc and Vccq provided by the PMU to the UFS storage system are relatively stable, the identifier for the host's peak power capability may be divided into two types, indicating the magnitude of Icc and Iccq provided by the host to the UFS storage system, respectively, at the peak power capability.

[0089] When the host sends an identifier indicating the size of Icc and Iccq to the UFS storage controller via the UFS interface, the identifier can be carried in the UFS data packet. Furthermore, the identifier can be added to the extension field of the UFS data packet. Table 2 shows the information added to the extension field of the UFS data packet for Icc and Iccq.

[0090] Table 2

[0091] Among them, "Size" indicates the number of bits occupied by the identifier indicating the size of Iccq or Icc in the extension field. "Name" indicates the name of the bits occupied by the identifier in the extension field. "Value" indicates the numeric type of the identifier. As shown in Table 2, the above identifier can be a hexadecimal value. "User Conf." indicates that the extension field needs to be pre-configured by a technician. "Description" shows the host peak power capability indicated by the identifier corresponding to Iccq or Icc when it takes different values.

[0092] In one example, when a host sends a UFS data packet to a UFS storage controller, it may only carry the identifier corresponding to Icc. Accordingly, the corresponding relationship of the UFS storage controller may store the corresponding relationship between different Icc identifiers and peak power management policies. In another example, when a host sends a UFS data packet to a UFS storage controller, it may only carry the identifiers corresponding to Icc and Iccq. Accordingly, the corresponding relationship of the UFS storage controller may store the corresponding relationship between different Icc and Iccq identifiers and peak power management policies.

[0093] In one example, a default peak power management policy is configured in the storage controller. This default peak power management policy can control the operating power of the storage system to meet the peak power capabilities supported by most hosts on the market. For example, the default peak power management policy can control the operating power of the storage system to meet the peak power capabilities supported by more than a preset number of hosts.

[0094] In this way, even if the host is unable to send an identifier indicating peak power capabilities to the storage controller, the storage controller can still control the operation of the storage system using the default peak power management policy. Furthermore, even if the storage controller is unable to match the peak power management policy based on the identifier sent by the host, the host sending the identifier to the storage controller will not affect the normal operation of the storage controller.

[0095] The present application also provides a host, which may be the host shown in Figures 1, 4 to 6. The host is configured with a first interface, through which the host is coupled to a second interface of a storage controller in a storage system and implements information exchange.

[0096] The host is configured to send an identifier to the second interface of the storage controller through the first interface, where the identifier is used to indicate the peak power capability supported by the host, and receive a response message sent by the storage controller through the first interface, where the response message is used to indicate that the storage controller has received the identifier.

[0097] Optionally, the host includes a power management unit, which is used to supply power to the storage system, and the identifier is used to indicate a peak power capability supported by the power management unit.

[0098] Optionally, the identifier is used to indicate the magnitude of current that the power management unit can provide to the storage system according to the supported peak power capability.

[0099] Optionally, the current that the power management unit can provide to the storage system according to the supported peak power capability includes Icc and / or Iccq.

[0100] Optionally, the host is further configured to send an I / O request to the second interface of the storage controller through the first interface.

[0101] Optionally, the storage system is a UFS storage system, the first interface is a UFS interface, and the identifier is carried in an extension field of a UFS data packet.

[0102] Optionally, the power management unit is a power management chip PMIC.

[0103] The host provided in the embodiments of the present application can execute the method steps performed by the host in the control method provided in the embodiments of the present application. For details, please refer to the contents of the above embodiments and will not be repeated here. The host provided in the embodiments of the present application can actively send the peak power capability supported by the host to the storage system, so that the storage system can adjust the peak power management policy of the storage system according to the peak power capability supported by the host to fully utilize the storage performance of the storage system.

[0104] The present application also provides a storage system, which may be the storage system shown in Figures 1 to 4. The storage system includes a storage controller and a memory, wherein the storage controller is configured with a second interface, and the storage controller is coupled to the first interface of the host through the second interface to implement information exchange.

[0105] The storage controller is configured to receive, through the second interface, an identifier sent by the host through the first interface and used to indicate the peak power capability supported by the host, and determine a peak power management policy according to the identifier;

[0106] The memory controller is configured to control the memory to process I / O requests according to the determined peak power management policy.

[0107] Optionally, a default peak power management policy is set in the storage controller;

[0108] The storage controller is configured to replace a default peak power management policy with the determined peak power management policy after determining the peak power management policy.

[0109] Optionally, the peak power management policy includes parameters for controlling the operation of the storage system.

[0110] Optionally, the parameter includes at least one of a clock frequency, a parallelism of the flash memory NAND, and an operation delay of an I / O request.

[0111] Optionally, the storage system is a universal flash storage UFS storage system, the second interface is a UFS interface, and the identifier is carried in an extension field of the UFS data packet.

[0112] Optionally, the storage controller is further configured to send a response message through the second interface after receiving the identifier, where the response message is used to indicate that the storage controller has received the identifier.

[0113] The storage system provided in the embodiments of the present application can execute the method steps performed by the storage system in the control method provided in the embodiments of the present application. For details, please refer to the contents of the above embodiments and will not be repeated here. The storage system provided in the embodiments of the present application can receive an identifier indicating the peak power capability of the host and then, based on the identifier, determine and apply the peak power management policy of the storage system, thereby fully utilizing the storage performance of the storage system.

[0114] An embodiment of the present application further provides a system, which may be the system 100 shown in FIG. 1 . The system includes a host and a storage system, wherein the host is configured with a first interface, the storage system includes a storage controller, and the storage controller is configured with a second interface. The host and the storage system are coupled through the first interface and the second interface to implement information exchange; wherein,

[0115] The host is configured to send, through the first interface, an identifier indicating a peak power capability supported by the host.

[0116] The storage controller is configured to receive the identifier through the second interface and determine a peak power management policy according to the identifier.

[0117] Optionally, the host includes a power management unit, which is used to supply power to the storage system, and the identifier is used to indicate a peak power capability supported by the power management unit.

[0118] Optionally, the identifier is used to indicate the magnitude of current that the power management unit can provide to the storage system according to the supported peak power capability.

[0119] Optionally, the current that the power management unit can provide to the storage system according to the supported peak power capability includes Icc and / or Iccq.

[0120] Optionally, a default peak power management policy is set in the storage controller. The storage controller is configured to replace the default peak power management policy with the determined peak power management policy after determining the peak power management policy.

[0121] Optionally, the peak power management policy includes parameters for controlling the operation of the storage system.

[0122] Optionally, the parameter includes at least one of a clock frequency, a parallelism of the flash memory NAND, and an operation delay of an I / O request.

[0123] Optionally, the storage system is a universal flash storage UFS storage system, and the first interface and the second interface are UFS interfaces.

[0124] Optionally, the identifier is carried in an extension field of the UFS data packet.

[0125] Optionally, the power management unit is a power management chip PMIC.

[0126] Optionally, the storage controller is further configured to send a response message through the second interface after receiving the identifier, the response message being used to indicate that the storage controller has received the identifier. The host is further configured to receive the response message through the first interface.

[0127] Optionally, the host is further configured to send an I / O request through the first interface. The storage controller is further configured to receive the I / O request through the second interface and control the memory to process the I / O request according to the determined peak power management policy.

[0128] The system provided by the embodiment of the present application includes a host and a storage system, which can implement the control method of the system in the above embodiment. For details, please refer to the contents of the above embodiment, which will not be repeated here. In the system provided by the embodiment of the present application, the host can send an identifier corresponding to the supported peak power capability to the storage controller. The storage controller can determine the peak power management policy that matches the peak power capability of the host based on the received identifier, and then process the I / O request according to the determined peak power management policy. In this way, the storage controller can adjust the peak power management policy according to the peak power capability of the host, without limiting the storage performance of the storage system in advance, and can fully utilize the performance of the storage system.

[0129] 7 shows a schematic circuit diagram of an exemplary memory 700 including peripheral circuits according to some aspects of the present disclosure. The memory 700 may be a memory included in the memory system in the above embodiments, such as the memory shown in FIG1 to FIG5.

[0130] The memory 700 may include a memory cell array device 701 and a peripheral circuit 702 coupled to the memory cell array device 701. The memory cell array device 701 may be a NAND flash memory cell array, wherein memory cells 706 are provided in the form of an array of NAND memory strings 708, each NAND memory string 708 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 708 includes a plurality of memory cells 706 coupled in series and stacked vertically. Each memory cell 706 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped within the region of the memory cell 706. Each memory cell 706 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0131] In some embodiments, each memory cell 706 is a single-level cell (SLC) that has two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 706 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than or equal to four storage states. For example, the MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erased state to assume one of three possible storage states by writing one of the three possible nominal storage values ​​to the cell, with a fourth nominal storage value available for the erased state.

[0132] As shown in FIG7 , each NAND string 708 may include a source select gate (SSG) 710 at its source terminal and a drain select gate (DSG) 712 at its drain terminal. The SSG 710 and DSG 712 may be configured to activate a selected NAND string 708 (column of the array) during read and program processes. In some embodiments, the sources of the NAND strings 708 in the same block 704 are coupled via the same source line (SL) 714 (e.g., a common SL). In other words, according to some embodiments, all NAND strings 708 in the same block 704 have an array common source (ACS). According to some embodiments, the DSG 712 of each NAND string 708 is coupled to a corresponding bit line 716, from which data may be read or written via an output bus (not shown). In some embodiments, each NAND memory string 708 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having DSG 712) or a deselect voltage (e.g., 0V) to the corresponding DSG 712 via one or more DSG lines 713 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having SSG 710) or a deselect voltage (e.g., 0V) to the corresponding SSG 710 via one or more SSG lines 715.

[0133] As shown in FIG7 , a memory cell array device 701 includes a plurality of blocks 704, each block 704 including a plurality of NAND memory strings 708. Each of the plurality of blocks 704 may have a common source line 714 (e.g., coupled to ground). In some embodiments, each block 704 is a basic data unit for an erase operation, i.e., all memory cells 706 on the same block 704 are erased simultaneously. To erase the memory cells 706 in a selected block 704 a, the source lines 714 coupled to the selected block 704 a and to unselected blocks 704 b in the same plane as the selected block 704 a may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20 V or higher)). It should be understood that in some examples, the erase operation may be performed at a half-block level, at a quarter-block level, or at a level having any suitable number of blocks or any suitable fraction of a block. The memory cells 706 of adjacent NAND memory strings 708 can be coupled by word lines 718, which select which row of memory cells 706 is affected by read and programming processes. In some embodiments, each word line 718 is coupled to multiple memory cells 706. Each word line 718 can include multiple control gates (gate electrodes) at each memory cell 706 in a corresponding page 720 and a gate line coupling the control gates.

[0134] In an embodiment of the present application, a peak power management strategy that matches the peak power capabilities supported by different hosts can be set according to the specific type of storage unit included in the memory, so that the power of the memory during operation does not exceed the peak power of the power supply host.

[0135] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" refers to one or more, and the term "plurality" refers to two or more, unless otherwise clearly defined.

[0136] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

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