Register configuration system and method, and electronic device

Abstract

The present application relates to the technical field of computers. Provided are a register configuration system and method, and an electronic device. The register configuration system comprises: a display processor, a memory and a hardware automatic control unit, wherein the display processor comprises a plurality of registers; at least one configuration instruction is pre-stored in the memory, and the configuration instruction is used for indicating a target register which is in the display processor and which is required to be configured; and the hardware automatic control unit is connected to a register configuration interface of the display processor, and the hardware automatic control unit is used for receiving a start instruction, on the basis of the start instruction, acquiring the configuration instruction from the memory and parsing the configuration instruction, and on the basis of the parsed configuration instruction, configuring the target register in the display processor, the start instruction comprising a storage address of the configuration instruction. A register is configured by means of a hardware automatic control unit, replacing a traditional mode in which a register is configured by using a CPU, thereby minimizing the configuration bandwidth burden on a CPU.

Description

Register configuration system, method and electronic device Technical Field

[0001] The present application relates to the technical field of computers, and in particular to a register configuration system, method, and electronic device. Background Art

[0002] With the growing demand for high-definition displays, the entire algorithm unit of the display processor (DPU) and its internal processing flow are becoming increasingly complex. Consequently, various control processes are also becoming increasingly complex. At the same time, the number of registers that software needs to configure has increased significantly, and the interaction between software and hardware has become more frequent. These new problems make it more difficult and impractical to rely solely on traditional CPU (Central Processing Unit) control methods to handle various control and configuration processes. In other words, this operating method no longer meets actual performance requirements.

[0003] Summary of the Invention

[0004] The present application provides a register configuration system, method and electronic device to solve the problem in the prior art that various control and configuration processes relying on traditional CPU control methods are difficult to meet actual performance requirements.

[0005] In a first aspect, the present application provides a register configuration system, comprising: a display processor, a memory, and a hardware automatic control unit, wherein the display processor includes multiple registers; at least one configuration instruction is pre-stored in the memory, and the configuration instruction is used to indicate a target register in the display processor that needs to be configured; the hardware automatic control unit is connected to the register configuration interface of the display processor, and the hardware automatic control unit is used to receive a startup instruction, and obtain and parse the configuration instruction from the memory based on the startup instruction, and configure the target register in the display processor based on the parsed configuration instruction, wherein the startup instruction includes the storage address of the configuration instruction.

[0006] In the embodiment of the present application, register configuration is performed by a hardware automatic control unit, replacing the traditional method of using the CPU to configure registers, thereby reducing the configuration bandwidth burden of the CPU to the greatest extent. Even if the number of registers that need to be configured increases, the configuration of the registers can be achieved through this solution, realizing the optimization requirements of the display processing flow.

[0007] In combination with the technical solution provided in the first aspect above, in some possible implementations, the hardware automatic control unit is also connected to the interactive interface of each data path of the display processor; wherein different data paths include different registers; the hardware automatic control unit is also used to send a configuration instruction to the data path indicating the start of configuring the target register, and to receive a configuration status signal fed back by the data path, wherein the configuration status signal indicates whether all registers included in the data path have been configured.

[0008] In an embodiment of the present application, the hardware automatic control unit can clearly display the register configuration status of each data path of the processor by interacting with data of each data path of the display processor, thereby facilitating the hardware automatic control unit to determine whether there are still data paths that require register configuration.

[0009] In combination with the technical solution provided in the first aspect above, in some possible implementations, the display processor includes multiple data paths, and the hardware automatic control unit is further used to record the configuration status of the register included in each data path based on the configuration status signal fed back by each data path; the configuration status indicates whether the register has completed configuration.

[0010] In the embodiment of the present application, the hardware automatic control unit records the configuration status of the registers included in each data path, thereby facilitating the subsequent determination of which data path registers still need to be configured.

[0011] In combination with the technical solution provided in the first aspect above, in some possible implementations, the register configuration system further includes: a central processing unit, the central processing unit is connected to the hardware automatic control unit, and the central processing unit is used to send the startup instruction to the hardware automatic control unit.

[0012] In combination with the technical solution provided in the first aspect above, in some possible implementations, the hardware automatic control unit is also used to send its own internal state to the central processing unit; the central processing unit determines whether the hardware automatic control unit is abnormal based on the received state of the hardware automatic control unit, and if the hardware automatic control unit is abnormal, sends an interrupt instruction to the hardware automatic control unit, and the interrupt instruction is used to instruct the hardware automatic control unit to stop working.

[0013] In the embodiment of the present application, the central processing unit monitors the internal state of the hardware automatic control unit, so that if the hardware automatic control unit fails, an interrupt instruction can be sent to the hardware automatic control unit to stop the hardware automatic control unit. This prevents register configuration errors caused by hardware automatic control unit failures and improves the reliability of the register configuration system.

[0014] In combination with the technical solution provided in the first aspect above, in some possible implementations, the configuration instruction includes the instruction type, the number of target registers with consecutive addresses, the offset address of the first target register, the instruction body, and the instruction end flag.

[0015] In combination with the technical solution provided in the first aspect above, in some possible implementations, the instruction text records the calculation method of the actual configuration address of each target register; the hardware automatic control unit is specifically used to parse the configuration instruction according to the instruction type to obtain the number of target registers, the offset address of the first target register, the instruction text, and the instruction end flag; based on the number of target registers with continuous addresses, the offset address of the first target register and the calculation method in the instruction text, determine the actual configuration address of each target register; and configure each target register based on the actual configuration address of each target register.

[0016] In an embodiment of the present application, since the instruction text records the calculation method of the actual configuration address of each target register, combined with the number of target registers with consecutive addresses and the offset address of the first target register, the address of the target register to be configured can be calculated, thereby realizing the configuration of multiple registers through one instruction, reducing the number of configuration instructions that need to be sent, and thus improving configuration efficiency.

[0017] In combination with the technical solution provided in the first aspect above, in some possible implementations, the instruction text also records a method for calculating the total number of target registers with consecutive addresses; the hardware automatic control unit is specifically used to determine the total number of target registers with consecutive addresses based on the number of target registers with consecutive addresses and the method for calculating the total number of target registers; and determine the actual configuration address of each target register based on the total number of target registers with consecutive addresses, the offset address of the first target register and the instruction text.

[0018] In the embodiment of the present application, since the length of the field used to record the number of target registers with consecutive addresses in the configuration instruction is limited, if the number of target registers with consecutive addresses is large, the method for calculating the total number of target registers with consecutive addresses can be recorded in the instruction body, thereby calculating the total number of target registers with consecutive addresses. There is no need to split it into multiple configuration instructions, which reduces the number of configuration instructions that need to be sent, thereby improving configuration efficiency.

[0019] In a second aspect, the present application provides a register configuration method, which is applied to the hardware automatic control unit in the register configuration system described in the first aspect above and / or in combination with any possible implementation of the first aspect above, the method comprising: receiving a startup instruction; obtaining and parsing the configuration instruction from the memory based on the startup instruction; and configuring the target register in the display processor based on the parsed configuration instruction.

[0020] In a third aspect, the present application provides an electronic device, comprising: the register configuration system described in the first aspect and / or in combination with any possible implementation of the first aspect.

[0021] The beneficial effect of this application is that the display processor registers are configured through a hardware automatic control unit, replacing the traditional method of using the CPU to configure registers, thereby minimizing the CPU's configuration bandwidth burden. Even if the number of registers to be configured increases, the register configuration can be achieved through this solution, achieving the optimization requirements of the display processing flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0023] FIG1 is a structural block diagram of a first register configuration system shown in an embodiment of the present application;

[0024] FIG2 is a schematic structural diagram of a hardware automatic control unit connected to a display processor according to an embodiment of the present application;

[0025] FIG3 is a schematic diagram of an instruction end mark shown in an embodiment of the present application;

[0026] FIG4 is a schematic diagram of the structure of a first configuration instruction shown in an embodiment of the present application;

[0027] FIG5 is a schematic diagram of the structure of a second configuration instruction shown in an embodiment of the present application;

[0028] FIG6 is a schematic diagram of the structure of a third configuration instruction shown in an embodiment of the present application;

[0029] FIG7 is a schematic diagram of the structure of a fourth configuration instruction shown in an embodiment of the present application;

[0030] FIG8 is a structural block diagram of a second register configuration system shown in an embodiment of the present application;

[0031] FIG9 is a flow chart of a register configuration method according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0033] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0034] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0035] Please refer to FIG. 1 , which is a schematic structural diagram of a register configuration system 100 according to an embodiment of the present application. The register configuration system 100 includes a display processor 110 , a memory 130 , and a hardware automatic control unit 120 .

[0036] The display processor 110 includes a plurality of registers.

[0037] Optionally, the display processor 110 includes at least one data path. When the display processor 110 includes multiple data paths, different data paths include different registers.

[0038] The display processor 110 may be any existing type of display processor 110 , and the specific type of the display processor 110 is not limited herein.

[0039] At least one configuration instruction is pre-stored in the memory 130 , and the configuration instruction is used to indicate a target register that needs to be configured in the display processor 110 .

[0040] The memory 130 may be any existing type of memory 130, such as a USB flash drive, a mobile hard disk, a read-only memory 130 (ROM), a random access memory 130 (RAM), a magnetic disk, or an optical disk, or any other medium capable of storing program code. The specific type of the memory 130 is not limited herein.

[0041] The hardware automatic control unit 120 is connected to the register configuration interface of the display processor 110. The hardware automatic control unit 120 is used to receive a startup instruction, and obtain and parse the configuration instruction from the memory 130 based on the startup instruction, and configure the target register in the display processor 110 based on the parsed configuration instruction, wherein the startup instruction includes the storage address of the configuration instruction.

[0042] The hardware automatic control unit 120 may be a PDMA (Programming Direct Memory Access), but is not limited thereto.

[0043] In one implementation, the specific connection between the hardware automatic control unit 120 and the display processor is shown in FIG2 .

[0044] The hardware automatic control unit 120 is connected to the pre-processor (pre-processor shown in FIG2 ), crossbar (crossbar shown in FIG2 ), post-processor (post-processor shown in FIG2 ), and output interface (output interface shown in FIG2 ) of the display processor 110. The hardware automatic control unit 120 configures the registers of the display processor 110 by sending instructions to at least one of the pre-processor, crossbar, post-processor, and output interface. The hardware automatic control unit 120 obtains startup instructions and configuration instructions via a bus interface (BUS interface shown in FIG2 ).

[0045] Compared with the existing technology, which requires the CPU to send instructions to the display processor, and then the display processor distributes the instructions sent by the CPU to the pre-processor, cross-switch matrix, post-processor, and output interface to configure the registers of the display processor, this solution does not require the display processor to perform data distribution operations, thereby improving the configuration efficiency of the registers.

[0046] Optionally, the hardware automatic control unit 120 may be independently provided, or the hardware automatic control unit 120 may be provided inside the display processor 110 .

[0047] In one embodiment, the configuration instruction includes a register address, so that the hardware automatic control unit 120 can subsequently determine and configure a target register according to the register address.

[0048] In order to facilitate the hardware automatic control unit 120 to parse the configuration instruction, the configuration instruction may optionally further include an instruction type.

[0049] Among them, the instruction type can be a type that represents a configuration instruction, such as a 16-bit instruction, a 32-bit instruction, etc. The examples here are only for ease of understanding and should not be regarded as limitations on this application.

[0050] In one implementation, multiple configuration instructions may be stored in the memory 130 in the form of an instruction list. In this case, in order to distinguish different configuration instructions, the configuration instruction further includes an instruction end flag.

[0051] The instruction end mark is usually located at the end of a configuration instruction. After reading the instruction end mark, it can be confirmed that the entire content of the current configuration instruction has been read.

[0052] The instruction end flag may be a character string or a binary code, and the specific implementation method of the instruction end flag is not limited here.

[0053] Optionally, in some special applications, multiple different display areas may need to be activated multiple times within a single frame. Since this operation is highly time-sensitive, the hardware automatic control unit 120 needs to automatically trigger and fully automate the multiple activations through handshake interactions with the different hardware blocks of the display processor 110. Therefore, a flag indicating the end of the configuration data for this image area can be set in the command end flag.

[0054] After reading the flag indicating that the configuration data of the current image area has ended, the hardware automatic control unit 120 can automatically jump to the offset position of the next image area according to the flag, and then control the parsing, configuration and execution of the next configuration instruction.

[0055] For ease of understanding, one implementation of the instruction end flag is shown in Figure 3. The Next section size indicates the size of the next image area, and the Next section address offset indicates the offset address of the next image area. After reading the Next section size and Next section address offset, the offset position of the next image area can be determined and jumped to.

[0056] The LSB (Least Significant Bit) is the least significant bit in a binary number. The MSB (Most Significant Bit) is the most significant bit in a binary number. Generally speaking, the MSB is located on the leftmost side of a binary number, and the LSB is located on the rightmost side.

[0057] The examples here are only for ease of understanding and should not be construed as limiting this application.

[0058] Optionally, other data beyond the instruction end mark can be regarded as invalid data.

[0059] In order to reduce the number of configuration instructions, in one implementation, the register address in the configuration instruction can be represented by the number of target registers with consecutive addresses, the offset address of the first target register, and the instruction body.

[0060] Optionally, in addition to representing the register address, the instruction text may also store other content, such as register configuration commands, register quantity, etc. The content included in the instruction text is not limited here.

[0061] Optionally, the instruction text may record a calculation method for the actual configuration address of each target register.

[0062] In one implementation, the configuration instruction includes an instruction type, the number of target registers with consecutive addresses, an offset address of the first target register, an instruction body, and an instruction end flag.

[0063] Among them, the specific functions and principles of the instruction type, the number of target registers with consecutive addresses, the offset address of the first target register, the instruction body, and the instruction end flag are the same as those recorded above and are not repeated here for the sake of brief description.

[0064] The structure of the configuration instruction is shown in Figure 4. Instruction is the instruction type, Length is the number of target registers with consecutive addresses, Address is the offset address of the first target register, Configure data is the instruction body, End of frame flag is the instruction end flag, and Invalid data is invalid data.

[0065] Optionally, when the instruction body contains a calculation method for the actual configuration address of each target register, the hardware automatic control unit 120 is specifically configured to parse the configuration instruction according to the instruction type to obtain the number of target registers, the offset address of the first target register, the instruction body, and the instruction end flag. The actual configuration address of each target register is then determined based on the number of target registers with consecutive addresses, the offset address of the first target register, and the calculation method in the instruction body; and each target register is configured based on the actual configuration address of each target register.

[0066] To facilitate understanding of the specific process of the hardware automatic control unit 120 determining the target register address according to the configuration instruction, the configuration instruction shown in FIG. 5 is taken as an example for description.

[0067] As shown in Figure 5, Length = 3 indicates that there are three consecutive target registers with consecutive addresses. Address is the offset address of the first target register. The instruction body contains "Register offset base on Address," which represents the offset of these three consecutive registers based on the offset address of the first target register. Therefore, the actual offset of the first target register is Address + Register offset base on Address. The actual configuration address of the first target register is then calculated by adding the preset base address and the actual offset of the first target register.

[0068] Since the three target registers are consecutive, the actual configuration address of the second target register can be obtained by adding 1 to the actual configuration address of the first target register. The actual configuration address of the third target register can be obtained by adding 2 to the actual configuration address of the first target register.

[0069] The examples here are only for ease of understanding and should not be construed as limiting this application.

[0070] Since the length of the field for recording the number of target registers with consecutive addresses in the configuration instruction is limited, when there are too many consecutive target registers, the field for recording the number of target registers with consecutive addresses in the configuration instruction may not be able to fully represent them.

[0071] In this case, the instruction body may also include a calculation method for the total number of consecutively addressed target registers. Accordingly, the hardware automatic control unit 120 is specifically configured to determine the total number of consecutively addressed target registers based on the number of consecutively addressed target registers and the calculation method for the total number of target registers; and to determine the actual configuration address of each target register based on the total number of consecutively addressed target registers, the offset address of the first target register, and the instruction body.

[0072] Among them, the calculation method based on the number of target registers with consecutive addresses and the total number of target registers can be to record the second number of target registers with consecutive addresses in the instruction text, and then add the second number of target registers with consecutive addresses to the number of target registers with consecutive addresses recorded in the configuration instruction to obtain the total number of target registers with consecutive addresses.

[0073] For ease of understanding, the configuration instructions shown in FIG6 are taken as an example for description.

[0074] Where "Length = M" indicates that there are M consecutive target registers with consecutive addresses, where M is a positive integer. "Register number = M + N" indicates that the total number of consecutive target registers with consecutive addresses is M + N, where N is a positive integer. The rest of the content shown in FIG6 is the same as that described in FIG5 , and for the sake of brevity, it will not be repeated here.

[0075] The examples here are only for ease of understanding and should not be construed as limiting this application.

[0076] It should be noted that the specific implementation of the configuration instructions shown in this application is not limited to the above-mentioned examples.

[0077] Optionally, when there are multiple discontinuous target registers, the instruction text may further record the offset of each target register.

[0078] At this time, for each target register, the actual configuration address of each target register can be obtained based on the offset of the target register, the offset address of the first target register, and the preset reference address.

[0079] Optionally, the number of discontinuous target registers may be recorded in the instruction text.

[0080] For ease of understanding, the configuration instructions shown in FIG. 7 are taken as an example for description.

[0081] As shown in Figure 7, Length = 1 indicates that there is one target register with continuous addresses, Address is the offset address of the first target register, "Register number = 3" recorded in the instruction text indicates that the number of discontinuous target registers is 3, and "Offset of the 1st register", "Offset of the 2st register" and "Offset of the 3rd register" represent the offsets of these three discontinuous registers based on the offset address of the first target register.

[0082] Therefore, the actual offset of the first target register is Address + Offset of the 1st register. Then, based on the sum of the preset base address and the actual offset of the first target register, the actual configuration address of the first target register can be obtained.

[0083] Similarly, the actual offset of the second target register is Address + Offset of the 2nd register. The actual offset of the third target register is Address + Offset of the 3rd register.

[0084] “Configure data” described in the command text of FIG. 7 indicates configuration data.

[0085] The examples here are only for ease of understanding and should not be construed as limiting this application.

[0086] In one embodiment, the hardware automatic control unit 120 is further connected to an interactive interface of each data path of the display processor 110 ; wherein different data paths include different registers.

[0087] The hardware automatic control unit 120 is further configured to send a configuration instruction to the data path indicating the start of configuring the target registers, and receive a configuration status signal fed back by the data path, the configuration status signal indicating whether all registers included in the data path have been configured.

[0088] The configuration status signal may be one of an end feedback signal and a configuration incomplete signal.

[0089] The configuration incomplete signal may also include the number and storage address of the register that has not been configured.

[0090] Optionally, when the display processor 110 includes multiple data paths, the hardware automatic control unit 120 is further configured to record the configuration status of the registers included in each data path based on the configuration status signal fed back by each data path; the configuration status indicates whether the registers have been configured. By recording the configuration status of the registers included in each data path, the hardware automatic control unit 120 facilitates subsequent determination of which data path's registers still need to be configured.

[0091] In one implementation, when the display processor 110 includes multiple data paths, the hardware automatic control unit 120 is further configured to record information about the target registers configured by itself in the display processor 110 .

[0092] For example, the offset address or actual configuration address of the configured target register may be recorded. The examples here are only for ease of understanding. As long as the recorded information can uniquely represent the target register, it should not be used as a limitation to this application.

[0093] The target registers that have not been configured in each data path can be determined based on the recorded information, so as to facilitate the subsequent determination of which data path registers still need to be configured.

[0094] In one implementation, the register configuration system 100 further includes a central processing unit 140 , as shown in FIG8 .

[0095] The central processing unit 140 is connected to the hardware automatic control unit 120 , and the central processing unit 140 is used to send a startup instruction to the hardware automatic control unit 120 .

[0096] The startup instruction is used to instruct the hardware automatic control unit 120 to start and begin register configuration.

[0097] Optionally, the hardware automatic control unit 120 is further configured to send its own internal state to the central processing unit 140 .

[0098] Accordingly, the central processing unit 140 determines whether the hardware automatic control unit 120 is abnormal based on the received status of the hardware automatic control unit 120. If the hardware automatic control unit 120 is abnormal, the central processing unit 140 sends an interrupt instruction to the hardware automatic control unit 120, which is used to instruct the hardware automatic control unit 120 to stop working.

[0099] The CPU 140 monitors the internal state of the hardware automatic control unit 120. If the hardware automatic control unit 120 malfunctions, an interrupt instruction can be sent to the hardware automatic control unit 120 to stop the hardware automatic control unit 120. This prevents register configuration errors caused by malfunctions in the hardware automatic control unit 120 and improves the reliability of the register configuration system 100.

[0100] The central processing unit 1410 can be any type of central processing unit (CPU), and the specific model of the central processing unit 140 is not limited here.

[0101] Based on the same technical concept, the present application also provides a register configuration method, which is applied to the hardware automatic control unit 120 in the aforementioned register configuration system 100. As shown in FIG9 , the steps involved will be described below in conjunction with FIG9 .

[0102] S100: Receive a start instruction.

[0103] The startup instruction includes the storage address of the configuration instruction.

[0104] Optionally, the start instruction may be sent by the central processing unit to the hardware automatic control unit.

[0105] S200: Obtain and parse a configuration instruction from a memory based on the startup instruction.

[0106] After receiving the startup instruction, the configuration instruction can be obtained based on the storage address included in the startup instruction. The configuration instruction is then parsed to obtain the actual configuration address of the target register, and the target register is configured based on the actual configuration address.

[0107] The specific implementation of the configuration instruction and parsing the configuration instruction to obtain the actual configuration address of the target register has been clearly described in the previous text and will not be repeated here for the sake of brevity.

[0108] S300: configuring target registers in the display processor based on the parsed configuration instruction.

[0109] After parsing the configuration instruction, the actual configuration address of the target register can be obtained, and the target register can be configured based on the actual configuration address.

[0110] The specific method and logic for configuring the target register are well known to those skilled in the art and will not be described in detail here for the sake of brevity.

[0111] The register configuration method provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned register configuration system embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference can be made to the corresponding content in the aforementioned register configuration system embodiment.

[0112] Based on the same technical concept, the present application also provides an electronic device, which includes the aforementioned register configuration system.

[0113] The specific implementation method and principle of the register configuration system have been clearly described in the previous article and will not be repeated here for the sake of brevity.

[0114] The electronic device may be a computer, a server, or other electronic device that requires configuration of registers in a display processor. The specific type of the electronic device is not limited here.

[0115] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A register configuration system, characterized in that: include: A display processor, the display processor comprising a plurality of registers; A memory, wherein at least one configuration instruction is pre-stored in the memory, and the configuration instruction is used to indicate a target register to be configured in the display processor; A hardware automatic control unit, the hardware automatic control unit is connected to the register configuration interface of the display processor, the hardware automatic control unit is used to receive a startup instruction, and obtain and parse the configuration instruction from the memory based on the startup instruction, and configure the target register in the display processor based on the parsed configuration instruction, wherein the startup instruction includes a storage address of the configuration instruction.

2. The register configuration system according to claim 1, characterized in that: The hardware automatic control unit is also connected to the interactive interface of each data path of the display processor; wherein different data paths include different registers; The hardware automatic control unit is also used to send a configuration instruction to the data path to indicate the start of configuring the target register, and receive a configuration status signal fed back by the data path, wherein the configuration status signal indicates whether all registers included in the data path have completed configuration.

3. The register configuration system according to claim 2, characterized in that: The display processor includes multiple data paths, and the hardware automatic control unit is further used to record the configuration status of the register included in each data path according to the configuration status signal fed back by each data path; the configuration status represents whether the register has completed configuration.

4. The register configuration system according to claim 1, characterized in that: The register configuration system also includes: A central processing unit is connected to the hardware automatic control unit, and the central processing unit is used to send the startup instruction to the hardware automatic control unit.

5. The register configuration system according to claim 4, characterized in that: The hardware automatic control unit is also used to send its internal state to the central processing unit; The central processing unit determines whether the hardware automatic control unit is abnormal according to the received state of the hardware automatic control unit. If the hardware automatic control unit is abnormal, an interrupt instruction is sent to the hardware automatic control unit, and the interrupt instruction is used to instruct the hardware automatic control unit to stop working.

6. The register configuration system according to any one of claims 1 to 5, characterized in that: The configuration instruction includes the instruction type, the number of target registers with consecutive addresses, the offset address of the first target register, the instruction text, and the instruction end mark.

7. The register configuration system according to claim 6, characterized in that: The instruction text records the calculation method of the actual configuration address of each target register; The hardware automatic control unit is specifically used to parse the configuration instruction according to the instruction type to obtain the number of target registers, the offset address of the first target register, the instruction text, and the instruction end flag; Based on the number of target registers with consecutive addresses, the offset address of the first target register and the calculation method in the instruction text, the actual configuration address of each target register is determined; based on the actual configuration address of each target register, each target register is configured.

8. The register configuration system according to claim 7, characterized in that: The instruction text also records a method for calculating the total number of target registers with consecutive addresses; The hardware automatic control unit is specifically used to determine the total number of the target registers with consecutive addresses according to the number of the target registers with consecutive addresses and the calculation method of the total number of the target registers; Based on the total number of the target registers with consecutive addresses, the offset address of the first target register and the instruction text, the actual configuration address of each of the target registers is determined.

9. A register configuration method, characterized in that: Applied to a hardware automatic control unit in a register configuration system according to any one of claims 1 to 8, the method comprising: Receive a start command; Retrieving and parsing the configuration instruction from the memory based on the startup instruction; The target register in the display processor is configured based on the parsed configuration instruction.

10. An electronic device, characterized in that: include: A register configuration system as claimed in any one of claims 1 to 8.

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