Shift register and driving method therefor, gate drive circuit, and display apparatus

Abstract

A shift register (310), the shift register (310) comprising a first decoding sub-circuit (35) and a third control sub-circuit (36). The first decoding sub-circuit (35) is electrically connected to a plurality of selection control signal ends (DX), a second clock signal end (CK3), and a third node (N3). The first decoding sub-circuit (35) is configured to, under the control of a second clock signal and a working voltage from at least one selection control signal end (DX), select the shift register (310) to not output a scanning signal, or, under the control of the second clock signal and a non-working voltage of each selection control signal end (DX) amongst the plurality of selection control signal ends (DX), select the shift register (310) to output a scanning signal. The third control sub-circuit (36) is electrically connected to a first voltage signal end (VSS), a second node (N2), the third node (N3), and a signal output end (Out), and is configured to transmit a first voltage signal to the second node (N2) and the signal output end (Out) when the shift register (310) is selected to not output the scanning signal, and to transmit a first voltage signal to the third node (N3) when the shift register (310) is selected to output the scanning signal.

Description

Shift register and driving method thereof, gate driving circuit and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0002] With the continuous advancement of display technology, narrow-bezel, high-refresh-rate display devices have become a mainstream trend in the display industry. Organic Light-Emitting Diode (OLED) displays, owing to their self-luminescence, lack of a backlight, high contrast, thinness, wide viewing angle, fast response time, compatibility with flexible panels, wide operating temperature range, and simple structure and manufacturing processes, have gradually become a mainstream product in the display field. Display devices typically utilize Gate On Array (GOA) technology to achieve narrow or no-bezel displays.

[0003] Summary of the Invention

[0004] In one aspect, a shift register is provided. The shift register includes a first control subcircuit, a first output subcircuit, a second control subcircuit, a second output subcircuit, a first decoding subcircuit, and a third control subcircuit. The first control subcircuit is electrically connected to a first clock signal terminal and a first node, and is configured to transmit the first clock signal to the first node under the control of a first clock signal from the first clock signal terminal. The first output subcircuit is electrically connected to the first node, a first voltage signal terminal, and a signal output terminal, and is configured to transmit a first voltage signal from the first voltage signal terminal to the signal output terminal under the control of the voltage at the first node. The second control subcircuit is electrically connected to the first node, a second clock signal terminal, and a second node, and is configured to transmit the second clock signal to the second node under the control of a second clock signal from the second clock signal terminal and the voltage at the first node. The second output subcircuit is electrically connected to the second node, a third clock signal terminal, and the signal output terminal, and is configured to transmit a third clock signal from the third clock signal terminal to the signal output terminal under the control of the voltage at the second node. The first decoding sub-circuit is electrically connected to a plurality of selection control signal terminals, the second clock signal terminal, and a third node, and is configured to, under the control of an operating voltage from at least one selection control signal terminal and the second clock signal, select the shift register to not output a scan signal, or, under the control of a non-operating voltage at each of the plurality of selection control signal terminals and the second clock signal, select the shift register to output a scan signal. The third control sub-circuit is electrically connected to the first voltage signal terminal, the second node, the third node, and the signal output terminal, and is configured to transmit the first voltage signal to the second node and the signal output terminal when the shift register is selected not to output a scan signal, and to transmit the first voltage signal to the third node when the shift register is selected to output a scan signal.

[0005] In some embodiments, the first decoding sub-circuit includes a first transistor and a plurality of second transistors. The control electrode and the first electrode of the first transistor are both electrically connected to the second clock signal terminal, and the second electrode is electrically connected to a fourth node. The control electrode of each of the plurality of second transistors is electrically connected to a selection control signal terminal, and the plurality of first electrodes of the plurality of second transistors are all electrically connected to the fourth node, and the plurality of second electrodes are all electrically connected to the third node.

[0006] In some embodiments, the first decoding sub-circuit is further electrically connected to the second voltage signal terminal. The first decoding sub-circuit includes a first transistor and a plurality of second transistors. The control electrode of the first transistor is electrically connected to the second clock signal terminal, the first electrode is electrically connected to the fifth node, and the second electrode is electrically connected to the third node. The control electrode of each of the plurality of second transistors is electrically connected to a selection control signal terminal, and the plurality of first electrodes of the plurality of second transistors are electrically connected to the second voltage signal terminal, and the plurality of second electrodes are electrically connected to the fifth node.

[0007] In some embodiments, the shift register further includes a black insertion control subcircuit. The black insertion control subcircuit is electrically connected to the first control signal terminal, the fifth node, and the signal output terminal, and is configured to transmit the voltage of the fifth node to the signal output terminal under the control of a first control signal from the first control signal terminal.

[0008] In some embodiments, the black insertion control subcircuit includes a third transistor, wherein a control electrode of the third transistor is electrically connected to the first control signal terminal, a first electrode is electrically connected to the fifth node, and a second electrode is electrically connected to the signal output terminal.

[0009] In some embodiments, the shift register further includes a second decoding sub-circuit. The second decoding sub-circuit is electrically connected to a plurality of black insertion control signal terminals, a first control signal terminal, the second voltage signal terminal, and the signal output terminal, and is configured to transmit the second voltage signal from the second voltage signal terminal to the signal output terminal under the control of a black insertion control signal from at least one of the black insertion control signal terminals and a first control signal from the first control signal terminal.

[0010] In some embodiments, the second decoding sub-circuit includes a fifth transistor and a plurality of fourth transistors. A control electrode of each of the plurality of fourth transistors is electrically connected to a black insertion control signal terminal, and a plurality of first electrodes of the plurality of fourth transistors are electrically connected to the second voltage signal terminal, and a plurality of second electrodes of the plurality of fourth transistors are electrically connected to a sixth node. A control electrode of the fifth transistor is electrically connected to the first control signal terminal, a first electrode is electrically connected to the sixth node, and a second electrode is electrically connected to the signal output terminal.

[0011] In some embodiments, the plurality of black insertion control signal terminals and the plurality of selection control signal terminals are the same in number and correspond one to one. The black insertion control signal terminals and the selection control signal terminals corresponding to the black insertion control signal terminals are the same signal terminals or different signal terminals.

[0012] In some embodiments, the third control subcircuit includes a sixth transistor, a seventh transistor, and an eighth transistor. The sixth transistor has a control electrode electrically connected to the third node, a first electrode electrically connected to the first voltage signal terminal, and a second electrode electrically connected to the second node. The seventh transistor has a control electrode electrically connected to the third node, a first electrode electrically connected to the first voltage signal terminal, and a second electrode electrically connected to the signal output terminal. The eighth transistor has a control electrode electrically connected to the second node, a first electrode electrically connected to the first voltage signal terminal, and a second electrode electrically connected to the third node.

[0013] In some embodiments, the sixth transistor is a dual-gate transistor comprising two sub-transistors arranged in series, the two sub-transistors being connected via a seventh node. The shift register further comprises a leakage prevention electronic circuit. The leakage prevention electronic circuit is electrically connected to the second node, the second voltage signal terminal, and the seventh node, and is configured to transmit the second voltage signal to the seventh node under control of the voltage at the second node.

[0014] In some embodiments, the leakage prevention circuit includes a ninth transistor having a control electrode electrically connected to the second node, a first electrode electrically connected to the second voltage signal terminal, and a second electrode electrically connected to the seventh node.

[0015] In some embodiments, the third control subcircuit is further electrically connected to the first node, and the third control subcircuit is further configured to transmit the first voltage signal to the first node when the shift register is selected not to output a scan signal.

[0016] In some embodiments, the third control subcircuit further includes a tenth transistor having a control electrode electrically connected to the third node, a first electrode electrically connected to the first voltage signal terminal, and a second electrode electrically connected to the first node.

[0017] In some embodiments, the shift register further includes a time-sharing selection subcircuit and a fourth control subcircuit. The time-sharing selection subcircuit is electrically connected to the second control signal terminal, the third control signal terminal, the first decoding subcircuit, the third node, and the eighth node. The time-sharing selection subcircuit is configured to electrically connect the first decoding subcircuit to the third node under the control of a second control signal from the second control signal terminal, and to electrically connect the first decoding subcircuit to the eighth node under the control of a third control signal from the third control signal terminal. The fourth control subcircuit is electrically connected to the first voltage signal terminal, the second node, the eighth node, and the signal output terminal. The fourth control subcircuit is configured to transmit the first voltage signal to the second node and the signal output terminal when the shift register is selected not to output a scan signal, and to transmit the first voltage signal to the eighth node when the shift register is selected to output a scan signal. The first decoding subcircuit is electrically connected to the third node via the time-sharing selection subcircuit.

[0018] In some embodiments, the time-sharing selection subcircuit includes an eleventh transistor and a twelfth transistor. The eleventh transistor has a control electrode electrically connected to the second control signal terminal, a first electrode electrically connected to the first decoding subcircuit, and a second electrode electrically connected to the third node. The twelfth transistor has a control electrode electrically connected to the third control signal terminal, a first electrode electrically connected to the first decoding subcircuit, and a second electrode electrically connected to the eighth node. Within a display cycle, one of the second control signal terminal and the third control signal terminal transmits a corresponding control signal, and the second control signal terminal and the third control signal terminal alternately transmit corresponding control signals.

[0019] In some embodiments, the fourth control subcircuit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor. The control electrode of the thirteenth transistor is electrically connected to the eighth node, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the second node. The control electrode of the fourteenth transistor is electrically connected to the eighth node, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the signal output terminal. The control electrode of the fifteenth transistor is electrically connected to the second node, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the eighth node. The control electrode of the sixteenth transistor is electrically connected to the eighth node, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the first node.

[0020] In some embodiments, the first control subcircuit includes a seventeenth transistor, wherein the control electrode and first electrode of the seventeenth transistor are both electrically connected to the first clock signal terminal, and the second electrode is electrically connected to the first node. The first output subcircuit includes an eighteenth transistor, wherein the control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the signal output terminal. The second control subcircuit includes a nineteenth transistor and a twenty-first transistor. The control electrode and first electrode of the nineteenth transistor are both electrically connected to the second clock signal terminal, and the second electrode is electrically connected to the first electrode of the twentieth transistor. The control electrode of the twentieth transistor is electrically connected to the first node, and the second electrode is electrically connected to the second node. The second output subcircuit includes a twenty-first transistor, wherein the control electrode of the twenty-first transistor is electrically connected to the second node, the first electrode is electrically connected to the third clock signal terminal, and the second electrode is electrically connected to the signal output terminal.

[0021] In some embodiments, the shift register further includes a reset subcircuit, an initialization subcircuit, a first energy tank subcircuit, a second energy tank subcircuit, and a third energy tank subcircuit. The reset subcircuit is electrically connected to the third clock signal terminal, the first voltage signal terminal, and the first node, and is configured to transmit the first voltage signal to the first node under the control of the third clock signal. The initialization subcircuit is electrically connected to the first clock signal terminal, the first voltage signal terminal, and the third node, and is configured to transmit the first voltage signal to the third node under the control of the first clock signal. The first energy tank subcircuit is electrically connected to the first voltage signal terminal and the first node, and is configured to maintain the voltage of the first node. The second energy tank subcircuit is electrically connected to the second node and the signal output terminal, and is configured to maintain the voltage of the second node. The third energy tank subcircuit is electrically connected to the third node and the first voltage signal terminal, and is configured to maintain the voltage of the third node.

[0022] In some embodiments, the reset subcircuit includes a twenty-second transistor, wherein the control electrode of the twenty-second transistor is electrically connected to the third clock signal terminal, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the first node. The initialization subcircuit includes a twenty-third transistor, wherein the control electrode of the twenty-third transistor is electrically connected to the first clock signal terminal, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the third node. The first energy storage subcircuit includes a first capacitor, wherein one plate of the first capacitor is electrically connected to the first voltage signal terminal, and the other plate is electrically connected to the first node. The second energy storage subcircuit includes a second capacitor, wherein one plate of the first capacitor is electrically connected to the second node, and the other plate is electrically connected to the signal output terminal. The third energy storage subcircuit includes a third capacitor, wherein one plate of the third capacitor is electrically connected to the first voltage signal terminal, and the other plate is electrically connected to the third node.

[0023] In another aspect, a shift register driving method is provided, for driving the shift register described in any of the above embodiments. A display cycle includes a selection phase and an output phase. When the shift register is selected not to output a scan signal, the driving method includes: in the selection phase, at least one of a plurality of selection control signal terminals outputs an operating voltage, a first decoding subcircuit transmits an operating voltage to a third node, and a third control subcircuit transmits a first voltage signal to a second node and a third node under control of a turn-on voltage at the third node. In the output phase, the second output subcircuit is turned off under control of the first voltage signal at the second node and does not output a scan signal. When the shift register is selected to output a scan signal, the driving method includes: in the selection phase, all of the plurality of selection control signal terminals transmit a non-operating voltage, and the first and second control subcircuits transmit a second clock signal from a second clock signal terminal to the second node. In the output phase, the second output subcircuit transmits a third clock signal from a third clock signal terminal to a signal output terminal under control of the voltage at the second node.

[0024] In some embodiments, the selection phase includes a first phase and a third phase, which are sequentially arranged. When the shift register is selected not to output a scan signal, the driving method includes: in the first phase, the first control subcircuit transmits the first clock signal to the first node under the control of a first clock signal from the first clock signal terminal. In the third phase, the second control subcircuit transmits the second clock signal to the second node under the control of a second clock signal from the second clock signal terminal and the first clock signal from the first node.

[0025] In some embodiments, the shift register includes a second decoding sub-circuit, and a display cycle further includes a black insertion phase located after the output phase. The driving method further includes: during the black insertion phase, the second decoding sub-circuit transmits the second voltage signal from the second voltage signal terminal to the signal output terminal under the control of a black insertion control signal from at least one black insertion control signal terminal and a first control signal from the first control signal terminal.

[0026] In some embodiments, the shift register includes a black insertion control subcircuit, and a display cycle further includes a black insertion phase located after the output phase. The driving method further includes: during the black insertion phase, the first decoding subcircuit transmits a second voltage signal to a fifth node under the control of at least one selection control signal, and the black insertion control subcircuit transmits the voltage of the fifth node to the signal output terminal under the control of a first control signal from a first control signal terminal.

[0027] In yet another aspect, a gate drive circuit is provided. The gate drive circuit includes multiple shift registers as described in any of the above embodiments and multiple groups of selection control signal lines. Each group includes two selection control signal lines, each of which forms a selection control signal terminal. The first decoding sub-circuit of the shift register is electrically connected to one selection control signal line in each group of selection control signal lines, and each selection control signal line forms a selection control signal terminal.

[0028] In some embodiments, every four shift registers form a shift register group, and the four shift registers included in the shift register group are arranged in sequence as a first-stage shift register, a second-stage shift register, a third-stage shift register, and a fourth-stage shift register. The gate drive circuit further includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line. The first clock signal line is electrically connected to the first clock signal terminal of the first-stage shift register, the third clock signal terminal of the second-stage shift register, and the second clock signal terminal of the third-stage shift register, respectively. The second clock signal line is electrically connected to the first clock signal terminal of the second-stage shift register, the third clock signal terminal of the third-stage shift register, and the second clock signal terminal of the fourth-stage shift register, respectively. The third clock signal line is electrically connected to the second clock signal terminal of the first-stage shift register, the first clock signal terminal of the third-stage shift register, and the third clock signal terminal of the fourth-stage shift register, respectively. The fourth clock signal line is electrically connected to the third clock signal terminal of the first-stage shift register, the second clock signal terminal of the second-stage shift register, and the first clock signal terminal of the fourth-stage shift register, respectively.

[0029] In some embodiments, one of the two selection control signal lines in each group of selection control signal lines transmits an operating voltage, and the other transmits a non-operating voltage. The first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line sequentially output operating voltages.

[0030] In some embodiments, the shift register includes a second decoding sub-circuit, the second decoding sub-circuit being electrically connected to one selection control signal line in each group of selection control signal lines, wherein one of the selection control signal lines forms a black insertion control signal terminal. The second decoding sub-circuit and the first decoding sub-circuit are electrically connected to the same selection control signal line in the same group of selection control signal lines, or to different selection control signal lines.

[0031] In another aspect, a display device is provided, wherein the display device includes the shift register described in any one of the above embodiments, or the display device includes the gate driving circuit described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0033] FIG1 is a structural diagram of a display device according to some embodiments;

[0034] FIG2 is another structural diagram of a display device according to some embodiments;

[0035] FIG3 is an equivalent circuit diagram of a pixel circuit according to some embodiments;

[0036] FIG4A is a control timing diagram of a pixel circuit according to some embodiments;

[0037] FIG4B is another control timing diagram of a pixel circuit according to some embodiments;

[0038] FIG5 is a structural diagram of a gate driving circuit according to some embodiments;

[0039] FIG6 is a structural diagram of a shift register according to some embodiments;

[0040] FIG7 is an equivalent circuit diagram of a first decoding sub-circuit according to some embodiments;

[0041] FIG8 is another equivalent circuit diagram of the first decoding sub-circuit according to some embodiments;

[0042] FIG9A is an equivalent circuit diagram of a shift register according to some embodiments;

[0043] FIG9B is another equivalent circuit diagram of a shift register according to some embodiments;

[0044] FIG10 is another structural diagram of a shift register according to some embodiments;

[0045] FIG11 is another equivalent circuit diagram of a shift register according to some embodiments;

[0046] FIG12 is another equivalent circuit diagram of a shift register according to some embodiments;

[0047] FIG13 is another structural diagram of a shift register according to some embodiments;

[0048] FIG14 is another equivalent circuit diagram of a shift register according to some embodiments;

[0049] FIG15 is another structural diagram of a shift register according to some embodiments;

[0050] FIG16 is another equivalent circuit diagram of a shift register according to some embodiments;

[0051] FIG17 is another structural diagram of a shift register according to some embodiments;

[0052] FIG18 is another equivalent circuit diagram of a shift register according to some embodiments;

[0053] FIG19 is another equivalent circuit diagram of a shift register according to some embodiments;

[0054] FIG20 is another equivalent circuit diagram of a shift register according to some embodiments;

[0055] FIG21 is another equivalent circuit diagram of a shift register according to some embodiments;

[0056] FIG22 is another equivalent circuit diagram of a shift register according to some embodiments;

[0057] FIG23 is a control timing diagram of a shift register according to some embodiments;

[0058] FIG. 24 is another control timing diagram of a shift register according to some embodiments. DETAILED DESCRIPTION

[0059] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0060] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0061] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0062] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean fixed connection, detachable connection, or integration; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0063] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0064] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0065] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0066] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0067] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0068] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0069] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0070] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0071] FIG. 1 is an overall structural diagram of a display device according to some embodiments.

[0072] 1 , an embodiment of the present disclosure provides a display device 1000 , which is a product having an image display function. For example, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0073] For example, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone, a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a camera view display (e.g., a rearview camera display in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, an in-vehicle display, or an aircraft display. For example, as shown in FIG1 , the display device 1000 can be a mobile phone.

[0074] From the perspective of the light-emitting type of the display device 1000, the above-mentioned display device 1000 may be an organic light-emitting diode display device, a quantum dot electroluminescent display device (Quantum Dot Light Emitting Diodes; abbreviated as: QLED) or a micro light-emitting diode (Mini / Micro Light Emitting Display; abbreviated as: MLED), etc. From the perspective of the form of the display device 1000, the above-mentioned display device 1000 may be a flat display device, a curved display device or a foldable display device, etc. From the perspective of the shape of the display device 1000, the above-mentioned display device 1000 may be rectangular or circular, etc. The embodiments of the present disclosure do not specifically limit this. The following takes an organic light-emitting diode display device with a rectangular and flat display device as an example to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited to this, and any other display devices can also be considered as long as the same technical ideas are applied.

[0075] FIG2 is a structural diagram of a display device according to yet other embodiments.

[0076] In some embodiments, the display device 1000 includes a display panel 1100 and a driving circuit board 1200. The driving circuit board 1200 may include, for example, a timing controller (TCON), a power management chip DC / DC, and an adjustable resistor divider circuit (generating Vcom) and other driving circuits. The driving circuit board 1200 may also include other circuit structures, which are not listed here one by one. The driving circuit board 1200 is electrically connected to the display panel 1100 and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 may also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording, fingerprint recognition or face recognition, which are not specifically limited here.

[0077] Continuing with FIG. 2 , the display panel 1100 includes a display area AA and a peripheral area BB. The peripheral area BB is located on at least one side of the display area AA and, illustratively, surrounds the display area AA. The display area AA is the region of the display panel 1100 used for displaying images. The display area AA is provided with a plurality of sub-pixels P, which are the smallest light-emitting units on the display panel 1100 and are used to display images.

[0078] The multiple sub-pixels P can emit light of the same color, such as white light or blue light. In this case, the display panel also includes a color filter layer disposed on the display side, that is, the display panel adopts a COE (CF on Encapsulation) structure. Alternatively, the multiple sub-pixels P can emit light of different colors. For example, the multiple sub-pixels P include a red sub-pixel emitting red light, a green sub-pixel emitting green light, and a blue sub-pixel emitting blue light.

[0079] Multiple sub-pixels P are arranged in multiple rows and columns. Each row includes multiple sub-pixels P arranged along a first direction X, and multiple rows of sub-pixels P are arranged along a second direction Y. Each column includes multiple sub-pixels P arranged along the second direction Y, and multiple columns of sub-pixels P are arranged along the first direction X. The first direction X and the second direction Y intersect. For example, the first direction X is perpendicular to the second direction Y. A row of sub-pixels P arranged along the first direction X is also referred to as a pixel row.

[0080] As shown in FIG2 , the display panel 1100 further includes a plurality of data lines DL, which are arranged at intervals along a first direction X and extend along a second direction Y. Each data line DL may be electrically connected to a column of sub-pixels P, and the data lines DL are configured to transmit data signals to the column of sub-pixels P electrically connected to the data lines DL.

[0081] Each sub-pixel P includes a pixel circuit 100 and a light-emitting device 200. The pixel circuit 100 includes a plurality of thin film transistors (TFTs) and at least one capacitor Cst. Exemplarily, the pixel circuit 100 may be a "3T1C" circuit, a "7T1C" circuit, an "8T1C" circuit, etc. The embodiments of the present disclosure are not limited thereto, and any other pixel circuits may also be considered as long as the same technical concept is applied. Wherein, "T" refers to TFT, and the number before "T" refers to the number of TFTs; "C" refers to capacitor Cst, and the number before "C" refers to the number of capacitors Cst.

[0082] In some embodiments, the thin-film transistors may be oxide thin-film transistors. Oxide thin-film transistors, with their high electron mobility, low off-state current, and simple fabrication process, are the preferred choice for large-scale, high-resolution, low-power, and narrow-frame display panels. Pixel circuits fabricated using oxide thin-film transistors require external compensation to ensure they can drive the light-emitting devices to display the desired grayscale.

[0083] In the embodiment of the present application, each transistor includes a gate, a source and a drain. Among them, the connection mode of the source and drain of the transistor can be interchangeable, so the source and drain of each transistor in the embodiment of the present disclosure are actually the same. Here, it is only to distinguish the two poles of the transistor other than the control electrode (i.e., the gate), and one of the poles is called the drain and the other pole is called the source. The transistor used in the embodiment of the present application can be an N-type transistor or a P-type transistor. When the transistor used in the embodiment of the present application is an N-type transistor, its first pole is the source and the second pole is the drain. When the transistor used in the embodiment of the present application is a P-type transistor, its first pole is the drain and the second pole is the source. In the following embodiments, the transistor is an N-type transistor as an example for explanation, and the transistor is turned on when the signal received by its control electrode is a high voltage. It can be understood that when the transistor used in the embodiment of the present application is a P-type transistor, it is necessary to adjust the timing change of the drive signal accordingly. The specific details are not repeated here, but it is also within the scope of protection of the present application.

[0084] FIG. 3 is an equivalent circuit diagram of the pixel circuit 100 according to some embodiments.

[0085] Referring to FIG. 3 , in some embodiments, the pixel circuit 100 may be a “3T1C circuit.” The pixel circuit 100 includes a data write transistor T101, a drive transistor T102, a sense transistor T103, and a storage capacitor C101. The control electrode of the data write transistor T101 is electrically connected to a first scan signal terminal G1. The first scan signal terminal G1 can be electrically connected to a shift register of a gate drive circuit via a scan signal line (not shown). The first electrode of the data write transistor T101 is electrically connected to a data line DL for receiving a data signal provided by the data line DL. The data signal may include a display data signal, a sense data signal, and a black insertion data signal. The second electrode of the data write transistor T101 is electrically connected to a first circuit node S1. The control electrode of the drive transistor T102 is electrically connected to the first circuit node S1, that is, the control electrode of the drive transistor T102 is electrically connected to the second electrode of the data write transistor T101. The first electrode of the drive transistor T102 is electrically connected to a first power supply voltage terminal ELVDD. Exemplarily, the first power supply voltage terminal ELVDD is used to provide a high voltage signal. The second electrode of the driving transistor T102 is connected to the second circuit node S. One plate of the storage capacitor C101 is electrically connected to the first circuit node S1, and the other plate is electrically connected to the second circuit node S2. In other words, one plate of the storage capacitor C101 is electrically connected to the second electrode of the data write transistor T101 and the control electrode of the driving transistor T102, and the other plate is electrically connected to the second electrode of the driving transistor T102. The control electrode of the sensing transistor T103 is electrically connected to the second scan signal terminal G2, the first electrode is electrically connected to the second circuit node S2, and the second electrode is electrically connected to the sensing signal line SL. One end (the anode end) of the light-emitting device 200 is electrically connected to the second circuit node S2, and the other end (the cathode end) is electrically connected to the second power supply voltage terminal ELVSS. Exemplarily, the second power supply voltage terminal ELVSS is used to provide a low voltage signal.

[0086] FIG. 4A is a driving timing diagram of the pixel circuit 100 shown in FIG. 3 , including a display phase and a sensing phase.

[0087] 3 and 4A , a display cycle of the pixel circuit 100 may include three phases: a display data writing phase M101 , a light emitting phase M102 , and a sensing phase M105 .

[0088] In the display data writing phase M101 , the first scanning signal terminal G1 and the second scanning signal terminal G2 output high voltages, the data writing transistor T101 and the sensing transistor T103 are turned on, and the data writing transistor T101 transmits the display data signal transmitted by the data line DL to the first circuit node S1 .

[0089] It can be understood that in the embodiments of the present disclosure, the "first circuit node" in the pixel circuit and the "first node", "second node", etc. in the shift register below do not represent actual components, but represent the confluence points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the equivalent confluence points of related electrical connections in the circuit diagram.

[0090] During the light-emitting phase M102, the first scan signal terminal G1 and the second scan signal terminal G2 output a low voltage, and the data writing transistor T101 and the sensing transistor T103 are turned off. The storage capacitor C101 acts as a bootstrap, and the voltage (display data signal) at the first circuit node S1 is maintained constant by the storage capacitor C101. The driving transistor T102 is turned on under the control of the display data signal and drives the light-emitting device 200 to emit light.

[0091] During the sensing phase M105, the first scanning signal terminal G1 and the second scanning signal terminal G2 initially output a high voltage, the data line DL transmits a sensing data signal, the data write transistor T101 and the sensing transistor T103 turn on, and the data write transistor T101 transmits the sensing data signal transmitted by the data line DL to the first circuit node S1. Subsequently, the first scanning signal terminal G1 outputs a low high voltage, the data write transistor T101 turns off, the second scanning signal terminal G2 continues to output a high voltage, and the sensing transistor T103 remains on. The driving transistor T102 turns on, and the second electrode of the sensing transistor T103 outputs a pixel compensation signal, implementing compensation for the pixel circuit. Then, the first scan signal terminal G1 and the second scan signal terminal G2 output a high voltage, the data line DL transmits a black data insertion signal, the data write transistor T101 and the sensing transistor T103 are turned on, and the data write transistor T101 transmits the black data insertion signal to the first circuit node S1. The driving transistor T102 is turned off. The black data insertion signal can be, for example, a 0 grayscale signal to clear the sensing data signal stored in the sensing storage capacitor C101. Finally, the first scan signal terminal G1 and the second scan signal terminal G2 output a low voltage, and the data write transistor T101 and the sensing transistor T103 are turned off.

[0092] As shown in FIG2 , the peripheral area BB can be used to set up a gate driving circuit 300 and control signal lines (such as clock signal lines, power supply voltage signal lines, etc.). Of course, the functions of the peripheral area BB are not limited to this, and the undisclosed embodiments will not be described in detail.

[0093] In related art, a gate drive circuit includes multiple shift registers, which are cascaded. Based on this, the gate drive circuit can scan multiple rows of sub-pixels row by row (drive them row by row) along the second direction. Therefore, when the display device performs a local high-frequency (refresh rate) display or detects a portion of the rows, it is necessary to scan row by row starting from the first row, which is not conducive to reducing the power consumption of the display panel.

[0094] FIG5 is a structural diagram of a gate driving circuit according to some embodiments.

[0095] Referring to FIG. 5 , to address the aforementioned technical issues, an embodiment of the present disclosure provides a gate drive circuit 300. The gate drive circuit 300 includes a plurality of shift registers 310. Each shift register 310 is configured to be electrically connected to the pixel circuits of a row of sub-pixels and output a scan signal to the row of sub-pixels electrically connected to the shift register 310, thereby performing scan driving on the row of sub-pixels.

[0096] FIG6 is a structural diagram of a shift register according to some embodiments.

[0097] 6 , some embodiments of the present disclosure further provide a shift register 310 . The shift register 310 includes a first control subcircuit 31 , a first output subcircuit 32 , a second control subcircuit 33 , a second output subcircuit 34 , a first decoding subcircuit 35 , and a third control subcircuit 36 ​​.

[0098] As shown in Figure 6, the first control subcircuit 31 is electrically connected to the first clock signal terminal CK1 and the first node N1. The first control subcircuit 31 is configured to transmit the first clock signal to the first node N1 under the control of the first clock signal from the first clock signal terminal CK1. The first output subcircuit 32 is electrically connected to the first node N1, the first voltage signal terminal VSS, and the signal output terminal Out. The first output subcircuit 32 is configured to transmit the first voltage signal from the first voltage signal terminal VSS to the signal output terminal Out under the control of the voltage of the first node N1. The first voltage signal terminal VSS is used to transmit a first power supply signal, which can be, for example, a low voltage signal.

[0099] For example, when the first clock signal terminal CK1 transmits the first clock signal, the first control sub-circuit 31 transmits the first clock signal transmitted by the first clock signal terminal CK1 to the first node N1, and the first output sub-circuit 32 outputs the low voltage signal of the first voltage signal terminal VSS from the signal output terminal Out (without outputting the scan signal) under the control of the first clock signal of the first node N1.

[0100] The second control subcircuit 33 is electrically connected to the first node N1, the second clock signal terminal CK3, and the second node N2. The second control subcircuit 33 is configured to transmit the second clock signal to the second node N2 under the control of the second clock signal from the second clock signal terminal CK3 and the voltage of the first node N1. The second output subcircuit 34 is electrically connected to the second node N2, the third clock signal terminal CK4, and the signal output terminal Out. The second output subcircuit 34 is configured to transmit the third clock signal from the third clock signal terminal CK4 to the signal output terminal Out under the control of the voltage of the second node N2.

[0101] Exemplarily, the first control subcircuit 31 outputs a first clock signal to the first node N1. When the second clock signal terminal CK3 outputs a second clock signal, the second control subcircuit 33, under the control of the first and second clock signals at the first node N1, transmits the second clock signal to the second node N2. The second output subcircuit 34, under the control of the voltage (second clock signal) at the second node N2, transmits a third clock signal to the signal output terminal Out, which outputs a scan signal.

[0102] The first decoding sub-circuit 35 is electrically connected to a plurality of selection control signal terminals DX, a second clock signal terminal CK3, and a third node N3. For example, as shown in FIG6 , the first decoding sub-circuit 35 is electrically connected to N selection control signal terminals DX, where N is a positive integer greater than 0, and the N selection control signal terminals DX are sequentially arranged as a first selection control signal terminal D1, a second selection control signal terminal D2, ..., an (N-1)th selection control signal terminal D(N-1), and an Nth selection control signal terminal DN.

[0103] The first decoding sub-circuit 35 is configured to, under the control of an operating voltage from at least one selection control signal terminal DX and a second clock signal from the second clock signal terminal CK3, select the shift register 310 so as not to output a scan signal. Alternatively, under the control of a non-operating voltage at each of the plurality of selection control signal terminals DX and a second clock signal from the second clock signal terminal CK3, select the shift register 310 so as to output a scan signal.

[0104] It should be understood that, taking the transistors included in the pixel circuit and the gate drive circuit in the embodiment of the present disclosure as N-type transistors as an example, the operating voltage refers to the voltage that can turn on the N-type transistor, that is, the operating voltage refers to a high voltage. Conversely, the non-operating voltage refers to the voltage at which the N-type transistor is cut off, that is, the non-operating voltage refers to a low voltage. Moreover, the scan signal refers to the voltage that can turn on the transistor (data writing transistor T101), that is, the scan signal refers to a high voltage signal. In the case where the voltage of the signal output terminal Out is the first voltage signal provided by the first voltage signal terminal VSS, it is considered that the signal output terminal Out does not output the scan signal.

[0105] The third control subcircuit 36 ​​is electrically connected to the first voltage signal terminal VSS, the second node N2, the third node N3, and the signal output terminal Out. The third control subcircuit 36 ​​is configured to transmit the first voltage signal from the first voltage signal terminal VSS to the second node N2 and the signal output terminal Out when the shift register 310 is selected not to output a scan signal, and to transmit the first voltage signal from the first voltage signal terminal VSS to the third node N3 when the shift register 310 is selected to output a scan signal.

[0106] Exemplarily, at least one selection control signal terminal DX transmits an operating voltage, and the second clock signal terminal CK3 transmits a second clock signal. The first decoding sub-circuit 35 transmits an operating voltage to the third node N3. Under the control of the operating voltage at the third node N3, the third control sub-circuit 36 ​​transmits a first voltage signal from the first voltage signal terminal VSS to the second node N2 and the signal output terminal Out. The signal output terminal Out does not output a scan signal.

[0107] For example, each of the plurality of selection control signal terminals DX transmits a non-operating voltage, and the second clock signal terminal CK3 transmits the second clock signal or does not transmit the second clock signal. The first decoding sub-circuit 35 does not transmit any voltage signal to the third node N3. The third control sub-circuit 36, under the control of the voltage of the second node N2, transmits the first voltage signal of the first voltage signal terminal VSS to the third node N3. Under the control of the first voltage signal (non-operating voltage) at the third node N3, the third control sub-circuit 36 ​​disconnects the first voltage signal terminal VSS from the signal output terminal Out, and, under the control of the second control sub-circuit 33 and the second output sub-circuit 34, causes the signal output terminal Out to output the scan signal.

[0108] As shown in FIG5 , the gate drive circuit 300 further includes multiple groups of selection control signal lines KL. Each group of selection control signal lines KL includes two selection control signal lines KL. For example, the two selection control signal lines KL in a group are labeled as a first selection control signal line KL and a second selection control signal line KL. The first decoding sub-circuit 35 of the shift register 310 is electrically connected to one selection control signal line KL in each group of selection control signal lines KL. Specifically, each selection control signal terminal DX is electrically connected to one selection control signal line KL in a group of selection control signal lines KL, thereby forming one selection control signal terminal DX for each selection control signal line KL.

[0109] In some embodiments, a first selection control signal line KL and a second selection control signal line KL transmit completely opposite voltage signals. For example, the first selection control signal line KL transmits an operating voltage, while the second selection control signal line KL transmits a non-operating voltage; or, alternatively, the first selection control signal line KL transmits a non-operating voltage, while the second selection control signal line KL transmits an operating voltage. Based on this, the two first decoding sub-circuits connected to the first selection control signal line KL and the second selection control signal line KL, respectively, can have different compilation states.

[0110] Exemplarily, multiple groups of selection control signal lines KL correspond one-to-one to multiple selection control signal terminals DX connected to the first decoding sub-circuit 35. The display panel includes N groups of selection control signal lines KL, which are sequentially numbered as the first group of selection control signal lines KL1, the second group of selection control signal lines KL2, ..., the (N-1)th group of selection control signal lines KL(N-1), and the Nth group of selection control signal lines KLN. The first selection control signal terminal D1 connected to the first decoding sub-circuit 35 is electrically connected to one of the first group of first selection control signal lines KL1 and the first group of second selection control signal lines KL1 included in the first group of selection control signal lines KL1. For example, the first selection control signal terminal D1 is electrically connected to the first group of first selection control signal lines KL1. In this case, the first group of first selection control signal lines KL1 forms the first selection control signal terminal D1.

[0111] It is understandable that the multiple selection control signal terminals DX connected to at least two shift registers 310 are not identical. For example, the multiple selection control signal terminals DX connected to the shift register 310 include 2 N (2 to the power of N) different connection methods, so that the shift register 310 can compile 2 NAnd only in one compilation state (multiple selection control signal lines KL connected to multiple selection control signal terminals DX of the shift register 310 transmit non-working voltages at the same time), the shift register 310 can be selected to output the scan signal. Based on this, 2 N One of the shift registers 310 outputs a scan signal, while the other (2 N -1) shift register 310 does not output a scan signal.

[0112] In a specific example, the value of N can be 10, and the display panel includes 10 groups of selection control signal lines KL, that is, the display panel includes 20 selection control signal lines KL. The 10 selection control signal terminals DX electrically connected to the shift register 310 include 2 10 Different connection methods. Each selection control signal line KL transmits a working voltage marked as "1" and transmits a non-working voltage marked as "0". Each of the 10 selection control signal terminals DX can receive two voltages, 1 or 0. In this way, the shift register 310 can receive 2 N Different voltage combinations, that is, 2 N Different states, for example: 0000000000, 0000000001, 0000000010, 0000000011, 000000100, ..., 1111111110, 1111111111. Only when the shift register 310 receives the voltage combination formed by 0000000000, the shift register 310 is selected to output the scan signal.

[0113] In summary, the gate drive circuit 300 provided by the embodiment of the present disclosure, as shown in FIG5 , has a plurality of shift registers 310, each of which is directly electrically connected to a plurality of groups of selection control signal lines KL, and the plurality of shift registers 310 may not be cascaded, and any shift register 310 may be selected through the plurality of groups of selection control signal lines KL to output a scan signal. Based on this, the gate drive circuit 300 can arbitrarily adjust the order in which the plurality of shift registers 310 output scan signals (for example, scanning is not performed in a row-by-row order) and the scanning frequency of different shift registers 310. In this way, a specific row of sub-pixels and a specific scanning order can be arbitrarily selected to scan and drive one or more rows of sub-pixels according to display requirements (such as detecting a specific row of sub-pixels, or performing a high-frequency refresh display locally), which is beneficial to reducing the power consumption of the display panel.

[0114] FIG7 is an equivalent circuit diagram of a first decoding sub-circuit according to some embodiments. Referring to FIG7 , in some embodiments, the first decoding sub-circuit 35 includes a first transistor T1 and multiple second transistors T2. The control electrode and first electrode of the first transistor T1 are both electrically connected to the second clock signal terminal CK3, and the second electrode is electrically connected to the fourth node N3. The control electrode of each second transistor T2 is electrically connected to a select control signal terminal DX, and the multiple first electrodes of the multiple second transistors T2 are all electrically connected to the fourth node N4, and the multiple second electrodes are all electrically connected to the third node N3.

[0115] Exemplarily, the plurality of second transistors T2 are sequentially arranged as a first selection transistor T31, a second selection transistor T32, ..., an (N-1)th selection transistor T3(N-1), and an Nth selection transistor T3N. The control electrode of the first selection transistor T31 is electrically connected to the first selection control signal terminal D1, and the first selection control signal terminal D1 is electrically connected to one of the first group of first selection control signal lines KL1 and the first group of second selection control signal lines KL1 included in the first group of selection control signal lines KL1. That is, the control electrode of the first selection transistor T31 is electrically connected to the first group of first selection control signal lines KL1 or the first group of second selection control signal lines KL1. The control electrode of the second selection transistor T32 is electrically connected to the second selection control signal terminal D2, and is also electrically connected to the second group of first selection control signal lines KL2 or the second group of second selection control signal lines KL2. ..., the control electrode of the Nth selection transistor T3N is electrically connected to the Nth selection control signal terminal DN, and is also electrically connected to the Nth group of first selection control signal lines KLN or the Nth group of second selection control signal lines KLN.

[0116] When the second clock signal terminal CK3 transmits the second clock signal (operating voltage), the first transistor T1 is turned on and transmits the second clock signal transmitted by the second clock signal terminal CK3 to the fourth node N4. At the same time, when at least one of the multiple selection control signal terminals DX transmits an operating voltage (high voltage), the second transistor T2 connected to the selection control signal terminal DX transmitting the operating voltage among the multiple second transistors T2 is turned on and transmits the second clock signal received by the fourth node N4 to the third node N3. Exemplarily, the first selection control signal terminal D1 transmits the operating voltage, the first selection transistor T31 electrically connected to the first selection control signal terminal D1 is turned on, and the first selection transistor T31 transmits the second clock signal received by the fourth node N4 to the third node N3. The shift register 310 is selected not to output a scan signal.

[0117] Alternatively, when the second clock signal terminal CK3 transmits the second clock signal, the first transistor T1 is turned on and transmits the second clock signal transmitted by the second clock signal terminal CK3 to the fourth node N4. Simultaneously, the plurality of selection control signal terminals DX all transmit a non-operating voltage (low voltage), and the plurality of second transistors T2 are all in an off state. The second clock signal received by the fourth node N4 is not transmitted to the third node N3, meaning that the first decoding sub-circuit 35 does not transmit an operating voltage signal to the third node N3. The shift register 310 is selected to output a scan signal.

[0118] FIG8 is an equivalent circuit diagram of a first decoding sub-circuit according to some embodiments.

[0119] In other embodiments, referring to FIG8 , the first decoding sub-circuit 35 is further electrically connected to the second voltage signal terminal VDD. The second voltage signal terminal VDD is used to transmit a second power supply voltage signal, which can be, for example, a high voltage. The first decoding sub-circuit 35 includes a first transistor T1 and a plurality of second transistors T2. The control electrode of the first transistor T1 is electrically connected to the second clock signal terminal CK3, the first electrode is electrically connected to the fifth node N5, and the second electrode is electrically connected to the third node N3. Each of the plurality of second transistors T2 has a control electrode electrically connected to a selection control signal terminal DX, and the plurality of first electrodes of the plurality of second transistors T2 are electrically connected to the second voltage signal terminal VDD, and the plurality of second electrodes of the plurality of second transistors T2 are electrically connected to the fifth node N5.

[0120] Exemplarily, the plurality of second transistors T2 are sequentially arranged as a first selection transistor T31, a second selection transistor T32, ..., an (N-1)th selection transistor T3(N-1), and an Nth selection transistor T3N. The control electrode of the first selection transistor T31 is electrically connected to the first selection control signal terminal D1, and the first selection control signal terminal D1 is electrically connected to the first group of first selection control signal lines KL1 or the first group of second selection control signal lines KL1, that is, the control electrode of the first selection transistor T31 is electrically connected to the first group of first selection control signal lines KL1 or the first group of second selection control signal lines KL1. The control electrode of the second selection transistor T32 is electrically connected to the second selection control signal terminal D2 and to the second group of first selection control signal lines KL2 or the second group of second selection control signal lines KL2, .... The control electrode of the Nth selection transistor T3N is electrically connected to the Nth selection control signal terminal DN and to the Nth group of first selection control signal lines KLN or the Nth group of second selection control signal lines KLN.

[0121] When at least one of the plurality of selection control signal terminals DX transmits an operating voltage (high voltage), the second transistor T2 connected to the selection control signal terminal DX electrically connected to the transmission of the operating voltage among the plurality of second transistors T2 turns on and transmits the second voltage signal transmitted by the second voltage signal terminal VDD to the fifth node N5. Exemplarily, when the first selection control signal terminal D1 transmits an operating voltage, the first selection transistor T31 electrically connected to the first selection control signal terminal D1 turns on and transmits the second voltage signal to the fifth node N5. Furthermore, when the second clock signal terminal CK3 outputs the second clock signal, the first transistor T1 turns on and transmits the second voltage signal received by the fifth node N5 to the third node N3. The shift register 310 is selected to not output a scan signal.

[0122] Alternatively, when the plurality of selection control signal terminals DX transmit non-operating voltages, the plurality of second transistors T2 are all in the cut-off state, and the second voltage signal transmitted by the second voltage signal terminal VDD is not transmitted to the fifth node N5.

[0123] Even when the second clock signal terminal CK3 transmits the second clock signal, the first transistor T1 is turned on. Since the fifth node N5 does not receive the second voltage signal, the third node N3 cannot receive the second voltage signal. In other words, the first decoding sub-circuit 35 does not transmit the operating voltage (second voltage signal) to the third node N2, and the selected shift register 310 does not output the scan signal.

[0124] Figure 9A is an equivalent circuit diagram of a shift register when the first control sub-circuit is the structure shown in Figure 7. Figure 9B is an equivalent circuit diagram of a shift register when the first control sub-circuit is the structure shown in Figure 8.

[0125] 9A and 9B , in some embodiments, the first control subcircuit 31 includes a seventeenth transistor T17. The control electrode and first electrode of the seventeenth transistor T17 are both electrically connected to the first clock signal terminal CK1, and the second electrode is electrically connected to the first node N1. When the first clock signal terminal CK1 transmits a first clock signal (high voltage), the seventeenth transistor T17 turns on and transmits the first clock signal to the first node N1, which then reaches a high voltage.

[0126] In some embodiments, as shown in Figures 9A and 9B, the shift register 310 further includes a first tank sub-circuit 39. The first tank sub-circuit 39 is electrically connected to the first voltage signal terminal VSS and the first node N1. The first tank sub-circuit 39 is configured to maintain the voltage of the first node N1. For example, after the seventeenth transistor T17 transmits the first clock signal to the first node N1 and the seventeenth transistor T17 is turned off, the first tank sub-circuit 39 maintains the voltage of the first node N1 at the first clock signal, thereby reducing the voltage attenuation of the first node N1.

[0127] As shown in Figures 9A and 9B , the first energy storage sub-circuit 39 includes a first capacitor C1, one plate of which is electrically connected to the first voltage signal terminal VSS, and the other plate of which is electrically connected to the first node N1. The first capacitor C1 has a bootstrap function and can maintain the voltage of the first node N1.

[0128] The first output sub-circuit 32 includes an eighteenth transistor T18. The control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, the first electrode is electrically connected to the first voltage signal terminal VSS, and the second electrode is electrically connected to the signal output terminal Out. When the first clock signal is transmitted to the first node N1, the eighteenth transistor T18 is turned on under the control of the voltage at the first node N1 (the first clock signal). The eighteenth transistor T18 transmits the first voltage signal transmitted by the first voltage signal terminal VSS to the signal output terminal Out, and the shift register 310 does not output the scan signal.

[0129] 9A and 9B , the second control subcircuit 33 includes a nineteenth transistor T19 and a twentieth transistor T20. The control electrode and first electrode of the nineteenth transistor T19 are both electrically connected to the second clock signal terminal CK3, and the second electrode is electrically connected to the first electrode of the twentieth transistor T20. The control electrode of the twentieth transistor T20 is electrically connected to the first node N1, and the second electrode is electrically connected to the second node N2. When the second clock signal terminal CK3 transmits the second clock signal (high voltage), the nineteenth transistor T19 turns on and transmits the second clock signal to the second electrode of the nineteenth transistor T19. Simultaneously, the twentieth transistor T20 turns on under the control of the voltage at the first node N1 and transmits the second clock signal from the second electrode of the nineteenth transistor T19 to the second node N2, which is at a high voltage.

[0130] In some embodiments, as shown in Figures 9A and 9B, the shift register 310 further includes a second energy storage sub-circuit 40. The second energy storage sub-circuit 40 is electrically connected to the signal output terminal Out and the second node N2, and is configured to maintain the voltage of the second node N2. For example, after the nineteenth transistor T19 and the twentieth transistor T20 transmit the second clock signal to the second node N2 and the nineteenth transistor T19 and the twentieth transistor T20 are turned off, the second energy storage sub-circuit 40 maintains the voltage of the second node N2 at the second clock signal, thereby reducing the voltage attenuation of the second node N2.

[0131] As shown in Figures 9A and 9B, the second energy storage sub-circuit 40 includes a second capacitor C2, one plate of which is electrically connected to the second node N2, and the other plate of which is electrically connected to the signal output terminal Out. The second capacitor C2 has a bootstrap function, capable of maintaining the voltage of the second node N2 and raising the voltage of the second node N2 when the voltage of the signal output terminal Out increases.

[0132] Continuing with Figures 9A and 9B , the second output sub-circuit 34 includes a twenty-first transistor T21. The control electrode of the twenty-first transistor T21 is electrically connected to the second node N2, the first electrode is electrically connected to the third clock signal terminal CK4, and the second electrode is electrically connected to the signal output terminal Out. When the second node N2 is at a high voltage, the twenty-first transistor T21 turns on. When the third clock signal terminal CK4 transmits the third clock signal, the second transistor T21 transmits the third clock signal to the signal output terminal Out, causing the shift register 310 to output a scan signal. When the third clock signal is transmitted to the signal output terminal Out, the voltage of the second node N2 is raised due to the bootstrap effect of the second capacitor C2.

[0133] Continuing with Figures 9A and 9B, in some embodiments, the third control subcircuit 36 ​​includes a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The sixth transistor T6 has a control electrode electrically connected to the third node N3, a first electrode electrically connected to the first voltage signal terminal VSS, and a second electrode electrically connected to the second node N2. The seventh transistor T7 has a control electrode electrically connected to the third node N3, a first electrode electrically connected to the first voltage signal terminal VSS, and a second electrode electrically connected to the signal output terminal Out. The eighth transistor T8 has a control electrode electrically connected to the second node N2, a first electrode electrically connected to the first voltage signal terminal VSS, and a second electrode electrically connected to the third node N3.

[0134] When the shift register 310 is selected not to output a scan signal, the first decoding sub-circuit 35 transmits the second clock signal (as shown in FIG. 9A ) or the second voltage signal (as shown in FIG. 9B ) to the third node N3, and the voltage at the third node N3 is high. The sixth transistor T6 is turned on by the high voltage at the third node N3 and transmits the first voltage signal from the first voltage signal terminal VSS to the second node N2. The second output sub-circuit 34 (the twenty-first transistor T21) is turned off by the first voltage signal at the second node N2. Even if the third clock signal terminal transmits the third clock signal, the signal output terminal Out does not output a scan signal. The voltage at the second node N2 remains low, and the eighth transistor T8 remains turned off by the voltage at the second node N2. The seventh transistor T7 is turned on by the high voltage at the third node N3 and transmits the first voltage signal from the first voltage signal terminal VSS to the signal output terminal Out, causing the signal output terminal Out to continuously output a low voltage. In other words, the signal output terminal Out does not output a scan signal. The eighth transistor T8 remains turned off under the control of the voltage of the second node N2 (non-operating voltage), and the voltage of the third node N3 remains the voltage signal (second clock signal or second voltage signal) transmitted to the third node N3 by the first decoding sub-circuit 35.

[0135] When the shift register 310 is selected to output a scan signal, the first decoding sub-circuit 35 does not transmit any voltage signal to the third node N3, and the voltage at the third node N3 is low. The sixth transistor T6 is in an off state under the control of the low voltage at the third node N3 and does not affect the voltage at the second node N2. The seventh transistor T7 is in an off state under the control of the low voltage at the third node N3 and does not affect the voltage at the second node N1. Based on this, under the control of the first clock signal, the seventeenth transistor T17 transmits the first clock signal to the first node N1. Under the action of the first capacitor C1, the voltage at the first node N1 can maintain the first clock signal, and the twentieth transistor T20 is turned on. Subsequently, under the control of the second clock signal, the nineteenth transistor T19 is turned on. The second clock signal is transmitted to the second node N2 via the nineteenth transistor T19 and the twenty-first transistor T20 in sequence. Under the action of the second capacitor C2, the voltage at the second node N2 can maintain the second clock signal, and the eighth transistor T8 and the twenty-first transistor T21 are turned on. The eighth transistor T8 is turned on, transmitting the first voltage signal of the first voltage signal terminal VSS to the third node N3, and the voltage of the third node N3 remains low. Then, the twenty-first transistor T21 is turned on, and the fourth clock signal of the fourth clock signal terminal CK4 can be transmitted to the signal output terminal Out, that is, the shift register 310 outputs the scan signal. And under the bootstrap effect of the second capacitor C2, the voltage of the second node N2 is raised.

[0136] Continuing with Figures 9A and 9B , in some embodiments, the shift register 310 further includes a third tank sub-circuit 41. The third tank sub-circuit 41 is electrically connected to the first voltage signal terminal VSS and the third node N3 and is configured to maintain the voltage at the third node N3. For example, after the first decoding sub-circuit 35 transmits the second clock signal or the second voltage signal to the third node N3 and the first transistor T1 is turned off, the third tank sub-circuit 41 can maintain the voltage at the third node N3 at a high voltage, thereby reducing voltage attenuation at the third node N3.

[0137] As shown in Figures 9A and 9B , the third energy storage sub-circuit 41 includes a third capacitor C3. One plate of the third capacitor C3 is electrically connected to the third node N3, and the other plate is electrically connected to the first voltage signal terminal VSS. The third capacitor C3 has a bootstrap function, capable of maintaining the voltage at the third node N2.

[0138] It should be understood that the capacitance sizes of the first capacitor C1, the second capacitor C2 and the third capacitor C3 can all be the same, or all different, or the capacitances of any two of them can be the same and different from the capacitance of the other. The capacitance sizes of the first capacitor C1, the second capacitor C2 and the third capacitor C3 can be set as needed, as long as the same technical ideas as those disclosed in the present invention are adopted.

[0139] In some embodiments, referring to Figures 9A and 9B , the shift register 310 further includes a reset sub-circuit 37 and an initialization sub-circuit 38. The reset sub-circuit 37 is electrically connected to the third clock signal terminal CK4, the first voltage signal terminal VSS, and the first node N1. Under the control of the third clock signal from the third clock signal terminal CK4, the reset sub-circuit 37 is configured to transmit the first voltage signal transmitted from the first voltage signal terminal VSS to the first node N1, thereby resetting the voltage of the first node N1 and preventing the voltage of the first node N1 from remaining in the next display cycle. The initialization sub-circuit 38 is electrically connected to the first clock signal terminal CK1, the first voltage signal terminal VSS, and the third node N3. Under the control of the first clock signal from the first clock signal terminal CK1, the initialization sub-circuit 38 is configured to transmit the first voltage signal VSS to the third node N3, thereby initializing the voltage of the third node N3.

[0140] As shown in FIG9B , the reset sub-circuit 37 includes a twenty-second transistor T22. The twenty-second transistor T22 has a control electrode electrically connected to the third clock signal terminal CK4, a first electrode electrically connected to the first voltage signal terminal VSS, and a second electrode electrically connected to the first node N1. When the third clock signal terminal CK4 transmits the third clock signal, the twenty-second transistor T22 turns on and transmits the first voltage signal transmitted by the first voltage signal terminal VSS to the first node N1, causing the voltage at the first node N1 to be low, thereby resetting the voltage at the first node N1.

[0141] The initialization sub-circuit 38 includes a twenty-third transistor T23. The control electrode of the twenty-third transistor T23 is electrically connected to the first clock signal terminal CK1, the first electrode is electrically connected to the first voltage signal terminal VSS, and the second electrode is electrically connected to the third node N3. When the first clock signal terminal CK1 transmits the first clock signal, the twenty-third transistor T23 is turned on and transmits the first voltage signal transmitted by the first voltage signal terminal VSS to the third node N3, thereby initializing the voltage of the third node N3.

[0142] FIG10 is a circuit structure diagram of the shift register when the third control sub-circuit is also connected to the first node.

[0143] Referring to Figure 10, in some embodiments, the third control sub-circuit 36 ​​is also electrically connected to the first node N1. The third control sub-circuit 36 ​​is also configured to transmit the first voltage signal from the first voltage signal terminal VSS to the first node N1 when the shift register 310 is selected not to output the scan signal, so as to make the first node N1 at a non-working voltage and control the second control sub-circuit 33 (the twentieth transistor T20) to be cut off.

[0144] FIG11 is an equivalent circuit diagram of the shift register shown in FIG10 .

[0145] 11 , in some embodiments, the third control subcircuit 36 ​​further includes a tenth transistor T10 having a control electrode electrically connected to the third node N3 , a first electrode electrically connected to the first voltage signal terminal VSS, and a second electrode electrically connected to the first node N1 .

[0146] It is understood that when the third control sub-circuit 36 ​​includes the tenth transistor T10, the first decoding sub-circuit 35 can have the structure shown in FIG7 or the structure shown in FIG8 . FIG10 only illustrates the first decoding sub-circuit 35 having the structure shown in FIG8 as an example. Based on the present application, those skilled in the art can combine the above-mentioned multiple embodiments to obtain different embodiments. All embodiments obtained by combining different embodiments fall within the scope of protection of the present application.

[0147] Continuing to refer to FIG. 11 , as described above, when the shift register 310 is selected not to output the scan signal, the first decoding sub-circuit 35 transmits the second voltage signal to the third node N3, and the tenth transistor T10 is turned on under the control of the second voltage signal. The tenth transistor T10 transmits the first voltage signal transmitted by the first voltage signal terminal VSS to the first node N1, so that the first node N1 is at a non-operating voltage. The voltage of the first node N1 controls the twentieth transistor T20 to be in a turned-off state, and the second control sub-circuit 33 cannot transmit the second clock signal from the second clock signal terminal CK3 to the second node N2.

[0148] When the shift register 310 is selected to output a scan signal, the voltage of the third node N3 is a low voltage, the tenth transistor T10 is in a closed state, and will not affect the voltage of the first node N1. The seventeenth transistor T17 can transmit the first clock signal to the first node N1 under the control of the first clock signal, and keep the voltage of the first node N1 at a high voltage.

[0149] FIG. 12 is an equivalent circuit diagram of a shift register including a leakage protection electronic circuit.

[0150] 12 , in some embodiments, the sixth transistor T6 is a dual-gate transistor comprising two sub-transistors connected in series, which are connected via a seventh node N7 , thereby reducing leakage current of the sixth transistor T6 and the voltage drop at the second node N2 .

[0151] Exemplarily, the two sub-transistors are a first sub-transistor T61 and a second sub-transistor T62. The first sub-transistor T61 has a control electrode electrically connected to the third node N3, a first electrode electrically connected to the first voltage signal terminal VSS, and a second electrode electrically connected to the seventh node N7. The second sub-transistor T62 has a control electrode electrically connected to the third node N3, a first electrode electrically connected to the seventh node N7, and a second electrode electrically connected to the second node N2.

[0152] The shift register 310 further includes an anti-leakage electronic circuit 45 electrically connected to the second node N2, the second voltage signal terminal VDD, and the seventh node N7. The anti-leakage electronic circuit 45 is configured to transmit the second voltage signal from the second voltage signal terminal VDD to the seventh node N7 under control of the voltage at the second node N2. For example, when the second control sub-circuit 33 transmits the second clock signal to the second node N2, the voltage at the second node N2 is high. The second node N2 controls the anti-leakage electronic circuit 45 to transmit the second voltage signal to the seventh node N7, thereby reducing the voltage difference between the first and second electrodes of the second sub-transistor T62 (the seventh node N7 and the second node N2), thereby reducing the leakage current of the second sub-transistor T62.

[0153] Referring to FIG. 12 , in some embodiments, the leakage prevention circuit 45 includes a ninth transistor T9. The ninth transistor T9 has a control electrode electrically connected to the second node N2, a first electrode electrically connected to the second voltage signal terminal VDD, and a second electrode electrically connected to the seventh node N7. Exemplarily, when the voltage at the second node N2 is high, the ninth transistor T9 is turned on and transmits the second voltage signal to the seventh node N7.

[0154] FIG13 is a structural diagram of a shift register including a time-sharing selection subcircuit and a fourth control subcircuit.

[0155] Referring to FIG. 13 , in some embodiments, the shift register 310 further includes a time-sharing selection subcircuit 46 and a fourth control subcircuit 47. The time-sharing selection subcircuit 46 is electrically connected to the second control signal terminal K2, the third control signal terminal K3, the first decoding subcircuit 35, the third node N3, and the eighth node N8. The time-sharing selection subcircuit 46 is configured to electrically connect the first decoding subcircuit 35 to the third node N3 under the control of a second control signal from the second control signal terminal K2, and to electrically connect the first decoding subcircuit 35 to the eighth node N8 under the control of a third control signal from the third control signal terminal K3. The first decoding subcircuit 35 is electrically connected to the third node N4 via the time-sharing selection subcircuit 46.

[0156] Exemplarily, within one display cycle, one of the second control signal terminal and the third control signal terminal transmits a corresponding control signal. For example, within one display cycle, the second control signal terminal K2 transmits the second control signal, or the third control signal terminal K3 transmits the third control signal.

[0157] For example, in different display cycles, the second control signal terminal K2 and the third control signal terminal K3 alternately output corresponding control signals. For example, in two consecutive display cycles, the second control signal terminal K2 transmits the second control signal in one display cycle, and the third control signal terminal K3 transmits the third control signal in the other display cycle. In this way, the signal output by the first decoding sub-circuit 35 (such as the second voltage signal or the second clock signal) can be alternately transmitted to the third node N3 and the eighth node N8.

[0158] The fourth control subcircuit 47 is electrically connected to the first voltage signal terminal VSS, the second node N2, the eighth node N8, and the signal output terminal Out. When the shift register 310 is selected not to output a scan signal, the fourth control subcircuit 47 is configured to transmit the first voltage signal from the first voltage signal terminal VSS to the first node N1, the second node N2, and the signal output terminal Out. When the shift register 310 is selected to output a scan signal, the fourth control subcircuit 47 transmits the first voltage signal from the first voltage signal terminal VSS to the eighth node N8. The fourth control subcircuit 47 can perform the same function as the third control subcircuit 46. Consequently, the third control subcircuit 36 ​​and the fourth control subcircuit 47 can alternately control the voltages of the second node N2 and the signal output terminal Out during different display cycles, preventing the transistors controlled by the third node N3 (e.g., the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10) from being in the same bias state for extended periods, thereby reducing the risk of threshold voltage drift in the transistors controlled by the third node N3 preventing them from properly turning on or off.

[0159] FIG14 is an equivalent circuit diagram of a shift register including a time-sharing selection sub-circuit and a fourth control sub-circuit.

[0160] Referring to FIG. 14 , in some embodiments, the time-sharing selection sub-circuit 46 includes an eleventh transistor T11 and a twelfth transistor T12. The eleventh transistor T11 has a control electrode electrically connected to the second control signal terminal K2, a first electrode electrically connected to the first decoding sub-circuit 35 (e.g., the second electrode of the first transistor T1), and a second electrode electrically connected to the third node N3. The twelfth transistor T12 has a control electrode electrically connected to the third control signal terminal K3, a first electrode electrically connected to the first decoding sub-circuit 35 (e.g., the second electrode of the first transistor T1), and a second electrode electrically connected to the eighth node N8.

[0161] For example, when the first decoding sub-circuit 35 selects the shift register 310 to not output a scan signal, the first decoding sub-circuit 35 transmits the second voltage signal to the time-sharing selection sub-circuit 46. During the first display period, the second control signal terminal K2 transmits the second control signal, the eleventh transistor T11 turns on, and the eleventh transistor T11 transmits the second voltage signal to the third node N3. Simultaneously, the third control signal terminal K3 does not transmit the third control signal, the twelfth transistor T12 turns off, and the second voltage signal is not transmitted to the eighth node N8. The third control sub-circuit 36 ​​transmits the first voltage signal to the second node N2 and the signal output terminal Out. During the second display period, the third control signal terminal K3 transmits the third control signal, the twelfth transistor T12 turns on, and the twelfth transistor T12 transmits the second voltage signal to the eighth node N8. Simultaneously, the second control signal terminal K2 does not transmit the second control signal, the eleventh transistor T11 turns off, and the second voltage signal is not transmitted to the third node N3. The fourth control sub-circuit 47 transmits the first voltage signal to the second node N2 and the signal output terminal Out.

[0162] Continuing with FIG. 14 , in some embodiments, the fourth control subcircuit 47 includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16. The control electrode of the thirteenth transistor T13 is electrically connected to the eighth node N8, a first electrode is electrically connected to the first voltage signal terminal VSS, and a second electrode is electrically connected to the second node N2. The control electrode of the fourteenth transistor T14 is electrically connected to the eighth node N8, a first electrode is electrically connected to the first voltage signal terminal VSS, and a second electrode is electrically connected to the signal output terminal Out. The control electrode of the fifteenth transistor T15 is electrically connected to the second node N2, a first electrode is electrically connected to the first voltage signal terminal VSS, and a second electrode is electrically connected to the eighth node N8. The control electrode of the sixteenth transistor T16 is electrically connected to the eighth node N8, a first electrode is electrically connected to the first voltage signal terminal VSS, and a second electrode is electrically connected to the first node N1.

[0163] When the shift register 310 is selected not to output a scan signal and the time-sharing selection sub-circuit 46 transmits the second voltage signal from the second voltage signal terminal VDD to the eighth node N8, the voltage (second voltage signal) at the eighth node N8 controls the thirteenth transistor T13, the fourteenth transistor T14, and the sixteenth transistor T16 to conduct. The thirteenth transistor T13 transmits the first voltage signal from the first voltage signal terminal VSS to the second node N2, and the voltage at the second node N2 is low. The fourteenth transistor T14 transmits the first voltage signal from the first voltage signal terminal VSS to the signal output node Out, and the signal output node Out outputs a low voltage, i.e., no scan signal is output. The sixteenth transistor T16 transmits the first voltage signal from the first voltage signal terminal VSS to the first node N1, and the first node N1 remains at a low voltage. The voltage at the second node N2 is low, and the fifteenth transistor T15 is turned off under the control of the second node N2, without affecting the voltage at the third node N3.

[0164] In some embodiments, as shown in FIG14 , the shift register 310 may further include a twenty-fourth transistor T24 and a fourth capacitor C4. The twenty-fourth transistor T24 has a control electrode electrically connected to the first clock signal terminal CK1, a first electrode electrically connected to the first voltage signal terminal VSS, and a second electrode electrically connected to the eighth node N8. When the first clock signal terminal CK1 transmits a first clock signal, the twenty-fourth transistor T24 turns on and transmits the first voltage signal transmitted by the first voltage signal terminal VSS to the eighth node N8, thereby initializing the voltage of the third node N3. One plate of the fourth capacitor C4 is electrically connected to the first voltage signal terminal VSS, and the other plate is electrically connected to the eighth node N8. The fourth capacitor C4 is configured to maintain the voltage of the eighth node N8.

[0165] FIG. 4B is another driving timing diagram of the pixel circuit 100 shown in FIG. 3 .

[0166] During the display process of the display panel, in order to reduce the problem of image smear (afterimage) when switching between dynamic images, black insertion is generally performed between the display frames to improve the motion picture response time (MPRT enhancement) of the displayed image. Referring to Figures 3 and 4B , in some embodiments, the pixel circuit 100 may further include a black insertion data writing phase M103 and a black insertion holding phase M104 between the light emitting phase M102 and the sensing phase M105.

[0167] In the black insertion data writing phase M103 , the first scanning signal terminal G1 and the second scanning signal terminal G2 output high voltages, the data writing transistor T101 and the sensing transistor T103 are turned on, and the data writing transistor T101 transmits the black insertion data signal transmitted by the data line DL to the first circuit node S1 .

[0168] In the black insertion holding phase M104, the first scan signal terminal G1 and the second scan signal terminal G2 output low voltages, the data writing transistor T101 and the sensing transistor T103 are both turned off, the driving transistor T102 is turned off under the control of the black insertion data signal, and the light emitting device stops emitting light.

[0169] FIG15 is a circuit structure diagram of a shift register including a black insertion control subcircuit.

[0170] 15 , in some embodiments, when the first decoding sub-circuit 35 has the structure shown in FIG8 , the shift register 310 further includes a black insertion control sub-circuit 42. The black insertion control sub-circuit 42 is electrically connected to the first control signal terminal K1, the fifth node N5, and the signal output terminal Out, and is configured to transmit the voltage of the fifth node N1 to the signal output terminal Out under the control of the first control signal K1 from the first control signal terminal K1.

[0171] When black insertion data needs to be written, the rows requiring black insertion can be selected through multiple sets of selection control signal lines KL, and at least one second transistor T2 among the multiple second transistors T2 is turned on to transmit the second voltage signal transmitted by the second voltage signal terminal VDD to the fifth node N5. The first control signal terminal K1 transmits a first control signal to transmit the second voltage signal received by the fifth node N5 to the signal output terminal Out, thereby enabling the shift register 310 to output a scan signal.

[0172] It is understandable that when black data insertion is required, the first clock signal terminal CK1 , the second clock signal terminal CK2 and the third clock signal terminal CK3 do not transmit corresponding clock signals to prevent the first decoding sub-circuit 35 from affecting the voltage of the third node N3 .

[0173] FIG16 is an equivalent circuit diagram of a shift register including a black insertion control subcircuit.

[0174] 16 , in some embodiments, the black insertion control subcircuit 42 includes a third transistor T3 , the control electrode of the third transistor T3 being electrically connected to the first control signal terminal K1 , the first electrode being electrically connected to the fifth node N5 , and the second electrode being electrically connected to the signal output terminal Out.

[0175] When black data insertion is required, at least one second transistor T2 (e.g., the first selection transistor T31) among the plurality of second transistors T2 is turned on, and the at least one turned-on second transistor T2 transmits the second voltage signal to the fifth node N5. The third transistor T3 is turned on under the control of the first control signal from the first control signal terminal K1, and transmits the second voltage signal received at the fifth node N5 to the signal output terminal Out, thereby enabling the shift register 310 to output a scan signal.

[0176] FIG17 is a circuit structure diagram of a shift register including a second decoding sub-circuit.

[0177] In other embodiments, referring to FIG. 17 , the shift register 310 may further include a second decoding sub-circuit 43 . The second decoding sub-circuit 43 is configured to control the shift register 310 to output a scanning signal when black insertion data needs to be written.

[0178] The second decoding sub-circuit 43 is electrically connected to a plurality of black insertion control signal terminals EX, a first control signal terminal K1, a second voltage signal terminal VDD, and a signal output terminal Out. For example, as shown in FIG17 , the second decoding sub-circuit 43 is electrically connected to M black insertion control signal terminals EX, where M is a positive integer greater than 0. The M black insertion control signal terminals EX are sequentially arranged as a first black insertion control signal terminal E1, a second black insertion control signal terminal E2, ..., an (M-1)th black insertion control signal terminal E(M-1), and an Mth black insertion control signal terminal EM.

[0179] The second decoding sub-circuit 43 is further configured to transmit a second voltage signal from the second voltage signal terminal VDD to the signal output terminal Out under the control of a black insertion control signal from at least one black insertion control signal terminal EX and a first control signal from the first control signal terminal K1. When the at least one black insertion control signal terminal EX transmits the black insertion control signal and the first control signal terminal K1 transmits the first control signal, the second decoding sub-circuit 43 transmits the second voltage signal to the signal output terminal Out, and the shift register 310 outputs a scan signal, driving the pixel circuit to implement the black insertion data writing function.

[0180] Figure 18 is an equivalent circuit diagram of a shift register including a second decoding sub-circuit, wherein Figure 18 illustrates the first decoding sub-circuit 35 as shown in Figure 8 . It is understood that the first decoding sub-circuit 35 may also be as shown in Figure 7 .

[0181] Referring to FIG. 18 , in some embodiments, the second decoding sub-circuit includes a plurality of fourth transistors T4 and a fifth transistor T5. A control electrode of each of the plurality of fourth transistors T4 is electrically connected to a black insertion control signal terminal EX, and a plurality of first electrodes of the plurality of fourth transistors T4 are electrically connected to the second voltage signal terminal VDD, and a plurality of second electrodes of the plurality of fourth transistors T4 are electrically connected to a sixth node N6. The control electrode of the fifth transistor T5 is electrically connected to the first control signal terminal K1, a first electrode is electrically connected to the sixth node N6, and a second electrode is electrically connected to the signal output terminal Out.

[0182] Exemplarily, the second decoding sub-circuit includes M fourth transistors T4, which are sequentially arranged as a first black insertion control transistor T41, a second black insertion control transistor T42, ..., an (M-1)th black insertion control transistor T2(M-1), and an Mth black insertion control transistor T4M. The control electrode of the first black insertion control transistor T41 is electrically connected to the first black insertion control signal terminal E1, the control electrode of the second black insertion control transistor T42 is electrically connected to the second black insertion control signal terminal E2, ..., the control electrode of the (M-1)th black insertion control transistor T2(M-1) is electrically connected to the (M-1)th black insertion control signal terminal E(M-1), and the control electrode of the Mth black insertion control transistor T4M is electrically connected to the Mth black insertion control signal terminal EM.

[0183] When at least one of the M black insertion control signal terminals EX transmits a black insertion control signal, the fourth transistor T4 electrically connected to the black insertion control signal terminal EX transmitting the black insertion control signal is turned on, and the turned-on fourth transistor T4 transmits the second voltage signal to the sixth node N6. For example, when the first black insertion control signal terminal E1 transmits the black insertion control signal, the first black insertion control transistor T41 electrically connected to the first black insertion control signal terminal E1 is turned on, and the first black insertion control transistor T41 transmits the second voltage signal to the sixth node N6.

[0184] FIG19 is an equivalent circuit diagram when a plurality of black insertion control signal terminals and a plurality of selection control signal terminals are in one-to-one correspondence.

[0185] Referring to FIG. 19 , in some embodiments, the number of the plurality of black insertion control signal terminals EX and the number of the plurality of selection control signal terminals DX are equal and correspond one-to-one. In other words, the number of the black insertion control signal terminals EX is equal to the number of the selection control signal terminals DX. Thus, the number of the second transistors T2 is equal to the number of the fourth transistors T4, i.e., M=N.

[0186] The black insertion control signal terminal EX and the selection control signal terminal DX corresponding to the black insertion control signal terminal EX are the same signal terminal. For example, the first black insertion control signal terminal E1 and the first selection control signal terminal D1 are the same signal terminal, the second black insertion control signal terminal E2 and the second selection control signal terminal D2 are the same signal terminal, ..., the Mth black insertion control signal terminal EM and the Nth selection control signal terminal DN are the same signal terminal. This helps simplify the structure of the shift register 310 and the structure of the gate drive circuit.

[0187] Alternatively, at least one black insertion control signal terminal EX and the selection control signal terminal DX corresponding to the black insertion control signal terminal EX are different signal terminals. For example, the first black insertion control signal terminal E1 and the first selection control signal terminal D1 are different signal terminals. Thus, while the first selection control signal terminal D1 is electrically connected to the first group of first selection control signal lines KL1, the first black insertion control signal terminal E1 can be electrically connected to the first group of second selection control signal lines KL1. In other words, the first decoding sub-circuit 35 and the second decoding sub-circuit 43 share multiple groups of selection control signal lines KL. This reduces the number of signal lines used to control the gate drive circuit, facilitating a reduction in the width of the peripheral area BB and enabling a narrow bezel for the display device.

[0188] It should be understood that in some other embodiments, the number of black insertion control signal terminals EX and the number of selection control signal terminals DX may differ, that is, the number of second transistors T2 and the number of fourth transistors T4 may differ. For example, if the number of black insertion control signal terminals EX is less than the number of selection control signal terminals DX, that is, M < N; in this case, the second decoding sub-circuit 43 can still share multiple sets of selection control signal lines KL with the first decoding sub-circuit 35. Alternatively, if the number of black insertion control signal terminals EX is greater than the number of selection control signal terminals DX, that is, M > N; in this case, the N fourth transistors T4 of the second decoding sub-circuit 43 can share multiple sets of selection control signal lines KL with the first decoding sub-circuit 35, and the remaining fourth transistors T4 can be controlled by other signal lines. Alternatively, regardless of whether the number of black insertion control signal terminals EX is the same as the number of selection control signal terminals DX, the first decoding sub-circuit 35 and the second decoding sub-circuit 43 can be controlled by different signal lines.

[0189] 20 to 22 are equivalent circuit diagrams of the shift register 310 obtained by combining the above-mentioned multiple embodiments.

[0190] It is understandable that the above-mentioned embodiments may be implemented individually, or multiple embodiments may be selected and implemented in combination.

[0191] For example, referring to FIG20 , the first electrode and the control electrode of the first transistor T1 of the first decoding sub-circuit 35 are electrically connected to the first clock signal terminal CK1, the second electrode is electrically connected to the first electrode of the second transistor T2, and the second electrode of the second transistor T2 is electrically connected to the third node N3 and the eighth node N8 through the time-sharing control sub-circuit 46.

[0192] For example, referring to FIG. 21 , the first transistor T1 of the first decoding sub-circuit 35 has its first electrode and control electrode electrically connected to the first clock signal terminal CK1, its second electrode electrically connected to the first electrode of the second transistor T2, and its second electrode electrically connected to the third node N3. The shift register 310 also includes a second decoding sub-circuit 43. The structure and connection relationship of the second decoding sub-circuit 43 are described above and will not be further described here.

[0193] For example, referring to FIG. 22 , the first decoding sub-circuit 35 is also electrically connected to the second voltage signal terminal VDD, the first electrode of the second transistor T2 is electrically connected to the second voltage signal terminal VDD, and the second electrode of the second transistor T2 is electrically connected to the first electrode of the first transistor T1. The shift register 310 also includes a black insertion control sub-circuit 42, a time-sharing control sub-circuit 46, and a fourth control sub-circuit 47. The structures and connections of the black insertion control sub-circuit 42, the time-sharing control sub-circuit 46, and the fourth control sub-circuit 47 are described above and will not be further described here.

[0194] It is understood that the shift register 310 may also have various other embodiments and combinations thereof. The above embodiments only include some, not all, embodiments, as long as the same technical principles are adopted. For example, based on any of the embodiments of Figures 20 to 22 , the sixth transistor T6 may be configured as a dual-gate transistor and an anti-leakage electronic circuit may be added. This disclosure does not list all of these embodiments one by one.

[0195] 5 , in some embodiments, among the multiple shift registers 310 included in the gate driving circuit 300, every four shift registers 310 form a shift register group 310 ′, and the four shift registers 310 included in the shift register group 310 ′ are arranged sequentially as a first-stage shift register 311, a second-stage shift register 312, a third-stage shift register 313, and a fourth-stage shift register 314.

[0196] The gate drive circuit 300 further includes a first clock signal line CL1, a second clock signal line CL2, a third clock signal line CL3, and a fourth clock signal line CL4. The first clock signal line CL1 is electrically connected to the first clock signal terminal CK1 of the first-stage shift register 311, the third clock signal terminal CK4 of the second-stage shift register 312, and the second clock signal terminal CK3 of the third-stage shift register 313. The second clock signal line CL2 is electrically connected to the first clock signal terminal CK1 of the second-stage shift register 312, the third clock signal terminal CK4 of the third-stage shift register 313, and the second clock signal terminal CK3 of the fourth-stage shift register 314. The third clock signal line CL3 is electrically connected to the second clock signal terminal CK3 of the first-stage shift register 311, the first clock signal terminal CK1 of the third-stage shift register 313, and the third clock signal terminal CK4 of the fourth-stage shift register 414. The fourth clock signal line CL4 is electrically connected to the third clock signal terminal CK4 of the first stage shift register 311 , the second clock signal terminal CK3 of the second stage shift register 312 , and the first clock signal terminal CK1 of the fourth stage shift register 314 .

[0197] The first clock signal terminal CK1 of the first-stage shift register 311 is electrically connected to the first clock signal line CL1, the first clock signal terminal CK1 of the second-stage shift register 312 is electrically connected to the second clock signal line CL2, the first clock signal terminal CK1 of the third-stage shift register 313 is electrically connected to the third clock signal line CL3, and the first clock signal terminal CK1 of the fourth-stage shift register 314 is electrically connected to the fourth clock signal line CL4.

[0198] The second clock signal terminal CK3 of the first-stage shift register 311 is electrically connected to the third clock signal line CL3, the second clock signal terminal CK3 of the second-stage shift register 312 is electrically connected to the fourth clock signal line CL4, the second clock signal terminal CK3 of the third-stage shift register 313 is electrically connected to the first clock signal line CL1, and the second clock signal terminal CK3 of the fourth-stage shift register 314 is electrically connected to the second clock signal line CL2.

[0199] The third clock signal terminal CK4 of the first-stage shift register 311 is electrically connected to the fourth clock signal line CL4, the third clock signal terminal CK4 of the second-stage shift register 312 is electrically connected to the first clock signal line CL1, the third clock signal terminal CK4 of the third-stage shift register 313 is electrically connected to the second clock signal line CL2, and the third clock signal terminal CK3 of the fourth-stage shift register 314 is electrically connected to the third clock signal line CL3.

[0200] Based on this, the first decoding sub-circuit 35 and the first clock signal line CL1, the second clock signal line CL2, the third clock signal line CL3 and the fourth clock signal line CL4 can enable the shift register 310 to compile (4×2 N ) different compilation states. For example, when N is 10, a total of (4×2 10 )=4096. It can be applied to at least a display device with a resolution of 4K×2K. It should be noted that a display device with a resolution of 4K×2K includes 2160 rows of sub-pixels.

[0201] In some embodiments, the first clock signal line CL1, the second clock signal line CL2, the third clock signal line CL3, and the fourth clock signal line CL4 sequentially transmit operating voltages (as shown in FIG. 23 and FIG. 24 ). Furthermore, one of the two selection control signal lines KL in each group of selection control signal lines KL transmits an operating voltage, and the other transmits a non-operating voltage.

[0202] When the shift register 310 includes the second decoding sub-circuit 43, the second decoding sub-circuit 43 is electrically connected to one selection control signal line KL in each group of selection control signal lines KL, and each selection control signal line forms a black insertion control signal terminal EX. The first decoding sub-circuit 35 and the second decoding sub-circuit 43 share multiple groups of selection control signal lines KL. This reduces the number of signal lines used to control the gate drive circuit, facilitating a reduction in the width of the peripheral area BB and enabling a narrow bezel for the display device.

[0203] The embodiment of the present disclosure further provides a driving method of the shift register 310. One display period (one frame period) includes a selection phase M10 and an output phase M20.

[0204] When the shift register 310 is selected not to output the scan signal, the driving method includes:

[0205] In the selection stage M10 (not shown in the figure), at least one of the multiple selection control signal terminals DX (D1~DN) outputs the operating voltage (high voltage), the first decoding sub-circuit 35 transmits the operating voltage (second voltage signal) to the third node N3, and the third control sub-circuit 36 ​​transmits the first voltage signal to the second node N2 and the third node N3 under the control of the operating voltage of the third node N3.

[0206] In the output phase M20 , the second output sub-circuit 34 does not output the scan signal under the control of the first voltage signal at the second node N2 .

[0207] FIG23 is a control timing diagram of a shift register according to some embodiments. FIG23 is driven based on the circuit structure of the shift register 310 shown in FIG11 . In the shift register shown in FIG11 , the first clock signal terminal CK1 is electrically connected to the first clock signal line CL1, the second clock signal terminal CK3 is electrically connected to the third clock signal line CL3, and the fourth clock signal terminal CK4 is electrically connected to the fourth clock signal line CL4.

[0208] When the shift register is selected to output a scan signal, referring to FIG. 23 , the driving method includes:

[0209] In the selection phase M10 , the plurality of selection control signal terminals DX ( D1 ˜DN) all transmit a non-operating voltage, and the first control sub-circuit 31 and the second control sub-circuit 33 transmit the second clock signal from the second clock signal terminal CK3 to the second node N2 .

[0210] In the output phase M20 , the second output sub-circuit 34 transmits the third clock signal from the third clock signal terminal CK4 to the signal output terminal Out under the control of the voltage of the second node N2 .

[0211] Continuing to refer to FIG. 23 , in some embodiments, the selection stage M10 includes a first stage M11 and a third stage M13 that are sequentially arranged.

[0212] In the first phase M11 , the first control sub-circuit 31 transmits the first clock signal to the first node N1 under the control of the first clock signal from the first clock signal terminal CK1 (first clock signal line CL1 ).

[0213] Exemplarily, as shown in Figure 11, in the first stage M11, the first clock signal terminal CK1 transmits the first clock signal (high voltage), the seventeenth transistor T17 is turned on, and the seventeenth transistor T17 transmits the first clock signal from the first clock signal terminal CK1 to the first node N1; the voltage of the first node N1 is a high voltage.

[0214] The eighteenth transistor T18 is turned on under the control of the voltage of the first node N1 , and transmits the first voltage signal from the first voltage signal terminal VSS to the signal output terminal Out. The signal output terminal Out does not output the scan signal.

[0215] The 23rd transistor T23 is turned on and transmits the first voltage signal from the first voltage signal terminal VSS to the third node N3. The voltage of the third node N3 is low. The sixth transistor T6, the seventh transistor T7 and the tenth transistor T10 are turned off under the control of the low voltage of the third node N3.

[0216] In some embodiments, as shown in FIG. 23 , the selection stage M10 further includes a second stage M12 disposed between the first stage M11 and the third stage M13 .

[0217] In the second phase M12, the second clock signal line CL2 transmits the second clock signal. Since the shift register 310 is not connected to the second clock signal line CL2, it does not affect the voltages of the nodes of the shift register 310. The first clock signal terminal CK1 becomes low, the seventeenth transistor T17 is turned off, and the voltage of the first node N1 remains unchanged due to the action of the first capacitor C1.

[0218] 23 , in the third phase M13 , the second control sub-circuit 33 transmits the second clock signal CK3 to the second node N2 under the control of the second clock signal from the second clock signal terminal CK3 and the first clock signal of the first node N1 .

[0219] Exemplarily, as shown in FIG11 , in the third stage M13 , the second clock signal terminal CK3 transmits the second clock signal (high voltage), the nineteenth transistor T19 is turned on, and the nineteenth transistor T19 transmits the second clock signal from the second clock signal terminal CK3 to the second electrode of the nineteenth transistor T19 .

[0220] The seventeenth transistor T17 is turned off, and the first node N1 maintains a high voltage under the action of the first capacitor C1. The twentieth transistor T20 is turned on under the control of the first node N1. The twentieth transistor T20 further transmits the second clock signal transmitted to the second electrode of the nineteenth transistor T19 to the second node N2, and the voltage of the second node N2 is a high voltage.

[0221] The first transistor T1 is turned on, and since the plurality of second transistors T2 are all in the off state, the third node N3 has no signal output and maintains a low voltage.

[0222] The eighth transistor T8 is turned on under the control of the high voltage of the second node N2, and transmits the first voltage signal of the first voltage signal terminal VSS to the third node N3, and the third node N3 continues to maintain a low voltage.

[0223] During the output phase M20, the nineteenth transistor T19 is turned off, the second node N2 maintains a high voltage due to the action of the second capacitor C2, and the twenty-first transistor T21 is turned on. The third clock signal terminal CK4 transmits the third clock signal, and the twenty-first transistor T21 transmits the third clock signal from the third clock signal terminal CK4 to the signal output terminal Out. The signal output terminal Out outputs a high-voltage scan signal. As the voltage of the signal output terminal Out increases, the voltage of the second node N2 is also raised due to the bootstrap effect of the second capacitor C2.

[0224] The third clock signal terminal CK4 transmits the third clock signal, the 22nd transistor T22 is turned on, the 22nd transistor T22 transmits the first voltage signal to the first node N1, the voltage of the first node N1 is a low voltage, the 20th transistor T20 is turned off, and the voltage of the first node N1 is reset.

[0225] Continuing to refer to FIG. 23 , after the output phase M20 , the display cycle further includes a reset phase M30 and an initialization phase M40 .

[0226] In the reset phase M30 , the first clock signal terminal CK1 (first clock signal line CL1 ) transmits the first clock signal, the seventeenth transistor T17 is turned on, and the seventeenth transistor T17 transmits the first clock signal to the first node N1 , and the voltage of the first node N1 is a high voltage.

[0227] The eighteenth transistor T18 is turned on by the high voltage of the first node N1, and transmits the first voltage signal from the first voltage signal terminal VSS to the signal output terminal Out, and the signal output terminal Out stops outputting the high voltage scan signal.

[0228] During the initialization phase M40, at least one selection control signal terminal DX transmits an operating voltage, and the second transistor T2 transmits the second voltage signal from the second voltage signal terminal VDD to the fifth node N5. The second clock signal terminal CK3 transmits the second clock signal, and the first transistor T1 is turned on. The first transistor T1 transmits the second voltage signal received by the fifth node N5 to the third node N3, and the voltage of the third node N3 is a high voltage.

[0229] The sixth transistor T6 is turned on by the high voltage at the third node N3, and transmits the first voltage signal to the second node N2, thereby initializing the voltage at the second node N2. The seventh transistor T7 is turned on by the high voltage at the third node N3, and transmits the first voltage signal to the signal output terminal Out. The signal output terminal Out does not output the scan signal. The tenth transistor T10 is turned on by the high voltage at the third node N3, and transmits the first voltage signal to the first node N1, thereby initializing the voltage at the first node N1.

[0230] 19 , in some embodiments, when the shift register 310 includes the second decoding sub-circuit 43 , a display cycle further includes a black insertion phase M50 after the output phase M20 . It is understood that the black insertion phase M50 is also after the initialization phase M40 .

[0231] FIG24 is a control timing diagram of a shift register according to some embodiments, wherein FIG24 is driven based on the circuit structure of the shift register 310 shown in FIG19 .

[0232] Referring to FIG. 24 , the driving method further includes:

[0233] In the black insertion stage M50, referring to FIG. 24 , the second decoding sub-circuit 43 transmits the second voltage signal from the second voltage signal terminal VDD to the signal output terminal Out under the control of the black insertion control signal (selection control signal) from at least one black insertion control signal terminal EX (selection control signal terminal DX) and the first control signal from the first control signal terminal K1. The signal output terminal Out then outputs the scan signal.

[0234] 19 and 23 , the first black insertion control signal terminal E1 transmits a black insertion control signal, the first black insertion control transistor T41 electrically connected to the first black insertion control signal terminal E1 is turned on, and the first black insertion control transistor T41 transmits the second voltage signal transmitted by the second voltage signal terminal VDD to the sixth node N6.

[0235] The fifth transistor T5 is turned on under the control of the first control signal from the first control signal terminal K1 , and transmits the second voltage signal received by the sixth node N6 to the signal output terminal Out, and the signal output terminal Out outputs the scan signal.

[0236] Of course, in some other embodiments, referring to FIG13 , when the shift register 310 includes the black insertion control subcircuit 42 , a display cycle also includes a black insertion phase M50 after the output phase M20 . It is understood that the black insertion phase M50 also occurs after the initialization phase M40 .

[0237] During the black insertion phase M50, the first decoding sub-circuit 35 transmits the second voltage signal to the fifth node N5 under the control of at least one selection control signal DX. The black insertion control sub-circuit 42 transmits the second voltage signal received at the fifth node N5 to the signal output terminal Out under the control of the first control signal from the first control signal terminal K1. The signal output terminal Out then outputs the scan signal. It will be appreciated that the driving methods of the shift register shown in FIG13 and the shift register shown in FIG19 are similar and will not be further described here.

[0238] In some embodiments, the display cycle may further include a sensing phase following the black insertion phase M50. During the sensing phase, a shift register may be selected by the first decoding sub-circuit to output a scan signal, and the scan signal may be output to the pixel row connected to the selected shift register. It will be appreciated that the driving method of the shift register during the sensing phase is similar to the driving method during the selection and output phases described above when the shift register is selected to output a scan signal, and will not be further described here.

[0239] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A shift register, comprising: A first control sub - circuit, electrically connected to a first clock signal terminal and a first node, and configured to transmit the first clock signal to the first node under the control of a first clock signal from the first clock signal terminal; A first output sub - circuit, electrically connected to the first node, a first voltage signal terminal, and a signal output terminal, and configured to transmit a first voltage signal from the first voltage signal terminal to the signal output terminal under the control of the voltage of the first node; A second control sub - circuit, electrically connected to the first node, a second clock signal terminal, and a second node, and configured to transmit the second clock signal to the second node under the control of a second clock signal from the second clock signal terminal and the voltage of the first node; A second output sub - circuit, electrically connected to the second node, a third clock signal terminal, and the signal output terminal, and configured to transmit a third clock signal from the third clock signal terminal to the signal output terminal under the control of the voltage of the second node; A first decoding sub - circuit, electrically connected to a plurality of selection control signal terminals, the second clock signal terminal, and a third node, and configured to select that the shift register does not output a scan signal under the control of an operating voltage from at least one selection control signal terminal and the second clock signal, or select that the shift register outputs a scan signal under the control of a non - operating voltage of each selection control signal terminal among the plurality of selection control signal terminals and the second clock signal; A third control sub - circuit, electrically connected to the first voltage signal terminal, the second node, the third node, and the signal output terminal, and configured to transmit the first voltage signal to the second node and the signal output terminal when it is selected that the shift register does not output a scan signal, and transmit the first voltage signal to the third node when it is selected that the shift register outputs a scan signal.

2. The shift register according to claim 1, wherein, The first decoding sub - circuit includes: A first transistor, the control electrode and the first electrode of the first transistor are both electrically connected to the second clock signal terminal, and the second electrode is electrically connected to a fourth node; A plurality of second transistors, the control electrode of each second transistor is electrically connected to a selection control signal terminal, and the plurality of first electrodes of the plurality of second transistors are all electrically connected to the fourth node, and the plurality of second electrodes are all electrically connected to the third node.

3. The shift register according to claim 1, wherein, The first decoding sub - circuit is further electrically connected to a second voltage signal terminal; the first decoding sub - circuit includes: A first transistor, the control electrode of the first transistor is electrically connected to the second clock signal terminal, the first electrode is electrically connected to a fifth node, and the second electrode is electrically connected to the third node; A plurality of second transistors, the control electrode of each second transistor is electrically connected to a selection control signal terminal, and the plurality of first electrodes of the plurality of second transistors are all electrically connected to the second voltage signal terminal, and the plurality of second electrodes are all electrically connected to the fifth node.

4. The shift register according to claim 3, further Including: The black insertion control sub - circuit is electrically connected to the first control signal terminal, the fifth node, and the signal output terminal, and is configured to transmit the voltage of the fifth node to the signal output terminal under the control of a first control signal from the first control signal terminal.

5. The shift register according to claim 4, wherein, The black insertion control sub - circuit includes: A third transistor, the control electrode of the third transistor is electrically connected to the first control signal terminal, the first electrode is electrically connected to the fifth node, and the second electrode is electrically connected to the signal output terminal.

6. The shift register according to any one of claims 1 to 3, further including: The second decoding sub - circuit is electrically connected to a plurality of black insertion control signal terminals, the first control signal terminal, the second voltage signal terminal, and the signal output terminal, and is configured to transmit a second voltage signal from the second voltage signal terminal to the signal output terminal under the control of a black insertion control signal from at least one of the black insertion control signal terminals and a first control signal from the first control signal terminal.

7. The shift register according to claim 6, wherein, The second decoding sub - circuit includes: A plurality of fourth transistors, the control electrode of each fourth transistor is electrically connected to a black insertion control signal terminal, and the plurality of first electrodes of the plurality of fourth transistors are all electrically connected to the second voltage signal terminal, and the plurality of second electrodes of the plurality of fourth transistors are all electrically connected to the sixth node; A fifth transistor, the control electrode of the fifth transistor is electrically connected to the first control signal terminal, the first electrode is electrically connected to the sixth node, and the second electrode is electrically connected to the signal output terminal.

8. The shift register according to claim 6 or 7, wherein, The number of the plurality of black insertion control signal terminals is the same as and corresponds one - to - one with the number of the plurality of selection control signal terminals; the black insertion control signal terminal and the selection control signal terminal corresponding to the black insertion control signal terminal are the same signal terminal or different signal terminals.

9. The shift register according to any one of claims 1 to 8, wherein, The third control sub - circuit includes: A sixth transistor, the control electrode of the sixth transistor is electrically connected to the third node, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the second node; A seventh transistor, the control electrode of the seventh transistor is electrically connected to the third node, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the signal output terminal; An eighth transistor, the control electrode of the eighth transistor is electrically connected to the second node, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the third node.

10. The shift register according to claim 9, wherein, The sixth transistor is a double - gate transistor, including two sub - transistors connected in series, and the two sub - transistors are connected through a seventh node; The shift register further includes: The anti - leakage electronic circuit is electrically connected to the second node, the second voltage signal terminal, and the seventh node, and is configured to transmit the second voltage signal to the seventh node under the control of the voltage of the second node.

11. The shift register according to claim 10, wherein, the anti-leakage electronic circuit includes: a ninth transistor, the control electrode of the ninth transistor is electrically connected to the second node, the first electrode is electrically connected to the second voltage signal terminal, and the second electrode is electrically connected to the seventh node.

12. The shift register according to any one of claims 1 to 11, wherein, the third control sub-circuit is further electrically connected to the first node, and the third control sub-circuit is further configured to transmit the first voltage signal to the first node when the shift register is selected not to output a scan signal.

13. The shift register according to claim 12, wherein, the third control sub-circuit further includes: a tenth transistor, the control electrode of the tenth transistor is electrically connected to the third node, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the first node.

14. The shift register according to any one of claims 9 to 13, further comprises: a time-sharing selection sub-circuit, electrically connected to the second control signal terminal, the third control signal terminal, the first decoding sub-circuit, the third node and the eighth node, the time-sharing selection sub-circuit is configured to connect the first decoding sub-circuit to the third node under the control of a second control signal from the second control signal terminal, and connect the first decoding sub-circuit to the eighth node under the control of a third control signal from the third control signal terminal; wherein, the first decoding sub-circuit is electrically connected to the third node through the time-sharing selection sub-circuit; a fourth control sub-circuit, electrically connected to the first voltage signal terminal, the first node, the second node, the eighth node and the signal output terminal, configured to transmit the first voltage signal to the first node, the second node and the signal output terminal when the shift register is selected not to output a scan signal, and transmit the first voltage signal to the eighth node when the shift register is selected to output a scan signal.

15. The shift register according to claim 14, wherein, the time-sharing selection sub-circuit includes: an eleventh transistor, the control electrode of the eleventh transistor is electrically connected to the second control signal terminal, the first electrode is electrically connected to the first decoding sub-circuit, and the second electrode is electrically connected to the third node; a twelfth transistor, the control electrode of the twelfth transistor is electrically connected to the third control signal terminal, the first electrode is electrically connected to the first decoding sub-circuit, and the second electrode is electrically connected to the eighth node; wherein, within one display period, one of the second control signal terminal and the third control signal terminal transmits a corresponding control signal, and the second control signal terminal and the third control signal terminal alternately transmit corresponding control signals.

16. The shift register according to claim 14 or 15, wherein, the fourth control sub-circuit includes: a thirteenth transistor, the control electrode of the thirteenth transistor is electrically connected to the eighth node, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the second node; A fourteenth transistor, a control electrode of the fourteenth transistor is electrically connected to the eighth node, a first pole is electrically connected to the first voltage signal terminal, and a second pole is electrically connected to the signal output terminal; A fifteenth transistor, a control electrode of the fifteenth transistor is electrically connected to the second node, a first pole is electrically connected to the first voltage signal terminal, and a second pole is electrically connected to the eighth node; A sixteenth transistor, a control electrode of the sixteenth transistor is electrically connected to the eighth node, a first pole is electrically connected to the first voltage signal terminal, and a second pole is electrically connected to the first node.

17. The shift register according to any one of claims 1 to 16, wherein, The first control sub-circuit includes a seventeenth transistor, a control electrode and a first pole of the seventeenth transistor are both electrically connected to the first clock signal terminal, and a second pole is electrically connected to the first node; The first output sub-circuit includes an eighteenth transistor, a control electrode of the eighteenth transistor is electrically connected to the first node, a first pole is electrically connected to the first voltage signal terminal, and a second pole is electrically connected to the signal output terminal; The second control sub-circuit includes a nineteenth transistor and a twentieth transistor, a control electrode and a first pole of the nineteenth transistor are both electrically connected to the second clock signal terminal, and a second pole is electrically connected to a first pole of the twentieth transistor; A control electrode of the twentieth transistor is electrically connected to the first node, and a second pole is electrically connected to the second node; The second output sub-circuit includes a twenty-first transistor, a control electrode of the twenty-first transistor is electrically connected to the second node, a first pole is electrically connected to the third clock signal terminal, and a second pole is electrically connected to the signal output terminal.

18. The shift register according to any one of claims 1 to 17, further comprising: A reset sub-circuit, electrically connected to the third clock signal terminal, the first voltage signal terminal and the first node, and configured to transmit the first voltage signal to the first node under the control of the third clock signal; An initialization sub-circuit, electrically connected to the first clock signal terminal, the first voltage signal terminal and the third node, and configured to transmit the first voltage signal to the third node under the control of the first clock signal; A first energy storage sub-circuit, electrically connected to the first voltage signal terminal and the first node, and configured to maintain the voltage of the first node; A second energy storage sub-circuit, electrically connected to the second node and the signal output terminal, and configured to maintain the voltage of the second node; A third energy storage sub-circuit, electrically connected to the third node and the first voltage signal terminal, and configured to maintain the voltage of the third node.

19. The shift register according to claim 18, wherein, The reset sub-circuit includes a twenty-second transistor, a control electrode of the twenty-second transistor is electrically connected to the third clock signal terminal, a first pole is electrically connected to the first voltage signal terminal, and a second pole is electrically connected to the first node; The initialization sub-circuit includes a twenty-third transistor. The control electrode of the twenty-third transistor is electrically connected to the first clock signal terminal, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the third node; The first energy storage sub-circuit includes a first capacitor. One plate of the first capacitor is electrically connected to the first voltage signal terminal, and the other plate is electrically connected to the first node; The second energy storage sub-circuit includes a second capacitor. One plate of the first capacitor is electrically connected to the second node, and the other plate is electrically connected to the signal output terminal; The third energy storage sub-circuit includes a third capacitor. One plate of the third capacitor is electrically connected to the first voltage signal terminal, and the other plate is electrically connected to the third node.

20. A driving method for a shift register, applied to the shift register according to any one of claims 1 to 19, wherein, A display period includes a selection stage and an output stage; When it is selected that the shift register does not output a scan signal, the driving method includes: In the selection stage, at least one of the plurality of selection control signal terminals outputs a working voltage. The first decoding sub-circuit transmits the working voltage to the third node. The third control sub-circuit, under the control of the turn-on voltage of the third node, transmits the first voltage signal to the second node and the third node; In the output stage, the second output sub-circuit is cut off under the control of the first voltage signal at the second node and does not output a scan signal; When it is selected that the shift register outputs a scan signal, the driving method includes: In the selection stage, the plurality of selection control signal terminals all transmit a non-working voltage. The first control sub-circuit and the second control sub-circuit transmit the second clock signal from the second clock signal terminal to the second node; In the output stage, the second output sub-circuit, under the control of the voltage at the second node, transmits the third clock signal from the third clock signal terminal to the signal output terminal for output.

21. According to the driving method of claim 20, wherein, The selection stage includes a first stage and a third stage arranged in sequence; when it is selected that the shift register does not output a scan signal, the driving method includes: In the first stage, the first control sub-circuit, under the control of the first clock signal from the first clock signal terminal, transmits the first clock signal to the first node; In the third stage, the second control sub-circuit, under the control of the second clock signal from the second clock signal terminal and the first clock signal at the first node, transmits the second clock signal to the second node.

22. According to the driving method of claim 20 or 21, wherein, The shift register includes a second decoding sub-circuit. A display period further includes a blanking stage after the output stage; the driving method further includes: In the black insertion stage, the second decoding sub-circuit transmits the second voltage signal from the second voltage signal terminal to the signal output terminal under the control of the black insertion control signal from at least one black insertion control signal terminal and the first control signal from the first control signal terminal.

23. The driving method according to claim 20 or 21, wherein, the shift register includes a black insertion control sub-circuit, and a display period further includes a black insertion stage located after the output stage; the driving method further includes: In the black insertion stage, the first decoding sub-circuit transmits the second voltage signal to the fifth node under the control of at least one selection control signal, and the black insertion control sub-circuit transmits the voltage of the fifth node to the signal output terminal under the control of the first control signal from the first control signal terminal.

24. A gate driving circuit, comprising: a plurality of shift registers according to any one of claims 1 to 19; multiple sets of selection control signal lines, each set including two selection control signal lines, and each selection control signal line forms a selection control signal terminal; the first decoding sub-circuit of the shift register is electrically connected to one of the selection control signal lines in each set of selection control signal lines, and one of the selection control signal lines forms a selection control signal terminal.

25. The gate driving circuit according to claim 24, wherein, every four of the shift registers form a shift register group, and the four shift registers included in the shift register group are arranged in sequence as a first-stage shift register, a second-stage shift register, a third-stage shift register, and a fourth-stage shift register; the gate driving circuit further includes: a first clock signal line, which is electrically connected to the first clock signal terminal of the first-stage shift register, the third clock signal terminal of the second-stage shift register, and the second clock signal terminal of the third-stage shift register respectively; a second clock signal line, which is electrically connected to the first clock signal terminal of the second-stage shift register, the third clock signal terminal of the third-stage shift register, and the second clock signal terminal of the fourth-stage shift register respectively; a third clock signal line, which is electrically connected to the second clock signal terminal of the first-stage shift register, the first clock signal terminal of the third-stage shift register, and the third clock signal terminal of the fourth-stage shift register respectively; a fourth clock signal line, which is electrically connected to the third clock signal terminal of the first-stage shift register, the second clock signal terminal of the second-stage shift register, and the first clock signal terminal of the fourth-stage shift register respectively.

26. The gate driving circuit according to claim 25, wherein, one of the two selection control signal lines in each set of selection control signal lines transmits a working voltage, and the other transmits a non-working voltage; the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line sequentially output a working voltage.

27. The gate driving circuit according to any one of claims 24 to 26, wherein, The shift register includes a second decoding sub-circuit, and the second decoding sub-circuit is electrically connected to one selection control signal line in each group of selection control signal lines, and one selection control signal line forms a black insertion control signal terminal; The second decoding sub-circuit and the first decoding sub-circuit are electrically connected to the same selection control signal line or different selection control signal lines in the same group of selection control signal lines.

28. A display device, comprising: The shift register according to any one of claims 1 to 19; or, the gate driving circuit according to any one of claims 24 to 27.

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