Photoelectric integrated semiconductor packaging structure and preparation method therefor

Abstract

Provided in the preset invention are a photoelectric integrated semiconductor packaging structure and a preparation method therefor. By means of a re-distribution layer, a metal column, three-dimensional optical waveguide wiring, a packaging layer, an optical chip, an electrical chip, a metal bump, a substrate and a connector, the optical chip and the electric chip can be co-packaged, and the stacked interconnection and staggered wiring of electrical signal traces and optical-signal traces are realized, so as to reduce the packaging area, increase the wiring density, effectively shorten a transmission path of an optical signal and an electrical signal, and reduce the signal attenuation; moreover, an optical waveguide is led out from a side surface of a package, which can improve the modular combination capability, and realize system packaging, thereby satisfying the requirements of high-density integrated packaging.

Description

Photoelectric integrated semiconductor packaging structure and preparation method thereof Technical Field

[0001] The present invention belongs to the field of semiconductor packaging and relates to a photoelectric integrated semiconductor packaging structure and a preparation method thereof. Background Art

[0002] With the continuous development of big data, artificial intelligence, telemedicine, the Internet of Things, e-commerce, and 5G communications, global data traffic has grown explosively. Lower-cost, more reliable, faster, and higher-density circuits are the goals pursued by integrated circuit packaging.

[0003] To meet the demand for internet traffic, data center node bandwidth needs to reach 10Tb / s. To mitigate the growing trend of data center energy consumption, it is imperative to find ways to reduce the power consumption of systems and devices. Driven by ultra-high data capacity, traditional electronic chip manufacturing processes are approaching 10nm, and CMOS processes are approaching their physical limits. Due to the low signal attenuation, low energy consumption, high bandwidth, and CMOS compatibility of light, the industry generally believes that silicon photonics, by integrating mature microelectronics and optoelectronics technologies, can not only reduce chip size, lower cost and power consumption, but also improve reliability, making them a promising "More Than Moore" high-speed information engine. Therefore, the introduction of silicon photonics technology is essential. Since the goal of silicon photonics is to increase input / output (I / O) bandwidth and minimize energy consumption, the packaging of optical integrated circuits (PICs) and electrical integrated circuits (EICs) is crucial, as these factors directly impact I / O bandwidth and energy consumption.

[0004] Existing optoelectronic integrated semiconductor packaging structures mostly directly bond the optical and electrical integrated chips to a substrate, electrically connecting them via wirebonds or flip-chip bonding. Because silicon photonics process nodes are relatively backward compared to electrical chips—for example, the current monolithic silicon photonics process nodes are 45nm and 32nm, significantly behind the sub-10nm process nodes of electrical chips—existing optoelectronic integrated semiconductor packaging structures struggle to meet the demands of high-density integrated packaging.

[0005] Therefore, it is necessary to provide an optoelectronic integrated semiconductor packaging structure and a preparation method thereof.

[0006] Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide an optoelectronic integrated semiconductor packaging structure and a preparation method thereof, so as to solve the problem in the prior art that it is difficult to perform high-density integrated packaging of optical chips and electronic chips.

[0008] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing an optoelectronic integrated semiconductor packaging structure, comprising the following steps:

[0009] providing a first supporting substrate, and forming a first redistribution layer on the first supporting substrate;

[0010] forming a metal column and a three-dimensional optical waveguide wiring on the first redistribution layer, wherein a first end of the metal column is electrically connected to the first redistribution layer, and the three-dimensional optical waveguide wiring includes a waveguide optical port and a waveguide transmission port;

[0011] forming a packaging layer on the first rewiring layer, wherein the packaging layer covers the metal pillar and the three-dimensional optical waveguide wiring, and the second end of the metal pillar and the waveguide optical port are exposed on the surface of the packaging layer;

[0012] forming a second redistribution layer on the packaging layer, wherein the second redistribution layer is electrically connected to the second end of the metal pillar and has a through groove exposing the waveguide optical port;

[0013] Bonding an electrical chip and an optical chip on the second redistribution layer, wherein the electrical chip and the optical chip are both electrically connected to the second redistribution layer, and a photosensitive area of ​​the optical chip is arranged corresponding to the through groove;

[0014] removing the first supporting substrate, providing a second supporting substrate, and bonding the second supporting substrate to the surfaces of the electrical chip and the optical chip;

[0015] forming a metal bump on the first redistribution layer, the metal bump being electrically connected to the first redistribution layer, and removing the second supporting substrate to form a package body, wherein the waveguide transmission port is exposed on a side surface of the package layer;

[0016] Providing a substrate, bonding a plurality of the packages to the substrate, wherein the substrate is electrically connected to the metal bumps, and the waveguide transmission ports in adjacent packages are correspondingly arranged;

[0017] A connector is provided, and the connector is bonded to the substrate, and the connector is arranged corresponding to the waveguide transmission port.

[0018] Optionally, the method for forming the three-dimensional optical waveguide wiring includes a 3D printing method; the formed three-dimensional optical waveguide wiring includes organic polymer optical waveguide wiring, silicon-based optical waveguide wiring, lithium niobate optical waveguide wiring or lithium borate optical waveguide wiring.

[0019] Optionally, the method for preparing the package body includes a wafer-level preparation method, and the method for exposing the waveguide transmission port includes a cutting method.

[0020] Optionally, the method further includes interconnecting the connectors in adjacent packages.

[0021] Optionally, a method of forming the through-groove includes a mechanical drilling method, a laser drilling method or a chemical etching method.

[0022] Optionally, the method further includes providing a heat sink and bonding the heat sink, wherein the heat sink after bonding is in direct and / or indirect contact with the electrical chip and / or the optical chip.

[0023] Optionally, a first bottom filling layer for filling gaps is formed between the electrical chip, the optical chip and the second redistribution layer; and a second bottom filling layer for filling gaps is formed between the first redistribution layer and the substrate.

[0024] The present invention further provides a photoelectric integrated semiconductor packaging structure, the photoelectric integrated semiconductor packaging structure comprising:

[0025] A package, comprising:

[0026] a first rewiring layer;

[0027] a metal column, the metal column being located on the first redistribution layer, and a first end of the metal column being electrically connected to the first redistribution layer;

[0028] A three-dimensional optical waveguide wiring, the three-dimensional optical waveguide wiring is located on the first rewiring layer, and the three-dimensional optical waveguide wiring includes a waveguide optical port and a waveguide transmission port;

[0029] an encapsulation layer, the encapsulation layer being located on the first rewiring layer and covering the metal pillar and the three-dimensional optical waveguide wiring, wherein the second end of the metal pillar and the waveguide optical port are exposed on a surface of the encapsulation layer, and the waveguide transmission port is exposed on a side surface of the encapsulation layer;

[0030] a second redistribution layer, the second redistribution layer being located on the packaging layer, the second redistribution layer being electrically connected to the second end of the metal pillar and having a through groove exposing the waveguide optical port;

[0031] an electrical chip and an optical chip, wherein the electrical chip and the optical chip are both bonded to the second redistribution layer and electrically connected to the second redistribution layer, and a photosensitive area of ​​the optical chip is arranged corresponding to the through groove;

[0032] a metal bump, the metal bump being located on the first redistribution layer and electrically connected to the first redistribution layer;

[0033] A substrate, the substrate is bonded to the package body, the substrate is electrically connected to the metal bump, and the waveguide transmission ports in the adjacent packages are correspondingly arranged;

[0034] A connector is bonded to the substrate and is arranged corresponding to the waveguide transmission port.

[0035] Optionally, a heat sink is further included, and the heat sink is in direct and / or indirect contact with the electric chip and / or the optical chip.

[0036] Optionally, the connectors in adjacent packages are interconnected.

[0037] As described above, the optoelectronic integrated semiconductor packaging structure and preparation method of the present invention can seal the optical chip and the electrical chip by rewiring the layer, metal pillars, three-dimensional optical waveguide wiring, packaging layer, optical chip, electrical chip, metal bumps, substrate and connector, thereby realizing stacked interconnection and staggered routing of electrical signal wiring and optical signal wiring, thereby reducing the packaging area, increasing wiring density, effectively shortening the transmission path of optical signals and electrical signals, and reducing signal attenuation. In addition, the optical waveguide is led out from the side of the packaging body, which can increase the modular combination capability, realize system packaging, and meet the needs of high-density integrated packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG1 is a schematic diagram showing a process flow for preparing an optoelectronic integrated semiconductor packaging structure according to an embodiment of the present invention.

[0039] FIG. 2 is a schematic structural diagram showing a structure after forming a first redistribution layer according to an embodiment of the present invention.

[0040] FIG. 3 is a schematic diagram showing a structure after metal pillars and three-dimensional optical waveguide wiring are formed according to an embodiment of the present invention.

[0041] FIG4 is a schematic structural diagram of area A in FIG3 .

[0042] FIG. 5 is a schematic diagram showing a structure after forming an encapsulation layer in an embodiment of the present invention.

[0043] FIG. 6 is a schematic structural diagram showing a second redistribution layer formed in an embodiment of the present invention.

[0044] FIG. 7 is a schematic diagram showing the structure after bonding the electrical chip and the optical chip in an embodiment of the present invention.

[0045] FIG8 is a schematic diagram showing a structure after the first supporting substrate is removed to form metal bumps according to an embodiment of the present invention.

[0046] FIG. 9 is a schematic diagram showing the structure of a package body formed in an embodiment of the present invention.

[0047] FIG. 10 is a schematic diagram showing the structure of the package body and the substrate after bonding in an embodiment of the present invention.

[0048] FIG. 11 is a schematic top view of a photoelectric integrated semiconductor package structure according to an embodiment of the present invention.

[0049] FIG. 12 is a schematic diagram showing the structure of the interconnected connectors according to an embodiment of the present invention.

[0050] Explanation of component numbers: 110 - first supporting substrate; 120 - second supporting substrate; 210 - first redistribution layer; 220 - second redistribution layer; 221 - through groove; 300 - metal pillar; 400 - three-dimensional optical waveguide wiring; 401 - waveguide optical port; 402 - waveguide transmission port; 500 - packaging layer; 610 - electrical chip; 620 - optical chip; 621 - photosensitive area; 710 - first bottom filling layer; 720 - second bottom filling layer; 800 - metal bump; 900 - substrate; 100 - connector; A - area; B - package body. DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0053] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "over," and the like may be used herein to describe the relationship of one element or feature to other elements or features illustrated in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0054] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0055] As shown in Figure 1, this embodiment provides an optoelectronic integrated semiconductor packaging structure and a preparation method thereof. By rewiring a wiring layer, metal pillars, three-dimensional optical waveguide wiring, a packaging layer, an optical chip, an electrical chip, metal bumps, a substrate, and a connector, the optical chip and the electrical chip can be sealed together to achieve stacked interconnection and staggered routing of electrical signal wiring and optical signal wiring, thereby reducing the packaging area, increasing wiring density, effectively shortening the transmission path of optical and electrical signals, and reducing signal attenuation. In addition, the optical waveguide is led out from the side of the package body, which can increase modular combination capabilities, realize system packaging, and meet the needs of high-density integrated packaging.

[0056] The following further describes the preparation of the optoelectronic integrated semiconductor packaging structure in conjunction with Figures 2 to 12, specifically including:

[0057] First, referring to FIG. 1 and FIG. 2 , step S1 is performed to provide a first supporting substrate 110 , and to form a first redistribution layer 210 on the first supporting substrate 110 .

[0058] Specifically, the first supporting substrate 110 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., so as to provide support for subsequent processes through the first supporting substrate 110. In order to facilitate the subsequent removal of the first supporting substrate 110, in this embodiment, a first separation layer (not shown) is preferably formed on the surface of the first supporting substrate 110. The first separation layer includes but is not limited to a tape and a polymer layer. For example, the first separation layer may optionally use a photothermal conversion layer, so that the first separation layer can be subsequently heated by, for example, a laser to remove the first supporting substrate, thereby improving operational convenience.

[0059] As an example, the preparation of the optoelectronic integrated semiconductor packaging structure can be wafer-level, that is, the first supporting substrate 110 may include a wafer-level substrate with a size of 4 inches, 6 inches, 8 inches, 12 inches, etc., to further improve the process efficiency, but the size of the first supporting substrate 110 is not limited to this.

[0060] As an example, the first rewiring layer 210 may be a Damascus rewiring layer, an organic rewiring layer or a stacked combination of the two, that is, the material of the dielectric layer may include silicon oxide, silicon nitride or polyimide (PI), etc., and the material of the metal wiring may include copper, aluminum, etc. Regarding the material, number of layers, layout, preparation method, etc. of the first rewiring layer 210, it can be selected according to needs and no excessive restrictions are imposed here.

[0061] Next, referring to Figures 1 and 3, step S2 is performed to form a metal pillar 300 and a three-dimensional optical waveguide wiring 400 on the first redistribution layer 210, and the first end of the metal pillar 300 is electrically connected to the first redistribution layer 210. The three-dimensional optical waveguide wiring 400 includes a waveguide optical port 401 and a waveguide transmission port 402.

[0062] Specifically, the metal pillars 300 may be formed by bonding, electroplating, or the like, and the metal pillars 300 may be made of materials such as copper and aluminum. The material, distribution, and preparation methods of the metal pillars 300 are not specifically limited herein. The three-dimensional optical waveguide wiring 400 may be formed by 3D printing, but is not limited thereto. The three-dimensional optical waveguide wiring 400 may include organic polymer optical waveguide wiring, silicon-based optical waveguide wiring, lithium niobate optical waveguide wiring, or lithium borate optical waveguide wiring. For example, the organic polymer optical waveguide wiring may be made of materials such as polymethyl methacrylate (PMMA), polystyrene (PS), polycarbonate (PC), epoxy resin, or fluorinated polyimide. The material, distribution, and preparation of the three-dimensional optical waveguide wiring 400 are not specifically limited herein.

[0063] The order of forming the metal pillars 300 and the three-dimensional optical waveguide wiring 400 on the first rewiring layer 210 is not restricted. In this embodiment, the metal pillars 300 are prepared first and then the three-dimensional optical waveguide wiring 400.

[0064] Referring to FIG4 , which illustrates the structure of the three-dimensional optical waveguide wiring 400 in area A of FIG3 , the three-dimensional optical waveguide wiring 400 includes a vertical waveguide optical port 401 for optical transmission with the photosensitive area 621 of the subsequent optical chip 620, as shown in FIG7 . The three-dimensional optical waveguide wiring 400 also includes a lateral waveguide transmission port 402 for optical transmission with the waveguide transmission port 402 in the adjacent package B, as shown in FIG10 . The specific structure of the three-dimensional optical waveguide wiring 400 can be configured as needed and is not overly limited herein. As shown in FIG11 , in this embodiment, the three-dimensional optical waveguide wiring 400 is provided with the waveguide transmission ports 402 along its circumference to increase the optical transmission path, but the configuration of the three-dimensional optical waveguide wiring 400 is not limited to this.

[0065] Next, referring to Figures 1 and 5, step S3 is performed to form a packaging layer 500 on the first rewiring layer 210. The packaging layer 500 covers the metal column 300 and the three-dimensional optical waveguide wiring 400, and the surface of the packaging layer 500 exposes the second end of the metal column 300 and the waveguide optical port 401.

[0066] Specifically, the method of forming the packaging layer 500 may include molding, vacuum lamination and spin coating, etc. The material of the packaging layer 500 can be the more commonly used epoxy resin. There is no excessive restriction on the material and preparation method of the packaging layer 500. The packaging layer 500 can protect the metal column 300 and the three-dimensional optical waveguide wiring 400 and provide fixed support.

[0067] A polishing process, such as chemical mechanical polishing (CMP), can be used to thin the packaging layer 500 to expose the second end of the metal pillar 300 and the waveguide optical port 401, thereby obtaining a relatively flat surface to facilitate subsequent processing. The material and preparation method of the packaging layer 500 are not particularly limited herein.

[0068] 1 and 6 , step S4 is performed to form a second redistribution layer 220 on the packaging layer 500 . The second redistribution layer 220 is electrically connected to the second end of the metal pillar 300 and has a through groove 221 exposing the waveguide optical port 401 .

[0069] Specifically, the second rewiring layer 220 is preferably an organic rewiring layer, that is, the dielectric layer of the second rewiring layer 220 can be made of polyimide (PI), etc., so that when preparing the second rewiring layer 220, the influence of high temperature on the three-dimensional optical waveguide wiring 400 can be avoided. The material, number of layers, layout, preparation method, etc. of the second rewiring layer 220 can be selected according to needs and are not excessively restricted here.

[0070] As an example, a method for forming the through groove 221 may include a mechanical drilling method, a laser drilling method, or a chemical etching method, etc., and the specific method can be selected according to needs.

[0071] Next, referring to Figures 1 and 7, step S5 is executed to bond an electrical chip 610 and an optical chip 620 on the second rewiring layer 220. The electrical chip 610 and the optical chip 620 are both electrically connected to the second rewiring layer 220, and the photosensitive area 621 of the optical chip 620 is arranged corresponding to the through groove 221 to facilitate light transmission through the through groove 221.

[0072] Specifically, it is preferred that both the electrical chip 610 and the optical chip 620 are electrically connected to the second redistribution layer 220 by flip-chip bonding. There is no excessive restriction on the types of the electrical chip 610 and the optical chip 620.

[0073] Preferably, a first underfill layer 710 may be formed between the electrical chip 610, the optical chip 620, and the second rewiring layer 220 to fill the gaps, thereby forming a protective layer, improving bonding strength, and protecting against the effects of moisture, gas, etc. The material of the first underfill layer 710 can be selected as needed, and any insulating material is sufficient, and is not excessively limited herein.

[0074] Next, referring to FIG. 1 and FIG. 8 , step S6 is performed to remove the first support substrate 110 , provide a second support substrate 120 , and bond the second support substrate 120 to the surfaces of the electrical chip 610 and the optical chip 620 .

[0075] Specifically, the second supporting substrate 120 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., so as to provide support for subsequent processes through the second supporting substrate 120. In order to facilitate the subsequent removal of the second supporting substrate 120, in this embodiment, a second separation layer (not shown) is preferably formed on the surface of the second supporting substrate 120. The second separation layer includes but is not limited to a tape and a polymer layer. For example, the second separation layer may optionally use a photothermal conversion layer, so that the second separation layer can be subsequently heated by a laser or the like to remove the second supporting substrate 120, thereby improving operational convenience.

[0076] Next, referring to Figures 1, 8 and 9, step S7 is performed to form a metal bump 800, which is electrically connected to the first redistribution layer 210, and the second supporting substrate 120 is removed to form a package B. In the package B, the waveguide transmission port 402 is exposed on the side of the packaging layer 500.

[0077] The metal bump 800 may be a C4 metal bump, but is not limited thereto and is not overly restricted herein.

[0078] As an example, when preparing at the wafer level, after removing the second supporting substrate 120, a wafer cutting step can be performed to divide the wafer-level structure into a single structure as shown in Figure 9. The cutting process is not limited here. Furthermore, the waveguide transmission port 402 can be exposed while the wafer is being cut to improve the timeliness. However, the method of exposing the waveguide transmission port 402 is not limited to this. For example, methods such as CMP can also be used, and no excessive restrictions are made here.

[0079] Next, referring to FIG. 1 and FIG. 10 , step S8 is performed to provide a substrate 900 , and a plurality of packages B are bonded to the substrate 900 . The substrate 900 is electrically connected to the metal bumps 800 , and the waveguide transmission ports 402 in adjacent packages B are correspondingly disposed so that light transmission between adjacent packages B can be achieved through the waveguide transmission ports 402 .

[0080] Specifically, after bonding the metal bumps 800 to the substrate 900, a second underfill layer 720 can be formed between the first redistribution layer 210 and the substrate 900 to fill the gap. This provides a protective layer, enhances bonding strength, and protects against the effects of moisture, gas, and the like. The material of the second underfill layer 720 can be selected as needed, and any insulating material is sufficient, and is not particularly limited herein.

[0081] Furthermore, after the metal bumps 800 are bonded to the substrate 900 , a carrier (not shown) may be provided to form conductive metal bumps (not shown) on the surface of the substrate 900 for subsequent electrical extraction.

[0082] 1 and 11 , step S9 is performed to provide a connector 100 , bond the connector 100 to the substrate 900 , and arrange the connector 100 corresponding to the waveguide transmission port 402 to achieve optical transmission. The specific type of the connector 100 is not particularly limited herein.

[0083] Furthermore, the method may include providing a heat sink (not shown) and bonding the heat sink, wherein the heat sink after bonding may be in direct and / or indirect contact with the electrical chip 610 and / or the optical chip 620 .

[0084] Specifically, the heat sink may be an aluminum heat sink cover or a heat sink cover made of other materials, such as iron, copper, etc., without excessive restrictions, and the heat sink may be in direct or indirect contact with the electrical chip 610 and / or the optical chip 620, without excessive restrictions, so that good heat dissipation can be achieved through the heat sink.

[0085] Furthermore, as shown in FIG12 , the step of interconnecting the connectors 100 in the adjacent packages B may be included to perform modular combination and realize system packaging to meet the requirements of high-density integrated packaging.

[0086] 2 to 12 , this embodiment further provides a photoelectric integrated semiconductor packaging structure, which can be directly prepared using the above-mentioned preparation process. Thus, the materials, preparation process, etc. of the semiconductor packaging structure can all be referred to the above content. Of course, as needed, the photoelectric integrated semiconductor packaging structure can also be prepared using other preparation processes.

[0087] In this embodiment, the optoelectronic integrated semiconductor packaging structure includes: a package body B, a substrate 900 and a connector 100, wherein the package body B includes a first rewiring layer 210, a metal column 300, a three-dimensional optical waveguide wiring 400, a packaging layer 500, a second rewiring layer 220, an electrical chip 610, an optical chip 620 and a metal bump 800.

[0088] Specifically, the metal pillar 300 is located on the first rewiring layer 210, and the first end of the metal pillar 300 is electrically connected to the first rewiring layer 210; the three-dimensional optical waveguide wiring 400 is located on the first rewiring layer 210, and the three-dimensional optical waveguide wiring 400 includes a waveguide optical port 401 and a waveguide transmission port 402; the packaging layer 500 is located on the first rewiring layer 210 and covers the metal pillar 300 and the three-dimensional optical waveguide wiring 400, and the surface of the packaging layer 500 exposes the second end of the metal pillar 300 and the waveguide optical port 401, and the side of the packaging layer 500 exposes the waveguide transmission port 402; the second rewiring layer 220 is located on the packaging layer 500, and the second rewiring layer 220 is electrically connected to the second end of the metal pillar 300. And it has a through groove 221 that exposes the waveguide optical port 401; the electrical chip 610 and the optical chip 620 are both bonded to the second rewiring layer 220 and electrically connected to the second rewiring layer 220, and the photosensitive area 621 of the optical chip 620 is corresponding to the through groove 221 for light transmission; the metal bump 800 is located on the first rewiring layer 210 and electrically connected to the first rewiring layer 210; the substrate 900 is bonded to the package B, and the substrate 900 is electrically connected to the metal bump 800, and the waveguide transmission port 402 in the adjacent package B is correspondingly set for light transmission; the connector 100 is bonded to the substrate 900, and the connector 100 is corresponding to the waveguide transmission port 402 for light transmission.

[0089] Furthermore, the surface of the substrate 900 may further include conductive metal bumps (not shown) to facilitate subsequent electrical extraction.

[0090] Furthermore, a first bottom filling layer 710 may be provided between the electrical chip 610, the optical chip 620 and the second rewiring layer 220 to form a protective layer, thereby improving the bonding strength and avoiding the influence of moisture, gas, etc.; and a second bottom filling layer 720 for filling the gap may be provided between the first rewiring layer 210 and the substrate 900 to form a protective layer, thereby improving the bonding strength and avoiding the influence of moisture, gas, etc.

[0091] Furthermore, a heat sink (not shown) may be included. The heat sink may be in direct and / or indirect contact with the electrical chip 610 and / or the optical chip 620 to achieve good heat dissipation through the heat sink.

[0092] Furthermore, the connectors 100 in the adjacent packages B are interconnected to perform modular combination and realize system packaging to meet the requirements of high-density integrated packaging.

[0093] In summary, the optoelectronic integrated semiconductor packaging structure and its preparation method of the present invention can seal the optical chip and the electrical chip by rewiring the layer, metal pillars, three-dimensional optical waveguide wiring, packaging layer, optical chip, electrical chip, metal bumps, substrate and connector, and realize stacked interconnection and staggered routing of electrical signal wiring and optical signal wiring, so as to reduce the packaging area, increase the wiring density, effectively shorten the transmission path of optical signals and electrical signals, and reduce signal attenuation. In addition, the optical waveguide is led out from the side of the package body, which can increase the modular combination capability, realize system packaging, and meet the needs of high-density integrated packaging.

[0094] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing an optoelectronic integrated semiconductor packaging structure, characterized in that: The following steps are involved: Providing a first supporting substrate, and forming a first rewiring layer on the first supporting substrate; Forming a metal column and a three-dimensional optical waveguide wiring on the first rewiring layer, wherein a first end of the metal column is electrically connected to the first rewiring layer, and the three-dimensional optical waveguide wiring includes a waveguide light port and a waveguide transmission port; Forming a packaging layer on the first rewiring layer, wherein the packaging layer covers the metal column and the three-dimensional optical waveguide wiring, and the second end of the metal column and the waveguide optical port are exposed on the surface of the packaging layer; forming a second rewiring layer on the packaging layer, wherein the second rewiring layer is electrically connected to the second end of the metal column and has a through groove exposing the waveguide optical port; Bonding an electrical chip and an optical chip on the second rewiring layer, wherein the electrical chip and the optical chip are both electrically connected to the second rewiring layer, and a photosensitive area of ​​the optical chip is arranged corresponding to the through groove; removing the first supporting substrate, providing a second supporting substrate, and bonding the second supporting substrate to the surfaces of the electrical chip and the optical chip; Forming a metal bump on the first rewiring layer, the metal bump being electrically connected to the first rewiring layer, removing the second supporting substrate to form a package body, wherein the waveguide transmission port is exposed on the side of the package layer in the package body; Providing a substrate, bonding a plurality of the packages to the substrate, wherein the substrate is electrically connected to the metal bumps, and the waveguide transmission ports in the adjacent packages are correspondingly arranged; A connector is provided, the connector is bonded to the substrate, and the connector is arranged corresponding to the waveguide transmission port.

2. The method for preparing an optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method for forming the three-dimensional optical waveguide wiring includes a 3D printing method; the formed three-dimensional optical waveguide wiring includes an organic polymer optical waveguide wiring, a silicon-based optical waveguide wiring, a lithium niobate optical waveguide wiring or a lithium borate optical waveguide wiring.

3. The method for preparing an optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method for preparing the package body includes a wafer-level preparation method, and the method for exposing the waveguide transmission port includes a cutting method.

4. The method for preparing an optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method also includes the step of interconnecting the connectors in adjacent packages.

5. The method for preparing an optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method of forming the through-groove includes a mechanical drilling method, a laser drilling method or a chemical etching method.

6. The method for preparing an optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method further includes the steps of providing a heat sink and bonding the heat sink, wherein the heat sink after bonding is in direct and / or indirect contact with the electrical chip and / or the optical chip.

7. The method for preparing an optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: A first bottom filling layer filling the gap is formed between the electric chip, the optical chip and the second rewiring layer; and a second bottom filling layer filling the gap is formed between the first rewiring layer and the substrate.

8. An optoelectronic integrated semiconductor packaging structure, characterized in that: The optoelectronic integrated semiconductor packaging structure comprises: A package, the package comprising: A first rewiring layer; a metal column, the metal column being located on the first rewiring layer, and a first end of the metal column being electrically connected to the first rewiring layer; A three-dimensional optical waveguide wiring, the three-dimensional optical waveguide wiring is located on the first rewiring layer, and the three-dimensional optical waveguide wiring includes a waveguide light port and a waveguide transmission port; A packaging layer, the packaging layer is located on the first rewiring layer and covers the metal column and the three-dimensional optical waveguide wiring, and the second end of the metal column and the waveguide optical port are exposed on the surface of the packaging layer, and the waveguide transmission port is exposed on the side of the packaging layer; a second rewiring layer, the second rewiring layer being located on the packaging layer, the second rewiring layer being electrically connected to the second end of the metal column and having a through groove exposing the waveguide optical port; An electric chip and an optical chip, wherein the electric chip and the optical chip are both bonded to the second rewiring layer and electrically connected to the second rewiring layer, and a photosensitive area of ​​the optical chip is arranged corresponding to the through groove; a metal bump, the metal bump being located on the first rewiring layer and electrically connected to the first rewiring layer; A substrate, the substrate is bonded to the package body, and the substrate is electrically connected to the metal bump, and the waveguide transmission ports in the adjacent packages are correspondingly arranged; A connector is bonded to the substrate and is arranged corresponding to the waveguide transmission port.

9. The optoelectronic integrated semiconductor packaging structure according to claim 8, characterized in that: A heat sink is also included, and the heat sink is in direct and / or indirect contact with the electric chip and / or the optical chip.

10. The optoelectronic integrated semiconductor packaging structure according to claim 8, characterized in that: The connectors in adjacent packages are interconnected.

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