Photoelectric integrated semiconductor packaging structure and manufacturing method therefor

Abstract

The present invention provides a photoelectric integrated semiconductor packaging structure and a manufacturing method therefor. By means of a TSV base, a substrate, a rewiring layer, an optical waveguide wiring layer, and a micro-mirror, an optical chip and an electrical chip are packaged. In this way, the stacked interconnection and interlaced routing of electrical signal wiring and optical signal wiring can be achieved, thereby reducing the packaging area, increasing the wiring density, effectively shortening transmission paths of optical signals and electrical signals, reducing signal attenuation, and meeting the requirements of high-density integrated packaging.

Description

Photoelectric integrated semiconductor packaging structure and preparation method thereof Technical Field

[0001] The present invention belongs to the field of semiconductor packaging and relates to a photoelectric integrated semiconductor packaging structure and a preparation method thereof. Background Art

[0002] With the continuous development of big data, artificial intelligence, telemedicine, the Internet of Things, e-commerce, and 5G communications, global data traffic has grown explosively. Lower-cost, more reliable, faster, and higher-density circuits are the goals pursued by integrated circuit packaging.

[0003] To meet the demand for internet traffic, data center node bandwidth needs to reach 10Tb / s. To mitigate the growing trend of data center energy consumption, it is imperative to find ways to reduce the power consumption of systems and devices. Driven by ultra-high data capacity, traditional electronic chip manufacturing processes are approaching 10nm, and CMOS processes are approaching their physical limits. Due to the low signal attenuation, low energy consumption, high bandwidth, and CMOS compatibility of light, the industry generally believes that silicon photonics, by integrating mature microelectronics and optoelectronics technologies, can not only reduce chip size, lower cost and power consumption, but also improve reliability, making them a promising "More Than Moore" high-speed information engine. Therefore, the introduction of silicon photonics technology is essential. Since the goal of introducing silicon photonics is to increase input / output (I / O) bandwidth and minimize energy consumption, the packaging of optical integrated circuits (PICs) and electrical integrated circuits (EICs) is crucial, as these factors directly impact I / O bandwidth and energy consumption.

[0004] Existing optoelectronic integrated semiconductor packaging structures mostly directly bond the optical and electrical integrated chips to a substrate, electrically connecting them via wirebonds or flip-chip bonding. Because silicon photonics process nodes are relatively backward compared to electrical chips—for example, the current monolithic silicon photonics process nodes are 45nm and 32nm, significantly behind the sub-10nm process nodes of electrical chips—existing optoelectronic integrated semiconductor packaging structures struggle to meet the demands of high-density integrated packaging.

[0005] Therefore, it is necessary to provide an optoelectronic integrated semiconductor packaging structure and a preparation method thereof.

[0006] Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide an optoelectronic integrated semiconductor packaging structure and a preparation method thereof, so as to solve the problem in the prior art that it is difficult to perform high-density integrated packaging of optical chips and electronic chips.

[0008] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing an optoelectronic integrated semiconductor packaging structure, comprising the following steps:

[0009] Providing a TSV substrate, wherein a first surface of the TSV substrate exposes a first end of a TSV metal pillar;

[0010] forming a first redistribution layer on the first surface of the TSV substrate, wherein the first redistribution layer is electrically connected to the first end of the TSV metal pillar;

[0011] forming a patterned optical waveguide wiring layer, micro-reflectors, and a second redistribution layer on the first redistribution layer, wherein the second redistribution layer is electrically connected to the first redistribution layer, the optical waveguide wiring layer and the micro-reflectors are arranged correspondingly, and the second redistribution layer covers the optical waveguide wiring layer, exposing the micro-reflectors;

[0012] providing a first supporting substrate, and bonding the second rewiring layer to the first supporting substrate;

[0013] Thinning the TSV substrate to expose the second end of the TSV metal pillar;

[0014] forming a third redistribution layer on the second surface of the TSV substrate, wherein the third redistribution layer is electrically connected to the second end of the TSV metal pillar;

[0015] forming a metal bump on the third redistribution layer, wherein the metal bump is electrically connected to the third redistribution layer;

[0016] removing the first supporting substrate, providing a second supporting substrate, and bonding the metal bump to the second supporting substrate;

[0017] Bonding an electrical chip and an optical chip on the second redistribution layer, wherein the electrical chip and the optical chip are both electrically connected to the second redistribution layer, and a photosensitive area of ​​the optical chip is disposed corresponding to the micro-reflector;

[0018] removing the second supporting substrate, providing a base plate, bonding the metal bump to the base plate, and electrically connecting the base plate to the metal bump;

[0019] A connector is provided and bonded to the substrate, wherein the connector is arranged corresponding to the optical waveguide wiring layer.

[0020] Optionally, the method of forming the micro-mirror includes a semiconductor exposure and development patterning method or a bonding method.

[0021] Optionally, when a semiconductor exposure, development and patterning method is used to prepare the micro-mirror, the micro-mirror and the second rewiring layer are formed synchronously.

[0022] Optionally, the method of forming the optical waveguide wiring layer includes a semiconductor exposure and development method, and the formed optical waveguide wiring layer includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.

[0023] Optionally, the method further includes providing a heat sink and bonding the heat sink, wherein the heat sink after bonding is in direct and / or indirect contact with the electrical chip and / or the optical chip.

[0024] Optionally, after removing the second supporting substrate, the method further includes a step of wafer cutting.

[0025] Optionally, a first bottom filling layer for filling gaps is formed between the electrical chip, the optical chip and the second redistribution layer; and a second bottom filling layer for filling gaps is formed between the third redistribution layer and the substrate.

[0026] Optionally, the first rewiring layer formed includes a damascene rewiring layer; the second rewiring layer formed includes an organic rewiring layer; and the third rewiring layer formed includes an organic rewiring layer.

[0027] The present invention further provides a photoelectric integrated semiconductor packaging structure, the photoelectric integrated semiconductor packaging structure comprising:

[0028] A TSV substrate, wherein a first surface of the TSV substrate exposes a first end of a TSV metal pillar;

[0029] a first redistribution layer, the first redistribution layer being located on a first surface of the TSV substrate and electrically connected to a first end of the TSV metal pillar;

[0030] a patterned optical waveguide wiring layer, the optical waveguide wiring layer being located on the first rewiring layer;

[0031] A micro-reflector, wherein the micro-reflector is located on the first rewiring layer, and the optical waveguide wiring layer is arranged corresponding to the micro-reflector;

[0032] a second redistribution layer, the second redistribution layer being located on the first redistribution layer and electrically connected to the first redistribution layer, and covering the optical waveguide wiring layer to expose the micro-reflectors;

[0033] a third redistribution layer, the third redistribution layer being located on the second surface of the TSV substrate and electrically connected to the second end of the TSV metal pillar;

[0034] a metal bump, the metal bump being located on the third redistribution layer and electrically connected to the third redistribution layer;

[0035] an electrical chip and an optical chip, wherein the electrical chip and the optical chip are both bonded to the second redistribution layer, the electrical chip and the optical chip are both electrically connected to the second redistribution layer, and the photosensitive area of ​​the optical chip is arranged corresponding to the micro-reflector;

[0036] a substrate, the substrate being bonded to the metal bump and electrically connected to the metal bump;

[0037] A connector is bonded to the substrate and is arranged corresponding to the optical waveguide wiring layer.

[0038] Optionally, a heat sink is further included, and the heat sink is in direct and / or indirect contact with the electric chip and / or the optical chip.

[0039] As described above, the optoelectronic integrated semiconductor packaging structure and preparation method of the present invention seal the optical chip and the electrical chip through the TSV substrate, the base plate, the rewiring layer, the optical waveguide wiring layer and the micro-reflector, and can realize the stacked interconnection and staggered routing of the electrical signal wiring and the optical signal wiring, so as to reduce the packaging area, increase the wiring density, effectively shorten the transmission path of the optical signal and the electrical signal, reduce signal attenuation, and meet the needs of high-density integrated packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic diagram showing a process flow for preparing an optoelectronic integrated semiconductor packaging structure according to an embodiment of the present invention.

[0041] FIG. 2 is a schematic structural diagram showing a structure after forming a first redistribution layer according to an embodiment of the present invention.

[0042] FIG. 3 is a schematic structural diagram showing the structure after the optical waveguide wiring layer, micro-reflectors and the second re-wiring layer are formed in an embodiment of the present invention.

[0043] FIG. 4 is a schematic structural diagram showing a structure after a first supporting substrate is formed in an embodiment of the present invention.

[0044] FIG. 5 is a schematic diagram showing a structure after forming a first metal bump according to an embodiment of the present invention.

[0045] FIG6 is a schematic diagram showing the structure after the first supporting substrate is removed and the second supporting substrate is bonded in accordance with an embodiment of the present invention.

[0046] FIG. 7 is a schematic diagram showing the structure after bonding the electrical chip and the optical chip in an embodiment of the present invention.

[0047] FIG8 is a schematic diagram showing the structure after bonding with the substrate and forming the second metal bump in an embodiment of the present invention.

[0048] FIG. 9 is a schematic structural diagram showing a bonding connector according to an embodiment of the present invention.

[0049] FIG10 is a schematic diagram showing the structure after bonding the heat sink in an embodiment of the present invention.

[0050] Explanation of component numbers 100-TSV substrate; 200-TSV metal pillar; 310-first redistribution layer; 320-second redistribution layer; 330-third redistribution layer; 400-optical waveguide wiring layer; 500-micro-reflector; 610-first supporting substrate; 620-second supporting substrate; 611-first separation layer; 621-second separation layer; 710-first metal bump; 720-second metal bump; 810-electric chip; 820-optical chip; 821-photosensitive area; 910-first bottom filling layer; 920-second bottom filling layer; 110-substrate; 120-connector; 130-heat sink. DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0053] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "over," and the like may be used herein to describe the relationship of one element or feature to other elements or features illustrated in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0054] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0055] As shown in Figure 1, this embodiment provides a method for preparing an optoelectronic integrated semiconductor packaging structure. The optical chip and the electrical chip are sealed together through a TSV substrate, a base plate, a rewiring layer, an optical waveguide wiring layer and a micro-reflector. The stacked interconnection and staggered routing of the electrical signal wiring and the optical signal wiring can be achieved to reduce the packaging area, increase the wiring density, effectively shorten the transmission path of the optical signal and the electrical signal, reduce signal attenuation, and meet the needs of high-density integrated packaging.

[0056] The following further describes the preparation of the optoelectronic integrated semiconductor packaging structure in conjunction with Figures 2 to 10, specifically including:

[0057] First, referring to FIG. 1 and FIG. 2 , step S1 is performed to provide a TSV substrate 100 , wherein a first end of a TSV metal pillar 200 is exposed on a first surface of the TSV substrate 100 .

[0058] Specifically, the TSV substrate 100 may include a wafer-level substrate with a size of 4 inches, 6 inches, 8 inches, 12 inches, etc., to further improve process efficiency, but the size of the TSV substrate 100 is not limited thereto.

[0059] Next, step S2 is performed to form a first redistribution layer 310 on the first surface of the TSV substrate 100 , and the first redistribution layer 310 is electrically connected to the first end of the TSV metal pillar 200 .

[0060] Specifically, the first rewiring layer 310 may be a Damascus rewiring layer, wherein the material of the dielectric layer may include silicon oxide or silicon nitride, and the material of the metal wiring may include copper, aluminum, etc. A smaller line width and line spacing can be obtained through the first rewiring layer 310 to meet subsequent high-density connection requirements. The material, number of layers, layout, preparation method, etc. of the first rewiring layer 310 can be selected according to needs, and no excessive restrictions are imposed here.

[0061] Next, referring to Figures 1 and 3, step S3 is performed to form a patterned optical waveguide wiring layer 400, micro-reflectors 500 and a second re-wiring layer 320 on the first re-wiring layer 310. The second re-wiring layer 320 is electrically connected to the first re-wiring layer 310. The optical waveguide wiring layer 400 and the micro-reflectors 500 are arranged correspondingly to allow good light transmission between the optical waveguide wiring layer 400 and the micro-reflectors 500. The second re-wiring layer 320 covers the optical waveguide wiring layer 400 to expose the micro-reflectors 500, so as to facilitate light transmission through the exposed micro-reflectors 500.

[0062] As an example, a method for forming the optical waveguide wiring layer 400 may include a semiconductor exposure and development method. The formed optical waveguide wiring layer 400 may include an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer. For example, the material of the organic polymer optical waveguide wiring layer may be polymethyl methacrylate (PMMA), polystyrene (PS), polycarbonate (PC), epoxy resin, fluorinated polyimide, etc. The material, distribution, and preparation of the optical waveguide wiring layer 400 are not excessively limited herein.

[0063] As an example, the method for forming the micro-reflector 500 may include a semiconductor exposure and development patterning method, and preferably the micro-reflector 500 may be formed synchronously with the second rewiring layer 320, but is not limited to this. A bonding method may also be used to bond the pre-prepared micro-reflector 500 to the first rewiring layer 310.

[0064] The structure of the micro-reflector 500 may include a composite structure with a polymer material or inorganic silicon material inside and a metal material covering the surface. There is no excessive restriction on the material, distribution, morphology and preparation method of the micro-reflector 500.

[0065] As an example, the second rewiring layer 320 is preferably an organic rewiring layer, that is, the dielectric layer of the second rewiring layer 320 can be made of polyimide (PI) or the like, so as to facilitate subsequent electrical connection with the chip, and when preparing the second rewiring layer 320, the influence of high temperature on the optical waveguide wiring layer 400 can be avoided. The material, number of layers, layout, preparation method, etc. of the second rewiring layer 320 can be selected as needed and are not excessively restricted here.

[0066] Specifically, the order of forming the patterned optical waveguide wiring layer 400, the micro-reflectors 500 and the second re-wiring layer 320 on the first re-wiring layer 310 can be changed according to the process selected for each component. For example, the patterned optical waveguide wiring layer 400 can be formed on the first re-wiring layer 310 by a semiconductor exposure and development method, and then the pre-prepared micro-reflectors 500 are bonded to the first re-wiring layer 310 by a bonding method, and finally the second re-wiring layer 320 is formed by a semiconductor exposure and development method. Of course, the pre-prepared micro-reflectors 500 can also be bonded to the first re-wiring layer 310 by a bonding method, and then the optical waveguide wiring layer 400 and the second re-wiring layer 320 are formed. Of course, the optical waveguide wiring layer 400 can also be formed first and then the micro-reflectors 500 and the second re-wiring layer 320 having the same material composition are formed simultaneously. There is no restriction on the order of preparing the optical waveguide wiring layer 400 , the micro-reflector 500 and the second redistribution layer 320 .

[0067] Next, referring to FIG. 1 and FIG. 4 , step S4 is performed to provide a first supporting substrate 610 , and bond the second re-distribution layer 320 to the first supporting substrate 610 .

[0068] Specifically, the first supporting substrate 610 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., so as to provide support for subsequent processes through the first supporting substrate 610. In order to facilitate the subsequent removal of the first supporting substrate 610, in this embodiment, a first separation layer 611 is preferably formed on the surface of the first supporting substrate 610. The first separation layer 611 includes but is not limited to a tape and a polymer layer. For example, the first separation layer 611 can optionally use a photothermal conversion layer, so that the first separation layer 611 can be subsequently heated by, for example, a laser to remove the first supporting substrate 610, thereby improving operational convenience.

[0069] Next, referring to FIG. 1 and FIG. 5 , step S5 is performed to thin the TSV substrate 100 to expose the second end of the TSV metal pillar 200 .

[0070] Specifically, a chemical mechanical polishing (CMP) process may be used to expose the second end of the TSV metal pillar 200 and provide the TSV substrate 100 with a relatively flat surface to facilitate subsequent processes. Of course, only a process such as mechanical polishing may be used to expose the TSV metal pillar 200, and this is not overly limited here.

[0071] Next, step S6 is performed to form a third redistribution layer 330 on the second surface of the TSV substrate 100 . The third redistribution layer 330 is electrically connected to the second end of the TSV metal pillar 200 .

[0072] Next, step S7 is performed to form a first metal bump 710 on the third redistribution layer 330 . The first metal bump 710 is electrically connected to the third redistribution layer 330 .

[0073] Specifically, the third rewiring layer 330 can be an organic rewiring layer, that is, the material of the dielectric layer of the third rewiring layer 330 can be selected as PI, etc. The material, number of layers, layout, preparation method, etc. of the third rewiring layer 330 can be selected according to needs, and no excessive restrictions are imposed here.

[0074] The first metal bump 710 may be a C4 metal bump, but is not limited thereto and is not overly restricted herein.

[0075] Next, referring to FIG. 1 and FIG. 6 , step S8 is performed to remove the first support substrate 610 , provide a second support substrate 620 , and bond the first metal bump 710 to the second support substrate 620 .

[0076] Specifically, the second supporting substrate 620 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., so as to provide support for subsequent processes through the second supporting substrate 620. In order to facilitate the subsequent removal of the second supporting substrate 620, in this embodiment, a second separation layer 621 is preferably formed on the surface of the second supporting substrate 620. The second separation layer 621 includes but is not limited to a tape and a polymer layer. For example, the second separation layer 621 can optionally use a photothermal conversion layer, so that the second separation layer 621 can be subsequently heated by, for example, a laser to remove the second supporting substrate 620, thereby improving operational convenience.

[0077] Next, step S9 is executed to bond an electrical chip 810 and an optical chip 820 on the second rewiring layer 320. The electrical chip 810 and the optical chip 820 are both electrically connected to the second rewiring layer 320, and the photosensitive area 821 of the optical chip 820 is arranged corresponding to the micro-reflector 500 so that the micro-reflector 500 and the photosensitive area 821 can transmit light.

[0078] Specifically, it is preferred that both the electrical chip 810 and the optical chip 820 are electrically connected to the second redistribution layer 320 by flip-chip bonding. There is no excessive restriction on the types of the electrical chip 810 and the optical chip 820.

[0079] Preferably, a first underfill layer 910 may be formed between the electrical chip 810, the optical chip 820, and the second rewiring layer 320 to fill the gaps, thereby forming a protective layer, improving bonding strength, and protecting against the effects of moisture, gas, etc. The material of the first underfill layer 910 can be selected as needed, and any insulating material is sufficient, and is not excessively limited herein.

[0080] Next, referring to FIG. 1 and FIG. 7 , step S10 is performed to remove the second support substrate 620 .

[0081] As an example, when preparing at the wafer level, after removing the second supporting substrate 620 , a wafer cutting step may be performed to divide the wafer-level structure into single structures as shown in FIG. 7 . The cutting process is not limited here.

[0082] Next, referring to FIG. 8 , a substrate 110 is provided, the first metal bumps 710 are bonded to the substrate 110 , and the substrate 110 and the first metal bumps 710 are electrically connected.

[0083] As an example, referring to FIG8 , after bonding the first metal bump 710 to the substrate 110, a second underfill layer 920 can be formed between the third redistribution layer 330 and the substrate 110 to fill the gap. This provides a protective layer, enhances bonding strength, and protects against the effects of moisture, gas, and the like. The material of the second underfill layer 920 can be selected as needed, and any insulating material is sufficient, and is not excessively limited herein.

[0084] Furthermore, after the first metal bump 710 is bonded to the substrate 110 , a carrier may be provided to form a second metal bump 720 on the surface of the substrate 110 for subsequent electrical extraction.

[0085] 1 and 9 , step S11 is performed to provide a connector 120 and bond the connector 120 to the substrate 110 . The connector 120 is disposed correspondingly to the optical waveguide wiring layer 400 to achieve optical transmission. The specific type of the connector 120 is not particularly limited herein.

[0086] Furthermore, referring to FIG. 10 , the process may further include providing a heat sink 130 and bonding the heat sink 130 , wherein the heat sink 130 after bonding may be in direct and / or indirect contact with the electrical chip 810 and / or the optical chip 820 .

[0087] Specifically, the heat sink 130 can be made of an aluminum heat sink cover or a heat sink cover made of other materials, such as iron, copper, etc., without excessive restrictions, and the heat sink 130 can be in direct or indirect contact with the electrical chip 810 and / or the optical chip 820, without excessive restrictions, so that good heat dissipation can be achieved through the heat sink 130.

[0088] 2 to 10 , this embodiment further provides an optoelectronic integrated semiconductor packaging structure, which can be directly prepared using the above-mentioned preparation process. Thus, the materials, preparation process, etc. of the semiconductor packaging structure can all be referred to the above content. Of course, as needed, the optoelectronic integrated semiconductor packaging structure can also be prepared using other preparation processes.

[0089] Specifically, in this embodiment, the optoelectronic integrated semiconductor packaging structure includes: a TSV substrate 100, a first redistribution layer 310, an optical waveguide wiring layer 400, a micro-reflector 500, a second redistribution layer 320, a third redistribution layer 330, a first metal bump 710, an electrical chip 810, an optical chip 820, a substrate 110 and a connector 120.

[0090] Among them, the first surface of the TSV substrate 100 exposes the first end of the TSV metal column 200; the first rewiring layer 310 is located on the first surface of the TSV substrate 100, and the first rewiring layer 310 is electrically connected to the first end of the TSV metal column 200; the patterned optical waveguide wiring layer 400 is located on the first rewiring layer 310; the micro-mirror 500 is located on the first rewiring layer 310, and the optical waveguide wiring layer 400 is correspondingly arranged with the micro-mirror 500; the second rewiring layer 320 is located on the first rewiring layer 310 and is electrically connected to the first rewiring layer 310, and covers the optical waveguide wiring layer 400 to expose the micro-mirror 500; the third rewiring layer 330 is located on the TSV substrate 100 On the second surface, the third rewiring layer 330 is electrically connected to the second end of the TSV metal column 200; the first metal bump 710 is located on the third rewiring layer 330 and is electrically connected to the third rewiring layer 330; the electrical chip 810 and the optical chip 820 are both bonded to the second rewiring layer 320, and the electrical chip 810 and the optical chip 820 are both electrically connected to the second rewiring layer 320, and the photosensitive area 821 of the optical chip 820 is corresponding to the micro-reflector 500; the substrate 110 is bonded to the first metal bump 710, and the substrate 110 is electrically connected to the first metal bump 710; the connector 120 is bonded to the substrate 110, and the connector 120 is corresponding to the optical waveguide wiring layer 400.

[0091] Furthermore, the surface of the substrate 110 may further include a second metal bump 720 to facilitate subsequent electrical extraction.

[0092] Furthermore, a first bottom filling layer 910 may be provided between the electrical chip 810, the optical chip 820 and the second rewiring layer 320 to form a protective layer, thereby improving the bonding strength and avoiding the influence of moisture, gas, etc.; and a second bottom filling layer 920 for filling the gap may be provided between the third rewiring layer 330 and the substrate 110 to form a protective layer, thereby improving the bonding strength and avoiding the influence of moisture, gas, etc.

[0093] Furthermore, a heat sink 130 may be included. The heat sink 130 may be in direct and / or indirect contact with the electrical chip 810 and / or the optical chip 820 , so that good heat dissipation is achieved through the heat sink 130 .

[0094] In summary, the optoelectronic integrated semiconductor packaging structure and its preparation method of the present invention, through the TSV substrate, base plate, rewiring layer, optical waveguide wiring layer and micro-reflector, seal the optical chip and the electrical chip, and realize the stacked interconnection and staggered routing of electrical signal wiring and optical signal wiring, so as to reduce the packaging area, increase the wiring density, effectively shorten the transmission path of optical signals and electrical signals, reduce signal attenuation, and meet the needs of high-density integrated packaging.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing an optoelectronic integrated semiconductor packaging structure, characterized in that: The following steps are involved: Providing a TSV substrate, wherein a first surface of the TSV substrate exposes a first end of a TSV metal column; forming a first rewiring layer on the first surface of the TSV substrate, wherein the first rewiring layer is electrically connected to the first end of the TSV metal column; A patterned optical waveguide wiring layer, a micro-reflector and a second re-wiring layer are formed on the first re-wiring layer, wherein the second re-wiring layer is electrically connected to the first re-wiring layer, the optical waveguide wiring layer and the micro-reflector are arranged correspondingly, and the second re-wiring layer covers the optical waveguide wiring layer to expose the micro-reflector; providing a first supporting substrate, and bonding the second rewiring layer to the first supporting substrate; Thinning the TSV substrate to expose the second end of the TSV metal column; forming a third rewiring layer on the second surface of the TSV substrate, wherein the third rewiring layer is electrically connected to the second end of the TSV metal column; forming a metal bump on the third rewiring layer, wherein the metal bump is electrically connected to the third rewiring layer; removing the first supporting substrate, providing a second supporting substrate, and bonding the metal bump to the second supporting substrate; Bonding an electric chip and an optical chip on the second rewiring layer, wherein the electric chip and the optical chip are both electrically connected to the second rewiring layer, and a photosensitive area of ​​the optical chip is arranged corresponding to the micro-reflector; removing the second supporting substrate, providing a base plate, bonding the metal bump to the base plate, and electrically connecting the base plate to the metal bump; A connector is provided and bonded to the substrate, and the connector is arranged corresponding to the optical waveguide wiring layer.

2. The method for preparing an optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method of forming the micro-mirror includes a semiconductor exposure and development patterning method or a bonding method.

3. The method for preparing the optoelectronic integrated semiconductor packaging structure according to claim 2, characterized in that: When the micro-mirror is prepared by a semiconductor exposure and development patterning method, the micro-mirror and the second rewiring layer are formed synchronously.

4. The method for preparing an optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method of forming the optical waveguide wiring layer includes a semiconductor exposure and development method, and the formed optical waveguide wiring layer includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer or a lithium borate optical waveguide wiring layer.

5. The method for preparing an optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method further includes the steps of providing a heat sink and bonding the heat sink, wherein the heat sink after bonding is in direct and / or indirect contact with the electrical chip and / or the optical chip.

6. The method for preparing an optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: After removing the second supporting substrate, the method further includes a step of wafer cutting.

7. The method for preparing an optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: A first bottom filling layer filling the gap is formed between the electric chip, the optical chip and the second rewiring layer; and a second bottom filling layer filling the gap is formed between the third rewiring layer and the substrate.

8. The method for preparing an optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The first rewiring layer formed includes a damascene rewiring layer; the second rewiring layer formed includes an organic rewiring layer; and the third rewiring layer formed includes an organic rewiring layer.

9. An optoelectronic integrated semiconductor packaging structure, characterized in that: The optoelectronic integrated semiconductor packaging structure comprises: A TSV substrate, wherein a first surface of the TSV substrate exposes a first end of a TSV metal column; A first rewiring layer, the first rewiring layer is located on a first surface of the TSV substrate, and the first rewiring layer is electrically connected to a first end of the TSV metal column; a patterned optical waveguide wiring layer, the optical waveguide wiring layer being located on the first rewiring layer; A micro-reflector, wherein the micro-reflector is located on the first rewiring layer, and the optical waveguide wiring layer is arranged corresponding to the micro-reflector; a second rewiring layer, the second rewiring layer being located on the first rewiring layer and electrically connected to the first rewiring layer, and covering the optical waveguide wiring layer to expose the micro-reflector; A third rewiring layer, the third rewiring layer is located on the second surface of the TSV substrate, and the third rewiring layer is electrically connected to the second end of the TSV metal column; A metal bump, the metal bump is located on the third rewiring layer and is electrically connected to the third rewiring layer; An electrical chip and an optical chip, wherein the electrical chip and the optical chip are both bonded to the second rewiring layer, the electrical chip and the optical chip are both electrically connected to the second rewiring layer, and a photosensitive area of ​​the optical chip is arranged corresponding to the micro-reflector; A substrate, the substrate is bonded to the metal bump, and the substrate is electrically connected to the metal bump; A connector is bonded to the substrate and is arranged corresponding to the optical waveguide wiring layer.

10. The optoelectronic integrated semiconductor packaging structure according to claim 9, characterized in that: A heat sink is also included, and the heat sink is in direct and / or indirect contact with the electric chip and / or the optical chip.

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