2.5d photoelectric integrated semiconductor package structure and manufacturing method therefor

Abstract

The present invention provides a 2.5D photoelectric integrated semiconductor package structure and a manufacturing method therefor. An optical chip and an electric chip are jointly packaged by means of a TSV substrate, a substrate, rewiring layers, an optical waveguide wiring layer, and micro-mirrors, such that stacked interconnection and staggered distribution of electric and optical signal wirings can be implemented, thereby reducing the package area, increasing the wiring density, effectively shortening the transmission paths of optical and electric signals, reducing signal attenuation, and satisfying the requirement for high-density integrated packaging.

Description

2.5D optoelectronic integrated semiconductor packaging structure and preparation method thereof Technical Field

[0001] The present invention belongs to the field of semiconductor packaging and relates to a 2.5D optoelectronic integrated semiconductor packaging structure and a preparation method thereof. Background Art

[0002] With the continuous development of big data, artificial intelligence, telemedicine, the Internet of Things, e-commerce, and 5G communications, global data traffic has grown explosively. Lower-cost, more reliable, faster, and higher-density circuits are the goals pursued by integrated circuit packaging.

[0003] To meet the demand for internet traffic, data center node bandwidth needs to reach 10Tb / s. To mitigate the growing trend of data center energy consumption, it is imperative to find ways to reduce the power consumption of systems and devices. Driven by ultra-high data capacity, traditional electronic chip manufacturing processes are approaching 10nm, and CMOS processes are approaching their physical limits. Due to the low signal attenuation, low energy consumption, high bandwidth, and CMOS compatibility of light, the industry generally believes that silicon photonics, by integrating mature microelectronics and optoelectronics technologies, can not only reduce chip size, lower cost and power consumption, but also improve reliability, making them a promising "More Than Moore" high-speed information engine. Therefore, the introduction of silicon photonics technology is essential. Since the goal of introducing silicon photonics is to increase input / output (I / O) bandwidth and minimize energy consumption, the packaging of optical integrated circuits (PICs) and electrical integrated circuits (EICs) is crucial, as these factors directly impact I / O bandwidth and energy consumption.

[0004] Existing 2.5D optoelectronic integrated semiconductor packaging structures mostly directly bond the optical and electrical integrated chips to a substrate, electrically connecting them via wire bonds or flip-chip bonding. Because silicon photonics process nodes are relatively backward compared to electrical chips—for example, the current silicon photonics process nodes for monolithic integration are 45nm and 32nm, significantly behind the sub-10nm process nodes for electrical chips—existing 2.5D optoelectronic integrated semiconductor packaging structures struggle to meet the demands of high-density integrated packaging.

[0005] Therefore, it is necessary to provide a 2.5D optoelectronic integrated semiconductor packaging structure and a preparation method thereof.

[0006] Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a 2.5D optoelectronic integrated semiconductor packaging structure and a preparation method thereof, which is used to solve the problem in the prior art that it is difficult to perform high-density integrated packaging of optical chips and electronic chips.

[0008] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a 2.5D optoelectronic integrated semiconductor packaging structure, comprising the following steps:

[0009] Providing a TSV substrate, wherein a first surface of the TSV substrate exposes a first end of a TSV metal pillar;

[0010] forming a first redistribution layer on the first surface of the TSV substrate, wherein the first redistribution layer is electrically connected to the first end of the TSV metal pillar;

[0011] forming a second redistribution layer on the first redistribution layer, wherein the second redistribution layer is electrically connected to the first redistribution layer;

[0012] providing a first supporting substrate, and bonding the second rewiring layer to the first supporting substrate;

[0013] Thinning the TSV substrate to expose the second end of the TSV metal pillar;

[0014] forming a third redistribution layer on the second surface of the TSV substrate, wherein the third redistribution layer is electrically connected to the second end of the TSV metal pillar;

[0015] forming a metal bump on the third redistribution layer, wherein the metal bump is electrically connected to the third redistribution layer;

[0016] Performing patterning to form a groove penetrating the third redistribution layer, the TSV substrate, the first redistribution layer, and the second redistribution layer;

[0017] removing the first supporting substrate, providing a second supporting substrate, and bonding the metal bump to the second supporting substrate;

[0018] Bonding an electrical chip and an optical chip on the second redistribution layer, wherein the electrical chip and the optical chip are both electrically connected to the second redistribution layer, and a photosensitive area of ​​the optical chip is arranged corresponding to the groove;

[0019] removing the second supporting substrate to provide a base plate, wherein the base plate is provided with an optical waveguide wiring layer, a circuit wiring layer, and a micro-reflector, wherein the micro-reflector is provided corresponding to the optical waveguide wiring layer and is exposed on the base plate;

[0020] Bonding the substrate to the metal bump, electrically connecting the circuit wiring layer to the metal bump, and disposing the micro-mirrors corresponding to the photosensitive areas;

[0021] A connector is provided, and the connector is bonded to the substrate, and the connector is arranged corresponding to the optical waveguide wiring layer.

[0022] Optionally, the method further includes the step of forming an optical waveguide in the trench to fill the trench.

[0023] Optionally, the method further includes forming a light protection layer in the trench to cover the sidewalls of the trench.

[0024] Optionally, the method of patterning the grooves includes mechanical drilling, laser drilling or chemical etching.

[0025] Optionally, the method of forming the micro-mirror includes a semiconductor exposure and development patterning method or a bonding method.

[0026] Optionally, the method of forming the optical waveguide wiring layer includes a semiconductor exposure and development method, and the formed optical waveguide wiring layer includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.

[0027] Optionally, the method further includes providing a heat sink and bonding the heat sink, wherein the heat sink after bonding is in direct and / or indirect contact with the electrical chip and / or the optical chip; and performing wafer cutting after removing the second supporting substrate.

[0028] The present invention further provides a 2.5D optoelectronic integrated semiconductor packaging structure, the 2.5D optoelectronic integrated semiconductor packaging structure comprising:

[0029] A TSV substrate, wherein a first surface of the TSV substrate exposes a first end of a TSV metal pillar;

[0030] a first redistribution layer, the first redistribution layer being located on a first surface of the TSV substrate and electrically connected to a first end of the TSV metal pillar;

[0031] a second redistribution layer, the second redistribution layer being located on the first redistribution layer and electrically connected to the first redistribution layer;

[0032] a third redistribution layer, the third redistribution layer being located on the second surface of the TSV substrate and electrically connected to the second end of the TSV metal pillar;

[0033] a metal bump, the metal bump being located on the third redistribution layer and electrically connected to the third redistribution layer;

[0034] a trench, wherein the trench penetrates the third redistribution layer, the TSV substrate, the first redistribution layer, and the second redistribution layer;

[0035] an electrical chip and an optical chip, wherein the electrical chip and the optical chip are both bonded to the second redistribution layer and electrically connected to the second redistribution layer, and a photosensitive area of ​​the optical chip is arranged corresponding to the groove;

[0036] a substrate, the substrate being bonded to the metal bumps, the substrate being provided with an optical waveguide wiring layer, a circuit wiring layer, and a micro-reflector, the micro-reflector being provided corresponding to the optical waveguide wiring layer and exposed on the substrate, the circuit wiring layer being electrically connected to the metal bumps, and the micro-reflector being provided corresponding to the photosensitive area;

[0037] A connector is bonded to the substrate and is arranged corresponding to the optical waveguide wiring layer.

[0038] Optionally, the trench further comprises an optical waveguide filling the trench; or the trench further comprises a light protection layer covering the sidewall of the trench.

[0039] Optionally, the micro-mirrors are arranged in an array.

[0040] As described above, the 2.5D optoelectronic integrated semiconductor packaging structure and its preparation method of the present invention seal the optical chip and the electrical chip through the TSV substrate, the base plate, the rewiring layer, the optical waveguide wiring layer and the micro-reflector, and can realize the stacked interconnection and staggered routing of the electrical signal wiring and the optical signal wiring, so as to reduce the packaging area, increase the wiring density, effectively shorten the transmission path of the optical signal and the electrical signal, reduce signal attenuation, and meet the needs of high-density integrated packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG1 is a schematic diagram showing a process flow for preparing a 2.5D optoelectronic integrated semiconductor packaging structure according to an embodiment of the present invention.

[0042] FIG. 2 is a schematic structural diagram showing a structure after forming a first redistribution layer according to an embodiment of the present invention.

[0043] FIG. 3 is a schematic structural diagram showing a second redistribution layer formed in an embodiment of the present invention.

[0044] FIG. 4 is a schematic structural diagram showing a structure after forming a first metal bump according to an embodiment of the present invention.

[0045] FIG. 5 is a schematic diagram showing a structure after grooves are formed in an embodiment of the present invention.

[0046] FIG. 6 is a schematic diagram showing a structure after an optical waveguide filling a trench is formed according to an embodiment of the present invention.

[0047] FIG. 7 is a schematic structural diagram showing a structure after a light protection layer covering the sidewalls of the trench is formed according to an embodiment of the present invention.

[0048] FIG8 is a schematic diagram showing the structure after bonding the electrical chip and the optical chip in an embodiment of the present invention.

[0049] FIG. 9 is a schematic diagram showing the structure after the second supporting substrate is removed according to an embodiment of the present invention.

[0050] FIG. 10 is a schematic structural diagram of a substrate in an embodiment of the present invention.

[0051] FIG. 11 is a schematic structural diagram showing a second metal bump formed in an embodiment of the present invention.

[0052] FIG. 12 is a schematic structural diagram showing a bonding connector according to an embodiment of the present invention.

[0053] FIG13 is a schematic diagram showing the structure after bonding the heat sink in an embodiment of the present invention.

[0054] FIG. 14 is a schematic diagram of a partial top view of a 2.5D optoelectronic integrated semiconductor package structure according to an embodiment of the present invention.

[0055] Explanation of component numbers 100-TSV substrate; 200-TSV metal pillar; 310-first redistribution layer; 320-second redistribution layer; 330-third redistribution layer; 300-groove; 301-optical waveguide; 302-light protection layer; 410-optical waveguide wiring layer; 420-circuit wiring layer; 500-micro-reflector; 610-first supporting substrate; 620-second supporting substrate; 611-first separation layer; 621-second separation layer; 710-first metal bump; 720-second metal bump; 810-electric chip; 820-optical chip; 821-photosensitive area; 910-first bottom filling layer; 920-second bottom filling layer; 110-substrate; 120-connector; 130-heat sink. DETAILED DESCRIPTION

[0056] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0058] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "over," and the like may be used herein to describe the relationship of one element or feature to other elements or features illustrated in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0059] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0060] As shown in Figure 1, this embodiment provides a method for preparing a 2.5D optoelectronic integrated semiconductor packaging structure. Through the TSV substrate, base plate, rewiring layer, optical waveguide wiring layer and micro-reflector, the optical chip and the electrical chip are sealed together, which can realize the stacked interconnection and staggered routing of electrical signal wiring and optical signal wiring, so as to reduce the packaging area, increase the wiring density, effectively shorten the transmission path of optical and electrical signals, reduce signal attenuation, and meet the needs of high-density integrated packaging.

[0061] The following further describes the preparation of the 2.5D optoelectronic integrated semiconductor packaging structure with reference to FIG. 2 to FIG. 14 , specifically including:

[0062] First, referring to FIG. 1 and FIG. 2 , step S1 is performed to provide a TSV substrate 100 , wherein a first end of a TSV metal pillar 200 is exposed on a first surface of the TSV substrate 100 .

[0063] Specifically, the TSV substrate 100 may include a wafer-level substrate with a size of 4 inches, 6 inches, 8 inches, 12 inches, etc., to further improve process efficiency, but the size of the TSV substrate 100 is not limited thereto.

[0064] Next, step S2 is performed to form a first redistribution layer 310 on the first surface of the TSV substrate 100 , and the first redistribution layer 310 is electrically connected to the first end of the TSV metal pillar 200 .

[0065] Specifically, the first rewiring layer 310 may be a Damascus rewiring layer, wherein the material of the dielectric layer may include silicon oxide or silicon nitride, and the material of the metal wiring may include copper, aluminum, etc. A smaller line width and line spacing can be obtained through the first rewiring layer 310 to meet subsequent high-density connection requirements. The material, number of layers, layout, preparation method, etc. of the first rewiring layer 310 can be selected according to needs, and no excessive restrictions are imposed here.

[0066] Next, referring to FIG. 1 and FIG. 3 , step S3 is performed to form a second redistribution layer 320 on the first redistribution layer 310 . The second redistribution layer 320 is electrically connected to the first redistribution layer 310 .

[0067] Specifically, the second rewiring layer 320 is preferably an organic rewiring layer, that is, the dielectric layer of the second rewiring layer 320 can be made of polyimide (PI) or the like, so as to facilitate subsequent electrical connection with the chip. The material, number of layers, layout, preparation method, etc. of the second rewiring layer 320 can be selected according to needs and no excessive restrictions are imposed here.

[0068] Next, referring to FIG. 1 and FIG. 4 , step S4 is performed to provide a first supporting substrate 610 , and bond the second re-distribution layer 320 to the first supporting substrate 610 .

[0069] Specifically, the first supporting substrate 610 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., so as to provide support for subsequent processes through the first supporting substrate 610. In order to facilitate the subsequent removal of the first supporting substrate 610, in this embodiment, a first separation layer 611 is preferably formed on the surface of the first supporting substrate 610. The first separation layer 611 includes but is not limited to a tape and a polymer layer. For example, the first separation layer 611 can optionally use a photothermal conversion layer, so that the first separation layer 611 can be subsequently heated by, for example, a laser to remove the first supporting substrate 610, thereby improving operational convenience.

[0070] Next, step S5 is performed to thin the TSV substrate 100 to expose the second end of the TSV metal pillar 200 .

[0071] Specifically, a chemical mechanical polishing (CMP) process may be used to expose the second end of the TSV metal pillar 200 and provide the TSV substrate 100 with a relatively flat surface to facilitate subsequent processes. Of course, only a process such as mechanical polishing may be used to expose the TSV metal pillar 200, and this is not overly limited here.

[0072] Next, step S6 is performed to form a third redistribution layer 330 on the second surface of the TSV substrate 100 . The third redistribution layer 330 is electrically connected to the second end of the TSV metal pillar 200 .

[0073] Next, step S7 is performed to form a first metal bump 710 on the third redistribution layer 330 . The first metal bump 710 is electrically connected to the third redistribution layer 330 .

[0074] Specifically, the third rewiring layer 330 can be an organic rewiring layer, that is, the material of the dielectric layer of the third rewiring layer 330 can be selected as PI, etc. The material, number of layers, layout, preparation method, etc. of the third rewiring layer 330 can be selected according to needs, and no excessive restrictions are imposed here.

[0075] The first metal bump 710 may be a C4 metal bump, but is not limited thereto and is not overly restricted herein.

[0076] Next, referring to FIG. 1 and FIG. 5 , step S8 is executed to perform patterning to form a trench 300 penetrating the third redistribution layer 330 , the TSV substrate 100 , the first redistribution layer 310 , and the second redistribution layer 320 .

[0077] As an example, the method of patterning the groove 300 may include mechanical drilling, laser drilling or chemical etching, which can be selected according to needs and is not overly limited here.

[0078] In another embodiment, referring to FIG. 6 , the method may further include forming an optical waveguide 301 in the trench 300 to fill the trench 300 , so as to reduce light transmission loss through the optical waveguide 301 .

[0079] The material of the optical waveguide 301 may include an organic polymer optical waveguide, a silicon-based optical waveguide, a lithium niobate optical waveguide, or a lithium borate optical waveguide. For example, the material of the organic polymer optical waveguide may be polymethyl methacrylate (PMMA), polystyrene (PS), polycarbonate (PC), epoxy resin, fluorinated polyimide, etc. There is no excessive restriction on the material and preparation of the optical waveguide 301.

[0080] In another embodiment, referring to FIG. 7 , the method may further include forming a light protection layer 302 in the trench 300 to cover the sidewall of the trench 300 , so as to protect the sidewall of the trench 300 by the light protection layer 302 to reduce light transmission loss.

[0081] The light protection layer 302 can be formed by coating the groove 300 with metal through coating or vacuum sputtering to form a metal reflective film layer. Alternatively, the groove 300 can be filled with an organic or inorganic composite material and then mechanical drilling, laser drilling, or chemical etching can be used to form the light protection layer 302 only on the sidewalls of the groove 300. The material and preparation of the light protection layer 302 are not particularly limited.

[0082] Next, referring to FIG. 1 and FIG. 8 , step S9 is performed to remove the first support substrate 610 , provide a second support substrate 620 , and bond the first metal bumps 710 to the second support substrate 620 .

[0083] Specifically, the second supporting substrate 620 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., so as to provide support for subsequent processes through the second supporting substrate 620. In order to facilitate the subsequent removal of the second supporting substrate 620, in this embodiment, a second separation layer 621 is preferably formed on the surface of the second supporting substrate 620. The second separation layer 621 includes but is not limited to a tape and a polymer layer. For example, the second separation layer 621 can optionally use a photothermal conversion layer, so that the second separation layer 621 can be subsequently heated by, for example, a laser to remove the second supporting substrate 620, thereby improving operational convenience.

[0084] Next, step S10 is executed to bond an electrical chip 810 and an optical chip 820 on the second rewiring layer 320. The electrical chip 810 and the optical chip 820 are both electrically connected to the second rewiring layer 320, and the photosensitive area 821 of the optical chip 820 is arranged corresponding to the groove 300 so that the photosensitive area 821 can transmit light through the groove 300.

[0085] Specifically, it is preferred that both the electrical chip 810 and the optical chip 820 are electrically connected to the second redistribution layer 320 by flip-chip bonding. There is no excessive restriction on the types of the electrical chip 810 and the optical chip 820.

[0086] Preferably, a first underfill layer 910 may be formed between the electrical chip 810, the optical chip 820, and the second rewiring layer 320 to fill the gaps, thereby forming a protective layer, improving bonding strength, and protecting against the effects of moisture, gas, etc. The material of the first underfill layer 910 can be selected as needed, and any insulating material is sufficient, and is not excessively limited herein.

[0087] Next, referring to FIG. 1 and FIG. 9 , step S11 is performed to remove the second support substrate 620 .

[0088] As an example, when preparing at the wafer level, after removing the second supporting substrate 620 , a wafer cutting step may be performed to divide the wafer-level structure into single structures as shown in FIG. 9 . The cutting process is not limited here.

[0089] 10 , a substrate 110 is provided. The substrate 110 is provided with an optical waveguide wiring layer 410 , a circuit wiring layer 420 and micro-reflectors 500 . The micro-reflectors 500 are arranged corresponding to the optical waveguide wiring layer 410 and exposed on the substrate 110 .

[0090] Specifically, the optical waveguide wiring layer 410 and the micro-reflector 500 are arranged correspondingly to each other, so that good light transmission can be performed between the optical waveguide wiring layer 410 and the micro-reflector 500 , and the micro-reflector 500 exposed on the substrate 110 can facilitate subsequent light transmission.

[0091] As an example, a method for forming the optical waveguide wiring layer 410 may include a semiconductor exposure and development method, and the formed optical waveguide wiring layer 410 may include an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer. For example, the material of the organic polymer optical waveguide wiring layer may be polymethyl methacrylate (PMMA), polystyrene (PS), polycarbonate (PC), epoxy resin, fluorinated polyimide, etc. There is no excessive limitation on the material, distribution, and preparation of the optical waveguide wiring layer 410.

[0092] As an example, a method for forming the micro-mirror 500 may include a semiconductor exposure and development patterning method, but is not limited thereto. A bonding method may also be used to bond the pre-fabricated micro-mirror 500 to the substrate 110 .

[0093] The structure of the micro-reflector 500 may include a composite structure with a polymer material or inorganic silicon material inside and a metal material covering the surface. There is no excessive restriction on the material, distribution, morphology and preparation method of the micro-reflector 500.

[0094] Specifically, when preparing the substrate 110, the optical waveguide wiring layer 410 can be formed in the substrate 110 by a semiconductor exposure and development patterning method, so that the substrate 110 has both the optical waveguide wiring layer 410 and the circuit wiring layer 420 for circuit routing and optical routing, and the substrate 110 has a groove for accommodating the micro-reflector 500, and then the pre-prepared micro-reflector 500 can be attached to the groove in the substrate 110 by a bonding method, or the micro-reflector 500 can be formed in the groove by a semiconductor exposure and development method. The specific preparation is not overly restricted here.

[0095] 1 and 11 , step S12 is performed to bond the substrate 110 to the first metal bump 710 , electrically connect the circuit wiring layer 420 to the first metal bump 710 , and arrange the micro-mirrors 500 corresponding to the photosensitive regions 821 .

[0096] As an example, referring to FIG. 11 , after bonding the first metal bump 710 to the substrate 110, a second underfill layer 920 may be formed between the third redistribution layer 330 and the substrate 110 to fill the gap. This provides a protective layer, enhances bonding strength, and protects against the effects of moisture, gas, and the like. The material of the second underfill layer 920 can be selected as needed, and any insulating material is sufficient, and is not particularly limited herein.

[0097] Furthermore, after the first metal bump 710 is bonded to the substrate 110 , a carrier may be provided to form a second metal bump 720 on the surface of the substrate 110 for subsequent electrical extraction.

[0098] 1 and 12 , step S13 is performed to provide a connector 120 , bond the connector 120 to the substrate 110 , and arrange the connector 120 corresponding to the optical waveguide wiring layer 410 to achieve optical transmission. The specific type of the connector 120 is not particularly limited.

[0099] Furthermore, referring to FIG. 13 , the process may further include providing a heat sink 130 and bonding the heat sink 130 , wherein the heat sink 130 after bonding may be in direct and / or indirect contact with the electrical chip 810 and / or the optical chip 820 .

[0100] Specifically, the heat sink 130 can be made of an aluminum heat sink cover or a heat sink cover made of other materials, such as iron, copper, etc., without excessive restrictions, and the heat sink 130 can be in direct or indirect contact with the electrical chip 810 and / or the optical chip 820, without excessive restrictions, so that good heat dissipation can be achieved through the heat sink 130.

[0101] As an example, referring to FIG. 14 , the micro-reflectors 500 may be arranged in an array, and the number and arrangement of the micro-reflectors 500 are not excessively limited herein.

[0102] 2 to 14 , this embodiment further provides a 2.5D optoelectronic integrated semiconductor packaging structure. The 2.5D optoelectronic integrated semiconductor packaging structure can be directly prepared using the above-mentioned preparation process. For details about the material and preparation process of the semiconductor packaging structure, please refer to the above-mentioned content. Of course, as needed, the 2.5D optoelectronic integrated semiconductor packaging structure can also be prepared using other preparation processes.

[0103] Specifically, in this embodiment, the 2.5D optoelectronic integrated semiconductor packaging structure includes: a TSV substrate 100, a first redistribution layer 310, a second redistribution layer 320, a third redistribution layer 330, a first metal bump 710, a groove 300, an electrical chip 810, an optical chip 820, a substrate 110, an optical waveguide wiring layer 410, a micro-reflector 500 and a connector 120.

[0104] Among them, the first surface of the TSV substrate 100 exposes the first end of the TSV metal column 200; the first redistribution layer 310 is located on the first surface of the TSV substrate 100 and is electrically connected to the first end of the TSV metal column 200; the second redistribution layer 320 is located on the first redistribution layer 310 and is electrically connected to the first redistribution layer 310; the third redistribution layer 330 is located on the second surface of the TSV substrate 100 and is electrically connected to the second end of the TSV metal column 200; the first metal bump 710 is located on the third redistribution layer 330 and is electrically connected to the third redistribution layer 330; the groove 300 passes through the third redistribution layer 330, the TSV substrate 100, the first redistribution layer 310 and the second rewiring layer 320; the electrical chip 810 and the optical chip 820 are both bonded to the second rewiring layer 320 and electrically connected to the second rewiring layer 320, and the photosensitive area 821 of the photonic chip 820 is arranged corresponding to the groove 300; the substrate 110 is bonded to the first metal bump 710, and the substrate 110 is provided with an optical waveguide wiring layer 410, a circuit wiring layer 420 and a micro-reflector 500, the micro-reflector 500 is arranged corresponding to the optical waveguide wiring layer 410 and exposed on the substrate 110, and the circuit wiring layer 420 is electrically connected to the first metal bump 710, and the micro-reflector 500 is arranged corresponding to the photosensitive area 821; the connector 120 is bonded to the substrate 110 and arranged corresponding to the optical waveguide wiring layer 410.

[0105] Furthermore, the trench 300 further comprises an optical waveguide 301 filling the trench 300 ; or the trench 300 further comprises a light protection layer 302 covering the sidewall of the trench 300 .

[0106] Furthermore, the surface of the substrate 110 may further include a second metal bump 720 to facilitate subsequent electrical extraction.

[0107] Furthermore, a first bottom filling layer 910 may be provided between the electrical chip 810, the optical chip 820 and the second rewiring layer 320 to form a protective layer, thereby improving the bonding strength and avoiding the influence of moisture, gas, etc.; and a second bottom filling layer 920 for filling the gap may be provided between the third rewiring layer 330 and the substrate 110 to form a protective layer, thereby improving the bonding strength and avoiding the influence of moisture, gas, etc.

[0108] Furthermore, a heat sink 130 may be included. The heat sink 130 may be in direct and / or indirect contact with the electrical chip 810 and / or the optical chip 820 , so that good heat dissipation is achieved through the heat sink 130 .

[0109] Furthermore, the micro-mirrors 500 may be arranged in an array.

[0110] In summary, the 2.5D optoelectronic integrated semiconductor packaging structure and its preparation method of the present invention, through the TSV substrate, base plate, rewiring layer, optical waveguide wiring layer and micro-reflector, seals the optical chip and the electrical chip, and can realize the stacked interconnection and staggered routing of electrical signal wiring and optical signal wiring, so as to reduce the packaging area, increase the wiring density, effectively shorten the transmission path of optical signals and electrical signals, reduce signal attenuation, and meet the needs of high-density integrated packaging.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a 2.5D optoelectronic integrated semiconductor packaging structure, characterized in that: The following steps are involved: Providing a TSV substrate, wherein a first surface of the TSV substrate exposes a first end of a TSV metal column; forming a first rewiring layer on the first surface of the TSV substrate, wherein the first rewiring layer is electrically connected to the first end of the TSV metal pillar; forming a second rewiring layer on the first rewiring layer, wherein the second rewiring layer is electrically connected to the first rewiring layer; providing a first supporting substrate, and bonding the second rewiring layer to the first supporting substrate; Thinning the TSV substrate to expose the second end of the TSV metal column; forming a third rewiring layer on the second surface of the TSV substrate, wherein the third rewiring layer is electrically connected to the second end of the TSV metal column; forming a metal bump on the third rewiring layer, wherein the metal bump is electrically connected to the third rewiring layer; Performing patterning to form a groove penetrating the third rewiring layer, the TSV substrate, the first rewiring layer, and the second rewiring layer; removing the first supporting substrate, providing a second supporting substrate, and bonding the metal bump to the second supporting substrate; Bonding an electrical chip and an optical chip on the second rewiring layer, wherein the electrical chip and the optical chip are both electrically connected to the second rewiring layer, and a photosensitive area of ​​the optical chip is arranged corresponding to the groove; The second supporting substrate is removed to provide a base plate, wherein the base plate is provided with an optical waveguide wiring layer, a circuit wiring layer and a micro-reflector, wherein the micro-reflector is provided corresponding to the optical waveguide wiring layer and exposed on the base plate; Bonding the substrate to the metal bump, electrically connecting the circuit wiring layer to the metal bump, and arranging the micro-reflector to correspond to the photosensitive area; A connector is provided, the connector is bonded to the substrate, and the connector is arranged corresponding to the optical waveguide wiring layer.

2. The method for preparing the 2.5D optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The step of forming an optical waveguide in the trench filling the trench is also included.

3. The method for preparing the 2.5D optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method further includes forming a light protection layer in the trench and covering the sidewall of the trench.

4. The method for preparing the 2.5D optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method of patterning to form the groove includes mechanical drilling, laser drilling or chemical etching.

5. The method for preparing the 2.5D optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method of forming the micro-mirror includes a semiconductor exposure and development patterning method or a bonding method.

6. The method for preparing the 2.5D optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method of forming the optical waveguide wiring layer includes a semiconductor exposure and development method, and the formed optical waveguide wiring layer includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer or a lithium borate optical waveguide wiring layer.

7. The method for preparing the 2.5D optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method further includes the steps of providing a heat sink and bonding the heat sink, wherein the heat sink after bonding is in direct and / or indirect contact with the electrical chip and / or the optical chip; and the method further includes the step of wafer cutting after removing the second supporting substrate.

8. A 2.5D optoelectronic integrated semiconductor packaging structure, characterized in that: The 2.5D optoelectronic integrated semiconductor packaging structure comprises: A TSV substrate, wherein a first surface of the TSV substrate exposes a first end of a TSV metal column; A first rewiring layer, the first rewiring layer is located on a first surface of the TSV substrate and is electrically connected to a first end of the TSV metal column; a second rewiring layer, the second rewiring layer being located on the first rewiring layer and electrically connected to the first rewiring layer; A third rewiring layer, the third rewiring layer is located on the second surface of the TSV substrate and is electrically connected to the second end of the TSV metal column; a metal bump, the metal bump being located on the third rewiring layer and electrically connected to the third rewiring layer; A groove, wherein the groove penetrates the third rewiring layer, the TSV substrate, the first rewiring layer and the second rewiring layer; An electrical chip and an optical chip, wherein the electrical chip and the optical chip are both bonded to the second rewiring layer and electrically connected to the second rewiring layer, and a photosensitive area of ​​the optical chip is arranged corresponding to the groove; A substrate, the substrate is bonded to the metal bump, the substrate is provided with an optical waveguide wiring layer, a circuit wiring layer and a micro-reflector, the micro-reflector is provided corresponding to the optical waveguide wiring layer and exposed on the substrate, the circuit wiring layer is electrically connected to the metal bump, and the micro-reflector is provided corresponding to the photosensitive area; A connector is bonded to the substrate and is arranged corresponding to the optical waveguide wiring layer.

9. The 2.5D optoelectronic integrated semiconductor packaging structure according to claim 8, characterized in that: The trench further comprises an optical waveguide filling the trench; or the trench further comprises a light protection layer covering a side wall of the trench.

10. The 2.5D optoelectronic integrated semiconductor packaging structure according to claim 8, characterized in that: The micro-mirrors are arranged in an array.

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