Computing device

Abstract

Embodiments of the present application provide a computing device, comprising: a first power supply circuit, a second power supply circuit, a power supply control circuit, a first load circuit, and a second load circuit. An output end of the first power supply circuit is electrically connected to a first input end of the power supply control circuit; an output end of the second power supply circuit is electrically connected to a second input end of the power supply control circuit; a first output end of the power supply control circuit is electrically connected to an input end of the first load circuit; a second output end of the power supply control circuit is electrically connected to an input end of the second load circuit; and the power supply control circuit is used for: determining whether an output voltage of the second power supply circuit is greater than a preset voltage; and when the output voltage of the second power supply circuit is greater than the preset voltage, controlling the first power supply circuit to stop supplying power to the first load circuit, and controlling the second power supply circuit to supply power to the first load circuit. Moreover, only one power supply branch supplies power to a load, and there is no need to provide a DC / DC circuit, thereby saving the circuit area, and shortening the development period.

Description

A computing device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 20, 2023, with application number 202311230767.9 and application name “A Computing Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of server technology, and in particular to a computing device. Background Art

[0003] The data processing unit (DPU) in the server is used to perform data processing. If the power output of the power supply circuit is sufficient, a single power supply circuit can be used to ensure the normal operation of the DPU.

[0004] However, there is a power supply scenario where the output power of a single power supply circuit is insufficient, and the first power supply circuit and the second power supply circuit are required to supply power simultaneously.

[0005] When both the first power supply circuit and the second power supply circuit supply power to the load, the two circuits need to be current-balanced, that is, the supply currents of the two circuits need to be output in proportion to their respective output powers to prevent backflow from one circuit to the other.

[0006] In the prior art, both power supply units are provided with a direct current / direct current (DC / DC) conversion circuit to control the supply current. The circuit is complex, occupies a large circuit area, and has a long development cycle.

[0007] Summary of the Invention

[0008] An embodiment of the present application provides a computing device that can realize powering a load with only one power supply unit without providing a current balancing circuit, thereby saving circuit area and shortening the development cycle.

[0009] An embodiment of the present application provides a computing device, comprising: a first power supply circuit, a second power supply circuit, a power supply control circuit, a first load circuit, and a second load circuit; the output end of the first power supply circuit is electrically connected to the first input end of the power supply control circuit; the output end of the second power supply circuit is electrically connected to the second input end of the power supply control circuit; the first output end of the power supply control circuit is electrically connected to the input end of the first load circuit; the second output end of the power supply control circuit is electrically connected to the input end of the second load circuit; the power supply control circuit is used to: determine whether the output voltage of the second power supply circuit is greater than a preset voltage; when the output voltage of the second power supply circuit is greater than the preset voltage, control the first power supply circuit to stop supplying power to the first load circuit, and control the second power supply circuit to supply power to the first load circuit.

[0010] The computing device provided in the embodiment of the present application includes two power supply branches. The two power supply branches do not supply power to the same load together. Through hardware, only one power supply branch supplies power to the load at the same time. In this way, there is no need to set up DC / DC circuits on both power supply branches, and no current sharing control is required. The circuit structure is simple, circuit area is saved, and the development cycle is shortened.

[0011] In one possible implementation, the power supply control circuit includes a first power supply branch, a second power supply branch and a first controller; wherein the output end of the first power supply circuit is electrically connected to the input end of the first power supply branch; the output end of the first power supply branch is electrically connected to the input end of the second load circuit; the output end of the second power supply circuit is electrically connected to the input end of the second power supply branch; the output end of the second power supply branch is electrically connected to the input end of the first load circuit; the first output end of the first controller is electrically connected to the control end of the first power supply branch; the second output end of the first controller is electrically connected to the control end of the second power supply branch; the power supply control circuit is used to control the first power supply branch to stop supplying power to the first load circuit when the output voltage of the second power supply circuit is greater than a preset voltage, and to control the second power supply circuit to supply power to the first load circuit, including: the first controller is used to: control the first power supply branch to turn off when the output voltage of the second power supply circuit is greater than a preset voltage, and control the second power supply branch to turn on.

[0012] The computing device provided in the embodiment of the present application includes two power supply branches, and one of the power supply circuits can be selected to power the load by comparing the output voltage of the second power supply circuit with a preset voltage. That is, the two power supply branches do not jointly power the same load. Through hardware implementation, only one power supply branch powers the load at the same time. In this way, there is no need to set up DC / DC circuits on both power supply branches, no current sharing control is required, the circuit structure is simple, circuit area is saved, and the development cycle is shortened.

[0013] In a possible implementation, the first power supply branch includes a first controllable switch tube and a second controllable switch tube; the second power supply branch includes a third controllable switch tube and a fourth controllable switch tube; wherein the first end of the first controllable switch tube is electrically connected to the output end of the first power supply circuit; the second end of the first controllable switch tube is electrically connected to the second end of the second controllable switch tube; the first end of the second controllable switch tube is electrically connected to the input end of the second load circuit; the first end of the third controllable switch tube is electrically connected to the output end of the second power supply circuit; the second end of the third controllable switch tube is electrically connected to the second end of the fourth controllable switch tube; the first end of the fourth controllable switch tube is electrically connected to the input end of the first load circuit; the first output end of the first controller is two, wherein, The two first output ends of the first controller are electrically connected to the control end of the first controllable switch tube and the control end of the second controllable switch tube, respectively; the first controller has two second output ends, wherein the two second output ends of the first controller are electrically connected to the control end of the third controllable switch tube and the control end of the fourth controllable switch tube, respectively; the first controller is used to control the first power supply branch to be turned off and the second power supply branch to be turned on when the output voltage of the second power supply circuit is greater than the preset voltage, including: the first controller is used to: when the output voltage of the second power supply circuit is greater than the preset voltage, control the first controllable switch tube and the second controllable switch tube to be turned off, and control the third controllable switch tube and the fourth controllable switch tube to be turned on.

[0014] The embodiments of the present application do not specifically limit the type of controllable switch tube; any switch tube that can be controlled to turn on and off is sufficient. To ensure that the power supply branch can be shut off in both directions, that is, the bidirectional current is shut off, each power supply branch needs to include two controllable switch tubes connected in series in reverse order, and each controllable switch tube includes a body diode. That is, the body diode serves as an anti-parallel diode of the controllable switch tube, which can block the reverse current. The diodes of the two controllable switch tubes in series are connected in reverse order to completely shut off the current.

[0015] A possible implementation method is that the first power supply branch includes a first slow-start circuit and a second controllable switch tube; the second power supply branch includes a second slow-start chip and a fourth controllable switch tube; wherein, the input end of the first slow-start circuit is electrically connected to the output end of the first power supply circuit; the output end of the first slow-start circuit is electrically connected to the second end of the second controllable switch tube; the first end of the second controllable switch tube is electrically connected to the input end of the second load circuit; the input end of the second slow-start circuit is electrically connected to the output end of the second power supply circuit; the output end of the second slow-start circuit is electrically connected to the second end of the fourth controllable switch tube; the first end of the fourth controllable switch tube is electrically connected to the input end of the first load circuit; the first output end of the first controller controls the control end of the second controllable switch tube; the second output end of the first controller controls the control end of the fourth controllable switch tube; the first controller is used to control the first power supply branch to be turned off and the second power supply branch to be turned on when the output voltage of the second power supply circuit is greater than a preset voltage, including: the first controller is used to: control the second controllable switch tube to be turned off and control the fourth controllable switch tube to be turned on when the output voltage of the second power supply circuit is greater than a preset voltage.

[0016] In the computing device provided by the embodiments of the present application, the first controller can be implemented using a combining control chip. That is, the automatic selection of two power supply branches is achieved by utilizing a slow-start chip and a combining control chip. This simplifies implementation, simplifies control logic, and reduces costs. The slow-start chip operates under the control of an enable signal. The enable signal is externally triggered and, when the enable signal is valid, the controllable switch within the slow-start chip is turned on. When the enable signal is invalid, the controllable switch within the slow-start chip is turned off.

[0017] In one possible implementation, the power supply control circuit also includes: an inverter circuit; the input end of the inverter circuit is electrically connected to the first end or the second end of the second slow-start circuit; the output end of the inverter circuit is electrically connected to the control end of the first slow-start circuit; the first power supply end of the inverter circuit is electrically connected to the output end of the first power supply circuit; and the second power supply end of the inverter circuit is electrically connected to the ground.

[0018] In order to make only one power supply branch conductive at the same time, the working states of the first slow-start chip and the second slow-start chip are opposite. In the embodiment of the present application, the working state of the second slow-start chip is used to constrain the enable signal of the first slow-start chip, so that when the second slow-start chip is working, the first slow-start chip does not work. The embodiment of the present application uses an inverting circuit to implement the mutual exclusion constraint of the two slow-start chips. The output voltage (or output voltage) of the second slow-start chip and the output voltage of the first power supply circuit generate the enable signal of the first slow-start chip. When the second slow-start chip has an output, the enable signal of the first slow-start chip will be invalidated, so that even when there is voltage in the first power supply circuit, the first power supply branch cannot be turned on to supply power to the first load circuit.

[0019] In one possible implementation, the power supply control circuit includes: a first power supply branch, a second power supply branch and an inverter circuit; the first power supply branch includes a first slow-start circuit and a first diode; the second power supply control branch includes a second slow-start circuit and a second diode; wherein, the input end of the first slow-start circuit is electrically connected to the output end of the first power supply circuit; the output end of the first slow-start circuit is electrically connected to the first end of the first diode; the second end of the first diode is electrically connected to the input end of the second load; the input end of the second slow-start circuit is electrically connected to the output end of the second power supply circuit; the output end of the second slow-start circuit is electrically connected to the first end of the second diode; the second end of the second diode is electrically connected to the input end of the first load; the input end of the inverter circuit is electrically connected to the first end or the second end of the second slow-start circuit; the output end of the inverter circuit is electrically connected to the control end of the first slow-start circuit; the first power supply end of the inverter circuit is electrically connected to the output end of the first power supply circuit; and the second power supply end of the inverter circuit is electrically connected to the ground.

[0020] The computing device provided in the embodiment of the present application has a power supply branch including a soft-start circuit and a diode connected in series. Compared with a controllable switch tube, the diode is low in cost and does not require control, and can automatically achieve a reverse cutoff function. Since the diode and the diode in the soft-start circuit are connected in reverse series, the current in the power supply branch can be bidirectionally shut off.

[0021] In one possible implementation, the inverting circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a fifth switch tube; wherein the first end of the first resistor is electrically connected to the output end of the first power supply circuit; the second end of the first resistor, the first end of the second resistor, the first end of the fifth resistor and the first end of the fifth switch tube are all electrically connected together; the first end of the third resistor is electrically connected to the control end of the second soft-start circuit; the second end of the third resistor, the first end of the fourth resistor and the control end of the fifth switch tube are electrically connected together; the second end of the second resistor, the second end of the fourth resistor and the second end of the fifth switch tube are all electrically connected to the ground; and the second end of the fifth resistor is electrically connected to the control end of the first soft-start circuit.

[0022] When the second slow-start chip is operating, the output voltage is applied to the control terminal of the fifth switch, turning the fifth switch on. The enable signal is inactive, the first slow-start chip is inactive, and the second power supply circuit supplies power to the first load circuit via the second power supply branch. When the second slow-start chip is inactive, the fifth switch is disconnected, ENC is high, the enable signal is active, the first slow-start chip is inactive, and the first power supply circuit supplies power to the first load circuit via the first power supply branch.

[0023] In one possible implementation, the power supply control circuit also includes: a third slow start circuit; the input end of the third slow start circuit is electrically connected to the output end of the first power supply circuit; the output end of the third slow start circuit, the input end of the first slow start circuit and the input end of the second load circuit are electrically connected.

[0024] The function of the third slow-start chip is to prevent current impact on subsequent devices when the first power supply circuit is powered on. For example, when hot-plugging the first power supply circuit, the third slow-start chip can prevent instantaneous current impact.

[0025] In one possible implementation, the power supply control circuit is further configured to control the first power supply circuit to supply power to the first load circuit and the second load circuit when the output voltage of the second power supply circuit is less than or equal to a preset voltage.

[0026] The computing device provided in the embodiment of the present application preferentially uses the second power supply circuit to power the load corresponding to the first load circuit, and only uses the first power supply circuit to power the load corresponding to the first load circuit when the output voltage of the second power supply circuit is low.

[0027] In a possible implementation, the first load circuit and the second load circuit are located on a data processor (DPU) board.

[0028] Since the DPU has high requirements for power supply, two power supply circuits are set for the DPU, and only one power supply circuit is used to power it. There is no need to set a current sharing circuit, which saves the area of ​​the DPU board. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic diagram of a computing device provided in an embodiment of the present application;

[0030] FIG2A is a schematic diagram of another computing device provided in an embodiment of the present application;

[0031] FIG2B is a schematic diagram of another computing device provided in an embodiment of the present application;

[0032] FIG3 is a schematic diagram of another computing device provided in an embodiment of the present application;

[0033] FIG4 is a schematic diagram of another computing device provided in an embodiment of the present application;

[0034] FIG5 is a schematic diagram of an enable signal generating circuit of a first slow-start chip provided in an embodiment of the present application;

[0035] FIG6 is a schematic diagram of another computing device provided in an embodiment of the present application;

[0036] FIG7 is a flowchart of a method for controlling a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The computing devices provided in the embodiments of this application are not specifically limited to specific application scenarios. For example, the computing device is described using a server as an example, and the server type is not specifically limited. For example, the computing device can be a rack server or an edge server. The server can be located in a data center or other areas, and this is not specifically limited in the embodiments of this application.

[0038] A server is a type of computing device that runs faster and handles higher loads than regular computers. It provides computing or application services to other clients (such as PCs and smartphones) on a network. Servers feature high-speed CPU computing power, long-term reliable operation, strong external data throughput, and excellent scalability. Servers are categorized by their physical form factor into rack-mount, blade, tower, and cabinet types.

[0039] Single board, a common component in servers, is a general term that can be a mainboard, power management board, network data exchange board, etc. Single boards are equipped with electrical connectors, which can be plugged into other electrical components (for example, another single board).

[0040] The server generally includes a single board and a power supply, which is used to supply power to various loads on the single board. The embodiment of the present application does not specifically limit the voltage level provided by the power supply to the single board, for example, DC 12V is used as an example for introduction.

[0041] The embodiments of the present application do not specifically limit the type of single board. The single board may be a main board or other single board.

[0042] A motherboard is a circuit board in a server. It can include components such as a central processing unit (CPU), memory, controllers, and electrical connectors. The CPU can be electrically connected to peripheral devices via electrical connectors, such as a network card or graphics card. The controller can be one or more of a microcontroller unit (MCU), a complex programmable logic device (CPLD), or a field programmable gate array (FPGA).

[0043] A server's load generally includes multiple components, such as a CPU, fans, a baseboard management controller (BMC), a data processing unit (DPU), and memory. The present embodiment does not specifically limit the specific type of memory. For example, memory includes, but is not limited to, the following types: dual-inline memory modules (DIMMs). Furthermore, a motherboard may include one or more CPUs.

[0044] The BMC is an essential component of a server, used to monitor the server's operating status, such as temperature, fan speed, power supply status, and operating system status. The BMC operates independently of the server and is not affected by it. It can perform operations such as firmware upgrades, device monitoring, and remote startup on the server even when the server is powered off. It can also record critical logs in the event of a server crash.

[0045] Traditionally, the power supply for the entire server cabinet is generally supplied by at least two AC / DC power supplies, which serve as backup for each other. Inside the server, the input DC power is divided into several power supply units through a soft-start circuit or fuse on the server board. Each power supply unit is affected by the corresponding soft-start circuit or fuse, and the output power is limited. To prevent current backflow or current imbalance that causes certain power supply units to trigger overcurrent protection, the load in the entire server cabinet generally only draws power from one of the power supply units. If there is a scenario that requires power from two or more power supply units, two or more direct current / direct current (DC / DC) circuits need to be set up. The DC / DC circuit needs to have current sharing capability to prevent current backflow or triggering overcurrent protection of a certain power supply unit. However, the DC / DC circuit hardware is complex, occupies a large circuit area, and the current sharing control is also cumbersome.

[0046] In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, a detailed description is given below with reference to the accompanying drawings.

[0047] The computing device provided in the embodiment of the present application includes two power supply branches. The two power supply branches do not supply power to the same load together. Through hardware, only one power supply branch supplies power to the load at the same time. In this way, there is no need to set up DC / DC circuits on both power supply branches, and no current sharing control is required. The circuit structure is simple, circuit area is saved, and the development cycle is shortened.

[0048] See Figure 1, which is a schematic diagram of a computing device provided in an embodiment of the present application.

[0049] The computing device provided in an embodiment of the present application includes: a first power supply circuit A, a second power supply circuit B, a power supply control circuit 10, a first load circuit 30 and a second load circuit 40;

[0050] The output terminal of the first power supply circuit A is electrically connected to the first input terminal of the power supply control circuit 10;

[0051] The output terminal of the second power supply circuit B is electrically connected to the second input terminal of the power supply control circuit 10;

[0052] The first output terminal of the power supply control circuit 10 is electrically connected to the input terminal of the first load circuit 30;

[0053] The second output terminal of the power supply control circuit 10 is electrically connected to the input terminal of the second load circuit 40;

[0054] The power supply control circuit 10 is used for:

[0055] Determining whether the output voltage of the second power supply circuit B is greater than a preset voltage;

[0056] When the output voltage of the second power supply circuit B is greater than the preset voltage, the first power supply circuit A is controlled to stop supplying power to the first load circuit 30 , and the second power supply circuit B is controlled to supply power to the first load circuit 30 .

[0057] In one possible implementation, for example, the sum of the maximum power required by the first load circuit 30 and the maximum power required by the second load circuit 40 is greater than the maximum output power of the first power supply circuit A, and less than the sum of the maximum output power of the first power supply circuit A and the maximum output power of the second power supply circuit B; the maximum output power of the first power supply circuit A is greater than or equal to the maximum output power of the second power supply circuit B; and the maximum output power of the second power supply circuit B is greater than or equal to the maximum power required by the first load circuit.

[0058] In a possible implementation, the first load circuit 30 and the second load circuit 40 are located on a DPU board.

[0059] The embodiment of the present application does not specifically limit the number of loads included in the first load circuit 30 , and may include one load or multiple loads, wherein the loads may include but are not limited to FPGA.

[0060] In the computing device provided by an embodiment of the present application, the first power supply circuit A is always powered, and the power supply of the first power supply circuit A comes from a power supply cable.

[0061] The power supply of the second power supply circuit B can come from various interfaces, such as a PCIE interface, which is convenient for users to plug in.

[0062] When the power supply of the first power supply circuit is insufficient (the output power of the first power supply circuit is less than the sum of the power required by the first load circuit and the second load circuit), and the second power supply circuit B is powered, the first load circuit is powered by the second power supply circuit B. The first power supply circuit A can power the second load circuit 40. When the second power supply circuit B is depleted, the first power supply circuit A powers both the first load circuit and the second load circuit.

[0063] The embodiment of the present application does not specifically limit the number of loads included in the second load circuit. It may include one load or multiple loads. For example, the loads of the second load circuit may include but are not limited to: a hard disk, a CPLD, etc.

[0064] See Figure 2A, which is a schematic diagram of another computing device provided in an embodiment of the present application.

[0065] The power supply control circuit provided in the embodiment of the present application includes: a first power supply branch 101, a second power supply branch 102 and a first controller 103;

[0066] The output end of the first power supply circuit A is electrically connected to the input end of the first power supply branch 101; the output end of the first power supply branch 101 is electrically connected to the input end of the second load circuit 40;

[0067] The output end of the second power supply circuit B is electrically connected to the input end of the second power supply branch 102; the output end of the second power supply branch 102 is electrically connected to the input end of the first load circuit 30;

[0068] A first output terminal of the first controller 103 is electrically connected to a control terminal of the first power supply branch 101 ; a second output terminal of the first controller 103 is electrically connected to a control terminal of the second power supply branch 102 ;

[0069] The power supply control circuit is used to control the first power supply branch to stop supplying power to the first load circuit when the output voltage of the second power supply circuit is greater than a preset voltage, and to control the second power supply circuit to supply power to the first load circuit, including:

[0070] The first controller 103 is used to:

[0071] When the output voltage of the second power supply circuit B is greater than the preset voltage, the first power supply branch 101 is controlled to be turned off, and the second power supply branch 102 is controlled to be turned on.

[0072] The following are several specific implementation methods.

[0073] See Figure 2B, which is a schematic diagram of another computing device provided in an embodiment of the present application.

[0074] In the computing device provided by the embodiment of the present application, the first power supply branch includes a first controllable switch tube NMOS1 and a second controllable switch tube NMOS2 connected in series; the second power supply branch includes a third controllable switch tube NMOS3 and a fourth controllable switch tube NMOS4 connected in reverse series.

[0075] Wherein, a first end of the first controllable switch tube NMOS1 is electrically connected to the output end of the first power supply circuit; a second end of the first controllable switch tube NMOS1 is electrically connected to the second end of the second controllable switch tube NMOS2; a first end of the second controllable switch tube NMOS2 is electrically connected to the input end of the second load circuit;

[0076] A first end of the third controllable switch transistor NMOS3 is electrically connected to the output end of the second power supply circuit; a second end of the third controllable switch transistor NMOS3 is electrically connected to the second end of the fourth controllable switch transistor NMOS4; and a first end of the fourth controllable switch transistor NMOS4 is electrically connected to the input end of the first load circuit;

[0077] The first controller has two first output terminals, wherein the two first output terminals of the first controller are electrically connected to the control terminal of the first controllable switch transistor NMOS1 and the control terminal of the second controllable switch transistor NMOS2 respectively;

[0078] The first controller has two second output terminals, wherein the two second output terminals of the first controller are electrically connected to the control terminal of the third controllable switch transistor NMOS3 and the control terminal of the fourth controllable switch transistor NMOS4 respectively;

[0079] The first controller is used to control the first power supply branch to be turned off and the second power supply branch to be turned on when the output voltage of the second power supply circuit is greater than a preset voltage, including:

[0080] The first controller is used to:

[0081] When the output voltage of the second power supply circuit is greater than the preset voltage, the first controllable switch tube NMOS1 and the second controllable switch tube NMOS2 are both turned off, and the third controllable switch tube NMOS3 and the fourth controllable switch tube NMOS4 are both turned on.

[0082] The embodiments of the present application do not specifically limit the type of controllable switch tube. The embodiments of the present application are only introduced using a metal-oxide-semiconductor field-effect transistor (MOS) as an example. Specifically, an NMOS tube is taken as an example. It should be understood that the controllable switch tube can also be a PMOS tube, and the controllable switch tube can also be other types of controllable switch tubes other than MOS tubes.

[0083] In order to ensure that the power supply branch can be shut down in both directions, that is, the bidirectional current is shut down, each power supply branch needs to include two controllable switching tubes connected in reverse series, and each controllable switching tube includes a body diode, that is, the body diode serves as an anti-parallel diode of the controllable switching tube, which can play the role of reverse current blocking.

[0084] When the first power supply branch supplies power to the first load circuit 30, both the first controllable switch transistor NMOS1 and the second controllable switch transistor NMOS2 are turned on, that is, the first power supply circuit A supplies power to the first load circuit 30 through the turned-on NMOS1 and NMOS2; otherwise, both the first controllable switch transistor NMOS1 and the second controllable switch transistor NMOS2 are turned off.

[0085] When the second power supply branch supplies power to the first load circuit 30, the third controllable switch tube NMOS3 and the fourth controllable switch tube NMOS4 are both turned on, that is, the second power supply circuit B supplies power to the first load circuit 30 through the turned-on NMOS3 and NMOS4; otherwise, the third controllable switch tube NMOS3 and the fourth controllable switch tube NMOS4 are both turned off.

[0086] For example, if the second power supply circuit B supplies power to the first load circuit 30, NMOS3 and NMOS4 are turned on, while NMOS1 and NMOS2 are turned off. Due to the anti-parallel diode of NMOS1, although power is supplied to the first power supply circuit A, it will not supply power to the first load circuit 30. Furthermore, due to the anti-parallel diode of NMOS2, current from the second power supply circuit B will not flow back into the first power supply branch. It should be understood that when NMOS2 is turned off, even if NMOS1 is turned on, the current backflow prevention function will still be implemented.

[0087] For example, if the second power supply circuit B is de-energized and the first power supply circuit A is supplying power to the first load circuit 30, NMOS3 and NMOS4 are disconnected, while NMOS1 and NMOS2 are turned on. Due to the anti-parallel diode of NMOS4, the current from the first power supply circuit A will not flow back into the second power supply branch. It is understood that when NMOS4 is disconnected, even if NMOS3 is turned on, the current backflow prevention function will still be implemented.

[0088] From the above analysis, it can be seen that the computing device provided in the embodiment of the present application can realize that A or B can independently power the first load circuit 30 without the occurrence of current backflow, and can provide safe and stable power supply to the first load circuit.

[0089] In addition, the first power supply circuit A is also used to supply power to the second load circuit 40 .

[0090] The embodiment of the present application does not specifically limit the voltage levels of the first power supply circuit A and the second power supply circuit B. For example, the voltage of the power provided by the first power supply circuit A and the second power supply circuit B is both 12V.

[0091] The embodiment of the present application does not specifically limit the power of the first load circuit 30 and the power of the second load circuit 40. In one possible implementation, the power required by the first load circuit 30 is less than the power required by the second load circuit 40. For example, the power required by the first load circuit 30 is 75W, and the power required by the second load circuit 40 is greater than 100W.

[0092] The embodiment of the present application does not specifically limit the type of load included in the first load circuit 30. For example, the load may be an FPGA.

[0093] See FIG3 , which is a schematic diagram of another computing device provided in an embodiment of the present application.

[0094] The computing device provided in the embodiment of the present application further includes: a controller 50;

[0095] The controller 50 is configured to control the third controllable switch NMOS3 and the fourth controllable switch NMOS4 to be turned on, and control the first controllable switch NMOS1 and the second controllable switch NMOS2 to be turned off when determining that the voltage of the second power supply circuit B is greater than a preset voltage.

[0096] The voltage of the second power supply circuit B can be obtained by the voltage detection circuit 60 , and the voltage detection circuit 60 sends the detection voltage to the controller 50 .

[0097] The embodiment of the present application does not specifically limit the implementation form of the voltage detection circuit 60. It can be a detection circuit built with an analog circuit or a voltage detection chip.

[0098] In addition, the embodiments of the present application do not specifically limit the implementation method of the controller. The controller 50 can be implemented by a CPLD or a single-chip microcomputer. When the controller 50 is a CPLD or a single-chip microcomputer, it also needs to include a driving circuit, which is used to drive the switching state of each controllable switch tube, that is, on or off.

[0099] The computing device provided in the embodiment of the present application can realize power supply of two power supply branches by detecting the voltage of the second power supply circuit, and has simple hardware design and simple logic control.

[0100] The following introduces another power supply implementation method.

[0101] See FIG4 , which is a schematic diagram of another computing device provided in an embodiment of the present application.

[0102] The computing device provided in the embodiment of the present application uses a soft-start chip and a combining control chip 70 to realize automatic selection of two power supply branches, without using a controller to control the state of the controllable switch tube. This is simpler to implement, simplifies the control of the control logic, and reduces the cost.

[0103] The first power supply branch includes a first slow-start circuit and a second controllable switch tube NMOS2; the second power supply branch includes a second slow-start chip and a fourth controllable switch tube NMOS4; as shown in Figure 4, the first slow-start circuit includes a first slow-start chip 50 and the second slow-start circuit includes a second slow-start chip 60 as an example for introduction.

[0104] The input end of the first slow-start chip 50 is electrically connected to the output end of the first power supply circuit; the output end of the first slow-start chip 50 is electrically connected to the second end of the second controllable switch tube; the first end of the second controllable switch tube is electrically connected to the input end of the second load circuit;

[0105] The input end of the second slow-start chip 60 is electrically connected to the output end of the second power supply circuit; the output end of the second slow-start chip 60 is electrically connected to the second end of the fourth controllable switch tube; the first end of the fourth controllable switch tube is electrically connected to the input end of the first load circuit;

[0106] The first output end of the first controller controls the control end of the second controllable switch tube; the second output end of the first controller controls the control end of the fourth controllable switch tube;

[0107] The first controller is used to control the first power supply branch to be turned off and the second power supply branch to be turned on when the output voltage of the second power supply circuit is greater than a preset voltage, including:

[0108] The first controller is used to:

[0109] When the output voltage of the second power supply circuit is greater than the preset voltage, the second controllable switch tube is controlled to be turned off, and the fourth controllable switch tube is controlled to be turned on.

[0110] The first power supply branch includes a first slow-start chip 50 and a second controllable switch tube NMOS2 connected in series; the second power supply branch includes a second slow-start chip 60 and a fourth controllable switch tube NMOS4 connected in series; in the embodiment of the present application, the controllable switch tube is continued to be introduced as an NMOS tube as an example.

[0111] The first terminal C of the first slow-start chip 50 is used to be electrically connected to the first power supply circuit A, and the second terminal of the first slow-start chip 50 is electrically connected to the first load circuit 30 via the second controllable switch transistor NMOS2.

[0112] A first end of the second slow-start chip 60 is used to be electrically connected to the second power supply circuit B, and a second end of the second slow-start chip 60 is electrically connected to the first load circuit 30 via the fourth controllable switch transistor NMOS4.

[0113] In the embodiment of the present application, the first controller includes a combiner control chip 70 as an example for description.

[0114] The combining control chip 70 is used to control the states of the second controllable switch tube NMOS2 and the fourth controllable switch tube NMOS4 based on the voltage of the second power supply circuit B and the voltage of the first power supply circuit A.

[0115] The output voltage of the second slow-start chip 60 and the output voltage of the first power supply circuit A generate an enable signal for the first slow-start chip 50 .

[0116] The embodiment of the present application does not specifically limit the specific implementation of the combiner control chip 70. For example, it can be implemented using an ORing control chip.

[0117] The combining control chip 70 is configured to control the fourth controllable switch NMOS4 to be turned on and the second controllable switch NMOS2 to be turned off when the voltage of the second power supply circuit B is greater than a preset voltage; conversely, the fourth controllable switch NMOS4 is turned off and the second controllable switch NMOS2 is turned on.

[0118] When the second slow-start chip 60 has an output voltage, the enable signal of the first slow-start chip 50 is invalid, and the controllable switch tube in the first slow-start chip 50 is turned off; when the second slow-start chip 60 has no output voltage, the enable signal of the first slow-start chip 50 is valid, and the controllable switch tube in the first slow-start chip 50 is turned on;

[0119] The second slow-start chip 60 generates an enable signal based on the voltage of the second power supply circuit B. When there is voltage in the second power supply circuit B, the enable signal of the second slow-start chip 60 is valid, turning on the controllable switch tube in the second slow-start chip 60.

[0120] In a default state, the fourth controllable switch tube NMOS4 is in an off state.

[0121] The combining control chip 70 controls one of the second controllable switch tube NMOS2 and the fourth controllable switch tube NMOS4 to turn on. Specifically, when the second power supply circuit B is powered, for example, the voltage of the second power supply circuit B is detected. When the voltage is greater than a preset voltage, it is determined that the second power supply circuit B is powered. At this time, the fourth controllable switch tube NMOS4 is turned on. That is, when it is detected that the second power supply circuit B is powered, the second power supply circuit B is powered to supply power to the first load circuit 30.

[0122] When the combining control chip 70 detects that the first power supply circuit A has power and the second power supply circuit B has no power, it controls the second controllable switch tube NMOS2 to be turned on and controls the fourth controllable switch tube NMOS4 to be turned off. At this time, the first power supply circuit A supplies power to the first load circuit 30.

[0123] It should be understood that the combining control chip 70 cannot simultaneously control the second controllable switch transistor NMOS2 and the fourth controllable switch transistor NMOS4 to be turned on.

[0124] The working principle of the slow-start chip is controlled by the enable signal. The slow-start chip has an enable signal, which is triggered externally. When the enable signal is valid, the controllable switch tube in the slow-start chip is turned on. When the enable signal is invalid, the controllable switch tube in the slow-start chip is turned off.

[0125] In order to ensure that only one power supply branch is turned on at the same time, the working states of the first slow-start chip 50 and the second slow-start chip 60 are opposite. In the embodiment of the present application, the working state of the second slow-start chip 60 is used to constrain the enable signal of the first slow-start chip 50, so that when the second slow-start chip 60 is working, the first slow-start chip 50 is not working.

[0126] The output voltage (or output voltage) of the second slow-start chip 60 and the output voltage of the first power supply circuit A generate an enable signal for the first slow-start chip 50. To ensure that only one of the first and second power supply branches is conductive at the same time, and to use the second power supply branch to power the first load circuit when the second power supply circuit B is powered, the output of the second slow-start chip 60 on the second power supply branch controls the enable signal of the first slow-start chip. When the second slow-start chip 60 has an output, the enable signal of the first slow-start chip is disabled. As a result, even when voltage is present in the first power supply circuit A, the first power supply branch cannot be turned on to power the first load circuit.

[0127] The computing device provided by the embodiment of the present application, the power supply control circuit further includes: an inverter circuit;

[0128] The input end of the inverting circuit is electrically connected to the first end or the second end of the second slow-start circuit; the output end of the inverting circuit is electrically connected to the control end of the first slow-start circuit; the first power supply end of the inverting circuit is electrically connected to the output end of the first power supply circuit; and the second power supply end of the inverting circuit is electrically connected to the ground.

[0129] In one possible implementation, the power supply control circuit includes: a first power supply branch, a second power supply branch, and an inverter circuit; the first power supply branch includes a first slow-start circuit and a first diode; the second power supply branch includes a second slow-start circuit chip and a second diode;

[0130] The input end of the first slow-start circuit is electrically connected to the output end of the first power supply circuit; the output end of the first slow-start circuit is electrically connected to the first end of the first diode; and the second end of the first diode is electrically connected to the input end of the second load.

[0131] The input end of the second slow-start circuit is electrically connected to the output end of the second power supply circuit; the output end of the second slow-start circuit is electrically connected to the first end of the second diode; the second end of the second diode is electrically connected to the input end of the first load;

[0132] The input end of the inverting circuit is electrically connected to the first end or the second end of the second slow-start circuit; the output end of the inverting circuit is electrically connected to the control end of the first slow-start circuit;

[0133] The output end of the inverter circuit is electrically connected to the control end of the first slow-start circuit; the first power supply end of the inverter circuit is electrically connected to the output end of the first power supply circuit; and the second power supply end of the inverter circuit is electrically connected to the ground.

[0134] In order to facilitate understanding of the working states of the first slow-start chip 50 and the second slow-start chip 60, a detailed description is given below with reference to the accompanying drawings.

[0135] The inverting circuit of the first slow-start chip includes a fifth controllable switch tube NMOS5. In the embodiment of the present application, the NMOS tube is taken as an example for description.

[0136] The control terminal of the fifth controllable switch NMSO5 is electrically connected to the second terminal of the second slow-start chip 60 through the third resistor. The first terminal of the second slow-start chip 60 is electrically connected to the second power supply circuit. The control terminal of the fifth controllable switch NMSO5 is electrically connected to the ground through the fourth resistor R4.

[0137] A first terminal D of the fifth controllable switch NMSO5 is connected to a first terminal C of the first slow-start chip via a first resistor R1. The first terminal C of the first slow-start chip is electrically connected to the first power supply circuit. A first terminal D of the fifth controllable switch NMSO5 is electrically connected to ground via a second resistor R2. A second terminal of the fifth controllable switch NMSO5 is electrically connected to ground.

[0138] The first terminal D of the fifth controllable switch NMSO5 serves as an output terminal of the enable signal. To limit current, the first terminal D of the fifth controllable switch NMSO5 outputs the enable signal ENC of the first slow-start chip via a resistor.

[0139] The working principle of the inverting circuit is introduced below.

[0140] When the second slow-start chip 60 is working, the output voltage will be applied to the control terminal of NMOS5, causing NMOS5 to be turned on, so that the potential of point D is pulled down to ground, that is, ENC is at a low level, the enable signal is invalid, the first slow-start chip does not work, and the second power supply circuit supplies power to the first load circuit through the second power supply branch.

[0141] When the second slow-start chip 60 is not working and there is no output voltage, NMOS5 is disconnected. Since there is always voltage at point C, the voltage at point D is the voltage divided by R1 and R2. ENC is at a high level, the enable signal is valid, the first slow-start chip is working, and the first power supply circuit supplies power to the first load circuit through the first power supply branch.

[0142] In another implementation, the computing device provided by the embodiment of the present application further includes: a third slow-opening core 80;

[0143] The first slow-start chip 50 is electrically connected to the first power supply circuit A through the third slow-start chip 80;

[0144] The first power supply circuit A is also used to power the second load circuit 40 of the computing device via the third slow-start chip 80. The third slow-start chip automatically detects the voltage of the first power supply circuit. When the voltage of the first power supply circuit is greater than a preset voltage, an enable signal is asserted, turning on the internal controllable switch tube to achieve automatic startup.

[0145] The function of the third slow-start chip 80 is to prevent current shock to subsequent devices when the first power supply circuit A is powered on. For example, when hot-plugging the first power supply circuit A, the third slow-start chip 80 can prevent instantaneous current shock.

[0146] The current backflow prevention devices described in the above embodiments are all controllable switch tubes. The following describes how to implement current backflow prevention using diodes.

[0147] See FIG6 , which is a schematic diagram of another computing device provided in an embodiment of the present application.

[0148] The computing device provided in the embodiment of the present application differs from that in FIG4 in that NMOS2 is replaced by a first diode D1 and NMOS4 is replaced by a second diode D2. The embodiment of the present application continues to use the example of a slow-start circuit implemented by a slow-start chip for description.

[0149] The first power supply branch includes a first slow-start chip 50 and a first diode D1 connected in series; the second power supply branch includes a second slow-start chip 60 and a second diode D2 connected in series.

[0150] The power supply control circuit includes: a first power supply branch, a second power supply branch and an inverter circuit; the first power supply branch includes a first slow-start chip and a first diode; the second power supply control branch includes a second slow-start chip and a second diode D2;

[0151] The input end of the first slow-start chip 50 is electrically connected to the output end of the first power supply circuit; the output end of the first slow-start chip 50 is electrically connected to the first end of the first diode D1; the second end of the first diode D1 is electrically connected to the input end of the second load;

[0152] The input end of the second slow-start chip 60 is electrically connected to the output end of the second power supply circuit; the output end of the second slow-start chip 60 is electrically connected to the first end of the second diode D2; the second end of the second diode D2 is electrically connected to the input end of the first load;

[0153] The input end of the inverter circuit 100 is electrically connected to the first end or the second end of the second slow-start chip 60; the output end of the inverter circuit 100 is electrically connected to the control end of the first slow-start chip 50;

[0154] The first power supply terminal of the inverter circuit 100 is electrically connected to the output terminal of the first power supply circuit; the second power supply terminal of the inverter circuit 100 is electrically connected to the ground.

[0155] When the first power supply branch supplies power to the first load circuit 30, the controllable switch tube in the first slow-start chip 50 is turned on, and the controllable switch tube in the second slow-start chip 60 is turned off;

[0156] When the second power supply branch supplies power to the first load circuit 30 , the controllable switch in the second slow-start chip 60 is turned on, and the controllable switch in the first slow-start chip 50 is turned off.

[0157] Because diodes have unidirectional conduction characteristics, current can only flow from the anode to the cathode. For example, when the second power supply branch supplies power to the first load circuit 30, the presence of D1 prevents the supply current from flowing back into the first power supply branch. When the first power supply branch supplies power to the first load circuit 30, the presence of D2 prevents the supply current from flowing back into the second power supply branch.

[0158] It should be understood that compared with controllable switching tubes, diodes are low-cost and do not require control, and can automatically achieve reverse cutoff function.

[0159] Based on the computing device provided in the above embodiment, an embodiment of the present application further provides a method for controlling the computing device, which is described in detail below with reference to the accompanying drawings.

[0160] See FIG. 7 , which is a flowchart of a method for controlling a computing device provided in an embodiment of the present application.

[0161] An embodiment of the present application provides a control method for a computing device, wherein the computing device includes: a first power supply branch and a second power supply branch; a first end of the first power supply branch is used to electrically connect to a first power supply circuit, and a second end of the first power supply branch is used to power a first load circuit in the computing device; a first end of the second power supply branch is used to electrically connect to a second power supply circuit, and a second end of the second power supply branch is used to power the first load circuit; the first power supply branch and the second power supply branch both include a current backflow prevention device, and the current backflow prevention device includes a controllable switch tube or a diode;

[0162] Methods include:

[0163] S701: Detecting the voltage of the second power supply circuit;

[0164] The control method provided in the embodiment of the present application preferentially uses the second power supply circuit to power the first load circuit when the second power supply circuit has power. Therefore, priority power supply can be achieved by detecting the voltage of the second power supply circuit.

[0165] The embodiment of the present application does not specifically limit the power source of the first power supply circuit, which may be derived from a power supply cable. The power source of the second power supply circuit is derived from a PCIE adapter card.

[0166] S702: When the voltage of the second power supply circuit is greater than the preset voltage, the second end of the second power supply branch is used to power the first load circuit, and the first power supply branch does not power the first load circuit; the current backflow prevention device in the first power supply branch prevents the power supply current of the second power supply branch from backflowing.

[0167] The second power supply circuit may sometimes lose power. The power supply for the second power supply circuit can come from various adapters, such as a PCIE adapter card. Users may plug in any adapter, and the adapter may be out of power or underpowered. Therefore, the second power supply circuit may have power and sufficient power, or it may have power but insufficient power.

[0168] When the second power supply circuit is powered, the second power supply circuit is preferentially used to power the first load circuit. The first power supply circuit can also power the second load circuit. When the second power supply circuit is powered, the first power supply circuit powers both the first load circuit and the second load circuit.

[0169] The first power supply branch and the second power supply branch both include a current backflow prevention device, and the current backflow prevention device includes a controllable switch tube or a diode.

[0170] Taking any of the power supply branches as an example, it should be understood that to prevent current backflow, when the current backflow prevention device includes a diode, the cathode of the diode is electrically connected to the first load circuit, and the anode of the diode is electrically connected to the power supply unit. When the power supply branch includes a controllable switch, the controllable switch includes an anti-parallel diode. Since the first power supply circuit is always powered, the first power supply circuit does not supply power to the first load circuit, and only the second power supply circuit supplies power to the first load circuit. This requires bidirectional current shutoff of the first power supply circuit.

[0171] When the first power supply branch supplies power to the first load circuit, the current backflow prevention device in the second power supply branch is used to prevent the power supply current of the first power supply branch from backflowing; when the second power supply branch supplies power to the first load circuit, the current backflow prevention device in the first power supply branch prevents the power supply current of the second power supply branch from backflowing.

[0172] The computing device provided in the embodiment of the present application includes two power supply branches, one of the two power supply branches can supply power to the first load circuit, when the second power supply branch has power, the second power supply branch supplies power to the first load circuit, and when the second power supply branch has no power, the first power supply branch supplies power to the first load circuit, thereby realizing backup power supply for the first load circuit. Since the first power supply branch and the second power supply branch include current backflow prevention devices, the power supply branch that is not powered can prevent the power supply current from backflowing. This technical solution does not require the installation of DC / DC circuits on both power supply branches, does not require current sharing control, has a simple circuit structure, saves circuit area, and shortens the development cycle.

[0173] In the control method provided in the embodiment of the present application, when the voltage of the second power supply circuit is less than or equal to a preset voltage, when the first power supply branch supplies power to the first load circuit, the current backflow prevention device in the second power supply branch is used to prevent the supply current of the first power supply branch from backflowing; the first power supply branch is also used to supply power to the second load circuit.

[0174] In a possible implementation, the first power supply branch includes a first controllable switch tube and a second controllable switch tube connected in reverse series; the second power supply branch includes a third controllable switch tube and a fourth controllable switch tube connected in reverse series;

[0175] When the first power supply branch supplies power to the first load circuit, the first controllable switch tube and the second controllable switch tube are controlled to be turned on; otherwise, the first controllable switch tube and the second controllable switch tube are controlled to be turned off;

[0176] When the second power supply branch supplies power to the first load circuit, the third controllable switch tube and the fourth controllable switch tube are controlled to be turned on; otherwise, the third controllable switch tube and the fourth controllable switch tube are controlled to be turned off.

[0177] The computing device includes a controller, which controls the third and fourth controllable switch tubes to be turned on and the first and second controllable switch tubes to be turned off when the voltage of the second power supply circuit is greater than a preset voltage.

[0178] In another possible implementation, the first power supply branch includes a first slow-start chip and a second controllable switch connected in series; the second power supply branch includes a second slow-start chip and a fourth controllable switch connected in series; the first end of the first slow-start chip is used to electrically connect to the first power supply circuit, and the second end of the first slow-start chip is electrically connected to the first load circuit through the second controllable switch; the first end of the second slow-start chip is used to electrically connect to the second power supply circuit, and the second end of the second slow-start chip is electrically connected to the first load circuit through the fourth controllable switch.

[0179] The computing device also includes: a combining control chip;

[0180] The combining control chip controls the states of the second controllable switch tube and the fourth controllable switch tube based on the voltage of the second power supply circuit and the voltage of the first power supply circuit; the output voltage of the second slow-start chip and the output voltage of the first power supply circuit generate an enable signal for the first slow-start chip.

[0181] Specifically, when the voltage of the second power supply circuit is greater than the preset voltage, the combining control chip controls the fourth controllable switch tube to be turned on and controls the second controllable switch tube to be turned off; otherwise, the fourth controllable switch tube is controlled to be turned off and the second controllable switch tube is controlled to be turned on; when the second slow-start chip has an output voltage, the enable signal of the first slow-start chip is invalid, and the controllable switch tube in the first slow-start chip is turned off; when the second slow-start chip has no output voltage, the enable signal of the first slow-start chip is valid, and the controllable switch tube in the first slow-start chip is turned on; the second slow-start chip generates an enable signal based on the voltage of the second power supply circuit. When there is voltage in the second power supply circuit, the enable signal of the second slow-start chip is valid, so that the controllable switch tube in the second slow-start chip is turned on.

[0182] The first power supply branch includes a first slow-start chip and a first diode connected in series; the second power supply branch includes a second slow-start chip and a second diode connected in series; when the first power supply branch supplies power to the first load circuit, the controllable switch tube in the first slow-start chip is controlled to be turned on, and the controllable switch tube in the second slow-start chip is turned off; when the second power supply branch supplies power to the first load circuit, the controllable switch tube in the second slow-start chip is controlled to be turned on, and the controllable switch tube in the first slow-start chip is turned off.

[0183] In another possible implementation, the computing device further includes: a third slow-start chip;

[0184] The first slow-start chip is electrically connected to the first power supply circuit via the third slow-start chip;

[0185] The first power supply circuit supplies power to the second load circuit of the computing device through the third slow-start chip, that is, the third slow-start chip automatically detects the voltage of the first power supply circuit. When the voltage of the first power supply circuit is detected to be greater than the preset voltage, the enable signal is valid, and the internal controllable switch tube is controlled to be turned on, thereby realizing automatic startup.

[0186] The above description is only a preferred embodiment of the present application and does not constitute any formal limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims

1. A computing device, characterized in that include: A first power supply circuit, a second power supply circuit, a power supply control circuit, a first load circuit, and a second load circuit; The output end of the first power supply circuit is electrically connected to the first input end of the power supply control circuit; The output end of the second power supply circuit is electrically connected to the second input end of the power supply control circuit; The first output terminal of the power supply control circuit is electrically connected to the input terminal of the first load circuit; The second output terminal of the power supply control circuit is electrically connected to the input terminal of the second load circuit; The power supply control circuit is used for: Determining whether the output voltage of the second power supply circuit is greater than a preset voltage; When the output voltage of the second power supply circuit is greater than the preset voltage, the first power supply circuit is controlled to stop supplying power to the first load circuit, and the second power supply circuit is controlled to supply power to the first load circuit.

2. The computing device according to claim 1, wherein: The power supply control circuit includes a first power supply branch, a second power supply branch and a first controller; Wherein, the output end of the first power supply circuit is electrically connected to the input end of the first power supply branch; the output end of the first power supply branch is electrically connected to the input end of the second load circuit; The output end of the second power supply circuit is electrically connected to the input end of the second power supply branch; the output end of the second power supply branch is electrically connected to the input end of the first load circuit; The first output end of the first controller is electrically connected to the control end of the first power supply branch; the second output end of the first controller is electrically connected to the control end of the second power supply branch; The power supply control circuit is used to control the first power supply branch to stop supplying power to the first load circuit and control the second power supply circuit to supply power to the first load circuit when the output voltage of the second power supply circuit is greater than the preset voltage, and includes: The first controller is used for: When the output voltage of the second power supply circuit is greater than the preset voltage, the first power supply branch is controlled to be turned off, and the second power supply branch is controlled to be turned on.

3. The computing device according to claim 2, characterized in that The first power supply branch includes a first controllable switch tube and a second controllable switch tube; the second power supply branch includes a third controllable switch tube and a fourth controllable switch tube; Wherein, the first end of the first controllable switch tube is electrically connected to the output end of the first power supply circuit; the second end of the first controllable switch tube is electrically connected to the second end of the second controllable switch tube; the first end of the second controllable switch tube is electrically connected to the input end of the second load circuit; The first end of the third controllable switch tube is electrically connected to the output end of the second power supply circuit; the second end of the third controllable switch tube is electrically connected to the second end of the fourth controllable switch tube; the first end of the fourth controllable switch tube is electrically connected to the input end of the first load circuit; The first controller has two first output terminals, wherein the two first output terminals of the first controller are electrically connected to the control terminal of the first controllable switch tube and the control terminal of the second controllable switch tube respectively; The number of second output terminals of the first controller is two, wherein the two second output terminals of the first controller are electrically connected to the control terminal of the third controllable switch tube and the control terminal of the fourth controllable switch tube respectively; The first controller is used to control the first power supply branch to be turned off and the second power supply branch to be turned on when the output voltage of the second power supply circuit is greater than the preset voltage, including: The first controller is used for: When the output voltage of the second power supply circuit is greater than the preset voltage, the first controllable switch tube and the second controllable switch tube are controlled to be turned off, and the third controllable switch tube and the fourth controllable switch tube are controlled to be turned on.

4. The computing device according to claim 2, wherein: The first power supply branch includes a first slow-start circuit and a second controllable switch tube; the second power supply branch includes a second slow-start chip and a fourth controllable switch tube; The input end of the first slow-start circuit is electrically connected to the output end of the first power supply circuit; the output end of the first slow-start circuit is electrically connected to the second end of the second controllable switch tube; the first end of the second controllable switch tube is electrically connected to the input end of the second load circuit; The input end of the second slow-start circuit is electrically connected to the output end of the second power supply circuit; the output end of the second slow-start circuit is electrically connected to the second end of the fourth controllable switch tube; the first end of the fourth controllable switch tube is electrically connected to the input end of the first load circuit; The first output end of the first controller controls the control end of the second controllable switch tube; the second output end of the first controller controls the control end of the fourth controllable switch tube; The first controller is used to control the first power supply branch to be turned off and control the second power supply branch to be turned on when the output voltage of the second power supply circuit is greater than the preset voltage, including: The first controller is used for: When the output voltage of the second power supply circuit is greater than the preset voltage, the second controllable switch tube is controlled to be turned off, and the fourth controllable switch tube is controlled to be turned on.

5. The computing device according to claim 4, characterized in that The power supply control circuit further includes: an inverting circuit; The input end of the inverter circuit is electrically connected to the first end or the second end of the second slow-start circuit; the output end of the inverter circuit is electrically connected to the control end of the first slow-start circuit; the first power supply end of the inverter circuit is electrically connected to the output end of the first power supply circuit; and the second power supply end of the inverter circuit is electrically connected to the ground.

6. The computing device according to claim 1, wherein: The power supply control circuit includes: a first power supply branch, a second power supply branch and an inverter circuit; the first power supply branch includes a first slow-start circuit and a first diode; the second power supply control branch includes a second slow-start circuit and a second diode; The input end of the first slow-start circuit is electrically connected to the output end of the first power supply circuit; the output end of the first slow-start circuit is electrically connected to the first end of the first diode; the second end of the first diode is electrically connected to the input end of the second load; The input end of the second slow-start circuit is electrically connected to the output end of the second power supply circuit; the output end of the second slow-start circuit is electrically connected to the first end of the second diode; the second end of the second diode is electrically connected to the input end of the first load; The input end of the inverter circuit is electrically connected to the first end or the second end of the second slow-start circuit; the output end of the inverter circuit is electrically connected to the control end of the first slow-start circuit; The first power supply end of the inverter circuit is electrically connected to the output end of the first power supply circuit; the second power supply end of the inverter circuit is electrically connected to the ground.

7. The computing device according to claim 5 or 6, characterized in that: The inverting circuit comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a fifth switch tube; Wherein, the first end of the first resistor is electrically connected to the output end of the first power supply circuit; the second end of the first resistor, the first end of the second resistor, the first end of the fifth resistor and the first end of the fifth switch tube are all electrically connected together; The first end of the third resistor is electrically connected to the control end of the second slow-start circuit; the second end of the third resistor, the first end of the fourth resistor and the control end of the fifth switch are electrically connected together; the second end of the second resistor, the second end of the fourth resistor and the second end of the fifth switch are all electrically connected to the ground; The second end of the fifth resistor is electrically connected to the control end of the first slow start circuit.

8. The computing device according to any one of claims 4 to 7, characterized in that: The power supply control circuit further includes: a third slow start circuit; The input end of the third slow start circuit is electrically connected to the output end of the first power supply circuit; the output end of the third slow start circuit, the input end of the first slow start circuit and the input end of the second load circuit are electrically connected.

9. The computing device according to any one of claims 1 to 8, characterized in that: The power supply control circuit is further configured to control the first power supply circuit to supply power to the first load circuit and the second load circuit when the output voltage of the second power supply circuit is less than or equal to the preset voltage.

10. The computing device according to any one of claims 1 to 9, characterized in that: The first load circuit and the second load circuit are located on a data processor DPU board.

Images