Integrated suspended transistor structure

Abstract

Disclosed in the present invention is an integrated suspended transistor structure, comprising a transistor and a local support structure connected to the lower side of the transistor, wherein the transistor is suspended by means of the local support structure. According to the technical solution provided by the present invention, a semiconductor material below a transistor is partially or completely removed to form an integrated suspended transistor structure, so that the area below the transistor is of a cavity structure, thereby improving the performances of the transistor and related circuits.

Description

Integrated suspended transistor structure Technical Field

[0001] The present invention relates to the field of radio frequency microwave, millimeter wave and terahertz circuits, and in particular to an integrated suspended transistor structure. Background Art

[0002] Transistors in integrated circuits (ICs) play an important role in radio frequency, microwave, millimeter wave, and terahertz circuits, and are mainly used for functions such as amplification, switching, mixing, and modulation of radio frequency signals.

[0003] Transistor performance is influenced by factors such as its material parameters, structural characteristics, and manufacturing process. Furthermore, the materials immediately below the transistor also significantly impact its performance. Typically, transistors are directly beneath semiconductor or semi-insulating materials such as germanium, silicon, selenium, gallium arsenide, cadmium sulfide, gallium phosphide, and indium antimonide. These semiconductor materials typically exhibit certain losses, which can affect or degrade transistor performance and, in turn, directly or indirectly impact overall circuit performance.

[0004] Summary of the Invention

[0005] The purpose of the present invention is to provide a high-performance integrated suspended transistor (IST) structure to address the problem in the prior art that transistors are affected by underlying materials, resulting in large losses.

[0006] To achieve the purpose of the present invention, the technical solution provided by the present invention is as follows:

[0007] An integrated suspended transistor structure comprises a transistor and a local support structure connected to the lower side of the transistor, wherein the transistor is suspended by the local support structure.

[0008] Furthermore, the transistor is a single transistor, a plurality of transistors, an integrated circuit chip designed by interconnecting a single transistor, or an integrated circuit chip designed by interconnecting a plurality of transistors.

[0009] Furthermore, the integrated circuit chip is a CMOS, BiCMOS, GaAs or GaN, SiC, or LDMOS chip.

[0010] Furthermore, the type of the transistor is a diode, a Schottky diode, a Gens diode or a detector diode, a rectifier diode, a voltage regulator diode, a switching diode, a germanium diode, a silicon diode, a varactor, a triode, a field effect transistor, a bipolar field effect transistor, an insulated gate transistor, a bipolar transistor, a heterojunction bipolar transistor, a carbon nanotube transistor, and a composite transistor.

[0011] Furthermore, the local support structure includes one or more layers of substrates, and the substrates are made of semiconductor materials, insulating materials, or metal materials.

[0012] Furthermore, the semiconductor material is silicon, germanium, gallium arsenide, indium phosphide, indium antimonide, glass semiconductor or amorphous semiconductor, organic semiconductor, gallium nitride, silicon carbide, zinc selenide, zinc oxide, diamond, aluminum nitride; the insulating material is ceramic, glass, polytetrafluoroethylene or polyimide, epoxy resin; the metal material is aluminum, copper or gold, silver.

[0013] Furthermore, the transistor is placed or grown on or inside the substrate, and a layer of the substrate below the transistor and connected to the transistor is partially removed.

[0014] Furthermore, the local support structure includes an oxide layer and a substrate connected in sequence from top to bottom, and the oxide layer below the transistor position is partially removed or not removed, and the substrate below the transistor position is partially or completely removed.

[0015] Furthermore, balls are planted on the lower side of the partially removed substrate, with gaps between the balls. After the ball planting operation, the suspension space below the transistor is increased.

[0016] Furthermore, the local support structure includes an oxide layer and a multi-layer substrate connected in sequence from top to bottom, and the oxide layer below the transistor position is partially removed or not removed, and a layer of substrate below the transistor position and connected to the oxide layer is partially removed or completely removed.

[0017] Furthermore, the local support structure includes an oxide layer and a multi-layer substrate connected sequentially from top to bottom, and balls are planted between the multi-layer substrates with gaps between the balls. After the ball planting operation, the suspension space below the transistor is increased.

[0018] Furthermore, the local support structure includes an oxide layer and a multi-layer substrate connected sequentially from top to bottom, and the substrate below the transistor position and located between the uppermost substrate and the lowermost substrate is partially or completely removed to form an air cavity structure.

[0019] Furthermore, balls are planted on the upper and / or lower side of the partially or completely removed substrate with gaps between the balls, or an adhesive material layer is provided on the upper and / or lower side of the partially or completely removed substrate and the adhesive material layer is partially or completely removed.

[0020] Furthermore, there are multiple transistors, and an air cavity structure is provided below each transistor, so that the transistor is suspended.

[0021] Furthermore, a partially removed first packaging substrate is provided on the upper side of the substrate or oxide layer connected to the lower side of the transistor, and the removed portion forms an air cavity structure. The transistor is located in the air cavity structure, and a second packaging substrate covering the air cavity structure is provided on the upper end of the first packaging substrate to constitute a suspended transistor structure of the packaging structure.

[0022] Furthermore, the suspended transistor structures of the multiple package structures can be stacked three-dimensionally in the horizontal direction and / or the vertical direction.

[0023] Furthermore, the transistor includes a transistor body and a substrate, and the transistor body is embedded in the substrate from the upper end of the substrate.

[0024] Furthermore, the electrode of the transistor is connected to an external circuit through a metal wire.

[0025] Furthermore, the metal wire is a suspended wire structure, and a cavity structure is provided below the metal wire so that the metal wire is suspended.

[0026] Furthermore, the electrode of the transistor is connected to an external circuit via a vertical metallized through-hole.

[0027] Furthermore, a multi-layer substrate is stacked above the transistor and the metal wire, a cavity structure is provided inside the multi-layer substrate, and the transistor and the metal wire are placed or grown in the cavity structure to form a packaging structure.

[0028] Furthermore, the cavity structure is divided into a plurality of cavities by setting isolation walls, and the transistors and metal lines are respectively located in different cavities for isolation.

[0029] It should be noted that the substrate in this application may also be referred to as a medium.

[0030] Compared with the existing technology, the technical solution provided by the present invention forms an integrated suspended transistor structure by partially or completely removing the semiconductor material under the transistor, making the area under the transistor a cavity structure, thereby improving the performance of the transistor and related circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a schematic cross-sectional view of a transistor placed on or grown on a semiconductor material;

[0032] FIG2 is a schematic cross-sectional view of a transistor placed on or grown on an oxide material on a semiconductor material;

[0033] FIG3 is a schematic cross-sectional view of the integrated suspended transistor structure after partial removal of semiconductor material;

[0034] FIG4 is a schematic cross-sectional view of the integrated suspended transistor structure after all semiconductor materials under the transistor are removed;

[0035] FIG5 is a schematic cross-sectional view of the integrated suspended transistor structure after partial removal of the semiconductor material and oxide layer below the transistor;

[0036] FIG6 is a schematic cross-sectional view of a suspended transistor after the semiconductor material and oxide layer below the transistor are removed and superimposed on another layer of semiconductor material;

[0037] FIG7 is a schematic cross-sectional view of a semiconductor material below a transistor after partial removal and subsequent ball planting below the transistor;

[0038] FIG8 is a schematic cross-sectional view of a suspended transistor after ball implantation and stacked with another layer of semiconductor material;

[0039] FIG9 is a schematic cross-sectional view of the suspended transistor structure after the semiconductor material and oxide layer under the transistor are removed;

[0040] FIG10 is a schematic cross-sectional view of the semiconductor material below the transistor after being polished and thinned, and then superimposed with another layer of semiconductor material by ball implantation;

[0041] FIG11 is a schematic cross-sectional view of the semiconductor material below the transistor after being polished and thinned and then laminated with two other layers of semiconductor material;

[0042] FIG12 is a schematic cross-sectional view of the semiconductor material below the transistor after being polished and thinned, and then subjected to multiple ball planting and then stacked with other multi-layer semiconductor materials;

[0043] FIG13 is a schematic cross-sectional view of the semiconductor material below the transistor after being polished and thinned, and then laminated with other multiple layers of semiconductor material through multiple wafer stacking processes;

[0044] FIG14 is a schematic cross-sectional view of a plurality of suspended transistors formed by grinding and thinning the semiconductor material below the transistor, and then performing multiple wafer stacking processes and then laminating with other multi-layer semiconductor materials;

[0045] FIG15 is a cross-sectional view of a suspended transistor structure formed by stacking multiple layers above the transistor to form an overall packaged suspended transistor;

[0046] FIG16 is a cross-sectional view of a plurality of suspended transistors formed on the basis of FIG15 ;

[0047] FIG17 is a first cross-sectional view of a structure in which a transistor is embedded in a semiconductor material;

[0048] FIG18 is a second cross-sectional view of a structure in which a transistor is embedded in a semiconductor material;

[0049] FIG19 is a third cross-sectional view of a structure in which a transistor is embedded in a semiconductor material;

[0050] FIG20 is a cross-sectional view showing a transistor connected to an external circuit via a metal wire;

[0051] FIG21 is a plan view corresponding to the circuit in FIG20;

[0052] FIG22 is a schematic cross-sectional view of a suspended transistor structure in which multiple layers of semiconductor material are stacked above the transistor and metal lines to form a package structure;

[0053] FIG23 is a cross-sectional view of FIG22 showing the isolation of transistors and metal lines by setting an isolation wall;

[0054] FIG24 is a schematic cross-sectional view of a transistor connected to an external circuit via a vertical metallized through-hole;

[0055] FIG25 is a cross-sectional view of a suspension circuit in a complete package formed by stacking multiple layers of structures on top of the circuit in FIG24 . DETAILED DESCRIPTION

[0056] The following is a clear and complete description of the technical solutions in the embodiments of the present invention, in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts are within the scope of protection of the present invention.

[0057] As shown in FIG1 , semiconductor material 3 is generally located below transistor 1, wherein transistor 1 is a single transistor, multiple transistors, an integrated circuit chip designed by interconnecting single transistors, or an integrated circuit chip designed by interconnecting multiple transistors, etc. The integrated circuit chip is a CMOS, BiCMOS, GaAs or GaN, SiC, LDMOS chip, etc.

[0058] The type of the transistor is a diode, a Schottky diode, a Gens Gunn diode or a detector diode, a rectifier diode, a voltage regulator diode, a switching diode, a germanium diode, a silicon diode, a varactor, a triode, a field effect transistor, a bipolar field effect transistor, an insulated gate transistor, a bipolar transistor, a heterojunction bipolar transistor, a carbon nanotube transistor, and a composite transistor.

[0059] The semiconductor material can be silicon, germanium, gallium arsenide, indium phosphide, indium antimonide, glass semiconductor or amorphous semiconductor, organic semiconductor, gallium nitride, silicon carbide, zinc selenide, zinc oxide, diamond, aluminum nitride and other semiconductor materials.

[0060] As shown in Figure 2, there is usually an oxide layer 2 between the transistor 1 and the semiconductor material 3. The main function of this oxide layer is to form the transistor structure above. It should be noted that the oxide layer can be an oxide thin film.

[0061] The semiconductor material below the transistor is partially removed, as shown in FIG3 , so that the transistor 1 is suspended by a local support structure. The semiconductor material can be partially removed, as shown in FIG3 , or the entire semiconductor material below the transistor can be removed, as shown in FIG4 , or the oxide layer below the transistor can be removed at the same time, as shown in FIG5 . The semiconductor material below the transistor 1 can be a single layer or multiple layers. As shown in FIG6 , two layers of semiconductor materials 3 and 31 are included, the upper layer of semiconductor material below the transistor position is partially removed, and the lower layer of semiconductor material below the transistor position is completely removed.

[0062] For a suspended transistor structure with partially removed semiconductor materials, a ball 10 can be planted underneath. The ball 10 can be any type of ball material and shape. As shown in FIG7 , after the ball planting operation, the suspension space below the suspended transistor is increased. The suspended transistor structure after ball planting is then stacked and combined with other layers of semiconductor materials to form a new suspended transistor structure. As shown in FIG8 , it is overlapped with another layer of semiconductor material 7. It is also possible to directly overlap the suspended transistor structure with other layers of semiconductor materials without using ball planting. As shown in FIG9 , the suspended transistor structure composed of transistor 1, oxide layer 2, and semiconductor material 3 is overlapped with semiconductor material 4 to form a new suspended transistor structure.

[0063] The semiconductor material below the transistor can be left uncut. Instead, a ball-planting process can be used to create a gap structure below the suspended transistor, utilizing the spaces between the balls, as shown in Figure 10. The semiconductor material layer 3 can be polished and thinned to reduce its impact on transistor performance. The ball-planting process can then be used to laminate the suspended transistor above onto the semiconductor material 7 below, utilizing the spaces between the balls 10.

[0064] The semiconductor material immediately below the transistor may not be removed, as shown in FIG11 . Instead, a layer of semiconductor material 71 may be partially removed. After the semiconductor material 71 is partially removed, the transistor 1, oxide layer 2, and semiconductor material 3, which constitute the transistor and support portion, the partially removed semiconductor material 71, and the bottom semiconductor material 72 are stacked up in multiple layers, thereby forming an air cavity structure at the position of the semiconductor material 71 layer. The air cavity structure is located below the transistor, and the transistor can also be suspended, thereby realizing a suspended transistor structure.

[0065] In addition, for the multi-layer stacking process in Figure 11, multi-layer stacking can also be performed by ball planting. As shown in Figure 12, a ball planting 10 is placed between the semiconductor material layer 3, the semiconductor material 71, and the semiconductor material 72 to achieve a multi-layer stacking process.

[0066] In addition, for the multi-layer stacking process in Figure 11, multi-layer stacking can also be performed using various adhesive materials. As shown in Figure 13, an adhesive material layer 20 is placed between the semiconductor material layer 3, the semiconductor material 71, and the semiconductor material 72 to achieve a multi-layer stacking process.

[0067] In addition to realizing a single suspended transistor structure, multiple suspended transistor structures can also be realized on the entire wafer. As shown in FIG14 , multiple suspended transistor structures are formed, including multiple suspended transistors, namely transistor 11, transistor 12, and transistor 13.

[0068] In addition, multiple layers of semiconductor materials can be stacked on top of the suspended transistor to form a suspended transistor structure of a packaging structure, as shown in Figure 15. A semiconductor material layer 5 is placed on the transistor layer, and after the semiconductor material 5 is partially removed, the position of the locally removed semiconductor material is made to correspond to the position of the transistor, and then the packaging of the internal transistor structure is achieved through the top semiconductor material layer 6.

[0069] In addition to realizing multiple suspended transistors in the horizontal direction, it is also possible to realize three-dimensional stacking of multiple suspended transistors in the vertical direction by stacking more layers of wafers. As shown in FIG16 , a total of multiple layers of transistors 01, transistor 02, transistor 03, and transistor 04 are suspended, using more layers of semiconductor material 23, semiconductor material 24, semiconductor material 25, and oxide layer 22, etc.

[0070] The transistor structure can be completely placed or grown on top of the semiconductor material, or it can be embedded in the semiconductor material 101, as shown in Figures 17, 18, and 19. The position and shape of the transistor are related to the type of transistor used and the processing technology. The above-mentioned transistors include various types of transistor structures.

[0071] The connection between the transistor and the external circuit can be through a metal wire. For example, the metal wire M0 in Figure 20 connects the pole of the transistor to the external circuit. The pole of the transistor may be the emitter, base and collector, or the source, gate and drain. The definition of the pole depends on the type of transistor used. The transistor is connected to the metal layer of the external circuit to form a complete circuit structure. As shown in Figure 20, the M0 metal wire can also form a suspension wire structure, that is, a cavity structure is also formed under the M0 metal wire through related process methods. The planar schematic diagram corresponding to the circuit in Figure 20 is shown in Figure 21. At this time, the suspended transistor and the suspension wire simultaneously constitute a suspension circuit.

[0072] In addition, based on FIG20, multiple layers of semiconductor material can be stacked above the suspended transistor and the metal line to form a suspended transistor structure of the package structure, as shown in FIG22. Multiple cavity structures can also be formed, as shown in FIG23. By providing an isolation wall 51 to isolate the transistor and the metal line, the mutual influence can be avoided, thereby achieving the integrated packaging integration of the suspended transistor and the suspension line.

[0073] The interconnection between the suspended transistor and the external circuit can be achieved, on the one hand, through the metal wire M0 of the same layer, as shown in FIG20; on the other hand, it can also be connected to the metal wire M1 of a different layer through a vertical metallized through-hole V1. The semiconductor material 50 below the metal wire M1 is provided with a cavity structure, so that the metal wire M1 is a suspension mechanism, as shown in FIG24. As shown in FIG24, both the metal wire M1 and the metal wire M0 can be used to implement passive circuits in various radio frequency circuits, and metallized through-holes can also be used between the metal wire M0 and the metal wire M1 for interconnection of signals. In addition, multiple layers of structure can be stacked on top of the circuit to form a complete packaged suspension circuit, as shown in FIG25. In addition, more layers of circuit structure can be stacked to achieve more layers of integrated suspended transistors and integrated suspension lines, ultimately achieving an integrated suspension circuit with a higher degree of integration.

[0074] It should be noted that in the structures of Figures 1 to 25, all semiconductor materials can be replaced with insulating materials or metal materials. The insulating materials can be ceramics, glass, polytetrafluoroethylene, polyimide, epoxy resin, etc.; the metal materials can be aluminum, copper, gold, silver, etc.

[0075] The basic principles, main features and advantages of the present invention are shown and described above. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0076] Therefore, from any point of view, the embodiments should be regarded as illustrative and non-restrictive, and the scope of the invention is limited by the appended claims rather than the above description. Therefore, it is intended that all changes that fall within the meaning and range of equivalent elements of the claims are included in the present invention, and any figure signs in the claims should not be regarded as limiting the claims involved.

[0077] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. An integrated suspended transistor structure, characterized in that: The invention comprises a transistor and a local support structure connected to the lower side of the transistor, wherein the transistor is suspended by the local support structure.

2. The integrated suspended transistor structure according to claim 1, characterized in that: The transistor is a single transistor, a plurality of transistors, an integrated circuit chip designed by interconnecting a single transistor, or an integrated circuit chip designed by interconnecting a plurality of transistors.

3. The integrated suspended transistor structure according to claim 2, characterized in that: The integrated circuit chip is a CMOS, BiCMOS, GaAs or GaN, SiC, or LDMOS chip.

4. The integrated suspended transistor structure according to claim 2, characterized in that: The type of the transistor is a diode, a Schottky diode, a Gens diode or a detector diode, a rectifier diode, a voltage regulator diode, a switching diode, a germanium diode, a silicon diode, a varactor, a triode, a field effect transistor, a bipolar field effect transistor, an insulated gate transistor, a bipolar transistor, a heterojunction bipolar transistor, a carbon nanotube transistor, and a composite transistor.

5. The integrated suspended transistor structure according to claim 1, characterized in that: The local support structure includes one or more layers of substrates, and the substrates are made of semiconductor materials, insulating materials or metal materials.

6. The integrated suspended transistor structure according to claim 5, characterized in that: The semiconductor material is silicon, germanium, gallium arsenide, indium phosphide, indium antimonide, glass semiconductor or amorphous semiconductor, organic semiconductor, gallium nitride, silicon carbide, zinc selenide, zinc oxide, diamond, aluminum nitride; the insulating material is ceramic, glass, polytetrafluoroethylene or polyimide, epoxy resin; the metal material is aluminum, copper or gold, silver.

7. The integrated suspended transistor structure according to claim 5, characterized in that: The transistor is placed or grown on or inside the substrate, and a layer of the substrate below the transistor and connected to the transistor is partially removed.

8. The integrated suspended transistor structure according to claim 1, characterized in that: The local support structure includes an oxide layer and a substrate layer connected in sequence from top to bottom, and the oxide layer below the transistor position is partially removed or not removed, and the substrate layer below the transistor position is partially or completely removed.

9. The integrated suspended transistor structure according to claim 7 or 8, characterized in that: Balls are planted on the lower side of the partially removed substrate with gaps between the balls. After the ball planting operation, the suspension space under the transistor is increased.

10. The integrated suspended transistor structure according to claim 1, wherein: The local support structure includes an oxide layer and a multi-layer substrate connected in sequence from top to bottom, and the oxide layer below the transistor position is partially removed or not removed, and a layer of substrate below the transistor position and connected to the oxide layer is partially removed or completely removed.

11. The integrated suspended transistor structure according to claim 1, wherein: The local support structure includes an oxide layer and a multi-layer substrate connected in sequence from top to bottom. Balls are planted between the multi-layer substrates, and there are gaps between the balls. After the ball planting operation, the suspension space under the transistor is increased.

12. The integrated suspended transistor structure according to claim 1, wherein: The local support structure includes an oxide layer and a multi-layer substrate connected in sequence from top to bottom. The substrate below the transistor position and located between the uppermost substrate and the lowermost substrate is partially or completely removed to form an air cavity structure.

13. The integrated suspended transistor structure according to claim 12, characterized in that: Balls are planted on the upper and / or lower side of the partially or completely removed substrate with spaces between the balls, or an adhesive material layer is provided on the upper and / or lower side of the partially or completely removed substrate and the adhesive material layer is partially or completely removed.

14. The integrated suspended transistor structure according to claim 13, characterized in that: There are multiple transistors, and an air cavity structure is arranged under each transistor so that the transistor is suspended.

15. The integrated suspended transistor structure according to any one of claims 10 to 14, characterized in that: A first packaging substrate with part of the packaging substrate removed is provided on the upper side of the substrate or oxide layer connected to the lower side of the transistor, and the removed part forms an air cavity structure. The transistor is located in the air cavity structure, and a second packaging substrate covering the air cavity structure is provided on the upper end of the first packaging substrate, thereby forming a suspended transistor structure of the packaging structure.

16. The integrated suspended transistor structure according to claim 15, characterized in that: The suspended transistor structures of the multiple package structures can be three-dimensionally stacked in the horizontal direction and / or the vertical direction.

17. The integrated suspended transistor structure according to claim 1, wherein: The transistor comprises a transistor body and a substrate, wherein the transistor body is embedded in the substrate from the upper end of the substrate.

18. The integrated suspended transistor structure according to claim 1, wherein: The electrode of the transistor is connected to an external circuit through a metal wire.

19. The integrated suspended transistor structure according to claim 18, characterized in that: The metal wire is a suspended wire structure, and a cavity structure is arranged below the metal wire so that the metal wire is suspended.

20. The integrated suspended transistor structure according to claim 1, wherein: The electrodes of the transistors are connected to external circuits through vertical metallized vias.

21. The integrated suspended transistor structure according to any one of claims 18 to 20, characterized in that: A multi-layer substrate is stacked above the transistor and the metal wire, a cavity structure is arranged inside the multi-layer substrate, and the transistor and the metal wire are placed or grown in the cavity structure to form a packaging structure.

22. The integrated suspended transistor structure according to claim 21, characterized in that: The cavity structure is divided into a plurality of cavities by setting an isolation wall, and the transistors and metal wires are respectively located in different cavities for isolation.

Images