Power module, manufacturing method therefor and power device

Abstract

The present application provides a power module, a processing method therefor and a power device, and is characterized in that the power module comprises a chip body, a first electrode layer and a metal layer, wherein the first electrode layer is connected to the chip body, the projection of the first electrode layer on a first plane is located within the projection range of the chip body on the first plane, the first plane is parallel to the contact surface between the chip body and the first electrode layer, the metal layer coats the periphery of the first electrode layer, the surface of the metal layer close to the chip body is in contact with the chip body, and the projection of the chip body on the first plane does not exceed the projection range of a combination of the first electrode layer and the metal layer on the first plane. In the solution of the present application, the metal layer can coat the periphery of the first electrode layer, such that the back side of the chip body will be not exposed, so as to prevent the chip body from separating from a soldering layer, thus avoiding the failure of the power module, and improving the stability of the power module.

Description

A power module and its manufacturing method, and power equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on September 22, 2023, with application number 202311242885.1 and application name “A power module, its manufacturing method, and power equipment”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and more specifically, to a power module and a manufacturing method thereof, and a power device. Background Art

[0003] The backside metallization (also known as backside metallization) of a wafer is typically composed of titanium / nickel / silver (Ti / Ni / Ag) or titanium / nickel / gold (Ti / Ni / Au). Ti serves as the bonding layer between the semiconductor and the metal; Ni is the solder diffusion layer; and Ag or Au is the solder wettability layer, preventing oxidation of the Ni layer. Silicon wafers (SiC wafers) are commonly cut using lasers, but laser cutting can easily cause the backside metallization to ablate, exposing the SiC semiconductor. Since SiC is not solderable, the exposed SiC cannot be soldered.

[0004] The chip is subsequently plastic-encapsulated to form a power module. In the plastic-encapsulated power module, the plastic encapsulation material enters the non-solderable gap (i.e., the area where the back gold ablation layer is located), forming an area filled with plastic encapsulation material. During subsequent use, temperature changes will cause the plastic encapsulation material in the non-solderable gap to generate cyclic tensile and compressive stresses on the back of the chip, causing the joint to fail quickly, thereby causing the chip and power module to fail.

[0005] Summary of the Invention

[0006] The present application provides a power module and a manufacturing method thereof, and a power device, which can avoid failure of the power module and improve the stability of the power module.

[0007] In a first aspect, a power module is provided, comprising: a chip body, a first electrode layer and a metal protective layer, wherein: the first electrode layer is connected to the chip body, the projection of the first electrode layer on the first plane is located within the projection range of the chip body on the first plane, and the first plane is parallel to the contact surface between the chip body and the first electrode layer; the metal protective layer is wrapped around the first electrode layer, and the metal protective layer is in contact with the chip body on a side close to the chip body.

[0008] In a possible implementation, a projection of the chip body on the first plane does not exceed a projection range of an entirety formed by the first electrode layer and the metal protection layer on the first plane.

[0009] It should be understood that when the wafer is cut to form a chip, ablation may occur on the back gold of the chip (i.e., the first electrode layer), which will form a notch around the first electrode layer. The notch is not filled with material and the chip body will be exposed. The metal protective layer in the embodiment of the present application can fill the notch around the first electrode layer so that the contact surface between the chip body and the first electrode layer will not be exposed. In other words, the metal protective layer can be coated around the first electrode layer and in contact with the chip body so that the back of the chip will not be exposed. Therefore, when the temperature changes during the long-term operation of the chip, the difference in thermal expansion coefficient between the metal protective layer and the first electrode layer is small, so the cyclic tensile and compressive stress generated is small, thereby avoiding the failure of the chip and the power module and improving the stability of the chip and the power module.

[0010] In one possible implementation, the material of the chip body is silicon carbide (i.e., SiC). SiC can increase the operating frequency of the chip and reduce the chip volume while meeting the same operating frequency. Therefore, when the chip is packaged into a power module, more space can be reserved for installing other electronic components in the power module.

[0011] In one possible implementation, the first electrode layer is any one of Ni / Ag, Ni / Au, Ti / Ni / Ag, Ti / Ni / Au, Ti / NiV / Ag, Ti / NiV / Au, Ni(P) / Pd / Au, Ni(P) / Pd / Ag, Ni(P) / Au or Ni(P) / Ag, where Ni(P) means P element doped into Ni element, and NiV refers to an alloy of Ni element and V element.

[0012] Exemplarily, the first electrode layer can be composed of titanium / nickel / silver (i.e., Ti / Ni / Ag) or titanium / nickel / gold (i.e., Ti / Ni / Au), wherein Ti is the bonding layer between the semiconductor and the metal; Ni is the solder diffusion layer; and Ag or Au is the solder wettability layer, which can prevent the Ni layer from oxidizing.

[0013] In one example, the power module further comprises a metal-clad substrate, which is connected to a side of the first electrode layer away from the chip body and in contact with the metal protective layer. The metal-clad substrate may be a copper-clad ceramic substrate, an active metal soldering substrate, or an insulating metal substrate, etc., without limitation herein. It should be understood that the metal-clad substrate may be a copper-clad ceramic substrate, that is, the metal-clad substrate may be formed by copper-clad layers on both sides of a ceramic substrate.

[0014] For example, the metal-clad substrate may be soldered to a side of the first electrode layer away from the chip body.

[0015] The solder can be selected from at least one of tin solder and lead solder. The tin solder can be selected from at least one of SnSb5, SnSb8, SnSbAg, SAC305, SAC multi-reinforced solder, and SnSb10. The solder material can be selected based on specific needs. SnSb5 refers to a solder containing 5% by weight of Sb in the Sn element, SnSb8 refers to a solder containing 8% by weight of Sb in the Sn element, and SnSb10 refers to a solder containing 10% by weight of Sb in the Sn element. The "SAC" in SAC306 stands for Sn, Ag, and Cu, indicating that the product is composed of Sn (tin), Ag (silver), and Cu (copper). "3" represents 3% Ag, and "05" represents 0.5% Cu. SAC multi-reinforced solder includes other metal components in addition to Sn, Ag, and Cu to enhance solder reliability.

[0016] For example, when the first electrode layer and the metal-clad substrate are welded via solder (e.g., SnSb10), the metal layer (e.g., Ag or Au) in the first electrode layer welded to the metal-clad substrate may melt in the solder, and the intermediate layer (e.g., Ni) in the first electrode layer has a certain solder resistance effect on the solder, which can prevent the solder from climbing up and reacting with the metal protective layer.

[0017] It should be noted that if the metal-clad substrate is directly soldered to the side of the first electrode layer away from the chip body, the metal protective layer should be made of a material that provides a solder resist. For example, the metal protective layer can be made of any of the following materials: Cu, Ni, or Kovar. It should be understood that Cu, Ni, and Kovar provide a solder resist, preventing them from reacting with the solder and melting into it.

[0018] In another possible implementation, the power module also includes a second electrode layer, which is connected to the side of the first electrode layer away from the chip body, and the projection of the whole formed by the first electrode layer and the metal protective layer on the first plane does not exceed the projection range of the second electrode layer on the first plane.

[0019] It should be noted that the first electrode layer and the second electrode layer have thermal and electrical conductivity, so that the heat or current generated by the chip body can be transferred from the chip body to the first electrode layer and the second electrode layer and then to the metal-clad substrate.

[0020] In one example, the second electrode layer includes a metal support layer having a micro-nanostructured material on the interface between the metal support layer and the first electrode layer. The metal support layer can support the first electrode layer and provide electrical and thermal conductivity. The metal support layer may be made of any of the following: Cu, Ni, or Kovar alloy.

[0021] It should be understood that by performing surface micronization or surface nanometerization on the metal support layer, the surface connecting the metal support layer and the first electrode layer has a micro-nanostructured material (such as micron or nanostructured Cu, Ni), thereby improving the connection stability between the metal support layer and the first electrode layer.

[0022] It should be noted that surface micronization / nano-ization is a process that modifies the appearance, performance, or function of a material by introducing micron-scale / nano-scale structures, textures, or features onto its surface. This treatment can be applied to different types of materials, including metals, ceramics, and polymers, to achieve a variety of goals.

[0023] In another example, the second electrode layer may include a first connection layer and a metal support layer, wherein the first connection layer is connected between the first electrode layer and the metal support layer. The material of the first connection layer may include any one of the following: micron or nanostructured Ag, Cu, Au, or Ni.

[0024] It should be understood that the first connection layer is provided to bond and secure the first electrode layer, thereby improving the connection stability between the second electrode layer and the first electrode layer. The metal support layer can prevent solder from climbing up and reacting with the metal protective layer. The metal support layer can support the first electrode layer and the first connection layer and has both electrical and thermal conductivity.

[0025] In some embodiments, the second electrode layer further includes a second connection layer connected to a side of the metal support layer away from the first connection layer. The material of the second connection layer can be the same as that of the first connection layer.

[0026] It should be understood that the second connection layer is a solder wettability layer that can prevent oxidation of the metal support layer. It should be understood that a solder wettability layer can be a coating or material, typically applied to the soldering surface to improve the wetting properties of the solder or solder during the soldering process. The primary function of the wettability layer is to promote uniform distribution of the solder on the soldering surface and reduce surface tension, thereby achieving a better solder connection.

[0027] In some embodiments, the metal protective layer can be made of the same material as the first connection layer. Specifically, the metal protective layer can include any of the following: micro- or nanostructured Ag, Cu, Au, or Ni. It should be understood that the metal protective layer can be formed by pressure-sintering the first connection layer; therefore, the metal protective layer can be made of the same material as the first connection layer.

[0028] In some embodiments, the material of the second connection layer may be the same as that of the first connection layer. That is, the material of the second connection layer may include any one of the following: Ag, Cu, Au, Ni in micron or nanostructure.

[0029] In some embodiments, the power module further includes a metal-clad substrate connected to a side of the second electrode layer away from the chip body. The metal-clad substrate may be a copper-clad ceramic substrate, an active metal solder substrate, or an insulated metal substrate, etc., which is not limited in this application.

[0030] In one possible implementation, the power module further includes a package for encapsulating the chip body, the first electrode layer, the metal protective layer, the second electrode layer, and the metal-clad substrate. It should be understood that the packaged power module can be connected to a heat sink via a thermally conductive layer, so that heat generated by the chip can be transferred to the heat sink for dissipation.

[0031] It should be noted that the connection methods involved in the embodiments of the present application include but are not limited to welding, sintering and the like.

[0032] In a second aspect, a method for manufacturing a power module is provided, comprising: obtaining a chip and a second electrode layer, the chip comprising a chip body and a first electrode layer connected to the chip body, the projection of the first electrode layer on a first plane being within the projection range of the chip body on the first plane, the first plane being parallel to the contact surface between the chip body and the first electrode layer, and at least a portion of a side of the chip body close to the first electrode layer being not covered by the first electrode layer; sintering the second electrode layer on a side of the first electrode layer away from the chip body through a pressure sintering process, and extruding a metal layer connecting the second electrode layer to the first electrode layer around the first electrode layer along a first direction to form a metal protective layer, the first direction being perpendicular to the first plane, the metal protective layer covering all four sides of the first electrode layer, and the side of the metal protective layer close to the chip body being in contact with the chip body.

[0033] In a possible implementation, the manufacturing method further includes: a projection of the chip body on the first plane does not exceed a projection range of an entirety formed by the first electrode layer and the metal protection layer on the first plane.

[0034] The manufacturing method provided in the embodiment of the present application forms a metal protective layer around the first electrode layer by pressure sintering. The metal protective layer can cover the four sides of the first electrode layer and contact the chip body, so that the back side of the chip will not be exposed. Therefore, when the temperature changes during the long-term operation of the chip, the difference in thermal expansion coefficient between the metal protective layer and the first electrode layer is small, so the cyclic tensile and compressive stress generated is small, thereby avoiding failure of the chip and the power module and improving the stability of the chip and the power module.

[0035] In a possible implementation, the manufacturing method further includes: welding or sintering a metal-clad substrate on a side of the second electrode layer away from the chip body.

[0036] The metal-clad substrate may be a copper-clad ceramic substrate, an active metal solder substrate, or an insulating metal substrate, etc., without limitation herein. It should be understood that the metal-clad substrate may be a copper-clad ceramic substrate, that is, the metal-clad substrate may be formed by copper-clad layers on both sides of a ceramic substrate.

[0037] According to a third aspect, a chip is provided, comprising: a chip body, a first electrode layer and a metal protective layer, wherein: the first electrode layer is connected to the chip body, the projection of the first electrode layer on the first plane is located within the projection range of the chip body on the first plane, and the first plane is parallel to the contact surface between the chip body and the first electrode layer; the metal protective layer is wrapped around the first electrode layer, and the metal protective layer is in contact with the chip body on a side close to the chip body.

[0038] In a possible implementation, a projection of the chip body on the first plane does not exceed a projection range of an entirety formed by the first electrode layer and the metal protection layer on the first plane.

[0039] It should be understood that when the wafer is cut to form chips, ablation may occur around the chip, thereby forming a notch portion around the first electrode layer. The notch portion is not filled with material and the chip body is exposed. The metal protective layer in the embodiment of the present application can fill the first electrode layer to form a notch portion around it, so that the contact surface between the chip body and the first electrode layer will not be exposed. In other words, the metal protective layer can be wrapped around the first electrode layer and in contact with the chip body, so that the back of the chip will not be exposed. Therefore, during the long-term operation of the chip, when the temperature changes, the difference in thermal expansion coefficient between the metal protective layer and the first electrode layer is small, so the cyclic tensile and compressive stress generated is small, thereby avoiding chip failure and improving the stability of the chip.

[0040] In one possible implementation, the material of the chip body is silicon carbide (i.e., SiC). SiC can increase the operating frequency of the chip and reduce the chip volume while meeting the same operating frequency. Therefore, when the chip is packaged into a power module, more space can be reserved for installing other electronic components in the power module.

[0041] In one possible implementation, the first electrode layer is any one of Ni / Ag, Ni / Au, Ti / Ni / Ag, Ti / Ni / Au, Ti / NiV / Ag, Ti / NiV / Au, Ni(P) / Pd / Au, Ni(P) / Pd / Ag, Ni(P) / Au or Ni(P) / Ag, where Ni(P) means P element doped into Ni element, and NiV refers to an alloy of Ni element and V element.

[0042] Exemplarily, the first electrode layer can be composed of titanium / nickel / silver (i.e., Ti / Ni / Ag) or titanium / nickel / gold (i.e., Ti / Ni / Au), wherein Ti is the bonding layer between the semiconductor and the metal; Ni is the solder diffusion layer; and Ag or Au is the solder wettability layer, which can prevent the Ni layer from oxidizing.

[0043] In one possible implementation, the chip also includes a second electrode layer, which is connected to the side of the first electrode layer away from the chip body, and the projection of the whole formed by the first electrode layer and the metal protective layer on the first plane does not exceed the projection range of the second electrode layer on the first plane.

[0044] In a possible implementation, the material of the metal protection layer may be the same as that of the first connection layer. That is, the material of the metal protection layer may include any one of the following: Ag, Cu, Au, or Ni in a micron or nanostructure.

[0045] In one example, the second electrode layer includes a metal support layer, and the surface of the metal support layer connected to the first electrode layer has a micro-nanostructured material. The material of the metal support layer can include any one of the following: Cu, Ni, and Kovar alloy.

[0046] It should be understood that by performing surface micronization or surface nanometerization on the metal support layer, the surface connecting the metal support layer and the first electrode layer has a micro-nanostructured material (such as micron or nanostructured Cu, Ni), thereby improving the connection stability between the metal support layer and the first electrode layer.

[0047] In another example, the second electrode layer may include a first connection layer and a metal support layer, wherein the first connection layer is connected between the first electrode layer and the metal support layer. The material of the first connection layer may include any one of the following: micron or nanostructured Ag, Cu, Au, or Ni.

[0048] It should be understood that the first connection layer is provided to bond and secure the first electrode layer, thereby improving the connection stability between the second electrode layer and the first electrode layer. The metal support layer can prevent solder from climbing up and reacting with the metal protective layer. The metal support layer can support the first electrode layer and the first connection layer and has both electrical and thermal conductivity.

[0049] In a possible implementation, the second electrode layer further includes a second connection layer connected to a side of the metal support layer away from the first connection layer. The material of the second connection layer may be the same as that of the first connection layer.

[0050] It should be understood that the second connection layer is a solder wettability layer that can prevent oxidation of the metal support layer. It should be understood that a solder wettability layer can be a coating or material, typically applied to the soldering surface to improve the wetting properties of the solder or solder during the soldering process. The primary function of the wettability layer is to promote uniform distribution of the solder on the soldering surface and reduce surface tension, thereby achieving a better solder connection.

[0051] In a fourth aspect, a power device is provided, which is used for AC / DC conversion, and the power device includes a circuit board and a power module as in the first aspect and any one of the implementations of the first aspect, or the power device includes a circuit board and a power module made as in the second aspect and any one of the implementations of the second aspect, and the power module is arranged on the circuit board.

[0052] It should be noted that the beneficial effects of the fourth aspect can be referred to the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] FIG1 is a schematic diagram of a silicon wafer cut to form chips provided in an embodiment of the present application.

[0054] FIG2 is a schematic diagram of the cross-sectional structure of a chip provided in an embodiment of the present application.

[0055] FIG3 is a schematic diagram of the cross-sectional structure of another chip provided in an embodiment of the present application.

[0056] FIG4 is a schematic diagram of the cross-sectional structure of another chip provided in an embodiment of the present application.

[0057] FIG5 is a schematic diagram of the cross-sectional structure of a power module provided in an embodiment of the present application.

[0058] FIG6 is a schematic cross-sectional view of another power module provided in an embodiment of the present application.

[0059] FIG7 is a schematic cross-sectional view of another power module provided in an embodiment of the present application.

[0060] FIG8 is a flow chart of a method for processing a power module provided in an embodiment of the present application.

[0061] FIG9 is a structural diagram of a process for preparing a power module provided in an embodiment of the present application.

[0062] FIG10 is a flow chart of another method for processing a power module provided in an embodiment of the present application.

[0063] FIG11 is a flow chart of another method for processing a power module provided in an embodiment of the present application.

[0064] FIG12 is a structural diagram of a preparation process of another power module provided in an embodiment of the present application.

[0065] FIG13 is a schematic diagram of another structure of chips formed by wafer cutting provided in an embodiment of the present application. DETAILED DESCRIPTION

[0066] The technical solution in this application will be described below with reference to the accompanying drawings.

[0067] In the embodiments of the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first" and "second" can sensibly or implicitly include one or more features. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two, and "at least one" and "one or more" mean one, two or more. The singular expressions "one", "a", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless the context clearly indicates otherwise. The size of the sequence numbers of the processes below does not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. For example, in the embodiments of the present application, words such as "110", "120", and "130" are merely identifiers made for the convenience of description and do not limit the order of execution of the steps.

[0068] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0069] A wafer is a silicon wafer used to manufacture silicon semiconductor circuits. Its starting material is silicon (Si). High-purity polycrystalline silicon is dissolved, doped with silicon seed crystals, and then slowly pulled out to form a cylindrical single crystal. The silicon ingot is then ground, polished, and sliced ​​to form a silicon wafer. Domestic wafer production lines primarily focus on 8-inch and 12-inch wafers. Various circuit component structures can be fabricated on the silicon wafer, creating integrated circuit products with specific electrical functions.

[0070] The backside metallization (also known as backside metallization) of a wafer is typically composed of titanium / nickel / silver (Ti / Ni / Ag) or titanium / nickel / gold (Ti / Ni / Au). Ti serves as the bonding layer between the semiconductor and the metal; Ni is a solder diffusion layer; and Ag or Au provides a solder wettability layer, preventing oxidation of the Ni layer. Silicon wafers (SiC wafers) are commonly cut using lasers, but this process can easily lead to ablation of the backside metallization, exposing the SiC semiconductor.

[0071] As shown in Figure 1, Figure 1 shows a schematic diagram of a silicon wafer cut to form a chip. As shown in Figure 1 (a), the back of the silicon wafer 11 is connected to a back gold layer 12. The back gold layer 12 can be composed of titanium / nickel / silver (i.e., Ti / Ni / Ag). Specifically, the back gold layer 12 can include a titanium layer 13, a nickel layer 14, and a silver layer 15. The titanium layer 13, the nickel layer 14, and the silver layer 15 are stacked, and the titanium layer 13 is connected to the silicon wafer 11, and the nickel layer 14 is connected between the titanium layer 13 and the silver layer 15. When a laser is used to cut the silicon wafer 11 and the back gold layer 12, the laser cuts from bottom to top to form a chip 100. The specific structure of the chip 100 can be referred to Figure 1 (b).

[0072] It should be understood that when laser cutting is used to form the chip 100 from the silicon wafer 11 and the back gold layer 12, the back gold layer 12 will be ablated, forming a notch 111, and the chip body 110 (e.g., a SiC semiconductor) will be exposed. As shown in FIG1(b), the chip 100 formed after laser cutting of the silicon wafer 11 includes a chip body 110 and a first electrode layer 120. The first electrode layer 120 may include a titanium layer 121 (thickness approximately 0.2 μm), a nickel layer 122 (thickness approximately 0.4 μm), and a silver layer 123 (thickness approximately 1.2 μm) stacked in sequence. The nickel layer 122 is connected between the titanium layer 121 and the silver layer 123, and the titanium layer 121 is connected to the chip body 110.

[0073] As can be seen from Figure 1, laser cutting of silicon wafer 11 easily leads to back-gold ablation, forming a back-gold ablation layer on chip body 110, i.e., forming notch 111. Without metal filling, notch 111 will expose the SiC semiconductor, which is not solderable and cannot be soldered.

[0074] The chip 100 is subsequently plastic-sealed to form a power module. In the plastic-sealed power module, the plastic encapsulation material enters the non-solderable gap (i.e., the area where the notch 111 is located), forming an area filled with plastic encapsulation material. During subsequent use, temperature changes will cause the plastic encapsulation material in the non-solderable gap to generate cyclic tensile and compressive stresses on the back of the chip body 110, causing the joint to fail quickly. Specifically, there is a laser ablation area (i.e., the notch 111) around the first electrode layer 120 of the chip 100. This area contains metal oxide or SiC, which is non-solderable. After the chip body 110 is reflow soldered, there is no solder joint in the space around the substrate of the power module and the chip body 110, only plastic encapsulation material filling. The thermal expansion coefficient of the plastic encapsulation material is significantly different from that of the first electrode layer 120. The chip will continue to generate heat during operation. Under temperature cycling conditions, the plastic encapsulation material in the laser ablation area generates upward tensile and compressive stresses on the chip body 110. The repeated cycles of tensile and compressive stresses, if sustained for a long time, may cause the connection surfaces of SiC 110 and Ti 121 to separate, leading to failure of the solder layer and ultimately failure of the chip.

[0075] Furthermore, high-power modules process hundreds of kilowatts of energy, generating significant heat on the chip. To dissipate heat, a heat sink must be soldered to the power module's substrate. This high reflow temperature and prolonged reflow process causes the solder to significantly consume the nickel layer 122. During subsequent use of the product, the solder continues to react with the nickel layer 122. This depletion of the nickel layer 122 degrades the solder joint interface, leading to module failure.

[0076] Currently, one method used to achieve long-term reflow at high temperatures is to thicken the nickel layer 122 in the first electrode layer 120. However, this method increases the warpage of the wafer during subsequent processing, and excessive internal stress causes the coating to fall off.

[0077] Therefore, the embodiments of the present application provide a power module and a manufacturing method thereof, and a power device, which can avoid failure of the power module and improve the stability of the power module.

[0078] Figures 2 to 4 are schematic cross-sectional views of three chips provided in the embodiments of the present application. Figures 5 to 7 are schematic cross-sectional views of three power modules provided in the embodiments of the present application.

[0079] In some embodiments, the power module provided by the embodiments of the present application includes a chip 100, and a schematic cross-sectional structure diagram of the chip 100 can be referenced to FIG2 . Specifically, the chip 100 may include a chip body 110, a first electrode layer 120, and a metal protective layer 140, wherein: the first electrode layer 120 is connected to the chip body 110, the projection of the first electrode layer 120 on a first plane is located within the projection range of the chip body 110 on the first plane, and the first plane is parallel to the contact surface between the chip body 110 and the first electrode layer 120; the metal protective layer 140 is coated around the first electrode layer 120, and the side of the metal protective layer 140 close to the chip body 110 is in contact with the chip body 110.

[0080] In some examples, the projection of the chip body 110 on the first plane does not exceed the projection range of the entirety formed by the first electrode layer 120 and the metal protection layer 140 on the first plane.

[0081] It should be understood that the first surface of the chip body 110 close to the first electrode layer 120 can be divided into a first part and a second part, the first electrode layer 120 can be connected to the first part of the chip body 110, and the metal protection layer 140 can be connected to the second part of the chip body 110.

[0082] It should also be understood that when the wafer is cut into chips, the back gold of the chip (i.e., the first electrode layer 120) may be ablated, resulting in the formation of a notch 111 around the first electrode layer 120. The notch is not filled with material, and the chip body 110 is exposed. In other words, at least a portion of the surface of the chip body 110 close to the first electrode layer 120 is not covered by the first electrode layer 120. The metal protective layer 140 in the embodiment of the present application can fill the notch 111 around the first electrode layer 120, so that the first surface of the chip body 110 is not exposed. In other words, the metal protective layer 140 can cover the first electrode layer 120 and contact the chip body 110, so that the first surface of the chip body 110 is not exposed. Therefore, during the long-term operation of the chip, when the temperature changes, the difference in thermal expansion coefficient between the metal protective layer 140 and the first electrode layer 120 is small, so the cyclic tensile and compressive stress generated is small, thereby avoiding chip and power module failure and improving the stability of the chip and power module.

[0083] In some examples, the material of the chip body 110 can be silicon carbide (i.e., SiC). SiC can increase the operating frequency of the chip 100 and reduce the volume of the chip 100 while meeting the same operating frequency. Therefore, when the chip 100 is packaged into a power module, more space can be reserved for installing other electronic components in the power module.

[0084] In some examples, the first electrode layer 120 can be any one of Ni / Ag, Ni / Au, Ti / Ni / Ag, Ti / Ni / Au, Ti / NiV / Ag, Ti / NiV / Au, Ni(P) / Pd / Au, Ni(P) / Pd / Ag, Ni(P) / Au or Ni(P) / Ag, where Ni(P) means P element doped into Ni element, and NiV refers to an alloy of Ni element and V element.

[0085] It should be understood that the first electrode layer 120 can be composed of titanium / nickel / silver (i.e., Ti / Ni / Ag) or titanium / nickel / gold (i.e., Ti / Ni / Au), wherein Ti is a bonding layer between the semiconductor and the metal; Ni is a solder diffusion layer; and Ag or Au is a solder wettability layer that can prevent oxidation of the Ni layer. For example, the first electrode layer 120 can be Ti / Ni / Ag. Specifically, the first electrode layer 120 can include a nickel layer 121, a titanium layer 122, and a silver layer 123 stacked in sequence, with the nickel layer 122 connected between the titanium layer 121 and the silver layer 123, and the titanium layer 121 connected to the chip body 110. The thickness of the titanium layer 121 is approximately 0.2 μm, the thickness of the nickel layer 122 is approximately 0.4 μm, and the thickness of the silver layer 123 is approximately 1.2 μm.

[0086] In some embodiments, the power module provided by the embodiments of the present application includes a chip 100. A schematic cross-sectional structure diagram of the chip 100 may refer to Figure 3 or Figure 4 . Specifically, based on Figure 2 , the chip 100 may further include a second electrode layer 130. The second electrode layer 130 is connected to the side of the first electrode layer 120 away from the chip body 110. The projection of the entirety of the first electrode layer 120 and the metal protective layer 140 on the first plane does not exceed the projection range of the second electrode layer 130 on the first plane. The side of the metal protective layer 140 away from the chip body 110 may be connected to the second electrode layer 130.

[0087] It should be noted that in the embodiment of the present application, the first electrode layer 120 and the second electrode layer 130 can form a die bottom system (DBS). It should be understood that to improve the reliability of chip bonding, a metal sheet or a plated metal sheet is sintered to the back of the chip through sintering technology based on the chip back gold, so that the chip back gold and the metal sheet form a high-reliability chip back gold system, which is called DBS.

[0088] In one example, the second electrode layer 130 includes a metal support layer 132, and a micro-nanostructured material is provided on the connection surface between the metal support layer 132 and the first electrode layer 120. The material of the metal support layer 132 can include any one of the following: Cu, Ni, and Kovar alloy.

[0089] It should be understood that the metal support layer 132 can be subjected to surface micronization treatment or surface nanonization treatment, so that the connection surface between the metal support layer 132 and the first electrode layer 120 has a micro-nanostructured material (e.g., micron- or nanostructured Cu, Ni) to improve the connection stability between the metal support layer 132 and the first electrode layer 120.

[0090] It should be noted that surface micronization / nano-ization is a process that modifies the appearance, performance, or function of a material by introducing micron-scale / nano-scale structures, textures, or features onto its surface. This treatment can be applied to different types of materials, including metals, ceramics, and polymers, to achieve a variety of goals.

[0091] In another example, the second electrode layer 130 may include a first connection layer 131 and a metal support layer 132, wherein the first connection layer 131 is connected between the first electrode layer 120 and the metal support layer 132. The material of the first connection layer 131 may include any of the following: micro- or nano-structured Ag, Cu, Au, or Ni.

[0092] It should be understood that the first connection layer 131 is provided to bond and fix to the first electrode layer 120, thereby improving the connection stability between the second electrode layer 130 and the first electrode layer 120. The metal support layer 132 is provided to prevent solder from climbing up and reacting with the metal protective layer 140. The metal support layer 132 can support the first electrode layer 120 and the first connection layer 131 and has electrical and thermal conductivity.

[0093] In some examples, the second electrode layer 130 further includes a second connection layer 133 , which is connected to a side of the metal support layer 132 away from the first connection layer 131 . The material of the second connection layer 133 can be the same as that of the first connection layer 131 .

[0094] It should be understood that the second connection layer 133 is a solder wettability layer, which also serves to prevent oxidation of the metal support layer. A solder wettability layer can be a coating or material, typically applied to the soldering surface to improve the wetting properties of the solder or solder during the soldering process. The primary function of the wettability layer is to promote uniform distribution of the solder on the soldering surface and reduce surface tension, thereby achieving a better solder connection.

[0095] In some examples, the material of the metal protective layer 140 can be the same as that of the first connection layer 131. Specifically, the material of the metal protective layer 140 can include any of the following: micro- or nano-structured Ag, Cu, Au, or Ni. It should be understood that the metal protective layer 140 can be formed by pressure-sintering the first connection layer 131. Therefore, the material of the metal protective layer 140 can be the same as that of the first connection layer 131.

[0096] In one example, the cross-sectional structure of the chip 100 may be as shown in FIG3 , and the second electrode layer 130 may be Ag / Cu / Ag. That is, the first connection layer 131 may be a first silver layer (with a thickness of approximately 0.2-0.5 μm), the metal support layer 132 may be a copper layer (with a thickness of approximately 40-50 μm), and the second connection layer 133 may be a second silver layer (with a thickness of approximately 0.2-0.5 μm). Specifically, the second electrode layer 130 may include a first silver layer, a copper layer, and a second silver layer stacked in sequence, with the copper layer connected between the first silver layer and the second silver layer, and the first silver layer connected to the first electrode layer 120. It should be understood that the second electrode layer 130 may be obtained by coating two opposite sides of a copper substrate with silver layers.

[0097] In another example, the cross-sectional structure of the chip 100 can be as shown in FIG4 , and the second electrode layer 130 can be Ag / Ni / Cu / Ni / Ag. That is, the first connection layer 131 can be a first silver layer, the metal support layer 132 can include a first nickel layer 134, a copper layer 135, and a second nickel layer 136, and the second connection layer 133 can be a second silver layer. Specifically, the second electrode layer 130 can include a first silver layer, a first nickel layer 134, a copper layer 135, a second nickel layer 136, and a second silver layer stacked in sequence, and the first silver layer, the first nickel layer 134, the copper layer 135, the second nickel layer 136, and the second silver layer are connected in sequence along a first direction, and the first direction is perpendicular to the contact surface between the chip body 110 and the first electrode layer 120. It should be understood that in the embodiment of the present application, by providing the first nickel layer 134, the copper layer 135, and the second nickel layer 136, it is possible to further prevent the corrosion of the solder and further enhance the reliability of the welding.

[0098] In some embodiments, the power module 200 provided in the embodiments of the present application may include a chip 100 and a metal-clad substrate 150, wherein the structure of the power module 200 may refer to FIG5 , and the structure of the chip 100 may refer to FIG2 . That is, based on the chip 100 shown in FIG2 , a power module 200 as shown in FIG5 may be processed. Specifically, the power module 200 may include a chip body 110, a first electrode layer 120, a metal protective layer 140, and a metal-clad substrate 150, wherein the metal-clad substrate 150 is connected to a side of the first electrode layer 120 away from the chip body and is in contact with the metal protective layer 140. The metal-clad substrate 150 may be soldered to the side of the first electrode layer 120 away from the chip body 110 by solder 160.

[0099] The metal-clad substrate 150 may be a direct bond copper (DBC) substrate, an active metal brazed copper (AMB) substrate, or an insulated metal substrate (IMS), etc., which is not limited in this application.

[0100] 5 , the metal-clad substrate 150 may be a DBC substrate, that is, the metal-clad substrate 150 is composed of a first copper layer 151, a ceramic substrate 152, and a second copper layer 153. The first copper layer 151 may be soldered to the first electrode layer 120 via solder 160.

[0101] Solder 160 can be selected from at least one of tin solder and lead solder. The tin solder can be selected from at least one of SnSb5, SnSb8, SnSbAg, SAC305, SAC multi-reinforced solder, and SnSb10. The material of solder 160 can be selected as needed. SnSb5 refers to a solder containing 5% by weight of Sb in the Sn element, SnSb8 refers to a solder containing 8% by weight of Sb in the Sn element, and SnSb10 refers to a solder containing 10% by weight of Sb in the Sn element. The "SAC" in SAC306 stands for Sn, Ag, and Cu, indicating that the product is composed of Sn (tin), Ag (silver), and Cu (copper). "3" represents 3% Ag, and "05" represents 0.5% Cu. SAC multi-reinforced solder includes other metal components in addition to Sn, Ag, and Cu to enhance solder reliability.

[0102] When the first electrode layer 120 and the metal-clad substrate 150 are welded together using solder (e.g., SnSb10), the metal layer (e.g., Ag or Au) in the first electrode layer 120 welded to the metal-clad substrate 150 may melt in the solder 160, and the intermediate layer (e.g., Ni) in the first electrode layer 120 has a certain solder resistance effect on the solder, which can prevent the solder from climbing up and reacting with the metal protective layer 140.

[0103] For example, the first electrode layer 120 includes a nickel layer 121, a titanium layer 122 and a silver layer 123. When the first electrode layer 120 and the metal-clad substrate 150 are welded via a solder 160 (e.g., SnSb10), the silver layer 123 in the first electrode layer 120 will melt in the solder 160, and the copper layer 122 in the first electrode layer 120 has a certain solder resistance effect on the solder 160, thereby preventing the solder 160 from climbing up the copper layer 122 of the first electrode layer 120 and reacting with the silver layer 121.

[0104] It should be noted that if the metal-clad substrate 150 is directly soldered to the side of the first electrode layer 120 away from the chip body 110, the metal protective layer 140 must be made of a material that provides a solder resist. For example, the metal protective layer 140 can be made of any of the following materials: Cu, Ni, or Kovar alloy. It should be understood that Cu, Ni, and Kovar alloy provide a solder resist, preventing them from reacting with the solder 160 and melting into it.

[0105] In some embodiments, the power module provided by the embodiments of the present application includes a chip 100 and a metal-clad substrate 150, wherein the structure of the power module 200 can refer to FIG6, and the structure of the chip 100 can refer to FIG3. That is, based on the chip 100 shown in FIG3, the power module 200 shown in FIG6 can be processed. Specifically, the power module 200 may include a chip body 110, a first electrode layer 120, a metal protective layer 140, a second electrode layer 130 and a metal-clad substrate 150, wherein the metal-clad substrate 150 is connected to the side of the second electrode layer 130 away from the chip body. The metal-clad substrate 150 is soldered to the side of the second electrode layer 130 away from the chip body 110 by solder 160. The second electrode layer 130 may include a first connection layer 131 (such as a first silver layer) and a metal support layer 132 (such as a copper layer), and the first connection layer 131 is connected between the metal support layer 132 and the first electrode layer 120.

[0106] 3 and 6 , when the second electrode layer 130 and the metal-clad substrate 150 are welded via the solder 160 (e.g., SnSb10), the second connection layer 133 (e.g., the second silver layer) in the second electrode layer 130 will melt in the solder 160, and the metal support layer 132 (e.g., the copper layer) in the second electrode layer 130 has a certain solder resistance effect on the solder 160, thereby preventing the solder 160 from climbing onto the metal support layer 132 (e.g., the copper layer) and reacting with the first connection layer 131 (e.g., the first silver layer).

[0107] In some embodiments, the power module provided by the embodiments of the present application includes a chip 100 and a metal-clad substrate 150, wherein the structure of the power module 200 can refer to FIG7, and the structure of the chip 100 can refer to FIG4. That is, based on the chip 100 shown in FIG4, the power module 200 shown in FIG7 can be processed. Specifically, the power module 200 may include a chip body 110, a first electrode layer 120, a metal protective layer 140, a second electrode layer 130 and a metal-clad substrate 150, wherein the metal-clad substrate 150 is connected to the side of the second electrode layer 130 away from the chip body. The metal-clad substrate 150 is soldered to the side of the second electrode layer 130 away from the chip body 110 by solder 160. The second electrode layer 130 may include a first connection layer 131 (such as a first silver layer) and a metal support layer 132, and the metal support layer 132 may include a first nickel layer 134, a copper layer 135 and a second nickel layer 136 stacked in sequence. That is to say, the second electrode layer 130 may include a first connection layer 131 (such as a first silver layer), a first nickel layer 134, a copper layer 135 and a second nickel layer 136 stacked in sequence, and along a first direction, the first connection layer 131 (such as a first silver layer), the first nickel layer 134, the copper layer 135 and the second nickel layer 136 are connected in sequence, and the first direction is perpendicular to the contact surface between the chip body 110 and the first electrode layer 120.

[0108] 4 and 7 , when the second electrode layer 130 and the metal-clad substrate 150 are welded via solder 160 (e.g., SnSb10), the second connection layer 133 in the second electrode layer 130 will melt in the solder 160, and the first nickel layer 134, copper layer 135, and second nickel layer 136 in the second electrode layer 130 have a certain solder resistance effect on the solder 160, which can further prevent the solder 160 from climbing up the first nickel layer 134 in the second electrode layer 130 and reacting with the first connection layer 131.

[0109] In some examples, the power module 200 further includes a package for encapsulating the chip body 110, the first electrode layer 120, the metal protection layer 140, the second electrode layer 130, and the metal-clad substrate 150. It should be understood that the encapsulated power module can be connected to a heat sink via a thermally conductive medium layer, so that the heat generated by the chip can be transferred to the heat sink for dissipation.

[0110] It should be noted that the connection methods involved in the embodiments of the present application include but are not limited to welding, sintering and the like.

[0111] This application does not limit the type and number of chip bodies 110 in the power module. Chip bodies 110 can be any number of chips of any type used in the power module. For example, chip bodies 110 can be insulated gate bipolar transistors (IGBTs) and fast recovery diodes (FRDs).

[0112] FIG8 is a flow chart of a method for manufacturing a power module according to an embodiment of the present application. The manufacturing method 100 may include the following steps:

[0113] S101 , obtaining the chip 100 and the second electrode layer 130 .

[0114] In this step, the obtained chip 100 may be as shown in (a) of FIG9 , that is, the chip 100 may include a chip body 110 and a first electrode layer 120 , and there are notches 111 formed around the first electrode layer 120 due to laser cutting.

[0115] Specifically, the chip 100 includes a chip body 110 and a first electrode layer 120. The projection of the first electrode layer 120 on the first plane is located within the projection range of the chip body 110 on the first plane. The first plane is parallel to the contact surface between the chip body 110 and the first electrode layer 120. At least part of the side of the chip body 110 close to the first electrode layer 120 is not covered by the first electrode layer 120.

[0116] In some examples, the first electrode layer 120 can be any one of Ni / Ag, Ni / Au, Ti / Ni / Ag, Ti / Ni / Au, Ti / NiV / Ag, Ti / NiV / Au, Ni(P) / Pd / Au, Ni(P) / Pd / Ag, Ni(P) / Au or Ni(P) / Ag, where Ni(P) means P element doped into Ni element, and NiV refers to an alloy of Ni element and V element.

[0117] In some embodiments, the second electrode layer 130 can refer to FIG. 3 or FIG. 9 (a), that is, the second electrode layer 130 can include Ag / Cu / Ag. That is, the first connection layer 131 can be a first silver layer (with a thickness of approximately 0.2-0.5 μm), the metal support layer 132 can be a copper layer (with a thickness of approximately 40-50 μm), and the second connection layer 133 can be a second silver layer (with a thickness of approximately 0.2-0.5 μm). Specifically, the second electrode layer 130 can include a first silver layer, a copper layer, and a second silver layer stacked in sequence, with the copper layer connected between the first and second silver layers, and the first silver layer connected to the first electrode layer 120.

[0118] It should be noted that, in this embodiment, the second electrode layer 130 may be formed by plating silver on both sides of the copper foil.

[0119] In other embodiments, the second electrode layer 130 can refer to FIG4 , that is, the second electrode layer 130 can include Ag / Ni / Cu / Ni / Ag. That is, the first connection layer 131 can be a first silver layer, the metal support layer 132 can include a first nickel layer 134, a copper layer 135, and a second nickel layer 136, and the second connection layer 133 can be a second silver layer. Specifically, the second electrode layer 130 can include a first silver layer, a first nickel layer 134, a copper layer 135, a second nickel layer 136, and a second silver layer stacked in sequence, and the first silver layer, the first nickel layer 134, the copper layer 135, the second nickel layer 136, and the second silver layer are connected in sequence along a first direction, and the first direction is perpendicular to the contact surface between the chip body 110 and the first electrode layer 120. It should be understood that in the embodiment of the present application, by providing the first nickel layer 134, the copper layer 135, and the second nickel layer 136, it is possible to further prevent the corrosion of the solder and further enhance the reliability of the welding.

[0120] It should be noted that, in this embodiment, the second electrode layer 130 may be formed by plating silver and nickel on both sides of the copper foil.

[0121] In some embodiments, this step may also include: obtaining a chip body 110, a first electrode layer 120, and a second electrode layer 130. During specific processing, the chip body 110 and the first electrode layer 120 may be combined together to form the chip 100 by sputtering or evaporation, and then S102 is performed to pressure-sinter the second electrode layer 130 on a side of the first electrode layer 120 away from the chip body 110.

[0122] S102 , sintering the second electrode layer 130 under pressure on a side of the first electrode layer 120 away from the chip body 110 , and forming a metal protection layer 140 around the first electrode layer 120 .

[0123] Press sintering involves applying pressure to the bonded components at high temperatures, thereby increasing their density, promoting atomic diffusion between sintered material particles and at the interface between the sintered material and the bonded components, and enhancing bond strength and reliability. This application does not limit the pressure sintering process employed; any known method may be employed.

[0124] In a specific implementation, referring to FIG9( b ), the second electrode layer 130 and the first electrode layer 120 are laminated together and then placed on a pressurized base plate 210, so that the second electrode layer 130 contacts the pressurized base plate 210. The pressurized base plate 210 can be made of stainless steel or aluminum alloy.

[0125] In some embodiments, as shown in FIG9( b ), a positioning jig 220 may be placed around the chip 100. The distance between the positioning jig 220 and the chip should be within a certain range to facilitate positioning during subsequent pressurization. For example, the distance between the positioning jig 220 and the chip 100 may be less than 2 mm.

[0126] In some embodiments, a pressure head can be used to perform pressure sintering on the chip body 110. That is, pressure is applied to the side of the chip body 110 away from the second electrode layer 130. Taking a pressure head area of ​​50 mm*50 mm as an example, the parallelism of the pressure head can be set to ≤5 μm to reduce the risk of chip damage and control the thickness of the sintered layer.

[0127] Illustratively, the sintering conditions for pressure sintering are: the sintering temperature is controlled at 200° C. to 300° C., the applied pressure is controlled at 5 MPa to 30 MPa, and the sintering time is controlled at 1 min to 10 min.

[0128] In a specific implementation, the pressure sintering process can be performed in an air environment. To prevent product oxidation, the chip body 110 is pressure sintered in a protective atmosphere or vacuum environment. The protective atmosphere can be a reducing atmosphere or an inert atmosphere. Exemplary protective atmospheres include N2, a mixture of N2 and H2, Ar, He, or formic acid gas, etc., which are not limited here.

[0129] To prevent damage to the chip body 110 from the pressure head during the sintering process, a removable pressure buffer film 230 can be placed between the chip body 110 and the pressure head during pressure sintering, as shown in Figure 9 (c). During pressure sintering, the pressure buffer film 230 prevents direct contact between the pressure head and the chip body 110 and reduces damage caused by stress concentration on the chip body 110. After pressure sintering is completed, the pressure buffer film 230 can be removed.

[0130] Optionally, the thickness of the pressure buffer film 230 can be set to 50-90 μm, which is not limited here. For example, the pressure buffer film 230 can be made of an organic film such as a Teflon film.

[0131] For example, as shown in FIG9(d), after pressure is applied to the side of the chip body 110 away from the second electrode layer 130, the metal layer (i.e., the first connection layer 131) connecting the second electrode layer 130 and the first electrode layer 120 is squeezed around the first electrode layer 120 along a first direction perpendicular to the contact surface between the chip body 110 and the first electrode layer 120 to form a metal protective layer 140. Ultimately, the chip 100 shown in FIG3 or FIG9(e) can be formed.

[0132] The metal protection layer 140 covers all four sides of the first electrode layer 120 , and the metal protection layer 140 is in contact with the chip body 110 on a side close to the chip body 110 .

[0133] In some embodiments, the projection of the chip body 110 on the first plane does not exceed the projection range of the entirety of the first electrode layer 120 and the metal protection layer 140 on the first plane.

[0134] S103 , sintering or welding the metal-clad substrate 150 on the side of the second electrode layer 130 away from the chip body 110 .

[0135] In a specific implementation, the metal-clad substrate 150 may be welded to the side of the second electrode layer 130 away from the chip body 110 . Specifically, the metal-clad substrate 150 may be welded to the side of the second connection layer 133 away from the chip body 110 through solder 160 .

[0136] The metal-clad substrate 150 may be a DBC substrate, an AMC substrate, an IMS substrate, etc., which is not limited in this application.

[0137] Exemplarily, the metal-clad substrate 150 can be a DBC substrate, that is, the metal-clad substrate 150 can be composed of a first copper layer 151, a ceramic substrate 152, and a second copper layer 153. The first copper layer 151 can be soldered to the second electrode layer 130 via solder 160. The solder 160 can be selected from at least one of tin solder and lead solder. The tin solder can be selected from at least one of SnSb5, SnSb8, SnSbAg, SAC305, SAC multi-reinforced, and SnSb10. The material of the solder 160 can be selected as needed.

[0138] It should be noted that when the second electrode layer 130 and the metal-clad substrate 150 are welded via the solder 160 (e.g., SnSb10), the second connection layer 133 (e.g., the second silver layer) in the second electrode layer 130 will melt in the solder 160, thereby forming the power module 200 as shown in FIG6 or FIG9 (f). The metal support layer 132 (e.g., the copper layer) in the second electrode layer 130 has a certain solder resistance effect on the solder 160, which can prevent the solder 160 from climbing onto the metal support layer 132 and reacting with the first connection layer 131 and the metal protective layer 140.

[0139] In some embodiments, after S103 , the step may further include: packaging the power module 200 with a plastic package, that is, packaging the chip body 110 , the first electrode layer 120 , the metal protective layer 140 , the second electrode layer 130 and the metal-clad substrate 150 with a package.

[0140] FIG10 is a flow chart of another method for manufacturing a power module according to an embodiment of the present application. The manufacturing method 200 may include the following steps:

[0141] S201, printing a silver paste on the copper layer to form a silver layer on the surface of the copper layer.

[0142] The silver paste may include at least one of micrometer silver particle paste and nanometer silver particle paste. Micrometer silver paste is made from micrometer silver particles and an organic solvent, which is low-cost and safe. It is generally sintered under pressure, resulting in a high density of the sintered material, a strong interface bond between the bonded bodies, and high bond reliability. Nanometer silver paste is made from nanometer silver particles and an organic solvent, which is high-cost and carries the safety risks of nanoparticle operation.

[0143] Optionally, in order to improve the reliability of sintering bonding and reduce costs, in the embodiment of the present application, micron silver paste can be printed on the metal support layer 132 (such as a copper layer).

[0144] In some embodiments, as shown in (a) of FIG12 , a stencil printing process or a screen printing process can be used to print silver paste on the sintering area corresponding to the metal support layer 132 (such as a copper layer), thereby forming a first connection layer 131 (such as a silver layer) on the surface of the metal support layer 132 (such as a copper layer). Since the stencil printing process is low-cost and simple to manufacture compared to the screen printing process, the present application can use the stencil printing process to print the silver paste on the sintering area corresponding to the metal support layer 132 (such as a copper layer).

[0145] For example, the thickness of the printed silver paste can be controlled to be about 30 μm, and can be specifically designed according to the actual product, which is not limited here.

[0146] It should be noted that, in this step, the silver paste may be printed on the entire surface of the metal support layer 132 (eg, copper layer), or may be printed at the position where the chip needs to be sintered.

[0147] S202, pre-drying the silver layer.

[0148] In practice, the printed silver paste is pre-dried to prevent the silver paste from collapsing during pressurized sintering. In other words, the first connection layer 131 (eg, silver layer) on the surface of the metal support layer 132 (eg, copper layer) can be pre-dried.

[0149] S203 , mounting the chip 100 on the silver layer and performing pressure sintering to form a metal protection layer 140 around the first electrode layer 120 .

[0150] In a specific implementation, as shown in FIG12( b ), the chip 100 and the silver layer 131 are bonded together and then placed on a pressurized base plate 210. The pressurized base plate 210 can be made of stainless steel or aluminum alloy.

[0151] In some embodiments, as shown in (c) of FIG. 12 , a positioning jig 220 may be provided around the chip 100 . The distance between the positioning jig 220 and the chip should be within a certain range to facilitate positioning during subsequent pressurization.

[0152] In some embodiments, a pressure head can be used to perform pressure sintering on the chip body 110. That is, pressure is applied to the side of the chip body 110 away from the second electrode layer 130. Taking a pressure head area of ​​50 mm*50 mm as an example, the parallelism of the pressure head can be set to ≤5 μm to reduce the risk of chip damage and control the thickness of the sintered layer.

[0153] Illustratively, the sintering conditions for pressure sintering are: the sintering temperature is controlled at 200° C. to 300° C., the applied pressure is controlled at 5 MPa to 30 MPa, and the sintering time is controlled at 1 min to 10 min.

[0154] In a specific implementation, the pressure sintering process can be performed in an air environment. To prevent product oxidation, the chip body 110 is pressure sintered in a protective atmosphere or a vacuum environment. The protective atmosphere can be a reducing atmosphere or an inert atmosphere. Exemplary protective atmospheres include N2, a mixture of N2 and H2, Ar, He, or formic acid gas, etc., which are not limited here.

[0155] To prevent damage to the chip body 110 from the pressure head during the sintering process, a removable pressure buffer film 230 can be placed between the chip body 110 and the pressure head during pressure sintering, as shown in FIG12(d). During pressure sintering, the pressure buffer film 230 prevents direct contact between the pressure head and the chip body 110 and reduces damage caused by stress concentration on the chip body 110. After pressure sintering is completed, the pressure buffer film 230 can be removed.

[0156] Optionally, the thickness of the pressure buffer film 230 can be set to 50-90 μm, which is not limited here. For example, the pressure buffer film 230 can be made of an organic film such as a Teflon film.

[0157] For example, as shown in FIG12(d), after pressure is applied to the side of the chip body 110 away from the second electrode layer 130, the silver layer (i.e., the first connection layer 131) connecting the second electrode layer 130 and the first electrode layer 120 is squeezed around the first electrode layer 120 along a first direction perpendicular to the contact surface between the chip body 110 and the first electrode layer 120 to form the metal protective layer 140. Finally, the chip 100 shown in FIG3 or FIG12(e) can be formed.

[0158] Among them, the metal protective layer 140 is wrapped around the first electrode layer 120, and the metal protective layer 140 is in contact with the chip body 110 on the side close to the chip body 110, and the projection of the chip body 110 on the first plane does not exceed the projection range of the whole formed by the first electrode layer 120 and the metal protective layer 140 on the first plane.

[0159] S204 , sintering or soldering the metal-clad substrate 150 on the side of the copper layer away from the chip body 110 .

[0160] The specific content of this step can be referred to S103 and will not be repeated here.

[0161] FIG11 is a flow chart of another method for manufacturing a power module according to an embodiment of the present application. The manufacturing method 300 may include the following steps:

[0162] S301, attaching a silver film to the copper layer to form a silver layer on the surface of the copper layer.

[0163] In some embodiments, a whole silver film may be attached to one surface of the metal support layer 132 (eg, copper layer) to cover the surface of the metal support layer 132 (eg, copper layer).

[0164] In other embodiments, as shown in (a) in Figure 12, a silver film can be attached to a metal support layer 132 (such as a copper layer) at the position where the chip is sintered, and a silver layer (i.e., a first connection layer 131) can be formed on the surface of the metal support layer 132 (such as a copper layer).

[0165] S302 , mounting the chip 100 on the silver film attached to the copper layer, and performing pressure sintering to form a metal protection layer 140 around the first electrode layer 120 .

[0166] The specific content of this step can be referred to S203 and will not be repeated here.

[0167] S303 , soldering the metal-clad substrate 150 on the side of the copper layer away from the chip body 110 .

[0168] The specific content of this step can be referred to S103 and will not be repeated here.

[0169] It should be noted that power module manufacturing methods 100, 200, and 300 are three different power module manufacturing methods provided in the embodiments of this application. It should be understood that in the embodiments of this application, a silver layer (first connection layer 131) can be formed on the surface of the copper layer (i.e., the metal support layer 132) by applying silver paste or silver film.

[0170] The above description, combined with Figures 1 to 12 , illustrates that after obtaining the chip 100, the chip 100 is processed to obtain the final power module 200. In other embodiments provided in the present application, a wafer may be directly obtained and processed as a whole, that is, the wafer is pressure-sintered and then wafer dicing is performed to obtain the final chip 100.

[0171] For example, as shown in FIG13 , the back side of the wafer 11 is connected to a first back gold layer 12 and a second back gold layer 16. The first back gold layer 12 may be composed of titanium / nickel / silver (i.e., Ti / Ni / Ag). Specifically, the first back gold layer 12 may include a titanium layer 13, a nickel layer 14, and a silver layer 15. The titanium layer 13, the nickel layer 14, and the silver layer 15 are stacked, and the titanium layer 13 is connected to the silicon wafer 11, and the nickel layer 14 is connected between the titanium layer 13 and the silver layer 15. The second back gold layer 16 may be composed of silver / copper / silver (i.e., Ag / Cu / Ag). Specifically, the second back gold layer 16 may include a silver layer 17, a copper layer 18, and a silver layer 19. The silver layer 17, the copper layer 18, and the silver layer 19 are stacked, and the silver layer 17 is connected to the first back gold layer 12, and the copper layer 18 is connected between the silver layer 17 and the silver layer 19.

[0172] When laser cutting silicon wafer 11, the laser cuts from bottom to top to form chip 100. The specific structure of chip 100 can be seen in Figure 13 (b). The chip 100 formed after laser cutting of silicon wafer 11 can include a chip body 110, a first electrode layer 120, a metal protective layer 140, and a second electrode layer 130. The structure of chip 100 can be seen in the relevant description of Figure 3, and will not be repeated here.

[0173] It should be understood that when Ag / Cu / Ag is added (i.e., a second back gold layer 16 is added) and the wafer 11 is laser cut from bottom to top, the first back gold layer 12 and the second back gold layer 16 are ablated. After ablation, there is still metal residue on the back gold of the chip, forming a metal protective layer 140. During reflow, the metal oxide can be reduced and removed to obtain a good bond, thereby preventing the chip from being exposed. Therefore, during the long-term operation of the chip, when the temperature changes, the cyclic tensile and compressive stresses generated are small due to the small difference in thermal expansion coefficient between the metal protective layer 140 and the first electrode layer 120, thereby avoiding chip and power module failure and improving the stability of the chip and power module.

[0174] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A power module, characterized in that: include: A chip body (110), a first electrode layer (120) and a metal protection layer (140), wherein: The first electrode layer (120) is connected to the chip body (110), a projection of the first electrode layer (120) on a first plane is located within a projection range of the chip body (110) on the first plane, and the first plane is parallel to a contact surface between the chip body (110) and the first electrode layer (120); The metal protection layer (140) is coated around the first electrode layer (120), and a surface of the metal protection layer (140) close to the chip body (110) is in contact with the chip body (110).

2. The power module according to claim 1, characterized in that: The projection of the chip body (110) on the first plane does not exceed the projection range of the whole formed by the first electrode layer (120) and the metal protection layer (140) on the first plane.

3. The power module according to claim 1 or 2, characterized in that: The power module further comprises a metal-clad substrate (150), wherein the metal-clad substrate (150) is connected to a side of the first electrode layer (120) away from the chip body (110) and is in contact with the metal protection layer (140).

4. The power module according to claim 1 or 2, characterized in that: The power module further comprises a second electrode layer (130), the second electrode layer (130) being connected to a side of the first electrode layer (120) away from the chip body (110), and the projection of the whole formed by the first electrode layer (120) and the metal protective layer (140) on the first plane does not exceed the projection range of the second electrode layer (130) on the first plane.

5. The power module according to claim 4, characterized in that: The second electrode layer (130) comprises a metal support layer (132), and a micro-nano structure material is provided on a connection surface between the metal support layer (132) and the first electrode layer (120).

6. The power module according to claim 4, characterized in that: The second electrode layer (130) comprises a first connection layer (131) and a metal support layer (132), wherein the first connection layer (131) is connected between the first electrode layer (120) and the metal support layer (132).

7. The power module according to claim 6, characterized in that: The second electrode layer (130) further comprises a second connection layer (133), wherein the second connection layer (133) is connected to a side of the metal support layer (132) away from the first connection layer (131).

8. The power module according to claim 6 or 7, characterized in that: The material of the first connection layer (131) includes any one of the following: Ag, Cu, Au, Ni in micron or nano structure.

9. The power module according to any one of claims 5 to 8, characterized in that: The material of the metal support layer (132) includes any one of the following: Cu, Ni, and Kovar alloy.

10. The power module according to any one of claims 6 to 8, characterized in that: The material of the metal protection layer (140) is the same as the material of the first connection layer (131).

11. The power module according to any one of claims 4 to 10, characterized in that: The power module further comprises a metal-clad substrate (150), wherein the metal-clad substrate (150) is connected to a side of the second electrode layer (130) away from the chip body (110).

12. The power module according to any one of claims 1 to 11, characterized in that: The first electrode layer (120) is any one of Ni / Ag, Ni / Au, Ti / Ni / Ag, Ti / Ni / Au, Ti / NiV / Ag, Ti / NiV / Au, Ni(P) / Pd / Au, Ni(P) / Pd / Ag, Ni(P) / Au or Ni(P) / Ag, wherein Ni(P) means Ni element doped with P element, and NiV means an alloy of Ni element and V element.

13. A method for manufacturing a power module, characterized in that: include: Obtaining a chip (100) and a second electrode layer (130), wherein the chip (100) comprises a chip body (110) and a first electrode layer (120) connected to the chip body (110), a projection of the first electrode layer (120) on a first plane being located within a projection range of the chip body (110) on the first plane, the first plane being parallel to a contact surface between the chip body (110) and the first electrode layer (120), and a surface of the chip body (110) close to the first electrode layer (120) being at least partially not covered by the first electrode layer (120); The second electrode layer (130) is sintered on a side of the first electrode layer (120) away from the chip body (110) through a pressure sintering process, and a metal layer connecting the second electrode layer (130) and the first electrode layer (120) is squeezed around the first electrode layer (120) along a first direction to form a metal protective layer (140), wherein the first direction is perpendicular to the first plane. The metal protection layer (140) is coated around the first electrode layer (120), and a surface of the metal protection layer (140) close to the chip body (110) is in contact with the chip body (110).

14. The manufacturing method according to claim 13, characterized in that: The production method further comprises: The projection of the chip body (110) on the first plane does not exceed the projection range of the whole formed by the first electrode layer (120) and the metal protection layer (140) on the first plane, and the metal-clad substrate (150) is welded or sintered on the side of the second electrode layer (130) away from the chip body (110).

15. A power device, characterized in that: The power device is used for AC / DC conversion, and the power device includes a circuit board and a power module as described in any one of claims 1 to 13, or the power device includes a circuit board and a power module manufactured by the manufacturing method as described in claim 13 or 14, and the power module is arranged on the circuit board.

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