Integrated circuit current transducer

Abstract

Integrated circuit current transducer (1) comprising an integrated circuit (IC) chip device (2) and a lead frame arrangement (3) housed within an insulating overmold housing (7), the lead frame arrangement comprising a plurality of primary conductor terminals (13) and a secondary conductor arrangement (5), the IC chip device comprising a semiconductor IC die (8) having a first active side (9a) and a second side (9b), at least the first active side having active portions including electrical connection terminals (11) for connection to power and signal transmission conductors and a magnetic field sensor (12) arranged at or close to the surface of the active side. The IC chip device further comprises a primary conductor layer arrangement (19) including a plurality of primary conductor loops (20) connected in series and a plurality of insulation layers in a stacked relationship formed directly on the first active side of the semiconductor IC die.

Description

[0001] INTEGRATED CIRCUIT CURRENT TRANSDUCER

[0002] The present invention relates to an open-loop integrated circuit current transducer for surface mounting on a circuit board.

[0003] It is known to provide open-loop current transducers having surface mount electrical connections for mounting on a circuit board. In many applications, there is an advantage in having a very compact and low height current transducer having an integrated primary conductor within an overmolded insulative housing. Such coreless current transducers may include an integrated circuit (IC) chip having an active sensing layer thereon detecting the magnetic field induced by a current to be measured flowing in a primary conductor integrated within the current transducer, the integrated circuit chip being electrically connected to secondary contacts that supply power and allow transmission of the measurement signal to the external circuit board.

[0004] Despite the compacity of conventional IC base current transducers, there is a continuous desire to further reduce the size and / or increase the measurement accuracy and range of such transducers while reducing manufacturing costs. There are also many applications in which such transducers may be incorporated and which may have a large range of current amplitudes to measure.

[0005] In view of the foregoing, it is an object of the invention to provide an integrated circuit openloop current transducer that is compact and accurate, yet that is economical to manufacture.

[0006] It is advantageous to provide an IC open-loop current transducer that can be configured easily for different current measurement ranges.

[0007] It is advantageous to provide an IC open-loop current transducer that has a high measurement sensitivity.

[0008] It is advantageous to provide an IC open-loop current transducer adapted for surface mounting on a circuit board.

[0009] Objects of the invention have been achieved by providing an open loop current transducer according to claim 1. Objects of the invention have been achieved by providing an open loop current transducer according to claim 16.

[0010] Dependent claims set out various advantageous features of embodiments of the invention.

[0011] Disclosed herein is an integrated circuit current transducer comprising an integrated circuit (IC) chip device and a lead frame arrangement housed within an insulating overmold housing, the lead frame arrangement comprising a plurality of primary conductor terminals and a secondary conductor arrangement, the IC chip device comprising a semiconductor IC die having a first active side and a second side, at least the first active side having active portions including electrical connection terminals for connection to power and signal transmission conductors and a magnetic field sensor arranged at or close to the surface of the active side.

[0012] The IC chip device further comprises a primary conductor layer arrangement including a plurality of primary conductor loops connected in series and a plurality of insulation layers in a stacked relationship formed directly on the first active side of the semiconductor IC die.

[0013] In an advantageous embodiment, each primary conductor loop has a first connection end terminal at one end and a second connection end terminal at another end, the connection end terminals configured for connection to a primary conductor carrying the current to be measured.

[0014] In an advantageous embodiment, the primary conductor loops are connected in series by conductive vias between ends of the primary conductor loops through the insulation layer separating the primary conductor loops.

[0015] In an advantageous embodiment, the one or more primary conductor loops comprise a central conductor free area in which at least one magnetic field sensing portion of the magnetic field sensor is arranged.

[0016] In an advantageous embodiment, the material of the insulation layer comprises or consists of a polyimide material layer.

[0017] In an advantageous embodiment, connection end terminals of the one or more primary conductor loops comprise connection pad surfaces configured for wire bonding.

[0018] In an advantageous embodiment, the connection end terminals are arranged along an edge of the IC die. In an advantageous embodiment, the primary conductor loop connection end terminals are connected to respective primary conductor terminals by primary conductor bond wires.

[0019] In an advantageous embodiment, each primary conductor terminal is connected to respective connection end terminals of the primary conductor loops by a plurality of bond wires.

[0020] In an advantageous embodiment, there are three said primary conductor loops in said stacked relationship.

[0021] In an advantageous embodiment, a first connection end terminal of a first said primary conductor loop is connected via bond wires to a first primary conductor terminal, a second connection end terminal of the first primary conductor loop and a first connection end terminal of a second said primary conductor loop is connected via bond wires to a second primary conductor terminal, a second connection end terminal of the second primary conductor loop and a first connection end terminal of a third primary said conductor loop is connected via bond wires to a third primary conductor terminal, and a second connection end terminal of the third primary conductor loop is connected via bond wires to a fourth primary conductor terminal.

[0022] In an advantageous embodiment, the current transducer according to any preceding claim wherein the primary conductor loops and insulating layers are made by redistribution layer (RDL) technology.

[0023] In an advantageous embodiment, the magnetic field sensor comprises a first magnetic field sensing portion and a second magnetic field sensing portion at a certain distance from the first magnetic field sensing portion configured for a differential measurement of the magnetic field generated by the primary conductor loops.

[0024] In an advantageous embodiment, the first magnetic field sensing portion is surrounded on at least three sides by the primary conductor loops and the second magnetic field sensing portion is positioned adjacent an outer side of the primary conductor loops.

[0025] In an advantageous embodiment, the magnetic field sensing portion(s) comprise(s) Hall effect sensor(s) and the IC die is a CMOS die.

[0026] Further advantageous features of the invention will be apparent from the following detailed description of embodiments of the invention and the accompanying illustrations. Brief description of the figures

[0027] Figure 1 is a perspective schematic view of an integrated circuit (IC) current transducer according to an embodiment of the invention, the overmold housing portion being shown transparent;

[0028] Figure 2 is a perspective schematic exploded view of the IC current transducer of figure 1 (without overmold housing portion);

[0029] Figure 3 is a perspective schematic view illustrating steps (a) to (e) in the manufacturing of the IC current transducer of figure 1 ;

[0030] Figure 4 is a perspective schematic exploded view of primary conductor loops of the IC current transducer of figure 1 ;

[0031] Figure 5 is a schematic view illustrating interconnections between primary conductor terminals and different primary conductor loops (a) to (c) of the IC current transducer of figure 1.

[0032] Referring to the figures, an electric current transducer 1 for mounting on and connection to an external circuit board, comprises an integrated circuit (IC) chip device 2 and a lead frame arrangement 3 housed within an insulating overmold housing 7.

[0033] The lead frame arrangement 3 comprises a primary conductor arrangement 4 and a secondary conductor arrangement 5. The lead frame arrangement is formed from a sheet of conductive metal, more specifically in the form of a band or strip that is stamped and formed in a stamping and forming process to cut out, bend and / or emboss the sheet metal to form the primary and secondary conductors. Stamping and forming of lead frame arrangements from sheet metal are perse well known techniques.

[0034] The primary conductor arrangement comprises a plurality of primary conductor terminals 13, 13a, 13b, 13c, 13d configured on the one hand for connection to conductive traces on an external circuit board, and on the other hand to a primary conductor layer arrangement 19 formed on the IC chip device 2.

[0035] In an embodiment, primary conductor bond wires 6 interconnect the primary conductor layer arrangement 19 to the primary conductor terminals 13. The IC chip device 2 comprises a semiconductor IC die 8 and the primary conductor layer arrangement 19. The IC die 8 has a first active side 9a and a second side 9b, at least the first active side 9a having active portions including electrical connection terminals 11 for connection to power and signal transmission conductors and a magnetic field sensor 12 arranged at or close to the surface of the first side. In the illustrated embodiment, the magnetic field sensor comprises a first magnetic field sensing portion 12a and a second magnetic field sensing portion 12b at a certain distance from the first magnetic field sensing portion. The two magnetic field sensing portions are configured for a differential measurement of the magnetic field. In this embodiment, the first magnetic field sensing portion is preferably surrounded on at least three sides by the primary conductor loops and the second magnetic field sensing portion is positioned adjacent an outer side of the primary conductor loops.

[0036] In other embodiments it is however possible to have a magnetic field sensor with only the first magnetic field sensing portion 12a.

[0037] The magnetic field sensing portion(s) may comprise a Hall effect sensor, or a giant magnetoresistive sensor or other forms of magnetic field sensors that are perse well known in the art.

[0038] The IC die 8 may for instance be in the form of a CMOS die although other types of semiconductor integrated circuit dies with magnetic field sensing portions perse known in the art may be used. The semi-conductor die does not need to be further described, such semiconductor dies with magnetic field sensing portions and connection terminals being per se well known in the art.

[0039] In a preferred embodiment the magnetic field sensing portions comprise Hall effect sensors and the IC die is a CMOS die.

[0040] The primary conductor layer arrangement 19 comprises one or more primary conductor loops 20 and a plurality of insulation layers in a stacked relationship on the active side 9a of the IC die 8. An insulation layer separates the one or more primary conductor loops from the IC die active side and an insulation layer covers the top side of the one or more primary conductor loops, and in embodiments with a plurality of primary conductor loops, insulation layers separate adjacent primary conductor loops.

[0041] In the illustrated embodiment there are three primary conductor loops, however in variants, there may be only one primary conductor loop, or two primary conductor loops, or four or primary conductor loops. Each primary conductor loop has a first connection end terminal 21 at one end of the loop and a second connection end terminal 22 at the other end of the loop. The connection end terminals are configured for connection to a primary conductor carrying the current to be measured. A primary current flowing in the primary conductor loop(s) generates a magnetic field that is measured by the magnetic field sensing portion(s) of the IC die 8. The primary conductor loop(s) may advantageously route around at central conductor free area in which at least one magnetic field sensing portion is arranged, such that the magnetic field in the central area of the primary conductor loop is concentrated through the magnetic field sensing portion.

[0042] For embodiments with more than one primary conductor loop, for instance with three primary conductor loops 20a, 20b, 20c as in the illustrated embodiment, the primary conductor loops are connected together in series, wherein a second connection end terminal 22a of the first primary conductor loop 20a is connected to a first connection end terminal 21 b of the second primary conductor loop 20b, and a second connection end terminal 22b of the second primary conductor loop 20b is connected to a first connection end terminal 21c of the third primary conductor loop 20c. The interconnections between the primary conductor loop ends may be with conductive vias 24 through the insulation layer 22 separating the primary conductor loops.

[0043] The connection end terminals 21 , 22 of the one or more primary conductor loops may comprise connection pad surfaces advantageously configured for wire bonding. The connection end terminals 21 , 22 of the one or more primary conductor loops may be advantageously arranged along an edge of the IC die 8.

[0044] In embodiments with a plurality of primary conductor loops, the number of loops through with the primary current flows is configurable by selecting primary conductor terminals 13 of the transducer to which the external primary conductor is connected.

[0045] The primary conductor loop connection end terminals 21 , 22 are connected to respective primary conductor terminals 13 by the primary conductor bond wires 6. In an embodiment with a plurality of primary conductor loops, for instance with three primary conductor loops 20a, 20b, 20c as in the illustrated embodiment, a first connection end terminal 21 a of the first primary conductor loop 20a is connected via bond wires to a first primary conductor terminal 13a. A second connection end terminal 22a of the first primary conductor loop 20a and a first connection end terminal 21b of the second primary conductor loop 20b is connected via bond wires to a second primary conductor terminal 13b. A second connection end terminal 22b of the second primary conductor loop 20b and a first connection end terminal 21c of the third primary conductor loop 20c is connected via bond wires to a third primary conductor terminal 13c. Finally, a second connection end terminal 22b of the third primary conductor loop 20c is connected via bond wires to a fourth primary conductor terminal 13d.

[0046] If a user wishes to have a configuration with only one primary conductor loop connected, the connection ends of the external primary conductor may be connected to the first and second primary conductor terminals 13a, 13b, or alternatively to the second and third primary conductor terminals 13c, 13c, or yet alternatively to the third and fourth primary conductor terminals 13c, 13d. If a user wishes to have a configuration with two primary conductor loops connected, the connection ends of the external primary conductor may be connected to the first and third primary conductor terminals 13a, 13c, or alternatively to the second and fourth primary conductor terminals 13b, 13d. If a user wishes to have a configuration with three primary conductor loops connected, the connection ends of the external primary conductor may be connected to the first and fourth primary conductor terminals 13a, 13d. Thus the transducer offers the possibility to easily configure the sensitivity and current measurement range by selecting the pair of primary conductor terminals of the electric current transducer to which the external primary conductor is connected.

[0047] In an advantageous embodiment, the material of the insulating layer comprises or consists of a polyimide material layer which has a high electrical breakdown resistance, excellent electrical insulation properties and can be manufactured with high accuracy in its thickness. Other insulating materials such as ceramics or glass may also be used.

[0048] The primary conductor loops and insulating layers may advantageously be made by a perse known redistribution layer (RDL) technology that is used in prior art IC chip devices to redistribute the connection terminals of the die for easier connection to a circuit board. In the present invention, this technology is advantageously used to form primary conductor loops on top of the active surface of the die very close to the magnetic field sensing portion(s) thereby enhancing the coupling between the magnetic field generated by a current to be measured flowing in the primary conductor loop and the magnetic field sensing portion on the semiconductor die. Moreover, with RDL technology, multiple layers may be formed on top of the die which may be used to form multiple primary conductor loops.

[0049] In the illustrated embodiment, the primary conductor terminals 13 have exposed contact surfaces 18 on a mounting side 10 of the IC chip configured for surface mount connection to conductive traces on an external circuit board. The other side of the primary conductor terminals 13 forms a wire bonding surface 17. In variants, the primary conductor terminals may have stamped and formed contact portions with various shapes and configurations, for instance that project below and outwardly from the IC chip housing lower surface 10, adapted for surface mount connection to circuit board conductive traces as perse known in the art.

[0050] The well known bonding wire connection technique allows to employ cost efficient manufacturing processes for interconnecting the primary conductor layer arrangement 19 to the primary conductor terminals 13, and cost efficient manufacturing process to form the secondary conductors and primary conductor terminals out of a lead frame, while ensuring positioning of the primary conductor in very close proximity to the magnetic field sensing portion of the IC chip, in an overall compact transducer arrangement.

[0051] In order to ensure that a high primary current may flow between the primary conductor terminals 13 and the connection end terminals 21 , 22 of the primary conductor loops 20, a plurality of bond wires 6 may be connected. This allows to use standard wire bond connection techniques yet have sufficient current carrying capacity for the primary conductor by simply increasing the number of bond wires 6. The number of wires can be changed based on the bond wire diameter and the intended current carrying capability of the transducer.

[0052] The secondary conductors 5 which serve to interconnect the IC chip 2 to power and signal connections of an external circuit to which the current transducer is intended to be connected, comprise a plurality of conductors formed from the lead frame arrangement as previously discussed, each secondary conductor comprising a connection portion 15 on one side and a surface mount connection terminal 16 on the other side. The surface mount connection terminal 16 may be for instance arranged in a row presenting contact pads intended for surface mount solder or welding connection, as per se known in the art, to circuit traces of an external circuit board. The surface mount connection terminals 16 are thus positioned proximate an outer edge of the transducer overmold housing 7, the IC connection side 15 being positioned proximate the IC chip 2 allowing bond wire connections between the IC chip 2 and the IC connection side 15 of the secondary conductors. In variants, the secondary conductor terminals may have stamped and formed contact portions with various shapes and configurations, for instance that project below and outwardly from the IC chip housing lower surface 10, adapted for surface mount connection to circuit board conductive traces as per se known in the art.

[0053] Bond wires 14 are connected between the IC connection side 15 of each secondary conductor 5 and connection terminals 11 on the active first side 9a of the IC chip 2. It may be noted that certain secondary conductors may have no connection to the IC chip, forming a redundant secondary conductor for use with semi-conductor chips with more connection portions. In other words, the number of connections depend on the functions incorporated in the IC chip. The lead frame conductor arrangement 3 may have a constant configuration, whereas the number of wire bond interconnections between the secondary conductors and IC die may depend on the configuration of the IC chip and desired functionalities to be incorporated in the transducer.

[0054] The lead frame may be plated with any suitable wire bondable layer in accordance with the bond wires used for the primary and secondary conductors.

[0055] The plurality of secondary conductors may include a grounded conductor (not shown) positioned below and overlapping the IC chip 2, whereby the IC chip is mounted on the grounded conductor separated therefrom by the insulating layer. The grounded conductor may serve either as a shielding conductor for electrical shielding of the IC chip device, or serve as a heat conductor to evacuate heat from the IC chip device, or both as an electrical shielding conductor and heat transfer conductor.

[0056] Example of manufacturing process

[0057] . 1. **Substrate Preparation:**

[0058] - Start with a substrate such as a silicon wafer or a package substrate with a plurality of IC dies.

[0059] - Apply a base insulation layer to isolate the copper RDL of the primary conductor loops from the IC dies.

[0060] - Deposit a thin adhesion layer (often titanium or tantalum) to enhance the bonding between the insulation and subsequent copper layers which form the primary conductor loop layers.

[0061] 2. **Seed Layer Deposition:**

[0062] - Deposit a thin copper seed layer on the adhesion layer using techniques like physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0063] - The seed layer provides a surface for better adhesion of the subsequent copper layers.

[0064] 3. **Polyimide (PI) Layer Deposition:**

[0065] - Apply a layer of liquid polyimide precursor onto the substrate.

[0066] - Use spin-coating to evenly distribute the precursor over the surface.

[0067] - Heat the coated substrate to cure the polyimide, forming the insulation layer.

[0068] - Repeat this process for each desired insulation layer on copper layer.

[0069] 4. **Photoresist Patterning and Via Formation:**

[0070] - Apply a layer of photoresist on top of the cured polyimide insulation layer.

[0071] - Expose the photoresist to UV light through a via mask to define the locations where vias (vertical interconnect access) are needed. - Develop the photoresist to create openings for vias in the polyimide insulation layer.

[0072] 5. **Via Etching and Seed Layer Deposition:**

[0073] - Etch through the exposed areas of the cured polyimide insulation layer to expose the underlying copper seed layer.

[0074] - Deposit a thin barrier layer (such as a layer of tantalum or titanium) followed by a copper seed layer within the via openings.

[0075] - This barrier layer prevents copper migration and enhances adhesion.

[0076] 6. **Copper Electroplating:**

[0077] - Electroplate copper into the via openings and over the cured polyimide insulation layer.

[0078] - Copper builds up both within the vias and on top of the polyimide insulation layer, forming the RDL traces that constitute the primary conductor loops.

[0079] 7. **Planarization:**

[0080] - Apply a chemical-mechanical planarization (CMP) process to remove excess copper on top of the polyimide insulation layer and achieve a flat surface.

[0081] 8. **Repeat for Multiple RDL Layers:**

[0082] - Repeat the steps above for each additional RDL layer required, with alternating layers of cured polyimide insulation layers and copper traces.

[0083] - Careful alignment is crucial to ensure proper connections between different RDL layers.

[0084] 9. **Top Passivation:**

[0085] - After the final RDL layer, deposit a protective passivation layer to insulate and protect the entire structure.

[0086] - This layer safeguards the RDL traces from environmental factors and potential damage.

[0087] List of references electric current transducer 1 integrated circuit chip device 2

[0088] IC die 8 first side (active side) 9a magnetic field sensing portion 12 first magnetic field sensing portion 12a second magnetic field sensing portion 12b connection terminals 11 second side 9b primary conductor layer arrangement 19 primary conductor loops 20 central conductor free area 23 first primary conductor loop 20a connection end terminals 21a, 22a second primary conductor loop 20b connection end terminals 21 b, 22b third primary conductor loop 20c connection end terminals 21c, 22c insulation layer 22 conductive via 24 primary conductor arrangement 4 primary conductor terminals 13 bonding surface 17 contact surface 18 primary conductor bond wires 6 primary conductor layer arrangement 19 (on IC die) primary conductor loops 20a, 20b, 20c secondary conductors 5

[0089] IC connection side 15 surface mount connection terminals 16 shield conductor secondary conductor bond wires 14 lead frame arrangement 3

[0090] Primary conductor terminals 13 secondary conductor terminals 5 overmold housing 7 mounting side 10

Claims

Claims1. Integrated circuit current transducer (1) comprising an integrated circuit (IC) chip device (2) and a lead frame arrangement (3) housed within an insulating overmold housing (7), the lead frame arrangement comprising a plurality of primary conductor terminals (13) and a secondary conductor arrangement (5), the IC chip device comprising a semiconductor IC die (8) having a first active side (9a) and a second side (9b), at least the first active side having active portions including electrical connection terminals (11) for connection to power and signal transmission conductors and a magnetic field sensor (12) arranged at or close to the surface of the active side, characterized in that the IC chip device further comprises a primary conductor layer arrangement (19) including a plurality of primary conductor loops (20) connected in series and a plurality of insulation layers in a stacked relationship formed directly on the first active side of the semiconductor IC die.

2. The current transducer according to claim 1 wherein each primary conductor loop has a first connection end terminal (21) at one end and a second connection end terminal (22) at another end, the connection end terminals configured for connection to a primary conductor carrying the current to be measured.

3. The current transducer according to any preceding claim wherein the primary conductor loops are connected in series by conductive vias (24) between ends of the primary conductor loops through the insulation layer separating the primary conductor loops.

4. The current transducer according to any preceding claim wherein the one or more primary conductor loops comprise a central conductor free area in which at least one magnetic field sensing portion of the magnetic field sensor is arranged.

5. The current transducer according to any preceding claim wherein the material of the insulation layer comprises or consists of a polyimide material layer.

6. The current transducer according to any preceding claim wherein connection end terminals (21 , 22) of the one or more primary conductor loops comprise connection pad surfaces configured for wire bonding.

7. The current transducer according to the preceding claim wherein the connection end terminals are arranged along an edge of the IC die.

8. The current transducer according to either of the two directly preceding claimswherein the primary conductor loop connection end terminals (21 , 22) are connected to respective primary conductor terminals (13) by primary conductor bond wires (6).

9. The current transducer according to the preceding claim wherein each primary conductor terminal is connected to respective connection end terminals (21 , 22) of the primary conductor loops by a plurality of bond wires.

10. The current transducer according to any preceding claim wherein there are three primary conductor loops (20a, 20b, 20c).11 . The current transducer according to the preceding claim wherein a first connection end terminal (21a) of a first said primary conductor loop (20a) is connected via bond wires to a first primary conductor terminal (13a), a second connection end terminal (22a) of the first primary conductor loop (20a) and a first connection end terminal (21b) of a second said primary conductor loop (20b) is connected via bond wires to a second primary conductor terminal (13b), a second connection end terminal (22b) of the second primary conductor loop (20b) and a first connection end terminal (21c) of a third primary said conductor loop (20c) is connected via bond wires to a third primary conductor terminal (13c), and a second connection end terminal (22b) of the third primary conductor loop (20c) is connected via bond wires to a fourth primary conductor terminal (13d).

12. The current transducer according to any preceding claim wherein the primary conductor loops and insulating layers are made by redistribution layer (RDL) technology.

13. The current transducer according to any preceding claim wherein the magnetic field sensor comprises a first magnetic field sensing portion (12a) and a second magnetic field sensing portion (12b) at a certain distance from the first magnetic field sensing portion configured for a differential measurement of the magnetic field generated by the primary conductor loops.

14. The current transducer according to the preceding claim wherein the first magnetic field sensing portion is surrounded on at least three sides by the primary conductor loops and the second magnetic field sensing portion is positioned adjacent an outer side of the primary conductor loops.

15. The current transducer according to any preceding claim wherein the magnetic field sensing portion(s) comprise Hall effect sensor(s) and the IC die is a CMOS die.

16. Integrated circuit current transducer (1) comprising an integrated circuit (IC) chip device (2) and a lead frame arrangement (3) housed within an insulating overmold housing (7), the lead frame arrangement comprising a plurality of primary conductor terminals (13) and a secondary conductor arrangement (5), the IC chip device comprising a semiconductor IC die (8) having a first active side (9a) and a second side (9b), at least the first active side having active portions including electrical connection terminals (11) for connection to power and signal transmission conductors and a magnetic field sensor (12) arranged at or close to the surface of the active side, characterized in that the IC chip device further comprises a primary conductor layer arrangement (19) including a plurality of primary conductor loops (20) connected in series and a plurality of insulation layers in a stacked relationship formed directly on the first active side of the semiconductor IC die, wherein the magnetic field sensor comprises a first magnetic field sensing portion (12a) and a second magnetic field sensing portion (12b) at a certain distance from the first magnetic field sensing portion configured for a differential measurement of the magnetic field generated by the primary conductor loops, and wherein the first magnetic field sensing portion is surrounded on at least three sides by the primary conductor loops and the second magnetic field sensing portion is positioned adjacent an outer side of the primary conductor loops.

17. The current transducer according to the preceding claim wherein the first magnetic field sensing portion is surrounded on at least three sides by the primary conductor loops and the second magnetic field sensing portion is positioned adjacent an outer side of the primary conductor loops.

18. The current transducer according to claim 16 or 17 wherein each primary conductor loop has a first connection end terminal (21) at one end and a second connection end terminal (22) at another end, the connection end terminals configured for connection to a primary conductor carrying the current to be measured.

19. The current transducer according to any preceding claim 16-18 wherein the primary conductor loops are connected in series by conductive vias (24) between ends of the primary conductor loops through the insulation layer separating the primary conductor loops.

20. The current transducer according to any preceding claim 16-19 wherein the one or more primary conductor loops comprise a central conductor free area in which at least one magnetic field sensing portion of the magnetic field sensor is arranged.21 . The current transducer according to any preceding claim 16-20 wherein the material of the insulation layer comprises or consists of a polyimide material layer.

22. The current transducer according to any preceding claim 16-21 wherein connection end terminals (21 , 22) of the one or more primary conductor loops comprise connection pad surfaces configured for wire bonding.

23. The current transducer according to the preceding claim wherein the connection end terminals are arranged along an edge of the IC die.

24. The current transducer according to either of the two directly preceding claims wherein the primary conductor loop connection end terminals (21 , 22) are connected to respective primary conductor terminals (13) by primary conductor bond wires (6).

25. The current transducer according to the preceding claim wherein each primary conductor terminal is connected to respective connection end terminals (21 , 22) of the primary conductor loops by a plurality of bond wires.

26. The current transducer according to any preceding claim 16-25 wherein there are three primary conductor loops (20a, 20b, 20c).

27. The current transducer according to the preceding claim wherein a first connection end terminal (21a) of a first said primary conductor loop (20a) is connected via bond wires to a first primary conductor terminal (13a), a second connection end terminal (22a) of the first primary conductor loop (20a) and a first connection end terminal (21b) of a second said primary conductor loop (20b) is connected via bond wires to a second primary conductor terminal (13b), a second connection end terminal (22b) of the second primary conductor loop (20b) and a first connection end terminal (21c) of a third primary said conductor loop (20c) is connected via bond wires to a third primary conductor terminal (13c), and a second connection end terminal (22b) of the third primary conductor loop (20c) is connected via bond wires to a fourth primary conductor terminal (13d).

28. The current transducer according to any preceding claim 16-27 wherein the primary conductor loops and insulating layers are made by redistribution layer (RDL) technology.

29. The current transducer according to any preceding claim 16-28 wherein the magnetic field sensing portion(s) comprise Hall effect sensor(s) and the IC die is a CMOS die.

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