Semiconductor device

Abstract

The present invention improves the reliability of a semiconductor device. A semiconductor device according to an embodiment comprises: at least one or more first transistors and at least one or more second transistors each having a first end connected to a first node and a second end connected to a second node; at least one or more third transistors and at least one or more fourth transistors each having a first end connected to the second node and a second end connected to a third node; a fifth transistor provided between a gate end of the at least one or more first transistors and the second node; a sixth transistor provided between a gate end of the at least one or more second transistors and the second node; a seventh transistor provided between a gate end of the at least one or more third transistors and the third node; and an eighth transistor provided between a gate end of the at least one or more fourth transistors and the third node.

Description

Semiconductor Devices

[0001] The embodiments relate to a semiconductor device.

[0002] A power module is known as a semiconductor device that achieves high output. A power module is configured as a single package in which a plurality of power semiconductor elements are mounted.

[0003] Japanese Patent No. 7157046

[0004] The reliability of the semiconductor device is improved.

[0005] The semiconductor device according to the embodiment includes at least one or more first transistors and at least one or more second transistors, each having a first end connected to a first node and a second end connected to a second node; at least one or more third transistors and at least one or more fourth transistors, each having a first end connected to the second node and a second end connected to a third node; a fifth transistor provided corresponding to the at least one or more first transistors, having a first end connected to a gate terminal of the at least one or more first transistors and a second end connected to the second node; a sixth transistor provided corresponding to the at least one second transistor and having a first end connected to a gate terminal of the at least one second transistor and a second end connected to the second node; a seventh transistor provided corresponding to the at least one third transistor and having a first end connected to a gate terminal of the at least one third transistor and a second end connected to the third node; and an eighth transistor provided corresponding to the at least one fourth transistor and having a first end connected to a gate terminal of the at least one fourth transistor and a second end connected to the third node.

[0006] FIG. 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor device according to an embodiment. FIG. 2 is a plan view showing the configuration of the semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2, showing an example of a cross-sectional structure of the semiconductor device according to an embodiment. FIG. 4 is a plan view showing the configuration of a semiconductor device according to a first modified example. FIG. 5 is a plan view showing the configuration of a semiconductor device according to a second modified example. FIG. 6 is a plan view showing the configuration of a semiconductor device according to a third modified example. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of a cross-sectional structure of the semiconductor device according to the third modified example. FIG. 8 is a plan view showing the configuration of a semiconductor device according to a fourth modified example. Embodiment

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and proportions of the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are designated by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0008] 1. Embodiment A semiconductor device according to an embodiment will be described.

[0009] The semiconductor device according to the embodiment is a power module, and is applied to, for example, a power conversion device for a railway vehicle, or industrial equipment for a renewable energy power generation system.

[0010] The configuration of the semiconductor device according to the embodiment will be described.

[0011] The circuit configuration of a semiconductor device according to an embodiment will be described with reference to FIG. 1 . FIG. 1 is a circuit diagram showing an example of the circuit configuration of a semiconductor device according to an embodiment. In the example of FIG. 1 , a semiconductor device 1 includes multiple transistors TU, TL, TCU, and TCL as internal semiconductor elements. In the following description, when the multiple transistors TU, TL, TCU, and TCL are not to be distinguished from one another, each of the multiple transistors TU, TL, TCU, and TCL will also be simply referred to as a transistor T.

[0012] The multiple transistors T are MOS (Metal-Oxide-Semiconductor) transistors. The multiple transistors T are n-type transistors. Each transistor T is, for example, a transistor selected from a MOS transistor using silicon carbide (SiC), a MOS transistor using silicon (Si), and a transistor using gallium nitride (GaN). Note that each transistor T may be, for example, an IGBT (Insulated-Gate Bipolar Transistor). The drain-source breakdown voltage of each of the multiple transistors TCU and TCL is, for example, higher than the gate-source breakdown voltage of each of the multiple transistors TU and TL. The drain-source breakdown voltage of each of the multiple transistors TCU and TCL is, for example, approximately 30 V. Note that in this embodiment, the number of transistors TU, the number of transistors TL, the number of transistors TCU, and the number of transistors TCL are each two or more. In FIG. 1, the circuit configuration is simplified, and only one of each of the plurality of transistors TU, TL, TCU, and TCL is shown.

[0013] The plurality of transistors TU are connected in parallel between a node P and a node AC (Alternating Current). The node P is an input terminal of the semiconductor device 1. In the circuit configuration of the semiconductor device 1, the node P has, for example, positive polarity. The node AC is an output terminal of the semiconductor device 1. Note that the node AC is connected to a monitor terminal, as will be described later. Each transistor TU has a drain terminal connected to the node P, a source terminal connected to the node AC, and a gate terminal connected to a node GU. The node GU is a control terminal. In the following description, each transistor TU will also be referred to as an upper semiconductor element.

[0014] Each of the plurality of transistors TCU is connected between the gate terminals of the plurality of transistors TU and the source terminals of the plurality of transistors TU. More specifically, each transistor TCU has a drain terminal connected to the gate terminals (node ​​GU) of the plurality of transistors TU, a source terminal connected to the source terminals (node ​​AC) of the plurality of transistors TU, and a gate terminal connected to a node GCU. The node GCU is a control terminal. In the following description, each transistor TCU is also referred to as an upper clamp element.

[0015] The plurality of transistors TL are connected in parallel between a node AC and a node N. The node N is an input terminal of the semiconductor device 1. In the circuit configuration of the semiconductor device 1, the node N has, for example, negative polarity. As will be described later, the node N is connected to a monitor terminal different from the monitor terminal connected to the node AC. Each transistor TL has a drain terminal connected to the node AC, a source terminal connected to the node N, and a gate terminal connected to a node GL. The node GL is a control terminal. In the following description, each transistor TL will also be referred to as a lower semiconductor element.

[0016] Each of the plurality of transistors TCL is connected between the gate terminals of the plurality of transistors TL and the source terminals of the plurality of transistors TL. More specifically, each transistor TCL has a drain terminal connected to the gate terminals (node ​​GL) of the plurality of transistors TL, a source terminal connected to the source terminals (node ​​N) of the plurality of transistors TL, and a gate terminal connected to a node GCL. The node GCL is a control terminal. In the following description, each transistor TCL is also referred to as a lower clamp element.

[0017] With the above configuration, the semiconductor elements inside the semiconductor device 1 can be controlled by a voltage supplied from outside the semiconductor device 1. For example, different signals are input from the outside to the nodes GU, GL, GCU, and GCL, respectively.

[0018] More specifically, when transistor TU is turned on and transistor TL is turned off, for example, an "H (High)" level signal is supplied to nodes GU and GCL, and an "L (Low)" level signal is supplied to nodes GL and GCU. Also, when transistor TU is turned off and transistor TL is turned on, for example, an "L" level signal is supplied to nodes GU and GCL, and an "H" level signal is supplied to nodes GL and GCU.

[0019] Next, the structure of the semiconductor device 1 according to the embodiment will be described.

[0020] First, the planar structure of the semiconductor device 1 according to the embodiment will be described with reference to Fig. 2. Fig. 2 is a plan view showing the configuration of the semiconductor device according to the embodiment.

[0021] The semiconductor device 1 further includes an insulating member 10, and conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36. The semiconductor device 1 also includes a base substrate, which is not shown in FIG.

[0022] The insulating member 10 is provided on a base substrate. The base substrate is a support having a flat portion. The base substrate includes, for example, copper or ceramics. The insulating member 10 includes, for example, resin or ceramics. The resin is, for example, polyphenylene sulfide (PPS). Note that, hereinafter, the structure of the semiconductor device 1 will be described using an X direction in a plane parallel to the top surfaces of the base substrate and the insulating member 10, a Y direction orthogonal to the X direction in the plane, and a Z direction perpendicular to the plane.

[0023] The conductors 21, 22, 23, 24, and 25 are provided on the insulating member 10. The conductors 21, 22, 23, 24, and 25 are provided spaced apart from one another. Each of the conductors 21, 22, 23, 24, and 25 has a portion extending along the X direction, for example. The portion of the conductor 22 extending along the X direction, the portion of the conductor 21 extending along the X direction, the portion of the conductor 23 extending along the X direction, the portion of the conductor 24 extending along the X direction, and the portion of the conductor 25 extending along the X direction are arranged, for example, in this order, along the Y direction. In the following description, of the portions of the conductors 22 and 25 extending in the X direction, the side on which the portion of the conductor 22 extending in the X direction is located will be referred to as one end side in the Y direction. Furthermore, of the portions of the conductors 22 and 25 extending in the X direction, the side on which the portion of the conductor 25 extending in the X direction is located is referred to as the other end side in the Y direction. The conductors 21, 23, and 24 each further have a portion extending in the Y direction. The portion of the conductor 23 extending in the Y direction and the portions of the conductors 21 and 24 extending in the Y direction are located at different ends along the X direction. In the following description, of the portions of the conductors 21, 23, and 24 extending in the Y direction, the side on which the portion of the conductor 23 extending in the Y direction is located is referred to as one end side in the X direction. Furthermore, of the portions of the conductors 21, 23, and 24 extending in the Y direction, the side on which the portions of the conductors 21 and 24 extending in the Y direction are located is referred to as the other end side in the X direction.

[0024] A plurality of transistors TU are arranged in the X direction on the upper surface of the portion of the conductor 21 extending along the X direction. The plurality of transistors TU are arranged, for example, at approximately equal intervals in the X direction. FIG. 2 shows an example in which nine transistors TU are arranged. Hereinafter, each of the three transistors TU at one end of the nine transistors TU in the X direction will also be referred to as transistor TU1. Of the six transistors TU excluding the three transistors TU1, each of the three transistors TU at one end of the X direction will also be referred to as transistor TU2. Of the nine transistors TU, each of the three transistors TU at the other end of the X direction will also be referred to as transistor TU3. The drain terminal of each transistor TU is provided on the lower surface of the transistor TU. The source terminal and gate terminal of each transistor TU are provided on the upper surface of the transistor TU. The drain terminal of each transistor TU is electrically connected to the conductor 21. The source terminal of each transistor TU is electrically connected to the conductor 23 via a wire. The gate terminal of each transistor TU is electrically connected to the conductor 22 via a wire.

[0025] 2 and the following description, the semiconductor device 1 includes three transistors TU1, three transistors TU2, and three transistors TU3, but is not limited to this. The number of transistors TU1, the number of transistors TU2, and the number of transistors TU3 may each be one, two, or four or more.

[0026] A plurality of transistors TCU are arranged side by side in the X direction on the upper surface of the portion of the conductor 22 extending along the X direction. The plurality of transistors TCU are arranged, for example, at substantially equal intervals in the X direction. FIG. 2 shows an example in which three transistors TCU are arranged side by side. Hereinafter, the three transistors TCU are also referred to as transistors TCU1, TCU2, and TCU3, respectively, from one end to the other end in the X direction. Transistors TCU1, TCU2, and TCU3 correspond to transistors TU1, TU2, and TU3, respectively. The drain terminal of each transistor TCU is provided on the lower surface of the transistor TCU. The source terminal and gate terminal of each transistor TCU are provided on the upper surface of the transistor TCU. The drain terminal of each transistor TCU is electrically connected to the conductor 22. The gate terminal of each transistor TCU is connected to node GCU. The source terminal of transistor TCU1 is electrically connected to the source terminal of each transistor TU1 via a wire. The source terminal of transistor TCU2 is electrically connected to the source terminal of each transistor TU2 via a wire. The source terminal of transistor TCU3 is electrically connected to the source terminal of each transistor TU3 via a wire.

[0027] The plurality of transistors TCU are arranged so as to reduce variation in the length of the wires electrically connecting the source terminal of each transistor TCU to the source terminal of the transistor TU corresponding to that transistor TCU. For example, the plurality of transistors TCU are arranged so that the average length along the extension direction of the wires connecting the source terminal of each transistor TCU to the source terminals of the plurality of transistors TU corresponding to that transistor TCU is approximately equal.

[0028] 2 and the following description, the semiconductor device 1 includes three transistors TCU, but this is not limiting. The number of transistors TCU may be two, or four or more. Each transistor TCU is required to be electrically connected to the source terminal of at least one transistor TU among the plurality of transistors TU.

[0029] A plurality of transistors TL are arranged in the X direction on the upper surface of the portion of the conductor 23 extending along the X direction. The plurality of transistors TL are arranged, for example, at approximately equal intervals in the X direction. FIG. 2 shows an example in which nine transistors TL are arranged. Hereinafter, each of the three transistors TL at one end of the nine transistors TL in the X direction will also be referred to as transistor TL1. Furthermore, each of the three transistors TL at one end of the six transistors TL excluding the three transistors TL1 in the X direction will also be referred to as transistor TL2. Furthermore, each of the three transistors TL at the other end of the nine transistors TL in the X direction will also be referred to as transistor TL3. The drain terminal of each transistor TL is provided on the lower surface of the transistor TL. The source terminal and gate terminal of each transistor TL are provided on the upper surface of the transistor TL. The drain terminal of each transistor TL is electrically connected to the conductor 23. The source terminal of each transistor TL is electrically connected to the conductor 24 via a wire. The gate terminal of each transistor TL is electrically connected to the conductor 25 via a wire.

[0030] 2 and the following description, the semiconductor device 1 includes three transistors TL1, three transistors TL2, and three transistors TL3, but is not limited to this. The number of transistors TL1, the number of transistors TL2, and the number of transistors TL3 may be one, two, or four or more.

[0031] A plurality of transistors TCL are arranged side by side in the X direction on the upper surface of the portion of the conductor 25 extending along the X direction. The plurality of transistors TCL are arranged, for example, at approximately equal intervals in the X direction. FIG. 2 shows an example in which three transistors TCL are arranged side by side. Hereinafter, the three transistors TCL will also be referred to as transistors TCL1, TCL2, and TCL3, respectively, from one end to the other end in the X direction. The transistors TCL1, TCL2, and TCL3 correspond to transistors TL1, TL2, and TL3, respectively. The drain terminal of each transistor TCL is provided on the lower surface of the transistor TCL. The source terminal and gate terminal of each transistor TCL are provided on the upper surface of the transistor TCL. The drain terminal of each transistor TCL is electrically connected to the conductor 25. The gate terminal of each transistor TCL is connected to a node GCL. The source terminal of transistor TCL1 is electrically connected to the source terminal of each transistor TL1 via a wire, the source terminal of transistor TCL2 is electrically connected to the source terminal of each transistor TL2 via a wire, and the source terminal of transistor TCL3 is electrically connected to the source terminal of each transistor TL3 via a wire.

[0032] The plurality of transistors TCL are arranged so as to minimize variations in the length of the wires electrically connecting the source terminal of each transistor TCL to the source terminal of the transistor TL corresponding to that transistor TCL. For example, the plurality of transistors TCL are arranged so that the average length along the extension direction of the wires connecting the source terminal of each transistor TCL to the source terminals of the plurality of transistors TL corresponding to that transistor TCL is approximately equal.

[0033] 2 and the following description, the semiconductor device 1 includes three transistors TCL, but this is not limiting. The number of transistors TCL may be two, or four or more. Each transistor TCL is required to be electrically connected to the source terminal of at least one transistor TL among the plurality of transistors TL.

[0034] In the embodiment, the transistors TU and TL are arranged so that the configuration of each transistor TU is similar to the configuration of each transistor TL when viewed from above. More specifically, the gate terminal of each transistor TU is arranged, for example, closer to one end in the Y direction than the source terminal of the transistor TU. The gate terminal of each transistor TL is also arranged, for example, closer to one end in the Y direction than the source terminal of the transistor TL.

[0035] The other end of the conductor 26 along the X direction is electrically connected to the portion of the conductor 21 that extends in the Y direction. The conductor 26 functions as a node P. In other words, the conductor 26 is a positive input terminal.

[0036] The other end of the conductor 27 along the X direction is electrically connected to the portion of the conductor 24 extending in the Y direction. The conductor 27 functions as a node N. That is, the conductor 27 is a negative polarity input terminal.

[0037] The conductors 28a and 28b are electrically connected at one end in the X direction to a portion of the conductor 23 that extends in the Y direction. The conductors 28a and 28b function as a node AC. That is, the conductors 28a and 28b are output terminals.

[0038] The conductors 31, 32, 33, 34, 35, and 36 are provided on the insulating member 10, similar to the conductors 21, 22, 23, 24, and 25. The conductor 31 is electrically connected to the conductor 22 via a wire. The conductor 31 functions as a node GU. That is, the conductor 31 corresponds to the control terminals of the plurality of transistors TU. The conductor 32 is electrically connected to the conductor 23 via a wire. The conductor 32 functions as a monitor terminal SSH connected to the node AC. The conductor 33 is electrically connected to the conductor 25 via a wire. The conductor 33 functions as a node GL. That is, the conductor 33 corresponds to the control terminals of the plurality of transistors TL. The conductor 34 is electrically connected to the conductor 24 via a wire. The conductor 34 functions as a monitor terminal SSL connected to the node N. The conductor 35 is electrically connected to the gate terminals of the plurality of transistors TCU, respectively, via a wire. The conductor 36 is electrically connected to the gate terminals of the plurality of transistors TCL via wires.

[0039] Next, the cross-sectional structure of the semiconductor device 1 according to the embodiment will be described with reference to Fig. 3. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 2, showing an example of the cross-sectional structure of the semiconductor device according to the embodiment.

[0040] The semiconductor device 1 further includes, for example, a heat dissipation member HS.

[0041] The heat dissipation member HS is a heat sink. The heat dissipation member HS is provided, for example, entirely on the lower surface of the base substrate B used as the support body described above. The heat dissipation member HS has a relatively large surface area due to the unevenness of the lower surface. The heat dissipation member HS includes, for example, copper or ceramics. The heat dissipation member HS may be formed integrally with the base substrate B.

[0042] Each transistor TU is provided on the upper surface of the conductor 21 via an adhesive member 41. The adhesive member 41 physically and electrically connects the drain terminal of each transistor TU to the conductor 21.

[0043] Each transistor TCU is provided on the upper surface of the conductor 22 via an adhesive member 43. The adhesive member 43 physically and electrically connects the drain end of each transistor TCU to the conductor 22.

[0044] Each transistor TL is provided on the upper surface of the conductor 23 via an adhesive member 42. The adhesive member 42 physically and electrically connects the drain terminal of each transistor TL to the conductor 23.

[0045] Each transistor TCL is provided on the upper surface of the conductor 25 via an adhesive member 44. The adhesive member 44 physically and electrically connects the drain terminal of each transistor TCL to the conductor 25.

[0046] According to the embodiment, it is possible to improve the reliability of the semiconductor device 1. Hereinafter, the improvement in reliability of the semiconductor device 1 according to the embodiment will be described.

[0047] In the semiconductor device 1 according to the embodiment, the source terminal of transistor TCU1 is electrically connected to the source terminal of one or more transistors TU1. The source terminal of transistor TCU2 is electrically connected to the source terminal of one or more transistors TU2. The source terminal of transistor TCL1 is electrically connected to the source terminal of one or more transistors TL1. The source terminal of transistor TCL2 is electrically connected to the source terminal of one or more transistors TL2. This configuration can suppress an increase in impedance in the wiring between the gate and source terminals of the upper semiconductor element via the upper clamp element and in the wiring between the gate and source terminals of the lower semiconductor element via the lower clamp element, compared to a semiconductor device including only one upper clamp element and one lower clamp element. This can improve the effect of suppressing malfunctions.

[0048] Additionally, in a semiconductor device including an upper semiconductor element and a lower semiconductor element, when one of the two semiconductor elements is turned on, a transient gate current may flow through the other semiconductor element, causing a rise in the gate terminal voltage of the other semiconductor element. As a result, when controlling only one semiconductor element to be turned on, the other semiconductor element may also be turned on. In such a case, to suppress the rise in the gate terminal voltage, for example, one upper clamp element and one lower clamp element are provided in each of the upper and lower semiconductor elements. The source terminal of one upper clamp element is electrically connected to each of the source terminals of all the upper semiconductor elements. Furthermore, the source terminal of one lower clamp element is electrically connected to each of the source terminals of all the lower semiconductor elements. In such a case (comparative example), for example, as the number of semiconductor elements increases, the length of the wiring between the upper clamp element and the upper semiconductor element and the length of the wiring between the lower clamp element and the lower semiconductor element may become longer. This increases the impedance of the wiring between the gate and source terminals of the upper semiconductor element and the wiring between the gate and source terminals of the lower semiconductor element, thereby reducing the effect of the clamp element in suppressing the voltage rise at the gate terminal.

[0049] According to the embodiment, the semiconductor device 1 includes a plurality of transistors TCU and a plurality of transistors TCL. This makes it possible to suppress an increase in the length of the wiring between the upper clamp element and the upper semiconductor element, and the length of the wiring between the lower clamp element and the lower semiconductor element. That is, by distributing the plurality of transistors TCU and the plurality of transistors TCL, it is possible to suppress an increase in the length of the wiring in each of the transistors TCU and TCL. Therefore, it is possible to suppress an increase in impedance of the wiring between the gate terminal and the source terminal of the upper semiconductor element and the wiring between the gate terminal and the source terminal of the lower semiconductor element via the clamp element.

[0050] Furthermore, according to the embodiment, an increase in the size of the semiconductor device 1 can be suppressed compared to the comparative example. Additionally, according to the embodiment, compared to the comparative example, the number of upper clamp elements relative to the number of upper semiconductor elements and the number of lower clamp elements relative to the number of lower semiconductor elements can be increased. This makes it possible to suppress an increase in the on-resistance of each of the upper clamp elements and the lower clamp elements. Therefore, compared to the comparative example, an increase in the size of each of the upper clamp elements and the lower clamp elements can be suppressed. Therefore, an increase in the size of the semiconductor device 1 is suppressed.

[0051] 2. Modifications Next, a semiconductor device according to a modification will be described. In the following, the description of the same configuration as the embodiment will be omitted, and the configuration different from the embodiment will be mainly described.

[0052] 2.1 First Modification In the embodiment, an example has been shown in which the multiple transistors TU and TL are arranged so that the configuration of each transistor TU and the configuration of each transistor TL are similar when viewed from above, but this is not limiting. The multiple transistors TU and TL may be arranged so that the configuration within each transistor TU and the configuration within each transistor TL are symmetrical in the Y direction.

[0053] The configuration of the semiconductor device 1 according to the first modification will be described with reference to Fig. 4. Fig. 4 is a plan view showing the configuration of the semiconductor device according to the first modification. Note that the configurations of the plurality of transistors TU, TL, TCU, and TCL, the insulating member 10, and the conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36 according to the first modification are the same as those according to the embodiment, except for the configuration of each transistor TL.

[0054] 4, in the first modification, the gate terminal of each transistor TL is disposed, for example, on the other end side in the Y direction than the source terminal of the transistor TL. As a result, the source terminal and gate terminal of each transistor TU and the source terminal and gate terminal of each transistor TL are disposed symmetrically in the Y direction.

[0055] The first modified example also achieves the same effects as the embodiment.

[0056] 2.2 Second Modification In the embodiment and the first modification, an example has been shown in which the source terminal of the transistor TCL is directly connected to the source terminal of the transistor TL, but this is not limiting. The source terminal of the transistor TCL and the source terminal of the transistor TL may be indirectly connected via a conductor.

[0057] The configuration of the semiconductor device 1 according to the second modification will be described with reference to Fig. 5. Fig. 5 is a plan view showing the configuration of the semiconductor device according to the second modification. Note that the configurations of the plurality of transistors TU, TL, TCU, and TCL, the insulating member 10, and the conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36 according to the second modification are the same as those according to the embodiment, except for the connection between the source terminal of the transistor TCL and the source terminal of the transistor TL.

[0058] 5 , in the second modification, the source terminal of each transistor TCL is connected by a wire to the conductor 24. As a result, the source terminal of the transistor TCL is indirectly connected to the source terminal of the transistor TL via the wire and the conductor 24.

[0059] The lengths or average values ​​of the wires connecting each of the plurality of transistors TCL to the conductor 24 are approximately equal.

[0060] The second modification also achieves the same effects as the embodiment and the first modification.

[0061] 2.3 Third Modification In the embodiment, the first modification, and the second modification, the cases where the plurality of transistors TCU and TCL are each vertical transistors have been described, but this is not limited thereto. The semiconductor device may also have the plurality of transistors TCU and TCL each horizontal transistor. Below, the configuration of the semiconductor device according to the third modification will be described, focusing on the differences from the semiconductor devices according to the embodiment, the first modification, and the second modification.

[0062] The configuration of the semiconductor device 1 according to the third modification will be described with reference to Fig. 6 and Fig. 7. Fig. 6 is a plan view showing the configuration of the semiconductor device according to the third modification. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6, showing an example of the cross-sectional structure of the semiconductor device according to the third modification.

[0063] The configurations of the plurality of transistors TU and TL, the insulating member 10, and the conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36 according to the third modification are the same as those according to the embodiment. In the following, the configuration of the plurality of transistors TCU and TCL will be mainly described.

[0064] The transistors TCU and TCL in the third modification are horizontal transistors. That is, the source, drain, and gate of each of the transistors TCU and TCL are provided on the upper surface of the transistor. The drain of each transistor TCU is connected to the conductor 22 by, for example, a wire. The drain of each transistor TCL is connected to the conductor 25 by, for example, a wire.

[0065] 7, each transistor TCU is provided on the upper surface of the conductor 22 via an adhesive member 51. The adhesive member 51 is an insulator that physically connects the lower surface of each transistor TCU to the conductor 22.

[0066] Each transistor TCU is provided on the upper surface of the conductor 25 via an adhesive member 52. The adhesive member 52 is an insulator that physically and electrically connects the drain end of each transistor TCU to the conductor 25.

[0067] The third modification also achieves the same effects as the embodiment, the first modification, and the second modification.

[0068] 2.4 Fourth Modification In the third modification, the transistors TCU and TCL are mounted on conductors via an insulator, but this is not limiting. Instead of the insulator, the transistors TCU and TCL may be mounted via an adhesive material similar to that used for the transistors TU and TL.

[0069] The configurations of the plurality of transistors TU, TL, TCU, and TCL, the insulating member 10, and the conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36 according to the fourth modification are the same as those according to the third modification, except for the arrangement of the plurality of TCUs and TCLs. The arrangement of the plurality of TCUs and TCLs will be mainly described below.

[0070] In the fourth modified example, the plurality of transistors TCU are provided on the upper surface of the conductor 23. The plurality of transistors TCL are provided on the upper surface of the conductor 24. Although not shown, the plurality of transistors TCU and TCL are mounted on the upper surfaces of the conductors 23 and 24 via adhesive members similar to the adhesive members 41 to 44 in the embodiment. The lower surface of each of the plurality of transistors TCU is at the same potential as the source terminal of the transistor TU or is an insulator. The lower surface of each of the plurality of transistors TCL is at the same potential as the source terminal of the transistor TL or is an insulator.

[0071] The fourth modification also achieves the same effects as the embodiment, the first modification, the second modification, and the third modification.

[0072] Furthermore, according to the fourth modification, the plurality of transistors TCU are mounted on the upper surface of the conductor 23 connected to the node AC and the source terminals of the plurality of transistors TU, and the plurality of transistors TCL are mounted on the upper surface of the conductor 24 connected to the node N and the source terminals of the plurality of transistors TL, thereby making it possible to mount the transistors on the upper surfaces of the conductors without using an insulator as an adhesive member, thereby preventing the manufacturing process from becoming complicated.

[0073] 3. Others In the above-described embodiment, first modification, second modification, third modification, and fourth modification, the number of wires connecting one component to another component may be one or more, and the number of wires is not limited. Furthermore, the wires included in the semiconductor device 1 according to the embodiment, first modification, second modification, third modification, and fourth modification may be replaced with other conductors. For example, the wires in the embodiment, first modification, second modification, third modification, and fourth modification may be replaced with conductors such as ribbons and lead frames.

[0074] In addition, in the second, third, and fourth modified examples, as in the embodiment, examples have been shown in which the configuration of each transistor TU and the configuration of each transistor TL are similar when viewed from above, but this is not limited to this. Although not shown, in the second, third, and fourth modified examples, as in the first modified example, the source terminal and gate terminal of each transistor TU and the source terminal and gate terminal of each transistor TL may be arranged symmetrically in the Y direction.

[0075] Furthermore, in the first, third, and fourth modified examples, as in the embodiment, an example has been shown in which the source terminal of each transistor TCL is directly connected to the source terminal of the transistor TL via a wire, but this is not limited to this. Although not shown, in the first, third, and fourth modified examples, the source terminal of each transistor TCL may be indirectly connected via the conductor 24, as in the second modified example. That is, the source terminal of each transistor TCL may be connected to the source terminal of the transistor TL by being connected to the conductor 24 via a wire.

[0076] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims.

Claims

1. at least one or more first transistors and at least one or more second transistors, each having a first end connected to a first node and a second end connected to a second node; at least one or more third transistors and at least one or more fourth transistors, each having a first end connected to the second node and a second end connected to a third node; a fifth transistor provided corresponding to the at least one or more first transistors, and having a first end connected to a gate terminal of the at least one or more first transistors and a second end connected to the second node; a sixth transistor provided corresponding to the at least one or more second transistors, and having a first end connected to a gate terminal of the at least one or more second transistors and a second end connected to the second node; and a seventh transistor provided corresponding to the at least one or more third transistors, and having a first end connected to a gate terminal of the at least one or more third transistors and a second end connected to the third node. an eighth transistor provided corresponding to the at least one or more fourth transistors, the eighth transistor having a first terminal connected to a gate terminal of the at least one or more fourth transistors and a second terminal connected to the third node.

2. The semiconductor device according to claim 1, wherein the semiconductor device includes a plurality of each of the at least one or more first transistors and the at least one or more second transistors.

3. The semiconductor device according to claim 2, wherein the second end of the fifth transistor is electrically connected to the second end of each of the at least one or more first transistors via a plurality of first conductors, and the second end of the sixth transistor is electrically connected to the second end of each of the at least one or more second transistors via a plurality of second conductors.

4. The semiconductor device according to claim 3, wherein an average length of said plurality of first conductors and an average length of said plurality of second conductors are substantially equal to each other.

5. The semiconductor device according to claim 3, wherein each of the plurality of first conductors and the plurality of second conductors is a wire, a ribbon, or a lead frame.

6. The semiconductor device according to claim 1, wherein the semiconductor device includes a plurality of the at least one or more third transistors and a plurality of the at least one or more fourth transistors.

7. The semiconductor device according to claim 6, wherein the second end of the seventh transistor is electrically connected to the second end of each of the at least one or more third transistors via a plurality of first conductors, and the second end of the eighth transistor is electrically connected to the second end of each of the at least one or more fourth transistors via a plurality of second conductors.

8. The semiconductor device according to claim 7, wherein an average length of said plurality of first conductors and an average length of said plurality of second conductors are substantially equal to each other.

9. The semiconductor device according to claim 1, wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a MOS transistor using silicon carbide (SiC), a MOS transistor using silicon (Si), an IGBT using silicon carbide (SiC), an IGBT using silicon (Si), or a transistor using gallium nitride (GaN).

10. The semiconductor device according to claim 1, wherein each of the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor is a MOS transistor using silicon (Si) or a transistor using gallium nitride (GaN), and is a vertical transistor or a horizontal transistor.

11. The semiconductor device according to claim 1, wherein a gate terminal of each of the at least one or more first transistors and a gate terminal of each of the at least one or more second transistors are connected to a fourth node, and a gate terminal of each of the at least one or more third transistors and a gate terminal of each of the at least one or more fourth transistors are connected to a fifth node.

12. The semiconductor device according to claim 11, wherein a gate terminal of said fifth transistor and a gate terminal of said sixth transistor are connected to a sixth node, and a gate terminal of said seventh transistor and a gate terminal of said eighth transistor are connected to a seventh node.

13. The semiconductor device according to claim 12, wherein the fourth node, the fifth node, the sixth node, and the seventh node are each a control terminal that receives a signal from an external device.

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