Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device comprises: a plurality of lower-layer conductive patterns formed above a substrate; a first insulating film formed above the substrate and embedded between the plurality of lower-layer conductive patterns; a plurality of upper-layer conductive patterns formed above the first insulating film and joined to the plurality of lower-layer conductive patterns; and a second insulating film formed above the first insulating film and embedded between the plurality of upper-layer conductive patterns. The semiconductor device includes a joining section in which: a recess is provided from a top surface of the first insulating film, an upper-end surface of the lower-layer conductive patterns serving as the bottom surface of the recess; and in an area of the joining section where the lower-layer conductive patterns and the upper-layer conductive patterns are displaced relative to one another, the upper-layer conductive patterns are located, in the recess, below the top surface of the first insulating film. The upper-layer conductive patterns are joined to the lower-layer conductive patterns so as to cover the entire upper-end surface of the lower-layer conductive patterns.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] As a technology relating to a semiconductor device and a method for manufacturing the same, Patent Document 1 below describes the following manufacturing method. First, a plurality of conductive vias embedded in a first dielectric layer are selectively etched to form recesses above the conductive vias in the first dielectric layer. Next, a second dielectric layer is formed on the upper surfaces of the first dielectric layer and the conductive vias via an etching stop layer. Next, trenches connected to each conductive via are formed in the second dielectric layer and the etching stop layer, and a conductive layer is filled in the trenches and the recesses above the conductive vias. This increases the distance between any conductive via and the conductive layer formed in the trench above the adjacent conductive via compared to a configuration in which the entire upper surface of the conductive via is flush with the surface of the first dielectric layer (see Patent Document 1, FIG. 7).

[0003] US10,727,124B2

[0004] In the technology of Patent Document 1, if misalignment occurs in a trench formed in a second conductive layer relative to a conductive via in a lower layer, a large distance can be secured between the conductive via and the conductive layer above the adjacent conductive via. This ensures a sufficient breakdown voltage between adjacent conductive patterns. However, due to the occurrence of the misalignment, the contact area between the conductive via and the conductive layer filled in the trench is narrowed by the etching stop layer. This causes a problem of increased connection resistance between the upper and lower conductive patterns.

[0005] Therefore, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress a decrease in breakdown voltage between adjacent conductive patterns due to the occurrence of misalignment while suppressing an increase in connection resistance between upper and lower conductive patterns.

[0006] In order to achieve this object, the present invention provides a semiconductor device comprising: a plurality of lower-layer conductive patterns formed above a substrate; a first insulating film formed above the substrate and filling spaces between the plurality of lower-layer conductive patterns; a plurality of upper-layer conductive patterns formed on the first insulating film and joined to the plurality of lower-layer conductive patterns; and a second insulating film formed on the first insulating film and filling spaces between the plurality of upper-layer conductive patterns, wherein a recess is provided from an upper surface of the first insulating film, with the upper surface of the lower-layer conductive pattern serving as a bottom surface, and in a portion where the lower-layer conductive pattern and the upper-layer conductive pattern are misaligned, the upper-layer conductive pattern has a junction portion within the recess that is located lower than the upper surface of the first insulating film, and the upper-layer conductive pattern is joined to the lower-layer conductive pattern so as to cover the entire upper surface of the lower-layer conductive pattern.

[0007] The present invention can provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress a decrease in breakdown voltage between adjacent conductive patterns due to misalignment while suppressing an increase in connection resistance between upper and lower conductive patterns.

[0008] FIG. 2 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment; FIG. 3 is an enlarged view of part A in FIG. 1; FIG. 4 is a process diagram (part 5) showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 5 is a process diagram (part 6) showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 6 is a process diagram (part 7) showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 7 is a process diagram (part 8) showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 8 is a process diagram (part 9) showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 9 is a process diagram (part 10) showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 10 is a process diagram (part 11) showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 11 is a process diagram (part 12) showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 13 is a process diagram (part 14) showing a method for manufacturing a semiconductor device according to the first embodiment. 15 is a process diagram (part 15) showing the method for manufacturing the semiconductor device of the first embodiment. FIG. 16 is a cross-sectional view of another portion of the semiconductor device of the first embodiment. FIG. 17 is a cross-sectional view of a main portion of the semiconductor device of the second embodiment. FIG. 18 is a cross-sectional view of another portion of the semiconductor device of the second embodiment. FIG. 19 is a cross-sectional view of a main portion of the semiconductor device of the third embodiment. FIG. 20 is a cross-sectional view of a main portion of the semiconductor device of the third embodiment. FIG. 21 is a cross-sectional view of a main portion of the semiconductor device of the fourth embodiment. FIG. 22 is a cross-sectional view of another portion of the semiconductor device of the fourth embodiment. FIG. 23 is a process diagram (part 1) showing the method for manufacturing the semiconductor device of the fourth embodiment. FIG. 24 is a cross-sectional view of a main portion of the semiconductor device of the fifth embodiment. FIG. 25 is a cross-sectional view of another portion of the semiconductor device of the fifth embodiment. FIG. 26 is a cross-sectional view of a main portion of the semiconductor device of the sixth embodiment. FIG. 27 is a cross-sectional view of another portion of the semiconductor device of the sixth embodiment. FIG. 28 is a process diagram (part 1) showing a characteristic portion of the method for manufacturing the semiconductor device of the sixth embodiment. FIG. 29 is a process diagram (part 2) showing a characteristic portion of the method for manufacturing the semiconductor device of the sixth embodiment. FIG. 29 is a cross-sectional view of a main portion of the semiconductor device of the seventh embodiment. FIG. 29 is a process diagram (part 1) showing a characteristic portion of the method for manufacturing the semiconductor device of the seventh embodiment.10A to 10C are process diagrams (part 2) showing characteristic parts of the method for manufacturing a semiconductor device according to the seventh embodiment; FIG. 10B are process diagrams (part 3) showing characteristic parts of the method for manufacturing a semiconductor device according to the seventh embodiment; FIG. 10C are process diagrams (part 1) showing a method for manufacturing a semiconductor device according to the ninth embodiment; FIG. 10D are process diagrams (part 2) showing a method for manufacturing a semiconductor device according to the ninth embodiment; FIG. 10E are process diagrams (part 3) showing a method for manufacturing a semiconductor device according to the ninth embodiment; FIG. 10F are process diagrams (part 4) showing a method for manufacturing a semiconductor device according to the ninth embodiment; FIG. 10F are process diagrams (part 5) showing a method for manufacturing a semiconductor device according to the ninth embodiment; FIG. 10F are process diagrams (part 1) showing a method for manufacturing a semiconductor device according to the tenth embodiment; FIG. 10C are process diagrams (part 2) showing a method for manufacturing a semiconductor device according to the tenth embodiment; FIG. 10F are process diagrams (part 3) showing a method for manufacturing a semiconductor device according to the ninth embodiment; FIG. 10H are process diagrams (part 1) showing a method for manufacturing a semiconductor device according to the tenth embodiment; 13A to 13C are process diagrams (part 3) showing a method for manufacturing a semiconductor device according to a tenth embodiment; FIG. 13B are process diagrams (part 4) showing a method for manufacturing a semiconductor device according to a tenth embodiment; FIG. 13C are process diagrams (part 5) showing a method for manufacturing a semiconductor device according to a tenth embodiment;

[0009] Hereinafter, each embodiment of the semiconductor device and the method for manufacturing the semiconductor device of the present invention will be described in detail with reference to the drawings. The semiconductor device and the method for manufacturing the semiconductor device described in each embodiment are effectively applied to those with a wiring pitch of 20 nm or less, but are not limited to this. Note that common components in each embodiment are given the same reference numerals, and duplicated explanations will be omitted.

[0010] First Embodiment Configuration of a Semiconductor Device 1 of the First Embodiment FIG. 1 is a cross-sectional view of a main portion of a semiconductor device 1 of the first embodiment. The semiconductor device 1 shown in FIG. 1 includes a semiconductor substrate 100 and a semiconductor element 100a formed on one main surface of the semiconductor substrate 100. The semiconductor element 100a is, for example, a transistor having a gate electrode 101 and a source / drain diffusion layer 102, and is formed in each region separated by element isolations 103 formed in the surface layer of the semiconductor substrate 100. Also provided on the upper portion of the semiconductor substrate 100 are a plug 201 connected to the semiconductor element 100a and a lower insulating film 300 provided over the entire surface of the semiconductor substrate 100 with the plug 201 embedded therein. Note that, although an example of a regular transistor is described as the semiconductor element 100a, structures such as FinFET, GAA, and CFET may also be used.

[0011] Also, on the upper part of the lower insulating film 300, there are provided a first wiring M1 connected to the plug 201, a first via V1 above the first wiring M1, and a first insulating film 500 that embeds these. The first wiring M1 and the first via V1 constitute a lower conductive pattern. On the upper part of the first insulating film 500, there are provided a second wiring M2 connected to the first via V1, a second via V2 above the second wiring M2, and a second insulating film 700 that embeds these. The second wiring M2 and the second via V2 constitute an upper conductive pattern.

[0012] Here, this semiconductor device 1 has a wiring pitch of 20 nm or less. In this case, in order to reduce wiring resistance, the first wiring M1 and the first via V1, as well as the second wiring M2 and the second via V2, are constructed using a post Cu material whose electron mean free path is shorter than that of copper (Cu). Examples of such materials include metal materials such as ruthenium (Ru), cobalt (Co), molybdenum (Mo), tungsten (W), rhodium (Rh), and iridium (Ir). Furthermore, no barrier metal or seed barrier is disposed on the sidewalls of the first wiring M1 and the first via V1, as well as the second wiring M2 and the second via V2.

[0013] Furthermore, the first wiring M1 and the first via V1 are integrally formed by patterning the same conductive layer, forming a via-equipped wiring structure in which the first via V1 is integrally provided on the first wiring M1. Furthermore, the first insulating film 500 that embeds the first wiring M1 and the first via V1 is made of the same layer. Similarly, the second wiring M2 and the second via V2 are also integrally formed by patterning the same conductive layer, and the second insulating film 700 that embeds them is made of the same layer. Note that the first wiring M1 and the first via V1, and the second wiring M2 and the second via V2 are not limited to being made of the same post Cu material. However, using the same post Cu material is preferable because it reduces the connection resistance between the first via V1 and the second wiring M2.

[0014] In the above configuration, the connection structure between the first via V1 and the second wiring M2 is as follows.

[0015] 2 is an enlarged view of portion A in FIG. 1. As shown in FIG. 2, the upper end surface V1a of the first via V1 is located lower than the upper surface 500a of the first insulating film 500. As a result, a recessed portion 500b is formed in the first insulating film 500, with the upper end surface V1a of the first via V1 as its bottom surface. The second wiring M2 is connected to the first via V1 over the entire bottom surface of the recessed portion 500b and is joined to the first via V1 so as to cover the entire upper end surface V1a of the first via V1. This ensures a connection area between the first via V1 and the second wiring M2, making it possible to suppress an increase in connection resistance.

[0016] Here, the second wiring M2 is aligned with the first via V1, but the figure shows a state in which misalignment has occurred. Without misalignment, the recess 500b would be completely filled with the second wiring M2. However, in a semiconductor manufacturing process with a wiring pitch of 20 nm, the alignment tolerance is 15%. Therefore, in a process with a wiring pitch of 20 nm and a line-and-space (L / S) ratio of 10 nm / 10 nm, a misalignment of less than 1.5 nm is permitted. Therefore, as shown in FIGS. 1 and 2 , the semiconductor device 1 may experience misalignment of the second wiring M2 with respect to the first via V1.

[0017] Even in such misaligned locations, the semiconductor device 1 has a configuration in which the first via V1 is disposed over the entire bottom surface of the recessed portion 500b, and the second wiring M2 and the first via V1 are connected over the entire bottom surface of the recessed portion 500b, as described above. The second wiring M2 also has a junction M2a within the recessed portion 500b that is located lower than the upper surface 500a of the first insulating film 500.

[0018] The depth [d1] of the recessed portion 500b, whose bottom surface is the upper end surface V1a of the first via V1, is preferably at least one-third of the minimum wiring spacing [s1]. This facilitates a configuration having a step [d2] as shown below. The minimum wiring spacing [s1] is the minimum spacing between the conductive patterns of the second wiring M2 adjacent to each other.

[0019] Furthermore, the step [d2] from the upper surface 500a of the first insulating film 500 to the junction M2a of the second wiring M2 is preferably at least half the depth [d1] of the recessed portion 500b and at least 30% of the minimum wiring spacing [s1] (e.g., 10 nm). This ensures that the effective shortest distance [s2] between the first via V1 and the second wiring M2 is at least 85% of the minimum wiring spacing [s1], ensuring a breakdown voltage (TDDB: Time Dependent Dielectric Breakdown) between the first via V1 and the second wiring M2 and between the second wiring M2. Furthermore, the effective shortest distance [s2] between the first via V1 and the second wiring M2 is one of the concerns regarding a decrease in breakdown voltage when there is an interface between the interlayer insulating film. However, the effective shortest distance [s2] between the first via V1 and the second wiring M2 does not pass through the interface between the first insulating film 500 and the second insulating film 700, but passes through the first insulating film 500. This also ensures the above-mentioned breakdown voltage.

[0020] In addition, the actual shortest distance [s2] between the first via V1 and the second wiring M2 is the distance between any second wiring M2 and the portion of the second wiring M2 located above the first via V1 adjacent to the second wiring M2 in the shift direction.

[0021] Furthermore, the second wiring M2 is preferably disposed on the upper end surface V1a of the first via V1 in the recess 500b with a thickness of at least 1 nm, and more preferably 2 nm or more, thereby achieving a stable and appropriate connection resistance between the first via V and the second wiring M2.

[0022] Furthermore, if the depth [d1] of the recess 500b can be increased between 50% and 150% of the minimum wiring spacing [s1], the step [d2] can be increased to 40% or more, and further improved breakdown voltage can be expected. Furthermore, it becomes easier to control the film thickness of the second wiring M2 remaining in the recess 500b, resulting in more stable and appropriate connection resistance. Furthermore, it is desirable for the sidewalls of the recess 500b described above to have a slightly forward tapered shape. This improves the metal embedding characteristics during the manufacturing process. Furthermore, if misalignment occurs during the metal etching process for forming the second wiring M2, there is an effect that metal residue is less likely to occur on the sidewalls of the first insulating film 500 in the metal-etched region of the recess 500b.

[0023] <Method of Manufacturing a Semiconductor Device According to the First Embodiment> Figures 3 to 17 are process diagrams (No. 1) to (No. 15) showing the method of manufacturing a semiconductor device according to the first embodiment. Some of Figures 3 to 17 show cross-sectional views, and others show cross-sectional views and plan views. The method of manufacturing a semiconductor device according to the first embodiment will be described below with reference to these figures.

[0024] First, as shown in FIG. 3 , a semiconductor element 100a is formed on one main surface of a semiconductor substrate 100. Then, plugs 201 connected to the semiconductor element 100a and a lower insulating film 300 filling the spaces between the plugs 201 are formed. At this time, the upper surfaces of the lower insulating film 300 and the plugs 201 are flush with each other. Then, a first conductive film 400, a conductive hard mask layer 401, and an insulating hard mask layer 402 are formed in this order on top of the lower insulating film 300 and the plugs 201. The first conductive film 400 is formed to a thickness of approximately 40 nm using a metal material other than copper, such as ruthenium. The conductive hard mask layer 401 is a sacrificial layer, and is formed, for example, of titanium nitride (TiN) to a thickness of 5 nm. The insulating hard mask layer 402 is formed, for example, of silicon nitride (SiN) to a thickness of 5 to 10 nm. Then, a resist pattern 403 is formed on the insulating hard mask layer 402. This resist pattern 403 has a wiring shape with a minimum line and space (L / S) of 10 nm / 10 nm, for example. Note that multi-patterning can also be applied here, and the same applies to each patterning below.

[0025] 4, using the resist pattern 403 (see FIG. 3) as a mask, the insulating hard mask layer 402, the conductive hard mask layer 401, and the first conductive film 400 are anisotropically dry etched in this order to pattern the first conductive film 400 into the shape of the first wiring. Thereafter, the resist pattern 403 is peeled off.

[0026] 5, a lower resist film 404 is formed so as to bury the patterned first conductive film 400, conductive hard mask layer 401, and insulating hard mask layer 402, and an LTO (Low Temperature Oxide) film 405 and an anti-reflective film (not shown and not described below) are formed on top of the lower resist film 404 in this order. Then, a via pattern mask 406 made of a resist material is formed by lithography. The via pattern mask 406 is formed to have a width larger than the line width of the first wiring (patterned first conductive film 400).

[0027] Next, using the via pattern mask 406 as a mask, the LTO film 405, the lower resist film 404, the insulating hard mask layer 402, and the conductive hard mask layer 401 are anisotropically dry etched in this order. Next, the remaining via pattern mask 406, the LTO film 405, and the lower resist film 404 are stripped. Thereafter, as shown in FIG. 6 , using the insulating hard mask layer 402 as a mask, the conductive hard mask layer 401 and the upper 20 nm of the first conductive film 400 are anisotropically dry etched. This forms a columnar first via V1 with a height of 20 nm and a first wiring M1 with a height of 20 nm below it.

[0028] 7, a first insulating film 500 is formed on the lower insulating film 300, burying the first wiring M1, the first via V1, and the patterned conductive hard mask layer 401 and insulating hard mask layer 402. The first insulating film 500 is preferably made of a low-dielectric material, such as silicon dioxide (SiOC), which has good gap-fill properties. If better gap-fill properties are desired, a methylsilsesquioxane (MSQ) film may be formed by coating and then fired.

[0029] 8, the first insulating film 500 is polished by CMP using the conductive hard mask layer 401 as a stopper, thereby removing the insulating hard mask layer 402 (see FIG. 7) on the conductive hard mask layer 401.

[0030] Next, as shown in FIG. 9 , the conductive hard mask layer 401 (see FIG. 8 ) formed as a sacrificial layer is removed by etching. The etching may be dry etching or wet etching. As a result, a recess 500b is formed on the upper surface 500a side of the first insulating film 500, with the first via V1 as its bottom surface. The depth [d1] of this recess 500b corresponds to the film thickness (5 nm in this example) of the conductive hard mask layer 401, and therefore can be a stable size.

[0031] Next, as shown in FIG. 10 , a second conductive film 600 is formed on the first insulating film 500 and the first via V1. The second conductive film 600 is formed to a thickness of approximately 40 nm using a metal material other than copper, such as ruthenium (Ru). The film is formed, for example, by a physical vapor deposition (PVD) method. If it is difficult to fill the recess, a stacked film formed by an atomic layer deposition (ALD) method and a PVD method, or a film formed only by an ALD method, may be used. Furthermore, the upper surface of the second conductive film 600 may be planarized by CMP after the film formation. Then, a conductive hard mask layer 601 and an insulating hard mask layer 602 are formed in this order on top of the second conductive film 600. The conductive hard mask layer 601 is formed by depositing, for example, titanium nitride (TiN) to a thickness of 5 nm, and the insulating hard mask layer 602 is formed by depositing, for example, silicon nitride (SiN) to a thickness of 5 to 10 nm. The titanium nitride (TiN) film is formed by, for example, PVD. The silicon nitride (SiN) film is formed by, for example, PECVD (plasma-enhanced chemical vapor deposition).

[0032] 11, a resist pattern 603 is formed on the insulating hard mask layer 602. This resist pattern 603 has a wiring shape with, for example, a wiring pitch of 20 nm and a minimum line and space (L / S) of 10 nm / 10 nm. The resist pattern 603 is also aligned and formed so as to completely overlap the first via V1. However, in a semiconductor manufacturing process with a wiring pitch of 20 nm, the alignment tolerance is 15%.

[0033] 12, using the resist pattern 603 (see FIG. 11) as a mask, the insulating hard mask layer 602, the conductive hard mask layer 601, and the second conductive film 600 are anisotropically dry etched in this order to pattern the second conductive film 600 into the shape of the second wiring. The etching of the second conductive film 600 is performed in two stages as follows, taking into consideration the possibility that misalignment may occur in the resist pattern 603 with respect to the first via V1 due to misalignment during the formation of the resist pattern 603.

[0034] First, in the first etching step, the second conductive film 600 is etched until the first insulating film 500 is exposed. Whether the first insulating film 500 is exposed or not is determined by detecting a decrease in the intensity of a specific wavelength using, for example, an optical endpoint system.

[0035] Thereafter, in the second-stage etching, the second conductive film 600 is etched so that the second conductive film 600 remains on the entire upper end surface V1a of the first via V1, which constitutes the bottom surface of the recessed portion 500b in the first insulating film 500, where the recessed portion 500b is exposed due to misalignment. At this time, the etching of the second conductive film 600 is advanced so that the step [d2] between the upper surface 500a of the first insulating film 500 and the junction M2a of the second wiring M2 is at least half the depth [d1] of the recessed portion 500b and at least 30% of the minimum wiring spacing [s1], as described above. Such second-stage etching is controlled by the etching time.

[0036] In addition, when the second-stage etching is performed to the predetermined depth [d2], in order to leave the second conductive film 600 on the entire bottom surface of the recessed portion 500b, it is essential that the original depth [d1] of the recessed portion 500b be equal to or greater than the predetermined depth [d2]. As described with reference to FIG. 9 , the depth [d1] of the recessed portion 500b corresponds to the film thickness of the conductive hard mask layer 401, and therefore can be set to an accurate depth. Therefore, the second-stage etching can be performed so as to leave the second conductive film 600 on the entire bottom surface of the recessed portion 500b by controlling the etching time.

[0037] Next, as shown in FIG. 13 , an organic film 604 is applied and formed so as to bury the patterned second conductive film 600, conductive hard mask layer 601, and insulating hard mask layer 602, and then planarized and baked. An LTO film 605 is formed on top of the organic film 604 by PECVD, and an anti-reflective film (not shown and not described below) is further formed on top of the LTO film 605. Thereafter, a via pattern mask 606 made of a resist material is formed by lithography. The via pattern mask 606 is formed to have a width larger than the line width of the second wiring (patterned second conductive film 600).

[0038] Next, using the via pattern mask 606 as a mask, the LTO film 605, the organic film 604, the insulating hard mask layer 602, and the conductive hard mask layer 601 are anisotropically dry etched in this order. The remaining via pattern mask 606, the LTO film 605, and the organic film 604 are then peeled off. Thereafter, as shown in FIG. 14 , using the insulating hard mask layer 602 as a mask, the conductive hard mask layer 601 and the upper 20 nm of the second conductive film 600 are anisotropically dry etched. This forms a columnar second via V2 with a height of 20 nm and a second wiring M2 with a height of 20 nm below the second via V2. After etching, the remaining organic film 604 (see FIG. 13 ) is removed by ashing.

[0039] 15 , a second insulating film 700 is formed on the first insulating film 500 in a state in which the second wiring M2, the second via V2, and the patterned conductive hard mask layer 601 and insulating hard mask layer 602 are embedded. The second insulating film 700 is preferably made of a low dielectric material, such as silicon carbonate (SiOC), which has good gap-filling properties.

[0040] 16, the second insulating film 700 is polished by CMP using the conductive hard mask layer 601 as a stopper, thereby removing the insulating hard mask layer 602 (see FIG. 15) on the conductive hard mask layer 601.

[0041] Next, as shown in FIG. 17 , the conductive hard mask layer 601 (see FIG. 16 ) is removed by etching. The etching may be dry etching or wet etching. As a result, a recess 700b is formed on the upper surface 700a side of the second insulating film 700, with the second via V2 as its bottom surface. The depth [d1′] of this recess 700b corresponds to the film thickness (5 nm in this example) of the conductive hard mask layer 601, and therefore has a stable size.

[0042] 10 to 16 are repeated to form upper layer wirings and vias. If the formed via is the top layer, the conductive hard mask layer 601 shown in FIG. 16 does not need to be removed, and the conductive hard mask layer 601 does not need to be formed.

[0043] 18 is a cross-sectional view of another portion of the semiconductor device 1 according to the first embodiment, showing a first portion 1a in which the first via V1 and the second via V2 are not arranged, and a second portion 1b in which no misalignment occurs between the first via V1 and the second wiring M2. As shown in the second portion 1b, when no misalignment occurs, the effective shortest distance [s2] between the first via V1 and the second wiring M2 is maintained at the minimum wiring spacing [s1].

[0044] Advantages of the First Embodiment According to the first embodiment described above, even in a portion where misalignment occurs between the first via V1 and the second wiring M2, the second wiring M2 is joined to the entire upper end surface V1a of the first via V1 within the recessed portion 500b having the first via V1 as its bottom surface. This makes it possible to suppress the upper layer of the connection resistance between the first via V1 and the second wiring M2, even when misalignment occurs.

[0045] Furthermore, in the portion where misalignment occurs, the second wiring M2 has a junction M2a within the recessed portion 500b that is located lower than the upper surface 500a of the first insulating film 500. This makes it possible to increase the substantial distance between any first via V1 and the second wiring M2 above the adjacent first via V1, compared to when the junction M2a or the upper end surface V1a of the first via V1 is at the same height as the upper surface of the first insulating film 500.

[0046] A specific description will be given based on Figure 2. For example, assume that the wiring pitch is 20 nm (L / S = 10 / 10 nm) and the misalignment between the first via V1 and the second wiring M2 due to misalignment is 2 nm, exceeding 1.5 nm, which is 15% of the tolerance. In this case, if the junction M2a or the upper end surface V1a of the first via V1 is flush with the upper surface of the first insulating film 500 and there is no step [d2], the shortest distance [s2'] is 8 nm, which is 80% of the minimum wiring spacing [s1] = 10 nm.

[0047] In contrast, when the depth [d1] of the recessed portion 500b is 4 nm and the step [d2] is 3 nm, the shortest distance [s2] between the adjacent first via V1 and second wiring M2 is approximately 8.54 nm. This is 85.4% of the minimum wiring spacing [s1] of 10 nm, and the shortest distance [s2] can be increased by 5.4% compared to when there is no step [d2]. As a result, the shortest distance [s2] can be made equal to or greater than the allowable 8.5 nm.

[0048] Furthermore, when the depth [d1] of the recessed portion 500b is 6 nm and the step [d2] is 4 nm, the shortest distance [s2] between the adjacent first via V1 and second wiring M2 is approximately 8.94 nm. This is 89.4% of the minimum wiring spacing [s1] of 10 nm, and the shortest distance [s2] can be increased by 9.4% compared to when there is no step [d2]. As a result, the shortest distance [s2] can be achieved with a margin of at least the allowable 8.5 nm.

[0049] Furthermore, the first wiring M1 and the first via V1 are embedded in a first insulating film 500 with no interface therebetween, and the second wiring M2 and the second via V2 are embedded in a single layer of a second insulating film 700 with no interface therebetween. This makes it possible to ensure the TDDB characteristics between adjacent first vias V1 and between adjacent second vias V2.

[0050] Although the above description is given of an example in which the wiring pitch is 20 nm (L / S=10 / 10 nm), the same effect can be obtained even in the case of a pitch smaller than that.

[0051] 19 is a cross-sectional view of a main portion of a semiconductor device 2 according to a second embodiment, showing a portion where misalignment occurs between a first via V1 and a second wiring M2. Also, FIG. 20 is a cross-sectional view of another portion of the semiconductor device 2 according to the second embodiment, showing a first portion 2a where the first via V1 and the second via V2 are not arranged, and a second portion 2b where no misalignment occurs between the first via V1 and the second wiring M2.

[0052] The semiconductor device 2 of the second embodiment shown in Figures 19 and 20 differs from the semiconductor device of the first embodiment in that a barrier insulating layer 501 is provided so as to cover the first insulating film 500 above the first via V1, but the other configurations are similar.

[0053] The barrier insulating layer 501 is a layer made of aluminum oxide (AlOx), and is provided on the upper surface of the first insulating film 500 and on the sidewall of the recessed portion 500b.

[0054] <Method for manufacturing semiconductor device of second embodiment> In the method for manufacturing the semiconductor device 2 of the second embodiment described above, a step of forming a barrier insulating layer 501 may be performed after the step described with reference to FIG. 9 in the method for manufacturing the semiconductor device of the first embodiment and before the step described with reference to FIG. 10 .

[0055] In the step of forming the barrier insulating layer 501, an insulating material such as aluminum oxide (AlOx) is selectively formed on the exposed surface of the first insulating film 500. This selective formation can be achieved, for example, by forming a SAM (self-assembled monolayer) on the metal (on the first via V1), then depositing an aluminum oxide (AlOx) film, and then removing the SAM on the first via V1.

[0056] 19 and 20, when forming an upper wiring structure, first, a barrier insulating layer is formed as described above so as to cover the second insulating film 700. Thereafter, the steps described with reference to FIGS.

[0057] 19 , the barrier insulating layer 501 is disposed at the shortest distance between the first via V1 and the adjacent second wiring M2. This increases the breakdown voltage between the first via V1 and the second wiring M2, and in addition to the effects of the first embodiment, it also has the effect of extending the TDDB lifetime compared to the first embodiment. Furthermore, covering the first insulating film 500 with the barrier insulating layer 501 prevents moisture absorption by the first insulating film 500 and prevents plasma damage to the first insulating film 500 during processing of upper layers.

[0058] 21 is a cross-sectional view of a main portion of a semiconductor device 3 according to a third embodiment, showing a portion where misalignment occurs between a first via V1 and a second wiring M2. Also, FIG. 22 is a cross-sectional view of another portion of the semiconductor device 3 according to the third embodiment, showing a first portion 3a where the first via V1 and the second via V2 are not arranged, and a second portion 3b where no misalignment occurs between the first via V1 and the second wiring M2.

[0059] The semiconductor device 3 of the third embodiment shown in Figures 21 and 22 differs from the semiconductor device of the first embodiment in that a first base barrier insulating layer 502 is provided below the first insulating film 500 and a second base barrier insulating layer 702 is provided below the second insulating film 700, but the other configurations are similar.

[0060] The first underlying barrier insulating layer 502 and the second underlying barrier insulating layer 702 are layers made of, for example, plasma silicon carbonitride (SiCN). The first underlying barrier insulating layer 502 is a layer formed before the first insulating film 500 is formed, and is provided below and on the sidewalls of the first insulating film 500. The second underlying barrier insulating layer 702 is a layer formed before the second insulating film 700 is formed, and is provided below and on the sidewalls of the second insulating film 700.

[0061] <Method of Manufacturing Semiconductor Device of Third Embodiment> In the method of manufacturing the semiconductor device 3 of the third embodiment described above, after the step described with reference to Fig. 6 in the method of manufacturing the semiconductor device of the first embodiment, a step of forming a first underlying barrier insulating layer 502 is performed immediately before the step of forming the first insulating film 500 described with reference to Fig. 7. When the first insulating film 500 is polished by CMP in the next step shown in Fig. 8, the first underlying barrier insulating layer 502 on the first via V1 is removed, but when the conductive hard mask layer 401 is etched away, the first underlying barrier insulating layer 502 is left on the sidewall of the recess recess 500b.

[0062] 14 in the manufacturing method of the semiconductor device of the first embodiment, and immediately before the step of forming the second insulating film 700 described with reference to Fig. 15, the manufacturing method of the semiconductor device 3 performs a step of forming a second underlying barrier insulating layer 702. When the second insulating film 700 is polished by CMP in the next step shown in Fig. 16, the second underlying barrier insulating layer 702 on the second via V2 is removed, but when the conductive hard mask layer 601 is etched away, the second underlying barrier insulating layer 702 is left on the sidewall of the recess recess 700b.

[0063] <Effects of the Third Embodiment> According to the third embodiment described above, the exposed surfaces of the first wiring M1 and the first via V1 are covered with the first underlying barrier insulating layer 502, and the exposed surfaces of the second wiring M2 and the second via V2 are covered with the second underlying barrier insulating layer 702. As a result, the withstand voltage of the first insulating film 500 and the second insulating film 700 is compensated for by the first underlying barrier insulating layer 502 and the second underlying barrier insulating layer 702. As a result, in addition to the effects of the first embodiment, an effect of extending the TDDB lifetime compared to the first embodiment can be obtained. Furthermore, since the metal materials of the first wiring M1, the first via V1, etc. are covered with the first underlying barrier insulating layer 502, metal corrosion can be prevented, and plasma damage in the processing of upper layers can also be prevented. Furthermore, since the first underlying barrier insulating layer 502 and the second underlying barrier insulating layer 702 are blanket deposited on the entire surface, more stable deposition is possible compared to the second embodiment in which selective deposition is performed.

[0064] 23 is a cross-sectional view of a main portion of a semiconductor device 4 according to a fourth embodiment, showing a portion where misalignment occurs between the first via V1 and the second wiring M2. Also, FIG. 24 is a cross-sectional view of another portion of the semiconductor device 4 according to the fourth embodiment, showing a first portion 4a where the first via V1 and the second via V2 are not arranged, and a second portion 4b where no misalignment occurs between the first via V1 and the second wiring M2.

[0065] The semiconductor device 4 of the fourth embodiment shown in Figures 23 and 24 differs from the semiconductor device of the first embodiment in that the first insulating film 500 has a cavity portion 500c and the second insulating film 700 has a cavity portion 700c, but the other configurations are similar.

[0066] Cavities 500c in the first insulating film 500 are formed between the first wirings M1 and between the first vias V1. These cavities 500c are enclosed within the first insulating film 500 and have a height smaller than the film thickness of the first insulating film 500. Cavities 700c in the second insulating film 700 are formed between the second wirings M2 and between the second vias V2. These cavities 700c are enclosed within the second insulating film 700 and have a height smaller than the film thickness of the second insulating film 700.

[0067] 25 and 26 are process diagrams (part 1) and (part 2) showing a method for manufacturing a semiconductor device according to a fourth embodiment, and correspond to the processes described with reference to FIGS. 7 and 8 in the method for manufacturing a semiconductor device according to the first embodiment. The method for manufacturing a semiconductor device 4 according to the fourth embodiment described above uses a film formation method with poor gap-fill characteristics when forming the first insulating film 500 described with reference to FIG. 7 in the method for manufacturing a semiconductor device according to the first embodiment. As a result, a first insulating film 500 having a cavity 500c is formed, as shown in FIG.

[0068] At this time, the first insulating film 500 is formed on the lower insulating film 300 in a state in which the first wiring M1, the first via V1, and further the patterned conductive hard mask layer 401 and insulating hard mask layer 402 are embedded. The first insulating film 500 is preferably made of a low dielectric material, and is made of, for example, silicon carbonate (SiOC), as in the first embodiment.

[0069] Furthermore, in forming the first insulating film 500, the gap-fill characteristics are controlled so that the cavity 500c is located lower than the upper surface of the conductive hard mask layer 401. As a result, as shown in FIG. 26 , when the first insulating film 500 is subjected to CMP polishing using the conductive hard mask layer 401 as a stopper, the cavity 500c is maintained in a closed state within the first insulating film 500. Furthermore, by using the conductive hard mask layer 401 as a stopper, the CMP polishing can be stopped at a position higher than the upper end surface V1a of the first via V1 by the height of the conductive hard mask layer 401. This has the advantage of allowing the cavity 500c to be positioned at a higher position. This also prevents slurry from penetrating into the cavity 500c during CMP polishing. Furthermore, in a subsequent process, when the conductive hard mask layer 401 is stripped, the etching gas or etching solution can be prevented from penetrating into the cavity 500c, eliminating the effects of such penetration.

[0070] Although not shown here, the process of forming the second insulating film 700 described using FIG. 15 in the method for manufacturing the semiconductor device of the first embodiment is carried out in the same manner as the process of forming the first insulating film 500 described above.

[0071] Advantages of the Fourth Embodiment According to the fourth embodiment described above, by providing the cavities 500c, 700c in the first insulating film 500 and the second insulating film 700, an advantage such as reduced inter-wiring capacitance can be obtained in addition to the advantages of the first embodiment. Furthermore, in the deposition process of the first insulating film 500, the gap-fill characteristics are controlled so that the cavities 500c are positioned lower than the upper surface of the conductive hard mask layer 401. Since the cavities 500c are not exposed to the outside of the first insulating film 500, subsequent processes can be carried out without being affected by the cavities 500c. This is also true for the deposition process of the second insulating film 700. Furthermore, by using the conductive hard mask layer 401 as a stopper, the CMP polishing of the first insulating film 500 can be stopped at a position higher than the upper end surface V1a of the first via V1, which has the advantage of allowing the cavities 500c to be positioned higher. This is also true for the CMP polishing process of the second insulating film 700.

[0072] The fourth embodiment can be combined with the second and third embodiments, and by combining them, it is possible to obtain the effects of those embodiments.

[0073] 27 is a cross-sectional view of a main portion of a semiconductor device 5 according to a fifth embodiment, showing a portion where misalignment occurs between a first via V1 and a second wiring M2. Also, FIG. 28 is a cross-sectional view of another portion of the semiconductor device 5 according to the fifth embodiment, showing a first portion 5a where the first via V1 and the second via V2 are not arranged, and a second portion 5b where no misalignment occurs between the first via V1 and the second wiring M2.

[0074] The semiconductor device 5 of the fifth embodiment shown in Figures 27 and 28 differs from the semiconductor device of the first embodiment in that a first barrier metal layer 407 is provided below the first wiring M1 and a second barrier metal layer 607 is provided below the second wiring M2, but the other configurations are similar.

[0075] The first barrier metal layer 407 and the second barrier metal layer 607 are layers made of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum nitride (MoN), ruthenium nitride (RuN), tungsten nitride (WN), etc. The second barrier metal layer 607 is provided on the bottom surface of the second wiring M2 and the sidewall of the recessed portion 500b.

[0076] <Method of Manufacturing Semiconductor Device of Fifth Embodiment> The method of manufacturing semiconductor device 5 of the fifth embodiment described above includes a step of forming first barrier metal layer 407 before forming first conductive film 400 in the step of the method of manufacturing a semiconductor device of the first embodiment described with reference to Fig. 3. Next, in the step described with reference to Fig. 4, following anisotropic dry etching of first conductive film 400, etching of first barrier metal layer 407 below first conductive film 400 may be performed.

[0077] 10, a step of forming a second barrier metal layer 607 is performed before forming the second conductive film 600. Then, in the step described with reference to FIG. 12, the second conductive film 600 is anisotropically dry etched, followed by etching of the underlying second barrier metal layer 607.

[0078] <Effects of Fifth Embodiment> According to the fifth embodiment described above, by providing the first barrier metal layer 407 below the first wiring M1 and the second barrier metal layer 607 below the second wiring M2, it is possible to improve the contact resistance between the first wiring M1 and the plug 201, and the contact resistance between the second wiring M2 and the first via V1. In addition, it is possible to improve the adhesion between the first wiring M1 and the plug 201 and the lower insulating film 300, and also to improve the adhesion between the second wiring M2 and the first via V1 and the first insulating film 500.

[0079] The fifth embodiment can be combined with the second to fourth embodiments. In this case, the fourth embodiment includes a combination with the second or third embodiment. By combining the fifth embodiment with each of these embodiments, it is possible to obtain the effects of these embodiments.

[0080] 29 is a cross-sectional view of a main portion of a semiconductor device 6 according to a sixth embodiment, showing a portion where misalignment occurs between the first via V1 and the second wiring M2. Also, FIG. 30 is a cross-sectional view of another portion of the semiconductor device 6 according to the sixth embodiment, showing a first portion 6a where the first via V1 and the second via V2 are not arranged, and a second portion 6b where no misalignment occurs between the first via V1 and the second wiring M2.

[0081] The semiconductor device 6 of the sixth embodiment shown in Figures 29 and 30 has a configuration in which an intermediate barrier metal layer 408 is provided between the first wiring M1 and the first via V1 of the semiconductor device of the fifth embodiment, and an intermediate barrier metal layer 608 is provided between the second wiring M2 and the second via V2.

[0082] The intermediate barrier metal layers 408 and 608 are made of the same material as the first barrier metal layer 407 and the second barrier metal layer 607, and are layers made of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), molybdenum nitride (MoN), ruthenium nitride (RuN), tungsten nitride (WN), etc. The intermediate barrier metal layer 408 may be provided on the entire surface of the first wiring M1, and the intermediate barrier metal layer 608 may be provided on the entire surface of the second wiring M2.

[0083] <Method of Manufacturing Semiconductor Device of Sixth Embodiment> In the method of manufacturing the semiconductor device 6 of the sixth embodiment described above, a step of forming a first barrier metal layer 407 is performed before forming the first conductive film 400 in the step of the method of manufacturing the semiconductor device of the first embodiment described with reference to FIG. 3. Next, an intermediate barrier metal layer 408 (see FIGS. 29 and 30 ) is formed at an intermediate position in the formation of the first conductive film 400 having a total thickness of 40 nm. Thereafter, in the step described with reference to FIG. 4 , anisotropic dry etching is performed on the first conductive film 400 sandwiching the intermediate barrier metal layer 408, followed by etching of the first barrier metal layer 407 below it.

[0084] 6 , the steps up to the step of forming the pillar-shaped first via V1 and the first wiring M1 below it may be performed in the same manner as described in the first embodiment. In this step, particularly when anisotropically dry etching is performed on the conductive hard mask layer 401 and the upper part of the first conductive film 400 using the insulating hard mask layer 402 as a mask, the intermediate barrier metal layer 408 is used as an etching stopper, as shown in FIG. 31 . This makes it possible to form the pillar-shaped first via V1 with a height of 20 nm and the first wiring M1 below it with a height of 20 nm with high precision.

[0085] Furthermore, in the manufacturing method of the semiconductor device 6 of the sixth embodiment, a step of forming a second barrier metal layer 607 is performed before the formation of the second conductive film 600 in the step described with reference to FIG. 10 in the manufacturing method of the semiconductor device of the first embodiment. Next, an intermediate barrier metal layer 608 (see FIGS. 29 and 30) is formed at an intermediate position in the formation of the second conductive film 600 having a total thickness of 40 nm. Thereafter, in the step described with reference to FIG. 12, anisotropic dry etching is performed on the second conductive film 600 sandwiching the intermediate barrier metal layer 608, followed by etching of the second barrier metal layer 607 below it.

[0086] 14, the steps up to forming the pillar-shaped second via V2 and the second wiring M2 below it may be performed in the same manner as described in the first embodiment. In this step, particularly when anisotropically dry etching is performed on the conductive hard mask layer 601 and the upper part of the second conductive film 600 using the insulating hard mask layer 602 as a mask, the intermediate barrier metal layer 608 is used as an etching stopper, as shown in FIG. 32. This makes it possible to form the pillar-shaped second via V2 with a height of 20 nm and the second wiring M2 below it with a height of 20 nm with high precision.

[0087] Advantages of the Sixth Embodiment According to the sixth embodiment described above, in addition to the advantages of the fifth embodiment, the first wiring M1, the first via V1, the second wiring M2, and the second via V2 can be formed with high height accuracy. This makes it possible to uniformize the wiring resistance and the via resistance within the surface of the semiconductor substrate 100.

[0088] The sixth embodiment can be combined with the second to fourth embodiments. In this case, the fourth embodiment includes a combination with the second or third embodiment. By combining the sixth embodiment with each of these embodiments, it is possible to obtain the effects of these embodiments.

[0089] Seventh Embodiment Configuration of Semiconductor Device of Seventh Embodiment Fig. 33 is a cross-sectional view of a main part of a semiconductor device 7 of a seventh embodiment. As shown in Fig. 33, the first via V1' does not need to be formed integrally with the wiring, and may be joined to the upper part of a plug 201 connected to the semiconductor substrate, for example. Such a first via V1' is formed in a MOL (middle of line) process between the element process and the wiring process.

[0090] <Method of Manufacturing Semiconductor Device of Seventh Embodiment> FIGS. 34 to 36 are process diagrams (parts 1) to (part 3) illustrating characteristic features of the method of manufacturing a semiconductor device of the seventh embodiment. In the method of manufacturing a semiconductor device 7 of the seventh embodiment, as shown in FIG. 34 , a first via V1′ is first formed in a state where it is bonded to a plug 201 embedded in a lower insulating film 300. The first via V1′ is formed by anisotropic dry etching of a first conductive film 400′ formed to a thickness corresponding to the height of the first via V1′. The first conductive film 400′ is made of a metal material other than copper, as described in the first embodiment. In this case, the process of forming the first wiring M1 described in FIGS. 3 and 4 in the first embodiment is not performed, and instead, a 20-nm-thick first conductive film 400′ and the conductive hard mask layer 401 and insulating hard mask layer 402 thereon are formed by anisotropic dry etching.

[0091] Thereafter, a first insulating film 500 is formed on the lower insulating film 300 in a state in which the first via V1′ and the patterned conductive hard mask layer 401 and insulating hard mask layer 402 are embedded. The first insulating film 500 is preferably made of a low dielectric material, and is preferably made of silicon carbonate (SiOC), which has good gap-fill properties, as in the first embodiment.

[0092] 8 and subsequent figures in the first embodiment can be performed. That is, as shown in Fig. 35, the first insulating film 500 is polished by CMP using the conductive hard mask layer 401 as a stopper. This removes the insulating hard mask layer 402 (see Fig. 34) on the conductive hard mask layer 401.

[0093] Next, as shown in FIG. 36 , the conductive hard mask layer 401 (see FIG. 35 ) is removed by etching. The etching may be dry etching or wet etching. As a result, a recess 500b is formed on the upper surface 500a side of the first insulating film 500, with the first via V1′ as its bottom surface. The depth [d1] of this recess 500b corresponds to the film thickness (5 nm in this example) of the conductive hard mask layer 401, and therefore can be made to a stable size.

[0094] Thereafter, similarly to the first embodiment, second wirings M2 and second vias V2 are formed.

[0095] <Effects of Seventh Embodiment> The seventh embodiment described above can also achieve the same effects as the first embodiment.

[0096] The seventh embodiment can be combined with the second to sixth embodiments. However, since the seventh embodiment does not include the first wiring, it can be combined with the second to sixth embodiments from which the configuration related to the first wiring has been removed. By combining the seventh embodiment with each of these embodiments, it is possible to obtain the effects of these embodiments.

[0097] 37 is a cross-sectional view of a main part of a semiconductor device 8 according to an eighth embodiment. The semiconductor device 8 shown in FIG. 37 is a modified example of the semiconductor device according to the seventh embodiment, and has a configuration in which a base barrier metal layer 409 is provided below the first via V1′, between the first via V1′ and the plug 201.

[0098] <Method for manufacturing semiconductor device of eighth embodiment> The method for manufacturing the semiconductor device 8 of the eighth embodiment described above is the same as the method for manufacturing the semiconductor device of the seventh embodiment, except that, before depositing the first conductive film 400′, an underlying barrier metal layer 409 is deposited, and in the anisotropic dry etching performed to form the first via V1′, the underlying barrier metal layer 409 is dry etched following the first conductive film 400′.

[0099] <Effects of Eighth Embodiment> According to the eighth embodiment described above, the provision of the underlying barrier metal layer 409 makes it possible to improve the contact resistance and adhesion between the plug 201 and the first via V1'.

[0100] The eighth embodiment can be combined with the second to sixth embodiments. However, since the eighth embodiment does not include the first wiring, it can be combined with the second to sixth embodiments from which the configuration related to the first wiring has been removed. By combining the eighth embodiment with each of these embodiments, it is possible to obtain the effects of these embodiments.

[0101] 38 is a cross-sectional view of a main portion of a semiconductor device 9 according to a ninth embodiment, showing a portion where misalignment occurs between a first via V1 and a second wiring M2. Also, FIG. 39 is a cross-sectional view of another portion of the semiconductor device 9 according to the ninth embodiment, showing a first portion 9a where the first via V1 and the second via V2 are not arranged, and a second portion 9b where no misalignment occurs between the first via V1 and the second wiring M2.

[0102] 38 and 39 differs from the semiconductor device of the first embodiment in that the second wiring M2 has a laminated structure made of a different conductive material, but the other configurations are the same. That is, the second wiring M2 is made of an anchor portion M21 joined to the first via V1 and a main layer M20 made of a conductive material different from that of the anchor portion M21.

[0103] Fig. 40 is a cross-sectional view of a main portion of the semiconductor device 9 of the ninth embodiment in the y direction, showing a cross section perpendicular to the cross-sectional view of the main portion of Fig. 38. Here, Fig. 41 is a plan view of a main portion of the semiconductor device 9 of the ninth embodiment. Fig. 38 corresponds to the X-X cross section of Fig. 41 and shows a state in which the second wiring M2 is displaced in the -X direction with respect to the first via V1. Fig. 40 corresponds to the Y-Y cross section of Fig. 41 and shows a state in which the second wiring M2 is displaced in the -Y direction with respect to the first via V1.

[0104] 38 to 40, the anchor portion M21 is a conductive member provided in the recessed portion 500b. The upper portion of the anchor portion M21 protrudes from the upper surface 500a of the first insulating film 500 and has a flange portion that extends over the upper surface 500a of the first insulating film 500.

[0105] The shape of the anchor portion M21 protruding from the first insulating film 500 is controlled by the formation conditions, and as shown, the top surface is flat and the flange is wide, or the top surface is curved and the flange is relatively narrow. If the top of the anchor portion M21 is flat, the protruding height above the first insulating film 500 can be reduced, which allows for efficient etching in the manufacturing process described below.

[0106] The anchor portion M21 is connected to the first via V1 over the entire bottom surface of the recessed portion 500b and is joined to the first via V1 so as to cover the entire upper end surface of the first via V1, thereby ensuring a connection area between the first via V1 and the second wiring M2 and suppressing an increase in connection resistance.

[0107] Furthermore, if there is no misalignment of the second wiring M2 with respect to the first via V1 (see the second portion 9b in FIG. 39), the recessed portion 500b will be completely filled with the anchor portion M21.

[0108] On the other hand, in a state where the second wiring M2 is misaligned with respect to the first via V1 (see FIGS. 38 and 40), the anchor M21 has, within the recessed portion 500b, a junction M2a that is located lower than the upper surface 500a of the first insulating film 500. Note that the step [d2] from the upper surface 500a of the first insulating film 500 to the junction M2a of the second wiring M2, and the depth [d1] of the recessed portion 500b are as described in the first embodiment.

[0109] The conductive material constituting the anchor portion M21 described above is a material that can act as an etching stopper when etching the conductive material constituting the main layer M20 of the second wiring M2. Furthermore, when the semiconductor device 9 has a wiring pitch of 20 nm or less, the conductive material constituting the anchor portion M21 is preferably selected from the post Cu materials described in the first embodiment. These materials are preferably made using post Cu materials whose electron mean free path is smaller than that of copper (Cu), and examples of such materials include metal materials such as ruthenium (Ru), cobalt (Co), molybdenum (Mo), tungsten (W), rhodium (Rh), and iridium (Ir).

[0110] 42 to 46 are process diagrams (parts 1) to (part 5) illustrating characteristic steps of the method for manufacturing a semiconductor device according to the ninth embodiment. In the method for manufacturing the semiconductor device 9 according to the ninth embodiment, first, after the recessed portion 500b is formed as described in the method for manufacturing a semiconductor device according to the first embodiment with reference to FIG. 9, a step of forming an anchor portion M21 is performed as shown in FIG. 42 before the second conductive film 600 is formed as described in FIG.

[0111] The anchor portion M21 shown in FIG. 42 is formed by, for example, selective metal growth on the material constituting the first via V1. In this case, for example, a molybdenum (Mo) film is selectively grown on the first via V1 by selective atomic layer deposition (ALD), resulting in the anchor portion M21. In this selective growth, the metal layer is grown higher than the recessed portion 500b, so that the metal grows isotropically in the portion extending above the recessed portion 500b. This selective metal growth results in the anchor portion M21 having a flange portion extending above the upper surface 500a of the first insulating film 500. In this selective metal growth, the shape of the portion of the anchor portion M21 protruding from the first insulating film 500 is controlled by adjusting the film formation conditions, such as temperature, gas flow rate, pressure, and ALD cycle time.

[0112] 43, a second conductive film 600, a conductive hard mask layer 601, and an insulating hard mask layer 602 are deposited in this order on the first insulating film 500 and the anchor portion M21. The deposition of these layers is performed in the same manner as in the first embodiment described with reference to FIG. 10. However, since the second conductive film 600 is a film that constitutes the main layer M20 (see FIG. 38) of the second wiring M2, it is deposited using a conductive material different from that of the anchor portion M21.

[0113] 44, a resist pattern 603 is formed on the insulating hard mask layer 602. The resist pattern 603 is formed in the same manner as in the first embodiment described with reference to FIG.

[0114] Next, as shown in FIG. 45, using the resist pattern 603 (see FIG. 44) as a mask, the insulating hard mask layer 602, the conductive hard mask layer 601, and the second conductive film 600 are anisotropically dry etched in this order, and the second conductive film 600 is patterned into the shape of the second wiring.

[0115] In particular, the etching of the second conductive film 600 is performed under etching conditions that provide a high selectivity to the anchor portion M21. For example, when the anchor portion M21 is made of molybdenum (Mo) and the second conductive film 600 is made of ruthenium (Ru), the etching is performed under conditions that provide a high selectivity to the anchor portion M21. ２ The second conductive film 600 is selectively anisotropically etched by plasma RIE (Reactive Ion Etching) using a SiO 2 -based etchant, thereby stopping the etching of the second conductive film 600 at the exposed surfaces of the first insulating film 500 and the anchor portion M21.

[0116] Thereafter, as shown in FIG. 46 , the anchor portion M21 is etched. At this time, in the portion where the recessed portion 500b is exposed from the second conductive film 600 in a planar view due to misalignment, the anchor portion M21 is etched so that the anchor portion M21 remains on the entire surface of the first via V1 that forms the bottom surface of the recessed portion 500b. Furthermore, the anchor portion M21 is etched so that the step [d2] between the upper surface 500a of the first insulating film 500 and the junction M2a of the anchor portion M21 is at least half the depth [d1] of the recessed portion 500b and at least 30% of the minimum wiring spacing [s1], as described above. The anchor portion M21 is etched while controlling the etching time, so that the anchor portion M21 remains on the entire surface of the recessed portion 500b. As an example, when the anchor portion M21 is made of molybdenum (Mo), the anchor portion M21 is etched using chlorine gas (Cl ). ２ ) and oxygen gas (O ２ RIE etching is performed using ) as a base etchant.

[0117] 45 and 46 may be performed consecutively. In this case, for example, the resist pattern 603 shown in FIG. 44 is used as a mask, and chlorine gas (Cl ２ ) and oxygen gas (O ２ ) as a base etchant, the second conductive film 600 and the anchor portion M21 are successively RIE-etched. In this etching, the etching time may be controlled so as to leave the anchor portion M21 in the recessed portion 500b as described above.

[0118] After the above, the same procedures as those described in the first embodiment with reference to Figures 13 to 17 are carried out to obtain the semiconductor device 9 described with reference to Figures 38 to 41. After the above, the steps described with reference to Figure 42 and subsequent steps are repeated to form wiring and vias in upper layers.

[0119] Effect of the Ninth Embodiment According to the ninth embodiment described above, the anchor portion M21 of the second wiring M2 that is joined to the first via V1 is made of a conductive material different from that of the main body layer M20 of the second wiring M2, thereby improving the processing accuracy of the second wiring M2. That is, in processing the second wiring M2, it is possible to etch the second conductive film 600 that constitutes the main body layer M20 with a high selectivity relative to the anchor portion M21. As a result, the etching accuracy of the anchor portion M21 is improved, and it is possible to leave the anchor portion M21 with a predetermined film thickness in the recessed portion 500b above the first via V1.

[0120] The ninth embodiment can be combined with the second to sixth embodiments. In this case, the fourth embodiment includes a combination with the second or third embodiment. When the fifth embodiment shown in FIG. 27 or the sixth embodiment shown in FIG. 28 is combined with the ninth embodiment, the second barrier metal layer 607 in FIGS. 27 and 28 is provided on the upper surface of the anchor portion M21.

[0121] Furthermore, the ninth embodiment and combinations of the ninth embodiment with other embodiments can also be applied to the seventh or eighth embodiment. By combining the ninth embodiment with each of these embodiments, it is possible to obtain the effects of these embodiments.

[0122] Tenth Embodiment Configuration of Semiconductor Device of Tenth Embodiment Figure 47 is a cross-sectional view of a main portion of a semiconductor device 10 of the tenth embodiment, showing a portion where misalignment occurs between the first via V1 and the second wiring M2. Figure 48 is a cross-sectional view of another portion of the semiconductor device 10 of the tenth embodiment, showing a first portion 10a where the first via V1 and the second via V2 are not arranged, and a second portion 10b where misalignment does not occur between the first via V1 and the second wiring M2. Figure 49 is a cross-sectional view of a main portion of the semiconductor device 10 of the tenth embodiment in the y direction (see Figure 41), showing a cross section perpendicular to the cross-sectional view of Figure 47. That is, Figure 47 corresponds to the X-X cross section of Figure 41 and shows a state in which the second wiring M2 is misaligned in the -X direction with respect to the first via V1. FIG. 49 corresponds to the YY cross section of FIG. 41, and shows a state in which the second wiring M2 is displaced in the −Y direction relative to the first via V1.

[0123] 47 to 49 differs from the semiconductor device of the first embodiment in that the second wiring M2 has a laminated structure made of different conductive materials, but the other configurations are the same. That is, the second wiring M2 is made of a wiring lower layer M22 joined to the first via V1 and a main layer M20 made of a conductive material different from that of the wiring lower layer M22.

[0124] The wiring lower layer M22 is a conductive member provided with a constant thickness on the upper surface 500a of the first insulating film 500. The wiring lower layer M22 is inserted into the recessed portion 500b of the first insulating film 500, is connected to the first via V1 over the entire bottom surface of the recessed portion 500b, and is joined to the first via V1 so as to cover the entire upper end surface of the first via V1. This ensures a connection area between the first via V1 and the second wiring M2, making it possible to suppress an increase in connection resistance.

[0125] Furthermore, if there is no misalignment of the second wiring M2 with respect to the first via V1 (see the second portion 10b in FIG. 48), the recessed portion 500b will be completely filled with the wiring lower layer M22.

[0126] On the other hand, in a state where the second wiring M2 is misaligned with respect to the first via V1 (see FIGS. 47 and 49), the wiring lower layer M22 has, within the recessed portion 500b, a junction M2a that is located lower than the upper surface 500a of the first insulating film 500. Note that the step [d2] from the upper surface 500a of the first insulating film 500 to the junction M2a of the second wiring M2, and the depth [d1] of the recessed portion 500b are as described in the first embodiment.

[0127] The conductive material constituting the wiring lower layer M22 as described above is a material that can act as an etching stopper when etching the conductive material constituting the main layer M20 of the second wiring M2. Furthermore, when the semiconductor device 10 has a wiring pitch of 20 nm or less, the conductive material constituting the wiring lower layer M22 is preferably selected from the post Cu materials described in the first embodiment.

[0128] 50 to 54 are process diagrams (parts 1) to (part 5) illustrating characteristic features of the method for manufacturing a semiconductor device according to the tenth embodiment. In the method for manufacturing the semiconductor device 10 according to the tenth embodiment, first, after the formation of the recessed portion 500b described with reference to FIG. 9 in the method for manufacturing a semiconductor device according to the first embodiment, a step of forming a wiring lower layer M22 is performed as shown in FIG. 50 before the formation of the second conductive film 600 described with reference to FIG.

[0129] The formation of the wiring lower layer M22 shown in FIG. 50 is performed in two stages as follows. First, a molybdenum (Mo) film is selectively grown on the first via V1 by, for example, selective ALD to a height that fills the recessed portion 500b. Then, a molybdenum (Mo) film is formed on the entire surface of the molybdenum (Mo) film selectively grown on the first via V1 and on the first insulating film 500 by ALD. As a result, the molybdenum (Mo) film selectively grown on the first via V1 and the molybdenum (Mo) film formed thereon constitute the wiring lower layer M22. Note that the two-stage film formation for forming the wiring lower layer M22 is performed consecutively without air-breaking the film formation environment.

[0130] 51, a second conductive film 600, a conductive hard mask layer 601, and an insulating hard mask layer 602 are deposited in this order on the wiring lower layer M22. The deposition of these layers is performed in the same manner as described in the first embodiment with reference to FIG. 10. However, since the second conductive film 600 is a film that constitutes the main layer M20 of the second wiring M2 (see FIGS. 47 to 49), it is deposited using a conductive material different from that of the wiring lower layer M22.

[0131] 52, a resist pattern 603 is formed on the insulating hard mask layer 602. The resist pattern 603 is formed in the same manner as in the first embodiment described with reference to FIG.

[0132] Next, as shown in FIG. 53, using the resist pattern 603 (see FIG. 52) as a mask, the insulating hard mask layer 602, the conductive hard mask layer 601, and the second conductive film 600 are anisotropically dry etched in this order, and the second conductive film 600 is patterned into the shape of the second wiring.

[0133] In particular, the etching of the second conductive film 600 is performed under etching conditions that provide a high selectivity to the wiring lower layer M22. For example, when the wiring lower layer M22 is made of molybdenum (Mo) and the second conductive film 600 is made of ruthenium (Ru), the etching is performed under ... ２ The second conductive film 600 is selectively anisotropically etched by plasma RIE (Reactive Ion Etching) using a fluorine-based etchant. As a result, the etching of the second conductive film 600 is stopped when the etching reaches the wiring lower layer M22.

[0134] Thereafter, as shown in FIG. 54 , etching of the wiring lower layer M22 is performed. At this time, the wiring lower layer M22 is etched so as to remove the wiring lower layer M22 exposed on the upper surface 500a of the first insulating film 500. Furthermore, in the portion where the recess 500b is exposed from the second conductive film 600 in a planar view due to misalignment, the wiring lower layer M22 is etched so as to leave the wiring lower layer M22 on the entire surface of the first via V1 that forms the bottom surface of the recess 500b. Furthermore, etching of the wiring lower layer M22 is performed so that the step [d2] between the upper surface 500a of the first insulating film 500 and the junction M2a of the wiring lower layer M22 is at least half the depth [d1] of the recess 500b and at least 30% of the minimum wiring spacing [s1], as described above. The etching of the wiring lower layer M22 is performed with time control, so that the wiring lower layer M22 remains in the recess 500b. For example, when the wiring lower layer M22 is made of molybdenum (Mo), chlorine gas (Cl ２ ) and oxygen gas (O ２ RIE etching is performed using ) as a base etchant.

[0135] 53 and 54 may be carried out successively. In this case, for example, the resist pattern 603 shown in FIG. 52 is used as a mask, and chlorine gas (Cl ２ ) and oxygen gas (O ２ ) as a base etchant, the second conductive film 600 and the wiring lower layer M22 are successively RIE-etched. In this etching, the etching time may be controlled so as to leave the wiring lower layer M22 in the recessed portion 500b as described above.

[0136] After the above, the same procedures as those described in the first embodiment with reference to Figures 13 to 17 are carried out to obtain the semiconductor device 10 described with reference to Figures 47 to 49. After the above, the steps described with reference to Figure 50 and subsequent steps are repeated to form wiring and vias in upper layers.

[0137] Effect of the Tenth Embodiment According to the tenth embodiment described above, the wiring lower layer M22 of the second wiring M2, which is connected to the first via V1, is made of a conductive material different from that of the main layer M20 of the second wiring M2. This improves the processing accuracy of the second wiring M2. That is, when processing the second wiring M2, the second conductive film 600 constituting the main layer M20 can be etched with a high selectivity relative to the wiring lower layer M22. Furthermore, when etching the second conductive film 600, the wiring lower layer M22 is provided over the entire surface of the first insulating film 500, including over the first via V1 (see FIG. 53 ). Therefore, the exposure of the wiring lower layer M22 can be easily confirmed based on the elemental intensities generated during etching of the second conductive film 600, and the etching endpoint of the second conductive film 600 can be detected with high accuracy. As a result, compared to the ninth embodiment, the etching accuracy of the wiring lower layer M22 after etching the second conductive film 600 can be further improved, and it is possible to leave the wiring lower layer M22 with a predetermined film thickness in the recessed portion 500b above the first via V1.

[0138] The tenth embodiment can be combined with the second to sixth embodiments. In this case, the fourth embodiment includes a combination with the second or third embodiment. When the fifth embodiment shown in FIG. 27 or the sixth embodiment shown in FIG. 28 is combined with the tenth embodiment, the second barrier metal layer 607 in FIGS. 27 and 28 is provided on the upper surface of the wiring lower layer M22.

[0139] Furthermore, the tenth embodiment and combinations of the tenth embodiment with other embodiments can also be applied to the seventh or eighth embodiment. By combining the tenth embodiment with each of these embodiments, it is possible to obtain the effects of these embodiments.

[0140] REFERENCE SIGNS LIST 1, 2, 3, 4, 5, 6, 7, 8, 9, 10...Semiconductor device 100...Semiconductor substrate M1...First wiring (lower layer conductive pattern) M2...Second wiring (upper layer conductive pattern) M2a...Joint portion M20...Main body layer M21...Anchor portion M22...Wiring lower layer V1, V1'...First via (lower layer conductive pattern) V1a...Upper end surface V2...Second via (upper layer conductive pattern) 401...Conductive hard mask layer (sacrificial layer) 407 First barrier metal layer 408 Intermediate barrier metal layer 500...First insulating film 500b, 700b...Recessed recess 500c, 700c...Cavity portion 501...Barrier insulating layer 502...First base barrier insulating layer 600...Second conductive film 607 Second barrier metal layer 608...Intermediate barrier metal layer 700...Second insulating film 702... Second underlying barrier insulating layer [d1]... Depth of recess [d2]... Paragraph [s1]... Minimum wiring spacing (minimum spacing)

Claims

1. A semiconductor device comprising: a plurality of lower-layer conductive patterns formed above a substrate; a first insulating film formed above the substrate and filling spaces between the plurality of lower-layer conductive patterns; a plurality of upper-layer conductive patterns formed on the first insulating film and bonded to the plurality of lower-layer conductive patterns; and a second insulating film formed on the first insulating film and filling spaces between the plurality of upper-layer conductive patterns, wherein a recess is provided from an upper surface of the first insulating film with the upper surface of the lower-layer conductive pattern as a bottom surface, and in a portion where the lower-layer conductive pattern and the upper-layer conductive pattern are misaligned, the upper-layer conductive pattern has a bonding portion within the recess that is located lower than the upper surface of the first insulating film, and the upper-layer conductive pattern is bonded to the lower-layer conductive pattern so as to cover the entire upper surface of the lower-layer conductive pattern.

2. The semiconductor device according to claim 1, wherein the step between the upper surface of said first insulating film and the upper surface of said junction in said upper conductive pattern is 30% or more of the minimum distance between said lower conductive patterns and between said upper conductive patterns.

3. The semiconductor device according to claim 2, wherein the depth of the recess is at least 1 / 3 of the minimum interval.

4. The semiconductor device according to claim 1, further comprising a barrier insulating layer provided on an upper surface of said first insulating film and on a side wall of said recess.

5. The semiconductor device according to claim 1, wherein a first base barrier insulating layer is provided on an underlayer of the first insulating film and on a sidewall of the first insulating film, and a second base barrier insulating layer is provided on an underlayer of the second insulating film and on a sidewall of the second insulating film.

6. The semiconductor device according to claim 1, wherein the first insulating film has a cavity between the lower conductive patterns, and the second insulating film has a cavity between the upper conductive patterns.

7. The semiconductor device according to claim 1, wherein a barrier metal layer is provided under the lower conductive pattern and under the upper conductive pattern.

8. The semiconductor device according to claim 7, wherein the lower conductive pattern and the upper conductive pattern are composed of a wiring and a via thereon, and an intermediate barrier metal layer is provided between the wiring and the via.

9. The semiconductor device according to claim 1, wherein the upper layer conductive pattern is composed of an anchor portion provided within the recess and a main body layer provided on an upper portion of the anchor portion and on the upper surface of the first insulating film, and the anchor portion and the main body layer are made of different conductive materials.

10. The semiconductor device according to claim 1, wherein the upper layer conductive pattern is composed of a wiring lower layer provided within the recess and on the upper surface of the first insulating film, and a main body layer provided on the upper surface of the wiring lower layer, and the wiring lower layer and the main body layer are made of different conductive materials.

11. A method for manufacturing a semiconductor device, comprising the steps of: forming a plurality of lower-layer conductive patterns above a substrate; forming a first insulating film above the substrate filling spaces between the plurality of lower-layer conductive patterns; forming a recess from the upper surface of the first insulating film by recessing and removing an upper portion of the lower-layer conductive pattern exposed on an upper surface of the first insulating film, so as to form a recess having a bottom surface at an upper end surface of the lower-layer conductive pattern; forming a plurality of upper-layer conductive patterns by patterning a conductive film formed on the lower-layer conductive pattern and the first insulating film; and forming a second insulating film on the first insulating film filling spaces between the plurality of upper-layer conductive patterns, wherein in the step of forming the upper-layer conductive pattern, the conductive film is patterned by anisotropic etching until the first insulating film is exposed, and then, in a portion where the lower-layer conductive pattern and the upper-layer conductive pattern are misaligned, the conductive film is further anisotropically etched so that the conductive film remains on the entire upper end surface of the lower-layer conductive pattern within the recess.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the uppermost part of the lower conductive pattern is constituted by a sacrificial layer, and when recessing and removing the upper part of the lower conductive pattern, the sacrificial layer is selectively removed to form the recess to a depth corresponding to a film thickness of the sacrificial layer.

13. A method for manufacturing a semiconductor device as described in claim 11, wherein in the step of forming the upper layer conductive pattern, an anchor portion of the conductive film is formed in the recess by selective growth on the lower layer conductive pattern, and then a main body layer of the conductive film made of a conductive material different from the anchor portion is formed on an upper portion of the anchor portion and on the first insulating film, and the main body layer is etched by etching with a high selectivity to the anchor portion, and then the anchor portion is etched, thereby forming the upper layer conductive pattern.

14. The method for manufacturing a semiconductor device according to claim 11, wherein in the step of forming the upper layer conductive pattern, a wiring underlayer of the conductive film is formed within the recess and on an upper surface of the first insulating film, then a main layer of the conductive film made of a conductive material different from the wiring underlayer is formed, and the main layer is etched by etching with a high selectivity to the wiring underlayer, and then the wiring underlayer is etched, thereby forming the upper layer conductive pattern.

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