Light detection apparatus, electronic device, and method for producing light detection apparatus

Abstract

Provided is a light detection apparatus that makes it possible to decrease chip area. The light detection apparatus comprises a semiconductor layer, a wiring layer, a terminal pad, and an element. The semiconductor layer has a photoelectric conversion unit. One surface of the semiconductor layer is a light entry surface, and the other surface is an element formation surface. The wiring layer is laminated onto the element formation surface of the semiconductor layer. At least part of the terminal pad is positioned at the semiconductor layer. The terminal pad is connected to metal wiring of the wiring layer. The element is disposed between the terminal pad and the wiring layer.

Description

Photodetector, electronic device, and method of manufacturing photodetector

[0001] The technology according to the present disclosure (the present technology) relates to a photodetector, an electronic device including the photodetector, and a method for manufacturing the photodetector.

[0002] In a solid-state imaging device, a certain number of protection elements are usually arranged in a chip corresponding to each terminal pad to protect the semiconductor element from ESD (Electrostatic Discharge), PID (Process Induced Damage), etc. Patent Document 1 discloses a structure in which the emitter region of a protection transistor is electrically connected below the terminal pad.

[0003] Japanese Patent Application Publication No. 10-335627

[0004] Although reduction in chip size is desirable for solid-state imaging devices, a certain number of protection elements are required within a chip, which increases the chip area.

[0005] The present disclosure has been made in view of the above circumstances, and aims to provide a photodetector, an electronic device, and a method for manufacturing a photodetector that are capable of reducing the chip area.

[0006] One aspect of the present disclosure is a photodetector device comprising: a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer stacked on the element formation surface of the semiconductor layer; a terminal pad at least a portion of which is located in the semiconductor layer and connected to metal wiring of the wiring layer; and an element disposed between the terminal pad and the wiring layer.

[0007] Another aspect of the present disclosure is a photodetector device comprising: a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer stacked on the element formation surface of the semiconductor layer; a terminal pad located on the wiring layer side of the element formation surface of the semiconductor layer and connected to metal wiring of the wiring layer; and a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface, wherein an element is placed at a formation position of the pad opening before the pad opening is formed.

[0008] Another aspect of the present disclosure is an electronic device including a photodetector device having: a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer stacked on the element formation surface of the semiconductor layer; a terminal pad at least a portion of which is located in the semiconductor layer and connected to metal wiring of the wiring layer; and an element disposed between the terminal pad and the wiring layer.

[0009] Another aspect of the present disclosure is an electronic device including a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer stacked on the element formation surface of the semiconductor layer; a terminal pad located on the wiring layer side of the element formation surface of the semiconductor layer and connected to metal wiring of the wiring layer; and a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface, the electronic device including a photodetector that positions an element at a formation position of the pad opening before the pad opening is formed.

[0010] Another aspect of the present disclosure is a method for manufacturing a photodetector, comprising: preparing a semiconductor chip having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface, and stacking a wiring layer on the element formation surface of the semiconductor layer; forming a terminal pad in the semiconductor layer, the terminal pad having an upper surface exposed to the outside; and connecting the lower surface of the terminal pad to the metal wiring of the wiring layer by a via so that an element to be placed in the semiconductor layer is located between the lower surface of the terminal pad and the wiring layer.

[0011] Furthermore, another aspect of the present disclosure is a method for manufacturing a photodetector, comprising: preparing a semiconductor chip having a photoelectric conversion unit, one surface of which is a light incident surface and the other surface of which is an element formation surface, and stacking a wiring layer on the element formation surface of a semiconductor layer; forming terminal pads connected to metal wiring of the wiring layer on the wiring layer side of the element formation surface of the semiconductor layer; and forming pad openings that extend from the light incident surface of the semiconductor layer to the terminal pads and expose the terminal pads from the light incident surface; and arranging an element at a formation position of the pad opening before forming the pad opening.

[0012] It is a plan layout diagram schematically showing a configuration example of a solid-state imaging device according to a first embodiment of the present disclosure. It is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present disclosure. It is an equivalent circuit diagram of a pixel unit of a solid-state imaging device according to a first embodiment of the present disclosure. It is a plan view (part 1) showing an example of a schematic structure of a solid-state imaging device according to a comparative example of the first embodiment of the present disclosure. It is a plan view (part 2) showing an example of a schematic structure of a solid-state imaging device according to a comparative example of the first embodiment of the present disclosure. It is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device cut along the line A-A' shown in FIG. 4A. It is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device cut along the line A-A' shown in FIG. 4B. It is a plan view (part 1) showing an example of a schematic structure of a solid-state imaging device according to a first embodiment of the present disclosure. It is a plan view (part 2) showing an example of a schematic structure of a solid-state imaging device according to a first embodiment of the present disclosure. It is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device cut along the line A-A' shown in FIG. 6A. It is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device cut along the line A-A' shown in FIG. 6B. It is a cross-sectional view (part 1) showing the process steps of a manufacturing method of a solid-state imaging device according to a first embodiment of the present disclosure. It is a cross-sectional view (part 2) showing the process steps of a manufacturing method of a solid-state imaging device according to a first embodiment of the present disclosure. It is a cross-sectional view (part 3) showing the process steps of a manufacturing method of a solid-state imaging device according to a first embodiment of the present disclosure. It is a cross-sectional view (part 4) showing the process steps of a manufacturing method of a solid-state imaging device according to a first embodiment of the present disclosure. It is a cross-sectional view (part 5) showing the process steps of a manufacturing method of a solid-state imaging device according to a first embodiment of the present disclosure. It is a cross-sectional view (part 6) showing the process steps of a manufacturing method of a solid-state imaging device according to a first embodiment of the present disclosure. It is a cross-sectional view (part 7) showing the process steps of a manufacturing method of a solid-state imaging device according to a first embodiment of the present disclosure. It is a cross-sectional view (part 8) showing the process steps of a manufacturing method of a solid-state imaging device according to a first embodiment of the present disclosure. It is a plan view (part 1) showing an example of a schematic structure of a solid-state imaging device according to a second embodiment of the present disclosure as seen from the element formation surface. It is a plan view (part 2) showing an example of a schematic structure of a solid-state imaging device according to a second embodiment of the present disclosure as seen from the element formation surface. It is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device cut along the line B-B' shown in FIG. 9A.9B . FIG. 9C is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device taken along line B-B′ shown in FIG. 9B . FIG. 9D is a cross-sectional view (part 1) showing a process procedure of a method for manufacturing a solid-state imaging device according to a second embodiment of the present disclosure. FIG. 9E is a cross-sectional view (part 2) showing a process procedure of a method for manufacturing a solid-state imaging device according to a second embodiment of the present disclosure. FIG. 9F is a cross-sectional view (part 4) showing a process procedure of a method for manufacturing a solid-state imaging device according to a second embodiment of the present disclosure. FIG. 9G is a cross-sectional view (part 5) showing a process procedure of a method for manufacturing a solid-state imaging device according to a second embodiment of the present disclosure. FIG. 9H is a partial cross-sectional view (part 1) showing an example of a schematic structure of a solid-state imaging device according to a third embodiment of the present disclosure. FIG. 9I is a partial cross-sectional view (part 2) showing an example of a schematic structure of a solid-state imaging device according to a fourth embodiment of the present disclosure. FIG. 9I is a partial cross-sectional view (part 1) showing an example of a schematic structure of a solid-state imaging device according to a fourth embodiment of the present disclosure. FIG. 9I is a partial cross-sectional view (part 2) showing an example of a schematic structure of a solid-state imaging device according to a fourth embodiment of the present disclosure. Fig. 19 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device according to a sixth embodiment of the present disclosure. Fig. 20 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device according to a seventh embodiment of the present disclosure. Fig. 21 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device according to an eighth embodiment of the present disclosure. Fig. 22 is a block diagram showing an example of a configuration of an imaging system as an electronic device to which the present technology is applied. Fig. 23 is a block diagram showing an example of a schematic configuration of a vehicle control system which is an example of a mobile body control system to which the technology according to the present disclosure can be applied. Fig. 24 is a diagram showing an example of an installation position of the imaging unit shown in Fig. 19.

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings referred to in the following description, identical or similar parts will be designated by identical or similar reference numerals, and redundant description will be omitted. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0014] In this specification, the "first conductivity type" refers to either p-type or n-type, and the "second conductivity type" refers to either p-type or n-type, which is different from the "first conductivity type." Furthermore, the "+" or "-" attached to "n" or "p" means that the semiconductor region has a relatively high or low impurity density, respectively, compared to a semiconductor region without the "+" or "-" attached. However, even if the semiconductor regions have the same "n" and "n" attached, this does not mean that the impurity densities of the respective semiconductor regions are strictly the same.

[0015] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical concept of the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if it is rotated 180 degrees and observed, up and down are inverted and read as such. Note that the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0016] First Embodiment In this embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described. The solid-state imaging device is an example of a photodetector. Photodetectors include not only solid-state imaging devices but also devices that only detect light, such as distance measuring devices. (Overall Configuration of Solid-State Imaging Device) First, the overall configuration of a solid-state imaging device 1A will be described. As shown in FIG. 1 , the solid-state imaging device 1A according to an embodiment of the present technology is mainly composed of a semiconductor chip 2 that has a rectangular two-dimensional planar shape when viewed from above. In other words, the solid-state imaging device 1A is mounted on the semiconductor chip 2. The solid-state imaging device 1A captures image light from a subject via an optical lens (not shown), converts the amount of incident light focused on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0017] As shown in FIG. 1, a semiconductor chip 2 on which a solid-state imaging device 1A is mounted includes, in a two-dimensional plane including an X direction and a Y direction which are orthogonal to each other, a square-shaped pixel region 2A provided in the center, and a peripheral region 2B arranged outside this pixel region 2A so as to surround the pixel region 2A.

[0018] The pixel region 2A is a light receiving surface that receives light collected by, for example, an optical lens. In the pixel region 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are orthogonal to each other within the two-dimensional plane.

[0019] 1, a plurality of terminal pads 14 are arranged in the peripheral region 2B. The plurality of terminal pads 14 are arranged, for example, along four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of terminal pads 14 is an input / output terminal used when electrically connecting the semiconductor chip 2 to an external device.

[0020] 2 , the semiconductor chip 2 includes a logic circuit 13 including a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 outputs an output voltage (Vout) for each pixel 3 to the outside. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit including, as field effect transistors, for example, a p-channel conductivity type (first conductivity type) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and an n-channel conductivity type (second conductivity type) MOSFET.

[0021] The vertical drive circuit 4 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel region 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion elements of each pixel 3 in accordance with the amount of light received to the column signal processing circuit 5 via vertical signal lines 11.

[0022] The column signal processing circuits 5 are arranged, for example, for each column of pixels 3, and perform signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuits 5 perform signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to each pixel.

[0023] The horizontal drive circuit 6 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0024] The output circuit 7 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0025] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0026] 3 is an equivalent circuit diagram showing an example of the configuration of a pixel 3. The pixel 3 includes a photoelectric conversion element PD, a charge accumulation region (floating diffusion) FD that accumulates (holds) signal charges photoelectrically converted by the photoelectric conversion element PD, and a transfer transistor TR that transfers the signal charges photoelectrically converted by the photoelectric conversion element PD to the charge accumulation region FD. The pixel 3 also includes a readout circuit 15 electrically connected to the charge accumulation region FD.

[0027] The photoelectric conversion element PD generates a signal charge according to the amount of light received. The photoelectric conversion element PD also temporarily accumulates (holds) the generated signal charge. The cathode side of the photoelectric conversion element PD is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground). For example, a photodiode is used as the photoelectric conversion element PD.

[0028] The drain region of the transfer transistor TR is electrically connected to the charge storage region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line among the pixel drive lines 10 (see FIG. 2). The charge retention region FD temporarily holds (accumulates) the signal charge transferred from the photoelectric conversion element PD via the transfer transistor TR.

[0029] The readout circuit 15 reads out the signal charges accumulated in the charge retention region FD and outputs a pixel signal based on the signal charges. The readout circuit 15 includes, but is not limited to, pixel transistors, such as an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. These transistors (AMP, SEL, RST) are field-effect transistors, such as MOSFETs with a silicon oxide (SiO2) film as a gate insulating film. These transistors may also be metal-insulator semiconductor FETs (MISFETs) with a silicon nitride (Si3N4) film or a stacked film of a silicon nitride film and a silicon oxide film as a gate insulating film.

[0030] The amplifier transistor AMP has a source region electrically connected to the drain region of the select transistor SEL, and a drain region electrically connected to the power supply line Vdd1, and a gate electrode of the amplifier transistor AMP is electrically connected to the charge storage region FD and the source region of the reset transistor RST.

[0031] The selection transistor SEL has a source region electrically connected to the vertical signal line 11 (VSL), a drain region electrically connected to the source region of the amplification transistor AMP, and a gate electrode electrically connected to a selection transistor drive line among the pixel drive lines 10 shown in FIG.

[0032] The reset transistor RST has a source region electrically connected to the charge storage region FD and the gate electrode of the amplification transistor AMP, and a drain region electrically connected to the power supply line Vdd2.

[0033] When the transfer transistor TR is turned on, it transfers the signal charge generated by the photoelectric conversion element PD to the charge holding region FD. When the reset transistor RST is turned on, it resets the potential (signal charge) of the charge holding region FD to the potential of the power supply line Vdd2. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 15.

[0034] The amplifier transistor AMP generates a pixel signal having a voltage corresponding to the level of the signal charge held in the charge holding region FD. The amplifier transistor AMP constitutes a source follower amplifier and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated by the photoelectric conversion element PD. When the selection transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the charge holding region FD and outputs a pixel signal corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0035] 4A and 4B are plan views showing an example of a schematic structure of a solid-state imaging device B1 according to a comparative example of the first embodiment of the present disclosure. Also, FIGS. 5A and 5B are partial cross-sectional views showing an example of a schematic structure of the solid-state imaging device B1 taken along line A-A' shown in FIGS. 4A and 4B.

[0036] As shown in FIG. 4A, the solid-state imaging device B1 includes a semiconductor chip B2. The semiconductor chip B2 is configured with a single-crystal silicon substrate of a first conductivity type, for example, p-type. The semiconductor chip B2 has a well region B21 of a second conductivity type, for example, n-type, and a well region B22 of a first conductivity type, for example, p-type. Protection diodes B31 to B33 are disposed in the p-type well region B22. A power supply terminal B34 is provided in the n-type well region B21 for applying a power supply VDD to the protection diodes B31 to B33. Furthermore, the semiconductor chip B2 is provided with a terminal B35 for supplying a reference potential.

[0037] 4B, a terminal pad B14 is provided in an area of ​​the semiconductor chip B2 adjacent to the protection diodes B31 to B33. The upper surface of the terminal pad B14 is exposed through an opening B41.

[0038] 5A , the semiconductor chip B2 includes a semiconductor layer B200 having a first surface S1 and a second surface S2 located opposite to each other, a first wiring layer B300 overlaid on the first surface S1 of the semiconductor layer B200, and a second wiring layer B400 overlaid on a third surface S3, which is the surface of the first wiring layer B300 opposite the surface facing the semiconductor layer B200. This stacked structure can be realized, for example, by stacking the first wiring layer B300 on the first surface S1 of the semiconductor layer B200 and then overlaying and bonding the second wiring layer B400 on the third surface S3 of the first wiring layer B300. The second surface S2, which is one surface of the semiconductor layer B200, is sometimes referred to as the light incident surface or back surface, and the first surface S1, which is the other surface of the semiconductor layer B200, is sometimes referred to as the element formation surface or front surface.

[0039] The semiconductor chip B2 has an element isolation section B210 on the first surface S1 side. The element isolation section B210 is a region that isolates each element including the protection diodes B31 to B33. The first wiring layer B300 is formed with, for example, a metal layer B310 connected to the anode of the protection diode B32, a metal layer B320 connected to the cathode of the protection diode B32, a metal layer B330 connected to the power supply terminal B34, and a metal layer B340 connected to the terminal B35.

[0040] 5B, terminal pads B14 are provided in an area of ​​the semiconductor chip B2 adjacent to the protection diodes B31 to B33. The terminal pads B14 are exposed to the outside from the second surface S2 of the semiconductor chip B2 through openings B41. However, in the solid-state imaging device B1 of the comparative example, an area is required within the semiconductor chip B2 for arranging a certain number of the protection diodes B31 to B33, which increases the chip area.

[0041] 6A and 6B are plan views showing an example of a schematic structure of a solid-state imaging device 1A according to a first embodiment of the present disclosure. Also, FIGS. 7A and 7B are partial cross-sectional views showing an example of a schematic structure of the solid-state imaging device 1A taken along line A-A' shown in FIGS. 6A and 6B.

[0042] As shown in FIG. 6A, the semiconductor chip 2 is composed of a single-crystal silicon substrate of a first conductivity type, e.g., p-type. The semiconductor chip 2 has a well region 21 of a second conductivity type, e.g., n-type, and a well region 22 of a first conductivity type, e.g., p-type. Protection diodes 31-33 are disposed in the p-type well region 22. A power supply terminal 34 is provided in the n-type well region 21 for applying a power supply voltage VDD to the protection diodes 31-33. The semiconductor chip 2 further has a terminal 35 for supplying a reference potential. Note that in addition to the protection diodes 31-33, elements such as transistors that protect the transistors in the semiconductor chip 2 from ESD and PID may also be provided. The semiconductor chip 2 has an isolation region 210 on the first surface S1 side.

[0043] 6B, terminal pads 14 are provided in the regions where the protection diodes 31 to 33 are provided on the semiconductor chip 2. The upper surfaces of the terminal pads 14 are exposed through openings 41 (an example of pad openings).

[0044] 7A , the semiconductor chip 2 includes a semiconductor layer 200 having a first surface S1 and a second surface S2 located opposite to each other, a first wiring layer 300 superimposed on the first surface S1 of the semiconductor layer 200, and a second wiring layer 400 superimposed on a third surface S3, which is the surface of the first wiring layer 300 opposite to the surface facing the semiconductor layer 200. This stacked structure can be realized, for example, by stacking the first wiring layer 300 on the first surface S1 of the semiconductor layer 200 and superimposing and bonding the second wiring layer 400 to the third surface S3 of the first wiring layer 300. The second surface S2, which is one surface of the semiconductor layer 200, is sometimes referred to as the light incident surface or back surface, and the first surface S1, which is the other surface of the semiconductor layer 200, is sometimes referred to as the element formation surface or front surface. The solid-state imaging device 1A is a back-illuminated imaging device (an example of a photodetector) in which the first surface S1 is the front surface and the second surface S2 is the back surface.

[0045] The semiconductor chip 2 has an element isolation section 210 on the first surface S1 side. The element isolation section 210 is a region that isolates each element including the protection diodes 31 to 33. In the first wiring layer 300, for example, a metal layer 310 connected to the anode of the protection diode 32, a metal layer 320 connected to the cathode of the protection diode 32, a metal layer 330 connected to the power supply terminal 34, and a metal layer 340 connected to the terminal 35 are formed.

[0046] (Terminal Pads) As shown in FIG. 7B , the terminal pads 14 are embedded in the semiconductor layer 200, i.e., located closer to the first surface S1 than the second surface S2 of the semiconductor layer 200, and have an upper surface 14a, a lower surface 14b opposite the upper surface 14a, and a via 14c. The upper surface 14a is an exposed surface exposed to the outside through the opening 41. The terminal pads 14 are input / output terminals used to electrically connect the solid-state imaging device 1A to an external device. Therefore, the terminal pads 14 are exposed to the outside. The lower surfaces 14b of the terminal pads 14 are connected to the via 14c. The terminal pads 14 are made of a conductive material such as aluminum.

[0047] A plurality of vias 14c are provided. More specifically, two vias 14c are provided. The vias 14c are embedded in the semiconductor layer 200 and electrically connect the terminal pad 14 to a metal layer 352 (described later). One end of the via 14c penetrates the semiconductor layer 200 and is connected to the lower surface 14b of the terminal pad 14. The other end of the via 14c extends in the thickness direction of the semiconductor layer 200, passing through the n-type well region 21 and p-type well region 22 that constitute the protection diodes 31 to 33 and the element isolation portion 210, and into the first wiring layer 300. The via 14c is then connected to a metal layer 352 in the first wiring layer 300. Here, the metal layer 352 to which the other end of the via 14c is connected is referred to as a metal layer 352a to distinguish it from the other metal layers 352. Therefore, the protection diodes 31 to 33 are located between the lower surface 14b of the terminal pad 14 and the metal layer 352a.

[0048] 7B , the first wiring layer 300 further includes an interlayer insulating film 351, a metal layer 352 (an example of metal wiring), a first connection pad 353, and a via 354. The metal layer 352 and the first connection pad 353 are stacked with the interlayer insulating film 351 interposed therebetween as shown. The via 354 connects the metal layers 352 to each other and connects the metal layer 352 to the first connection pad 353.

[0049] (Second Wiring Layer) As shown in FIG. 7B , the second wiring layer 400 includes an interlayer insulating film 411, a metal layer 412, a second connection pad 413, and a via 414. The metal layer 412 and the second connection pad 413 are stacked with the interlayer insulating film 411 interposed therebetween. The via 414 connects the metal layers 412 to each other and to the second connection pad 413. The second connection pad 413 is bonded to the first connection pad 353. This electrically connects the terminal pad 14 to the metal layer 412 of the second wiring layer 400. As shown in FIG. 7B , the terminal pad 14, the first connection pad 353, and the second connection pad 413 overlap in the thickness direction of the semiconductor chip 2. The second wiring layer 400 may include a logic substrate on which the logic circuit 13 is formed. The logic substrate includes, for example, the logic circuit 13, such as the control circuit 8 that controls the operation of each pixel 3.

[0050] <Method of Manufacturing Solid-State Imaging Device> Hereinafter, a method of manufacturing the solid-state imaging device 1A according to the first embodiment of the present disclosure will be described with reference to FIGS. 8A to 8H. FIGS. 8A to 8H are cross-sectional views showing the process steps of the method of manufacturing the solid-state imaging device 1A according to the first embodiment of the present disclosure. Note that the solid-state imaging device 1A is manufactured using various types of apparatus, such as a film formation apparatus (including a CVD (Chemical Vapor Deposition) apparatus and a sputtering apparatus), an ion implantation apparatus, a heat treatment apparatus, an etching apparatus, a CMP (Chemical Mechanical Polishing) apparatus, and a bonding apparatus. Hereinafter, these apparatuses will be collectively referred to as manufacturing apparatuses.

[0051] 8A, a substrate 51 is prepared in which a semiconductor layer 200, a first wiring layer 300, and a second wiring layer 400 are stacked in that order. An n-type well region 21, a p-type well region 22, an element isolation portion 210, and the like are already formed in the semiconductor layer 200. A first connection pad 353 and a second connection pad 413 are then bonded to each other.

[0052] Next, as shown in Fig. 8B, the manufacturing equipment forms openings 52 by etching on second surface S2 of semiconductor layer 200. Next, as shown in Fig. 8C, the manufacturing equipment forms openings 53 and 54 by etching from opening 52 to element isolation portion 210. Then, as shown in Fig. 8D, the manufacturing equipment fills openings 52, 53, and 54 with oxide film 55.

[0053] 8E, the manufacturing equipment etches the oxide film 55 to form an opening 56 for forming the terminal pad 14 and the via 14c therefor. At this time, the opening 56 penetrates the element isolation portion 210 and reaches the metal layer 320 of the first wiring layer 300. Next, as shown in FIG. 8F, the manufacturing equipment patterns aluminum, for example, in the opening 56 to form the terminal pad 14.

[0054] Next, as shown in Fig. 8G, the manufacturing equipment fills in the areas where the aluminum was not filled with oxide film 57. Next, as shown in Fig. 8H, the manufacturing equipment etches oxide film 57 to form openings 41 that expose upper surfaces 14a of terminal pads 14 to the outside.

[0055] <Effects of the First Embodiment> As described above, according to the first embodiment, by arranging the protection diodes 31 to 33 between the lower surface 14b of the terminal pad 14 and the first wiring layer 300, it is not necessary to secure an area for a certain number of protection diodes 31 to 33 in the semiconductor chip 2 separately from the terminal pad 14, thereby making it possible to reduce the chip area. Furthermore, by providing the terminal pad 14 in the semiconductor layer 200, wire bonding can be easily performed. Note that the terminal pad 14 may have a structure in which a portion is embedded in the semiconductor layer 200 and another portion protrudes above the semiconductor layer 200.

[0056] Second Embodiment Figures 9A and 9B are plan views showing an example of a schematic structure of a solid-state imaging device 1B according to a second embodiment of the present disclosure, as viewed from the element formation surface. Also, Figures 10A and 10B are partial cross-sectional views showing an example of a schematic structure of the solid-state imaging device 1B taken along line B-B' shown in Figures 9A and 9B. In Figures 9A and 9B, the same parts as those in Figures 6A and 6B are designated by the same reference numerals, and detailed descriptions thereof will be omitted. Also, in Figures 10A and 10B, the same parts as those in Figures 7A and 7B are designated by the same reference numerals, and detailed descriptions thereof will be omitted.

[0057] 9A, the semiconductor chip 60 of the solid-state imaging device 1B is made of a single-crystal silicon substrate of a second conductivity type, for example, n-type. The semiconductor chip 60 has a well region 61 of a first conductivity type, for example, p-type. The semiconductor chip 60 is provided with a power supply terminal 34 for applying a power supply VDD to the protection diodes 31 to 33. The cathodes of the protection diodes 31 to 33 are surrounded by a plurality of vias 354 of the first wiring layer 300, which will be described later.

[0058] 9B, a terminal pad 71 is provided in the region where the protection diodes 31 to 33 are provided on the semiconductor chip 60. An upper surface 71a of the terminal pad 71 is exposed by an opening 72 (an example of a pad opening).

[0059] 10A , the semiconductor chip 60 includes a semiconductor layer 200 having a first surface S1 and a second surface S2 located opposite to each other, a first wiring layer 300 superimposed on the first surface S1 of the semiconductor layer 200, and a second wiring layer 400 superimposed on a third surface S3, which is the surface of the first wiring layer 300 opposite to the surface facing the semiconductor layer 200. Such a stacked structure can be realized, for example, by stacking the first wiring layer 300 on the first surface S1 of the semiconductor layer 200 and superimposing and bonding the second wiring layer 400 to the third surface S3 of the first wiring layer 300. Furthermore, the second surface S2, which is one surface of the semiconductor layer 200, is sometimes referred to as the light incident surface or back surface, and the first surface S1, which is the other surface of the semiconductor layer 200, is sometimes referred to as the element forming surface or front surface.

[0060] An element isolation portion 210 is provided on the first surface S1 side of the semiconductor chip 60. In the first wiring layer 300, for example, a metal layer 310 connected to the anode of the protection diode 32, a metal layer 320 connected to the cathode of the protection diode 32, and a metal layer 330 connected to the power supply terminal 34 are formed.

[0061] The first wiring layer 300 further includes an interlayer insulating film 351, a metal layer 352 (an example of metal wiring), and a via 354. As shown in the figure, the metal layer 352 is stacked with the interlayer insulating film 351 interposed therebetween. The via 354 connects the metal layers 352 to each other.

[0062] The second wiring layer 400 includes a terminal pad 71, an interlayer insulating film 411, a metal layer 412, and a via 414. The terminal pad 71 and the metal layer 412 are stacked with the interlayer insulating film 411 interposed as shown. The via 414 connects the metal layers 412 to each other and between the metal layer 412 and the terminal pad 71. This electrically connects the terminal pad 71 to the metal layer 412 of the second wiring layer 400. The second wiring layer 400 may include a logic substrate on which a logic circuit is formed. The logic substrate includes, for example, a pixel control circuit that controls the operation of each pixel 3, a front-end circuit that realizes quenching and recharging of each pixel 3, and the like.

[0063] 10B , the terminal pad 71 is provided as a metal layer 412 in the second wiring layer 400, and has an upper surface 71a and a lower surface 71b opposite to the upper surface 71a. The upper surface 71a is an exposed surface exposed to the outside through the opening 72. The terminal pad 71 is an input / output terminal used to electrically connect the solid-state imaging device 1B to an external device. Therefore, the terminal pad 71 is exposed to the outside. The lower surface 71b of the terminal pad 71 is connected to the via 414. The via 414 electrically connects the terminal pad 71 and the metal layer 412.

[0064] 10B, the opening 72 is formed from the second surface S2 of the semiconductor layer 200, i.e., the light incident surface, to the terminal pad 71 of the second wiring layer 400. The protection diodes 31 to 33 are disposed at the formation position of this opening 72. After the formation of this opening 72, the protection diodes 31 to 33 disappear.

[0065] <Method of Manufacturing Solid-State Imaging Device> Hereinafter, a method of manufacturing the solid-state imaging device 1B according to the second embodiment of the present disclosure will be described with reference to FIGS. 11A to 11E. FIGS. 11A to 11E are cross-sectional views showing the process steps of the method of manufacturing the solid-state imaging device 1B according to the second embodiment of the present disclosure. Note that the solid-state imaging device 1B is manufactured using various types of apparatus, such as a film formation apparatus (including a CVD (Chemical Vapor Deposition) apparatus and a sputtering apparatus), an ion implantation apparatus, a heat treatment apparatus, an etching apparatus, a CMP (Chemical Mechanical Polishing) apparatus, and a bonding apparatus. Hereinafter, these apparatuses will be collectively referred to as manufacturing apparatuses.

[0066] First, as shown in Fig. 11A, a semiconductor chip 60 including only a semiconductor layer 200 is prepared. Next, as shown in Fig. 11B, a manufacturing apparatus forms a p-type well region 61 and an element isolation portion 210 in the semiconductor layer 200 of the semiconductor chip 60.

[0067] 11C , the manufacturing equipment stacks a first wiring layer 300 on the surface of the semiconductor layer 200 where the element isolation portion 210 is formed. At this time, an interlayer insulating film 351, a metal layer 352, and a via 354 are formed in the first wiring layer 300. In the process of forming the metal layer 352 and the via 354, plasma charges generated may cause PID (Process Induced Damage), which causes gate failure of a transistor. To protect the solid-state imaging device 1B from this PID, for example, a protection diode 32 is disposed in the arrangement region of the terminal pad 71, and, for example, a metal layer 310 connected to the anode of the protection diode 32, a metal layer 320 connected to the cathode of the protection diode 32, and a metal layer 330 connected to the power supply terminal 34 are formed in the first wiring layer 300.

[0068] Next, as shown in FIG. 11D, the manufacturing equipment stacks a second wiring layer 400 on the upper surface of the support substrate 73, inverts the semiconductor chip 60 from the state shown in FIG. 11C, and bonds the first connection pad 353 of the first wiring layer 300 to the second connection pad 413 of the second wiring layer 400.

[0069] 11E, the manufacturing equipment forms an opening 72 from the second surface S2 of the semiconductor layer 200, i.e., the light incident surface, to the terminal pad 71 of the second wiring layer 400, thereby exposing the upper surface 71a of the terminal pad 71 to the outside. With the formation of this opening 72, the protection diodes 31 to 33 arranged in the semiconductor layer 200 disappear.

[0070] <Effects of Second Embodiment> As described above, according to the second embodiment, when the terminal pad 71 is located on the second wiring layer 400, until the opening 72 is formed to expose the terminal pad 71 from the second surface S2 of the semiconductor layer 200, i.e., the light incident surface, the protection diodes 31 to 33 are disposed at the formation position of the opening 72. This makes it possible to protect other elements in the semiconductor layer 200 from ESD, PID, and the like until the opening 72 is formed, and also eliminates the need to secure an area for a certain number of protection diodes 31 to 33 in the semiconductor layer 200 separately from the terminal pad 71, thereby enabling a reduction in the chip area.

[0071] 12 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device 1C according to a third embodiment of the present disclosure. In Fig. 12, the same parts as those in Fig. 7B and Fig. 10A are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0072] The semiconductor chip 60 of the solid-state imaging device 1C is made of a single-crystal silicon substrate of a second conductivity type, for example, n-type. The semiconductor chip 60 has a well region 61 of a first conductivity type, for example, p-type. The semiconductor chip 60 is provided with a power supply terminal 34 for applying a power supply VDD to the protection diodes 31 to 33.

[0073] The terminal pads 14 are embedded in the semiconductor layer 200, i.e., located closer to the first surface S1 than the second surface S2 of the semiconductor layer 200, and have an upper surface 14a, a lower surface 14b opposite the upper surface 14a, and vias 14c. The upper surface 14a is an exposed surface exposed to the outside through the openings 41. The terminal pads 14 are input / output terminals used to electrically connect the solid-state imaging device 1A to an external device. Therefore, the terminal pads 14 are exposed to the outside. The lower surfaces 14b of the terminal pads 14 are connected to the vias 14c.

[0074] A plurality of vias 14c are provided. More specifically, two vias 14c are provided. The vias 14c are embedded in the semiconductor layer 200 and electrically connect the terminal pad 14 and the metal layer 352. One end of the via 14c penetrates the semiconductor layer 200 and is connected to the lower surface 14b of the terminal pad 14. The other end of the via 14c extends in the thickness direction of the semiconductor layer 200, passing through the n-type well region 21 and the p-type well region 22 that constitute the protection diodes 31 to 33 and the element isolation portion 210, and into the first wiring layer 300. The via 14c is then connected to a metal layer 352 in the first wiring layer 300. Here, the metal layer 352 to which the other end of the via 14c is connected is referred to as a metal layer 352a to distinguish it from the other metal layers 352. Therefore, the protection diodes 31 to 33 are located between the lower surface 14b of the terminal pad 14 and the metal layer 352a.

[0075] <Operational Effects of Third Embodiment> As described above, the third embodiment also provides the same operational effects as the first embodiment.

[0076] 13A and 13B are partial cross-sectional views showing an example of a schematic structure of a solid-state imaging device 1D according to a fourth embodiment of the present disclosure. In Fig. 13A and Fig. 13B, the same parts as those in Fig. 10A and Fig. 10B are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0077] 13A, the semiconductor chip 2 of the solid-state imaging device 1D is made of a single-crystal silicon substrate of a first conductivity type, for example, p-type. The semiconductor chip 2 has a well region 21 of a second conductivity type, for example, n-type, and a well region 22 of the first conductivity type, for example, p-type. Protection diodes 31 to 33 are disposed in the p-type well region 22. A power supply terminal 34 is provided in the n-type well region 21 for applying a power supply VDD to the protection diodes 31 to 33. Furthermore, the semiconductor chip 2 is provided with a terminal 35 for supplying a reference potential.

[0078] In the first wiring layer 300, for example, a metal layer 310 connected to the anode of the protection diode 32, a metal layer 320 connected to the cathode of the protection diode 32, a metal layer 330 connected to the power supply terminal 34, and a metal layer 340 connected to the terminal 35 are formed.

[0079] 13B , the terminal pad 71 is provided as a metal layer 412 in the second wiring layer 400, and has an upper surface 71a and a lower surface 71b opposite to the upper surface 71a. The upper surface 71a is an exposed surface exposed to the outside through the opening 72. The terminal pad 71 is an input / output terminal used to electrically connect the solid-state imaging device 1B to an external device. Therefore, the terminal pad 71 is exposed to the outside. The lower surface 71b of the terminal pad 71 is connected to the via 414. The via 414 electrically connects the terminal pad 71 and the metal layer 412.

[0080] 13B, the opening 72 is formed from the second surface S2 of the semiconductor layer 200, i.e., the light incident surface, to the terminal pad 71 of the second wiring layer 400. The protection diodes 31 to 33 are disposed at the formation position of this opening 72. After the formation of this opening 72, the protection diodes 31 to 33 disappear.

[0081] <Operational Effects of Fourth Embodiment> As described above, the fourth embodiment also provides the same operational effects as the second embodiment.

[0082] 14A and 14B are partial cross-sectional views showing an example of a schematic structure of a solid-state imaging device 1E according to a fifth embodiment of the present disclosure. In Fig. 14A and Fig. 14B, the same parts as those in Fig. 7A and Fig. 7B are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0083] As shown in FIG. 14A, the semiconductor chip 2 of the solid-state imaging device 1E comprises a semiconductor layer 200 having a first surface S1 and a second surface S2 located on opposite sides of each other, and a first wiring layer 300 superimposed on the first surface S1 of the semiconductor layer 200.

[0084] As shown in FIG. 14B, the terminal pad 14 is embedded in the semiconductor layer 200, i.e., is located closer to the first surface S1 than the second surface S2 of the semiconductor layer 200, and has an upper surface 14a, a lower surface 14b which is the surface opposite to the upper surface 14a, and a via 14c.

[0085] <Operational Effects of Fifth Embodiment> As described above, the fifth embodiment also provides the same operational effects as the first embodiment.

[0086] 15 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device 1F according to a sixth embodiment of the present disclosure. In Fig. 15, the same parts as those in Fig. 7B are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0087] 15 , the semiconductor chip 2 includes a semiconductor layer 200 having a first surface S1 and a second surface S2 located opposite to each other, a first wiring layer 300 superimposed on the first surface S1 of the semiconductor layer 200, a second wiring layer 400 superimposed on a third surface S3, which is the surface of the first wiring layer 300 opposite to the surface facing the semiconductor layer 200, and a third wiring layer 500 superimposed on a fourth surface S4, which is the surface of the second wiring layer 400 opposite to the third surface S3. Such a stacked structure can be realized, for example, by stacking the first wiring layer 300 on the first surface S1 of the semiconductor layer 200, superimposing and bonding the second wiring layer 400 to the third surface S3 of the first wiring layer 300, and superimposing and bonding the third wiring layer 500 to the fourth surface S4 of the second wiring layer 400.

[0088] 15 , the third wiring layer 500 includes an interlayer insulating film 511, a metal layer 512, and a via 513. The metal layer 512 is stacked with the interlayer insulating film 511 interposed therebetween as shown. The via 513 connects the metal layers 512 to each other. The metal layer 512 is joined to the metal layer 412 of the second wiring layer 400 by a through via 81 made of a conductive material. This electrically connects the terminal pad 14 to the metal layer 512 of the third wiring layer 500. The terminal pad 14, the first connection pad 353, and the second connection pad 413 overlap in the thickness direction of the semiconductor chip 2, but the terminal pad 14 and the through via 81 do not overlap in the thickness direction of the semiconductor chip 2.

[0089] (First Substrate) As shown in FIG. 15 , the second wiring layer 400 has a first substrate 415. The first substrate 415 is, for example, a second-stage pixel substrate or a logic substrate on which a logic circuit such as the control circuit 8 is formed. The first substrate 415 is located on the fourth surface S4 side and is composed of a semiconductor substrate of a first conductivity type, for example, p-type. The first substrate 415 is provided with an element isolation portion 416 that isolates a plurality of transistors and the like from other elements. Furthermore, the first substrate 415 is electrically connected to the metal layer 412 by vias 414.

[0090] 15 , the third wiring layer 500 includes a second substrate 514 on which a logic circuit such as the column signal processing circuit 5 is formed. The second substrate 514 is located on the surface opposite the fourth surface and is made of a semiconductor substrate of a first conductivity type, for example, a p-type. The second substrate 514 is provided with an element isolation portion 515 that isolates a plurality of transistors and the like from other elements. Furthermore, the second substrate 514 is electrically connected to the metal layer 512 by vias 513.

[0091] <Effects of the Sixth Embodiment> As described above, the sixth embodiment also provides the same effects as the first embodiment. Furthermore, according to the sixth embodiment, various circuits such as the column signal processing circuit 5 and the control circuit 8 that constitute the logic circuit 13 can be arranged in the thickness direction of the semiconductor chip 2, thereby reducing the overall area of ​​the solid-state imaging device 1F.

[0092] 16 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device 1G according to a seventh embodiment of the present disclosure. In Fig. 16, the same parts as those in Fig. 15 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0093] 16 , the third wiring layer 500 includes an interlayer insulating film 511, a metal layer 512, a via 513, and a third connection pad 516. The metal layer 512 and the third connection pad 516 are stacked with the interlayer insulating film 511 interposed therebetween as shown. The via 513 connects the metal layers 512 to each other and between the metal layer 512 and the third connection pad 516. The third connection pad 516 is joined to the second connection pad 413. As a result, the terminal pad 14 is electrically connected to the metal layer 512 of the third wiring layer 500.

[0094] The first substrate 415 is located on the third surface S3 side. The through via 81 joins the metal layer 352 of the first wiring layer 300 and the metal layer 412 of the second wiring layer 400. At this time, the through via 81 penetrates the first substrate 415.

[0095] <Operational Effects of Seventh Embodiment> As described above, the seventh embodiment also provides the same operational effects as the sixth embodiment.

[0096] 17 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device 1H according to an eighth embodiment of the present disclosure. In Fig. 17, the same parts as those in Figs. 13B and 15 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0097] 17 , the terminal pad 71 is provided as a metal layer 412 in the second wiring layer 400, and has an upper surface 71a and a lower surface 71b opposite to the upper surface 71a. The upper surface 71a is an exposed surface exposed to the outside through an opening 72. The metal layer 512 of the third wiring layer 500 is joined to the metal layer 412 of the second wiring layer 400 by a through via 81 made of a conductive material. This electrically connects the terminal pad 71 to the metal layer 512 of the third wiring layer 500.

[0098] <Effects of the Eighth Embodiment> As described above, the eighth embodiment can also achieve the same effects as the second embodiment. Furthermore, according to the eighth embodiment, various circuits such as the column signal processing circuit 5 and the control circuit 8 that constitute the logic circuit 13 can be arranged in the thickness direction of the semiconductor chip 2, thereby reducing the overall area of ​​the solid-state imaging device 1H.

[0099] <Other Embodiments> As described above, the present technology has been described using the first to eighth embodiments. However, the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Upon understanding the gist of the technical content disclosed in the first to eighth embodiments, it will be apparent to those skilled in the art that various alternative embodiments, examples, and operational techniques may be included in the present technology. Furthermore, the configurations disclosed in the first to eighth embodiments may be appropriately combined within a range that does not cause contradictions. For example, configurations disclosed in multiple different embodiments may be combined, or configurations disclosed in multiple different variations of the same embodiment may be combined.

[0100] <Application Example to Electronic Devices> The above-described solid-state imaging device can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, and other devices with imaging functions. Fig. 18 is a block diagram showing a configuration example of an imaging system as an electronic device to which the present technology is applied.

[0101] The imaging system 2201 shown in Figure 18 is configured with an optical system 2202, a shutter device 2203, a solid-state imaging element 2204 as a solid-state imaging device, a control circuit 2205, a signal processing circuit 2206, a monitor 2207, and two memories 2208, and is capable of capturing still images and moving images.

[0102] The optical system 2202 is configured with one or more lenses, and guides light (incident light) from a subject to the solid-state image sensor 2204, forming an image on the light receiving surface of the solid-state image sensor 2204. The shutter device 2203 is disposed between the optical system 2202 and the solid-state image sensor 2204, and controls the light irradiation period and light blocking period of the solid-state image sensor 2204 under the control of the control circuit 2205.

[0103] The solid-state imaging element 2204 is configured by a package including the above-mentioned solid-state imaging element. The solid-state imaging element 2204 accumulates signal charges for a certain period of time in response to light that is imaged on the light-receiving surface via the optical system 2202 and the shutter device 2203. The signal charges accumulated in the solid-state imaging element 2204 are transferred in accordance with a drive signal (timing signal) supplied from the control circuit 2205.

[0104] The control circuit 2205 outputs a drive signal that controls the transfer operation of the solid-state image sensor 2204 and the shutter operation of the shutter device 2203 , thereby driving the solid-state image sensor 2204 and the shutter device 2203 .

[0105] The signal processing circuit 2206 performs various signal processing on the signal charges output from the solid-state imaging element 2204. The image (image data) obtained by performing the signal processing by the signal processing circuit 2206 is supplied to a monitor 2207 for display, or supplied to a memory 2208 for storage (recording). In the imaging system 2201 configured in this manner, the solid-state imaging devices 1A to 1H can also be applied in place of the solid-state imaging element 2204 described above.

[0106] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0107] Fig. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 also includes a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0108] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0109] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0110] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0111] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0112] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0113] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0114] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0115] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0116] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 19, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0117] 20 is a diagram showing an example of the installation position of the image capturing unit 12031. In FIG. 20, a vehicle 12100 has image capturing units 12101, 12102, 12103, 12104, and 12105 as the image capturing unit 12031.

[0118] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0119] 20 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0120] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0121] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0122] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0123] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0124] The present disclosure may also be configured as follows. (1) A photodetector comprising: a semiconductor layer having a photoelectric conversion unit, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer stacked on the element formation surface of the semiconductor layer; a terminal pad at least a portion of which is located in the semiconductor layer and connected to metal wiring of the wiring layer; and an element arranged between the terminal pad and the wiring layer. (2) The photodetector according to (1), wherein the element is a protection diode that protects another element arranged in the semiconductor layer. (3) The photodetector according to (1), wherein the semiconductor layer is used in a back-illuminated photodetector in which the element formation surface is the front surface and the light incident surface is the back surface. (4) The photodetector according to (1), wherein the terminal pad is located closer to the element formation surface than the light incident surface of the semiconductor layer. (5) The photodetector according to (1), wherein a plurality of the wiring layers are stacked. (6) The photodetector according to (5), wherein the plurality of wiring layers include a first wiring layer stacked on the element formation surface of the semiconductor layer, and a second wiring layer stacked on a surface of the first wiring layer opposite to the surface on the semiconductor layer side, and the second wiring layer has a substrate on which a logic circuit is formed. (7) The photodetector according to (5), wherein the plurality of wiring layers include a first wiring layer stacked on the element formation surface of the semiconductor layer, a second wiring layer stacked on a surface of the first wiring layer opposite to the surface on the semiconductor layer side, and a third wiring layer stacked on a surface of the second wiring layer opposite to the surface on the first wiring layer side, and the second wiring layer has a first substrate on which a first logic circuit is formed, and the third wiring layer has a second substrate on which a second logic circuit is formed. (8) A photodetector comprising: a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer laminated on the element formation surface of the semiconductor layer; a terminal pad located on the wiring layer side of the element formation surface of the semiconductor layer and connected to metal wiring of the wiring layer; and a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface; and an element is placed at the formation position of the pad opening before the pad opening is formed.(9) The photodetector according to (8), wherein the element is a protection diode that protects other elements disposed in the semiconductor layer. (10) The photodetector according to (8), wherein the semiconductor layer is used in a back-illuminated photodetector in which the element formation surface is a front surface and the light incident surface is a back surface. (11) The photodetector according to (8), wherein the wiring layer is stacked in multiple layers. (12) The photodetector according to (11), wherein the multiple wiring layers include: a first wiring layer stacked on the element formation surface of the semiconductor layer; and a second wiring layer stacked on a surface of the first wiring layer opposite to the surface facing the semiconductor layer, and the second wiring layer has a substrate on which a logic circuit is formed. (13) The photodetector according to (12), wherein the terminal pad is located on the second wiring layer. (14) The photodetector according to (11), wherein the plurality of wiring layers include: a first wiring layer stacked on an element formation surface of the semiconductor layer; a second wiring layer stacked on a surface of the first wiring layer opposite to the surface on the semiconductor layer side; and a third wiring layer stacked on a surface of the second wiring layer opposite to the surface on the first wiring layer side, wherein the second wiring layer has a first substrate on which a first logic circuit is formed, and the third wiring layer has a second substrate on which a second logic circuit is formed. (15) The photodetector according to (14), wherein the terminal pad is located on the second wiring layer. (16) An electronic device comprising a photodetector including: a semiconductor layer having a photoelectric conversion unit, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer stacked on the element formation surface of the semiconductor layer; a terminal pad at least a portion of which is located in the semiconductor layer and connected to metal wiring of the wiring layer; and an element disposed between the terminal pad and the wiring layer.(17) An electronic device comprising a photodetector comprising: a semiconductor layer having a photoelectric conversion unit, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer laminated on the element formation surface of the semiconductor layer; a terminal pad located on the wiring layer side of the element formation surface of the semiconductor layer and connected to metal wiring of the wiring layer; and a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface, wherein an element is disposed at a formation position of the pad opening before the pad opening is formed. (18) A method for manufacturing a photodetector comprising: preparing a semiconductor chip in which a wiring layer is laminated on the element formation surface of a semiconductor layer having a photoelectric conversion unit, one surface of which is a light incident surface and the other surface of which is an element formation surface; forming a terminal pad connected to the metal wiring of the wiring layer in the semiconductor layer; (19) A method for manufacturing a photodetector, comprising: preparing a semiconductor chip having a photoelectric conversion unit, one surface of which is a light incident surface and the other surface of which is an element forming surface, and stacking a wiring layer on the element forming surface of the semiconductor layer; forming terminal pads connected to metal wiring of the wiring layer on the wiring layer side of the element forming surface of the semiconductor layer; and forming pad openings that reach the light incident surface of the semiconductor layer and expose the terminal pads from the light incident surface, wherein an element is disposed at a formation position of the pad opening before forming the pad opening.

[0125] 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, B1 Solid-state imaging device 2, 60 Semiconductor chip 2A Pixel region 2B Peripheral region 3 Pixel 4 Vertical drive circuit 5 Column signal processing circuit 6 Horizontal drive circuit 7 Output circuit 8 Control circuit 10 Pixel drive line 11 Vertical signal line 12 Horizontal signal line 13 Logic circuit 14, 71 Terminal pad 15 Readout circuit 14a, 71a Upper surface 14b, 71b Lower surface 14c Via 21, 22, 61 Well region 31, 32, 33 Protection diode 34 Power supply terminal 35 Terminal 41, 52, 53, 54, 56, 72 Opening 51 Substrate 55, 57 Oxide film 73 Support substrate 81 Through via 200 Semiconductor layer 210, 416, 515 Element isolation section 300 First wiring layer 310, 320, 330, 340, 352, 352a, 412, 512 Metal layer 351, 411, 511 Interlayer insulating film 353 First connection pad 354, 414, 513 Via 400 Second wiring layer 413 Second connection pad 415 First substrate 500 Third wiring layer 514 Second substrate 516 Third connection pad 2201 Imaging system 2202 Optical system 2203 Shutter device 2204 Solid-state imaging element 2205 Control circuit 2206 Signal processing circuit 2207 Monitor 2208 Memory 12000 Vehicle control system 12001 Communication network 12010 Drive system control unit 12020 Body system control unit 12030 Outside vehicle information detection unit 12031 Imaging unit 12040 Inside vehicle information detection unit 12041 Driver state detection unit 12050 Integrated control unit 12051 Microcomputer 12052 Audio and image output unit 12061 Audio speaker 12062 Display unit 12063 Instrument panel 12100 Vehicle 12101 to 12105 Imaging units 12111 to 12114 Imaging range

Claims

1. A photodetector comprising: a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer laminated on the element formation surface of the semiconductor layer; a terminal pad, at least a portion of which is located in the semiconductor layer and connected to metal wiring of the wiring layer; and an element disposed between the terminal pad and the wiring layer.

2. The photodetector device according to claim 1, wherein the element is a protection diode for protecting other elements disposed in the semiconductor layer.

3. The photodetector according to claim 1, wherein the semiconductor layer is used in a back-illuminated photodetector in which the element formation surface is the front surface and the light incidence surface is the back surface.

4. The photodetector according to claim 1, wherein the terminal pad is located closer to the element formation surface side than the light incident surface of the semiconductor layer.

5. The photodetector according to claim 1, wherein the wiring layer is laminated in multiple layers.

6. The photodetector device described in claim 5, wherein the plurality of wiring layers comprise a first wiring layer laminated on an element formation surface of the semiconductor layer, and a second wiring layer laminated on a surface of the first wiring layer opposite the surface on the semiconductor layer side, and the second wiring layer has a substrate on which a logic circuit is formed.

7. The photodetector device of claim 5, wherein the plurality of wiring layers comprise: a first wiring layer stacked on an element formation surface of the semiconductor layer; a second wiring layer stacked on a surface of the first wiring layer opposite to the surface facing the semiconductor layer; and a third wiring layer stacked on a surface of the second wiring layer opposite to the surface facing the first wiring layer, wherein the second wiring layer has a first substrate on which a first logic circuit is formed, and the third wiring layer has a second substrate on which a second logic circuit is formed.

8. A photodetector comprising: a semiconductor layer having a photoelectric conversion portion, one surface being a light incident surface and the other surface being an element formation surface; a wiring layer laminated on the element formation surface of the semiconductor layer; a terminal pad located on the wiring layer side of the element formation surface of the semiconductor layer and connected to metal wiring of the wiring layer; and a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface, wherein an element is placed at the formation position of the pad opening before the pad opening is formed.

9. The photodetector device according to claim 8, wherein the element is a protection diode for protecting other elements disposed in the semiconductor layer.

10. The photodetector according to claim 8, wherein the semiconductor layer is used in a back-illuminated photodetector in which the element formation surface is the front surface and the light incidence surface is the back surface.

11. The photodetector according to claim 8, wherein the wiring layer is formed by laminating a plurality of layers.

12. The photodetector device described in claim 11, wherein the plurality of wiring layers comprise a first wiring layer stacked on an element formation surface of the semiconductor layer, and a second wiring layer stacked on a surface of the first wiring layer opposite the surface facing the semiconductor layer, and the second wiring layer has a substrate on which a logic circuit is formed.

13. The photodetector device of claim 12, wherein the terminal pad is located on the second wiring layer.

14. The photodetector device described in claim 11, wherein the multiple wiring layers comprise: a first wiring layer stacked on an element formation surface of the semiconductor layer; a second wiring layer stacked on a surface of the first wiring layer opposite to the semiconductor layer side; and a third wiring layer stacked on a surface of the second wiring layer opposite to the first wiring layer side, wherein the second wiring layer has a first substrate on which a first logic circuit is formed, and the third wiring layer has a second substrate on which a second logic circuit is formed.

15. The photodetector device of claim 14, wherein the terminal pad is located on the second wiring layer.

16. An electronic device comprising a photodetector including: a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer stacked on the element formation surface of the semiconductor layer; a terminal pad, at least a portion of which is located in the semiconductor layer and connected to the metal wiring of the wiring layer; and an element disposed between the terminal pad and the wiring layer.

17. An electronic device comprising: a semiconductor layer having a photoelectric conversion portion, one surface being a light incident surface and the other surface being an element formation surface; a wiring layer laminated on the element formation surface of the semiconductor layer; a terminal pad located on the wiring layer side of the element formation surface of the semiconductor layer and connected to the metal wiring of the wiring layer; and a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface, and comprising a photodetector which positions an element at the formation position of the pad opening before the pad opening is formed.

18. A method for manufacturing a photodetector, comprising: preparing a semiconductor chip having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface, and laminating a wiring layer on the element formation surface of the semiconductor layer; forming a terminal pad, the upper surface of which is exposed to the outside, within the semiconductor layer; and connecting the lower surface of the terminal pad to the metal wiring of the wiring layer by a via so that an element to be placed in the semiconductor layer is located between the lower surface of the terminal pad and the wiring layer.

19. A method for manufacturing a photodetector, comprising: preparing a semiconductor chip having a photoelectric conversion section, one surface of which is a light incident surface and the other surface of which is an element formation surface, and laminating a wiring layer on the element formation surface of a semiconductor layer; forming a terminal pad connected to the metal wiring of the wiring layer on the wiring layer side of the element formation surface of the semiconductor layer; and forming a pad opening that extends from the light incident surface of the semiconductor layer to the terminal pad and exposes the terminal pad from the light incident surface; and placing an element at a formation position of the pad opening before forming the pad opening.

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