Power supply circuit and electric apparatus

Abstract

The present invention provides, for example, a power supply circuit with improved conversion efficiency.　The power supply circuit has: a converter that has at least a switching element and converts an AC voltage into a DC voltage to output the DC voltage; and a controller that generates a control signal for adjusting the output power of the converter on the basis of a comparison result signal generated in accordance with a first comparison result. The power supply circuit is configured so as to apply a bias voltage to the comparison result signal in accordance with a second comparison result.

Description

Power supply circuits and electrical equipment

[0001] The present disclosure relates to a power supply circuit and an electric device.

[0002] In recent years, from the viewpoint of environmental considerations, there has been a demand for further improvement in the conversion efficiency of power supplies. The conversion efficiency of a power supply circuit generally reaches its maximum at a load that is intermediate with respect to the maximum load, and tends to decrease at load rates that are smaller than the maximum load. In actual usage environments of electrical devices, the actual power consumption may be smaller than the maximum power, resulting in a decrease in power supply efficiency. For example, power supply circuits described in Patent Documents 1 and 2 are known as methods for improving power supply efficiency under such light loads.

[0003] Japanese Patent Application Laid-Open No. 2017-17767

[0004] JP 2012-85523 A

[0005] In such fields, further improvement in the conversion efficiency of power supply circuits is desired.

[0006] An object of the present disclosure is to provide a power supply circuit with improved conversion efficiency and an electrical device using the power supply circuit.

[0007] The present disclosure relates to a power supply circuit including, for example, a converter having at least a switching element for converting an AC voltage into a DC voltage and outputting the DC voltage, and a controller for generating a control signal for adjusting the output power of the converter based on a comparison result signal generated in accordance with a first comparison result, wherein a bias voltage is applied to the comparison result signal in accordance with a second comparison result. The present disclosure may also relate to an electrical device including the above-described power supply circuit.

[0008] 1 is a diagram for explaining an example of the configuration of a power supply device according to an embodiment; FIG. 2 is a diagram for explaining an example of the configuration of a general power supply circuit; FIGS. A to D are diagrams for explaining an example of the operation of a general power supply circuit; FIG. 3 is a diagram for explaining an example of the configuration of a power supply circuit according to a first embodiment; FIGS. A to D are diagrams for explaining an example of the operation of the power supply circuit according to the first embodiment; FIGS. A and B are diagrams referred to when explaining points to be considered in the power supply circuit according to the first embodiment; FIG. 4 is a diagram for explaining an example of the configuration of a power supply circuit according to a second embodiment; FIGS. A and B are diagrams referred to when explaining points to be considered in the power supply circuit according to the second embodiment; FIGS. 5 is a diagram for explaining an example of the configuration of a power supply circuit according to a third embodiment; FIGS. A and B are diagrams for explaining effects to be obtained in the power supply circuit according to the third embodiment;

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The description will be made in the following order: <Problems to be considered in the present disclosure> <First embodiment> <Second embodiment> <Third embodiment> <Modification> Note that the embodiments described below are preferred specific examples of the present disclosure, and the contents of the present disclosure are not limited to these embodiments.

[0010] <Issues to be Considered in the Present Disclosure> First, to facilitate understanding of the present disclosure, issues to be considered in the present disclosure will be described. As described above, in the field of power supply circuits, there is a demand for improved conversion efficiency. In general, the efficiency of power supply circuits is poor in a range of load factors lower than the maximum load, and many power supply circuits exhibit maximum conversion efficiency in a range of load factors intermediate to or greater than the maximum load. This tendency is particularly pronounced in power supply circuits that use resonance phenomena to reduce switching loss.

[0011] However, there are many electrical devices, such as motors, audio equipment, and lighting equipment, whose average operating power is low compared to their instantaneous maximum power. The power supply circuits installed in such electrical devices are used for long periods of time at loads that are low compared to their maximum loads, resulting in poor conversion efficiency. To solve this problem, the technology described in Patent Document 1 above improves the efficiency of a power factor correction (PFC) circuit under light loads by performing burst operation.

[0012] To realize the method described in Patent Document 1, a standby signal is required to transition to standby mode, and seamless switching between burst operation and normal operation is not possible. Also, operation limited to phase angles with large voltages in alternating current (AC) voltages increases current distortion as with capacitor-input rectification, and harmonic currents increase, which may have adverse effects on other electrical equipment and power transmission systems (AC circuits).

[0013] Furthermore, the technology described in Patent Document 2 suppresses noise such as harmonics by detecting zero voltage of the AC voltage and repeating operation and stopping for each AC cycle. However, this method requires detecting the zero crossing of the AC voltage and detecting two values ​​of the output voltage, and also requires complex control such as logic for mode transitions.

[0014] Therefore, there is a need for a power supply circuit that can improve efficiency, for example, under light load conditions, while minimizing the increase in circuit size and eliminating the need for complex control.

[0015] 1 is a diagram illustrating a configuration example of an electric device (electric device 1) to which a power supply circuit according to the present disclosure can be applied. The electric device 1 includes, for example, an AC power supply 10, a full-wave rectifier circuit 20, a power supply circuit 30, and a load 40. The power supply circuit 30 includes a PFC circuit 50, which is an example of a converter.

[0016] The AC power supply 10 is, for example, a grid power supply. However, the AC power supply 10 is not limited to a grid power supply as long as it supplies an AC voltage. The AC power supply 10 outputs the AC voltage to the full-wave rectifier circuit 20.

[0017] The full-wave rectifier circuit 20 generates a rectified voltage by full-wave rectifying the AC voltage from the AC power supply 10. The full-wave rectifier circuit 20 supplies the generated rectified voltage to the power supply circuit 30.

[0018] The power supply circuit 30 converts the rectified voltage from the full-wave rectifier circuit 20 into a DC voltage. The power supply circuit 30 supplies the converted DC voltage to a load 40.

[0019] The PFC circuit 50 included in the power supply circuit 30 is configured by, for example, a boost circuit. However, the PFC circuit 50 is not limited to a boost circuit.

[0020] The load 40 is, for example, an integrated circuit (IC) that processes audio signals and video signals in a television set. That is, the electrical device 1 according to this embodiment is a television set. However, the load 40 is not limited to a circuit included in a television set. The load 40 may be a lighting device such as an LED (Light Emitting Diode), a motor drive circuit, an IC included in audio equipment, or the like.

[0021] [Regarding a General Power Supply Circuit] (Circuit Configuration Example) Before describing the power supply circuit according to this embodiment, a general power supply circuit will be described as a comparative example. Fig. 2 is a diagram for explaining a configuration example of a general power supply circuit (power supply circuit 30A).

[0022] The power supply circuit 30A includes a PFC circuit 50 and a control circuit 60 serving as a PFC controller.

[0023] The PFC circuit 50 includes at least a switching element Q1. Specifically, the PFC circuit 50 is configured as a boost circuit including, for example, a capacitor C1, an inductor L1, a diode D1, a capacitor C2, and the switching element Q1. However, as described above, the PFC circuit 50 is not limited to a boost circuit. An input voltage Vac and an input current Iac, which are AC voltages, are input to the PFC circuit 50 from the full-wave rectifier circuit 20 via an input terminal TA. The PFC circuit 50 also outputs an output voltage Vo and an output current Io, which are DC voltages. The output voltage Vo and the output current Io are output to the load 40 via an output terminal TB. That is, the PFC circuit 50 converts the AC voltage into a DC voltage and outputs it to the load 40. The input terminal TA and the output terminal TB are connected by a high-voltage side electrical circuit ECA, and a portion of the electrical circuit ECA is provided in the PFC circuit 50.

[0024] One end of capacitor C1 is connected to connection point PA, which is the point on the electrical circuit ECA where the input terminal TA is connected. The connection point refers to a predetermined position on the electrical circuit and does not necessarily have to be the midpoint of the connection. The other end of capacitor C1 is connected to a low-voltage electrical circuit (not shown). In addition, inductor L1 is connected between connection point PA and connection point PB on electrical circuit ECA. Specifically, one end of inductor L1 is connected to connection point PA, and the other end of inductor L1 is connected to connection point PB.

[0025] The anode of a diode D1 is connected to the connection point PB, in other words, the other end of the inductor L1. The cathode of the diode D1 is connected to the connection point PC. The connection point PC is a connection point on the electrical path ECA that is connected to the output terminal TB. One end of a capacitor C2 is connected to the connection point PC. The other end of the capacitor C2 is connected to a low-voltage electrical path (not shown).

[0026] As the switching element Q1, for example, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is applied. As the switching element Q1, a P-channel MOSFET, a silicon power device, a SiC power device, an IGBT (Insulated Gate Bipolar Transistor), or the like may also be applied. A gate signal generated by a control circuit 60 (specifically, a gate signal generating circuit 61 described later) is input to the gate terminal of the switching element Q1. The switching element Q1 is driven in response to the gate signal input to the gate terminal. The drain terminal of the switching element Q1 is connected to a connection point PB, and the source terminal is connected to a low-voltage side electrical path (not shown).

[0027] The control circuit 60, which is an example of a controller, is configured with, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). The control circuit 60 executes a program stored in a storage unit (not shown) or the like, using a RAM (Random Access Memory) or the like as a work area. The control circuit 60 may be realized by an integrated circuit, for example, an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). The control circuit 60 may be realized by a combination of hardware and software.

[0028] The control circuit 60 has three terminals (terminal TC, terminal TD, and terminal TE). The control circuit 60 also has a gate signal generation circuit 61, a first comparison reference voltage generation unit 62 that generates a first comparison reference voltage V1, a reference voltage generation unit 63 that generates a reference voltage Vstop, and an error amplifier U1. The reference voltage Vstop is used as an operation stop reference voltage when the control circuit 60 determines whether to stop outputting a control signal to the switching element Q1.

[0029] The inverting input terminal of the error amplifier U1 is connected to the terminal TC, and the non-inverting input terminal of the error amplifier U1 is connected to a first comparison reference voltage generator 62. An electric circuit ECB is connected to the output terminal of the error amplifier U1, and a terminal TD is connected to the electric circuit ECB. A gate signal generator 61 is connected to a node PD on the electric circuit ECB. The gate signal generator 61 is also connected to a reference voltage generator 63 and a terminal TE.

[0030] Resistors R1 and R2 are connected in series to the connection point PC. The output voltage Vo is resistively divided by the resistors R1 and R2. The output voltage Vo of the PFC circuit 50 is input to the inverting input terminal of the error amplifier U1. For example, a voltage obtained by dividing the output voltage Vo by the resistors R1 and R2 (hereinafter, also referred to as the divided value of the output voltage Vo or simply as the divided value) is input to the inverting input terminal of the error amplifier U1 via the terminal TC.

[0031] The error amplifier U1 obtains a first comparison result by comparing a divided value of the output voltage Vo input to its inverting input terminal with a first comparison reference voltage V1 input to its non-inverting input terminal, and operates in accordance with the first comparison result. For example, the error amplifier U1 generates an error voltage Verr (an example of a comparison result signal) corresponding to the difference between the divided value of the output voltage Vo input to its inverting input terminal and the first comparison reference voltage V1 input to its non-inverting input terminal. For example, the error amplifier U1 generates the error voltage Verr in the electric circuit ECB by inputting and outputting charge corresponding to an error current signal corresponding to the difference between the divided value of the output voltage Vo and the first comparison reference voltage V1 to the electric circuit ECB. Specifically, when the divided value of the output voltage Vo is lower than the first comparison reference voltage V1, the error amplifier U1 outputs a current corresponding to the error current signal to the electric circuit ECB so that the error voltage Verr increases. Furthermore, when the divided value of the output voltage Vo exceeds the first comparison reference voltage V1, the error amplifier U1 draws a current corresponding to the error current signal from the electrical path ECB toward the error amplifier U1 so that the error voltage Verr decreases. Note that, in this specification, "A exceeds B" may mean that A is greater than B or that A is equal to or greater than B. Conversely, "A is lower than B" may mean that A is less than B or that A is equal to or less than B.

[0032] The error voltage Verr generated by the error amplifier U1 is input to the gate signal generation circuit 61. The gate signal generation circuit 61 generates a gate signal (an example of a control signal) corresponding to the error voltage Verr. For example, the gate signal generation circuit 61 generates a gate signal such that the input current Iac increases (the output power of the PFC circuit 50 increases) as the error voltage Verr increases. Conversely, the gate signal generation circuit 61 generates a gate signal such that the input current Iac decreases (the output power of the PFC circuit 50 decreases) as the error voltage Verr decreases. The gate signal generated by the gate signal generation circuit 61 is input to the gate terminal of the switching element Q1. For example, by appropriately adjusting the duty of the PWM (Pulse Width Modulation) modulated gate signal, a gate signal capable of adjusting the magnitude of the input current Iac can be generated. Specifically, the gate signal generation circuit 61 generates a gate signal having a duty such that the on-time increases as the error voltage Verr increases.

[0033] The gate signal generating circuit 61 compares the error voltage Verr with the reference voltage Vstop, and if the error voltage Verr falls below the reference voltage Vstop, the gate signal generating circuit 61 stops operating. In this case, the gate signal generating circuit 61 stops outputting the gate signal to the switching element Q1. This turns off the switching element Q1, and the input current Iac becomes zero.

[0034] The electric circuit ECB is led out of the control circuit 60 via the terminal TD. A series circuit of a resistor R3 and a capacitor C3 is connected to the electric circuit ECB. Specifically, one end of the resistor R3 is connected to the electric circuit ECB, and the other end of the resistor R3 is connected to one end of the capacitor C3. The other end of the capacitor C3 is connected to a low-voltage electric circuit (not shown). Furthermore, a capacitor C4 is connected in parallel to the series circuit of the resistor R3 and the capacitor C3. One end of the capacitor C4 is connected to the electric circuit ECB, and the other end of the capacitor C4 is connected to the low-voltage electric circuit. The error voltage Verr is phase compensated by the resistor R3, the capacitor C3, and the capacitor C4.

[0035] (Operation Example) Next, an operation example of the power supply circuit 30A will be described with reference to Fig. 3. Fig. 3A shows fluctuations in the output current Io, Fig. 3B shows fluctuations in the output voltage Vo, Fig. 3C shows fluctuations in the error voltage Verr, and Fig. 3D shows fluctuations in the input current Iac.

[0036] Assume that the load 40 becomes heavier at time t1 from the steady state. At time t1, the output current Io increases. As the output current Io increases, the current required by the load 40 increases relative to the input current Iac of the PFC circuit 50, causing the output voltage Vo to decrease. As the output voltage Vo decreases, the divided voltage input to the inverting input terminal of the error amplifier U1 decreases and falls below the first comparison reference voltage V1. Because the divided voltage of the output voltage Vo is smaller than the first comparison reference voltage V1, the error amplifier U1 outputs an error current signal to the electrical circuit ECB. This charges capacitors C3 and C4, causing the error voltage Verr in the electrical circuit ECB to increase. When the error voltage Verr increases, the gate signal generation circuit 61 generates a gate signal to increase the input current Iac. The generated gate signal is input to the gate terminal of the switching element Q1. The switching element Q1 operates in response to the gate signal input to the gate terminal, thereby increasing the input current Iac.

[0037] The input current Iac increases, and at the next time t2, when the input current Iac becomes larger than the output current Io, the output voltage Vo increases.

[0038] As the output voltage Vo increases, the divided voltage value input to the inverting input terminal of the error amplifier U1 also increases. At time t3, when this divided value becomes greater than the first comparison reference voltage V1, the error amplifier U1 operates to draw in the error current signal. This causes capacitors C3 and C4 to discharge, and the error voltage Verr decreases. When the error voltage Verr decreases, the gate signal generation circuit 61 generates a gate signal to reduce the input current Iac. The generated gate signal is input to the gate terminal of the switching element Q1. The switching element Q1 operates in accordance with the gate signal input to the gate terminal, thereby reducing the input current Iac.

[0039] At time t4, the input and output currents of the PFC circuit 50 are balanced, and the waveforms of each part become constant.

[0040] Suppose that the load 40 becomes lighter at time t5. At time t5, the output current Io decreases. As the output current Io decreases, the current required by the load 40 decreases relative to the input current Iac of the PFC circuit 50, causing the output voltage Vo to increase. As the output voltage Vo increases, the divided voltage input to the inverting input terminal of the error amplifier U1 increases and exceeds the first comparison reference voltage V1. Because the divided voltage of the output voltage Vo is greater than the first comparison reference voltage V1, the error amplifier U1 draws in the error current signal on the electrical circuit ECB. This discharges capacitors C3 and C4, causing the error voltage Verr on the electrical circuit ECB to decrease. When the error voltage Verr decreases, the gate signal generation circuit 61 generates a gate signal to reduce the input current Iac. The generated gate signal is input to the gate terminal of the switching element Q1. The switching element Q1 operates in response to the gate signal input to the gate terminal, thereby reducing the input current Iac.

[0041] At time t6, when the error voltage Verr becomes equal to or lower than the reference voltage Vstop, the gate signal generating circuit 61 stops operating and stops outputting the gate signal. This turns off the switching element Q1, and the input current Iac becomes zero. Thereafter, the output current Io exceeds the input current Iac, and the output voltage Vo drops.

[0042] At time t7, the output voltage Vo decreases, and the divided voltage input to the inverting input terminal of the error amplifier U1 falls below the first comparison reference voltage V1. This causes the error amplifier U1 to output an error current signal, which charges the capacitors C3 and C4, causing the error voltage Verr to increase.

[0043] At time t8, when the error voltage Verr exceeds the reference voltage Vstop, the gate signal generation circuit 61 starts operating. That is, the gate signal generation circuit 61 generates a gate signal corresponding to the error voltage Verr and inputs the generated gate signal to the gate terminal of the switching element Q1. This turns on the switching element Q1, causing the input current Iac to flow and the output voltage Vo to rise.

[0044] At time t9, the output voltage Vo rises, and the divided voltage input to the inverting input terminal of the error amplifier U1 exceeds the first comparison reference voltage V1. The error amplifier U1 then draws in the error current signal on the electrical circuit ECB. This discharges capacitors C3 and C4, causing the error voltage Verr on the electrical circuit ECB to drop. When the error voltage Verr drops below the reference voltage Vstop, the gate signal generating circuit 61 stops operating and stops outputting gate signals. This turns off the switching element Q1, and the input current Iac becomes zero. The output current Io then exceeds the input current Iac, causing the output voltage Vo to drop.

[0045] At time t10, when the output voltage Vo decreases and the divided voltage input to the inverting input terminal of the error amplifier U1 falls below the first comparison reference voltage V1, the error amplifier U1 outputs an error current signal, which charges the capacitors C3 and C4 and increases the error voltage Verr.

[0046] At time t11, when the error voltage Verr exceeds the reference voltage Vstop, the gate signal generation circuit 61 starts operating. That is, the gate signal generation circuit 61 generates a gate signal corresponding to the error voltage Verr and inputs the generated gate signal to the gate terminal of the switching element Q1. This turns on the switching element Q1, causing the input current Iac to flow and the output voltage Vo to rise.

[0047] At time t12, the output voltage Vo rises, and the divided voltage input to the inverting input terminal of the error amplifier U1 exceeds the first comparison reference voltage V1. The error amplifier U1 then draws in the error current signal on the electrical circuit ECB. This discharges capacitors C3 and C4, causing the error voltage Verr on the electrical circuit ECB to decrease. When the error voltage Verr falls below the reference voltage Vstop, the gate signal generating circuit 61 stops operating and ceases outputting the gate signal. This turns off the switching element Q1, and the input current Iac becomes zero. The output current Io then exceeds the input current Iac, causing the output voltage Vo to gradually decrease. Similar operations are then repeated.

[0048] In such a general power supply circuit 30A, the use of a fixed reference voltage Vstop causes the switching element Q1 to repeatedly turn on and off without synchronizing with the AC phase under light load conditions, resulting in a problem of reduced efficiency. Furthermore, because the reference voltage Vstop is often a fixed value, the power supply circuit 30A does not actually transition to light load operation until the load is significantly lightened, which is a factor in reduced efficiency. The present disclosure provides a power supply circuit that improves these problems.

[0049] [Regarding the power supply circuit according to the first embodiment] (Circuit configuration example) Fig. 4 is a diagram showing a configuration example of the power supply circuit (power supply circuit 30B) according to the first embodiment. Note that the same or similar components as those in the general power supply circuit 30A described above are given the same reference numerals, and duplicated descriptions will be omitted as appropriate.

[0050] In addition to the components of the power supply circuit 30A, the power supply circuit 30B includes resistors R4, R5, R6, R7, a comparator U2, and a voltage generating unit 64 that generates a voltage V2.

[0051] An electric circuit ECB, which is led out of the control circuit 60 via terminal TD, is connected to the non-inverting input terminal of a comparator U2. An electric circuit ECC is led from the output terminal of the comparator U2, and the other end of a capacitor C3 is connected to a connection point PE of the electric circuit ECC. The other end of a capacitor C4 is connected to a connection point PF (e.g., the end of the electric circuit ECC) of the electric circuit ECC. A resistor R4 is connected to the electric circuit ECC. Specifically, one end of the resistor R4 is connected to the output terminal of the comparator U2, and the other end of the resistor R4 is connected to the connection point PE. A resistor R5 is connected in series with the capacitor C4 with respect to the connection point PF. Specifically, one end of the resistor R5 is connected to the connection point PF, in other words, the other end of the capacitor C4, and the other end of the resistor R5 is connected to a low-voltage electric circuit (not shown).

[0052] An electric circuit ECD is connected to the inverting input terminal of the comparator U2. A voltage generator 64 is connected to the electric circuit ECD. A resistor R6 is connected between the inverting input terminal of the comparator U2 and the voltage generator 64. Specifically, one end of the resistor R6 is connected to the voltage generator 64, and the other end of the resistor R6 is connected to the inverting input terminal of the comparator U2. A connection point PG is set between the output terminal of the comparator U2 and one end of the resistor R4, and a connection point PH is set between the other end of the resistor R6 and the inverting input terminal of the comparator U2. A resistor R7 is connected between the connection points PG and PH. Specifically, one end of the resistor R7 is connected to the connection point PH, and the other end of the resistor R7 is connected to the connection point PG.

[0053] The error voltage Verr is input to the non-inverting input terminal of the comparator U2. The second comparison reference voltage Vu2- is input to the inverting input terminal of the comparator U2. The comparator U2 obtains a second comparison result by comparing the error voltage Verr with the second comparison reference voltage Vu2- and operates based on the second comparison result. For example, when the error voltage Verr increases and reaches the second comparison reference voltage Vu2- (when the error voltage Verr exceeds the second comparison reference voltage Vu2-), the comparator U2 outputs a current to generate a bias voltage Vr5 across the resistor R5. This applies the bias voltage Vr5 to the error voltage Verr, causing the error voltage Verr to increase by the amount of the bias voltage Vr5. The resistance values ​​of the resistors R4 and R5 are set so that the increased error voltage Verr is greater than the reference voltage Vstop. Furthermore, for example, the comparator U2 stops outputting current when the error voltage Verr drops to the second comparison reference voltage Vu2- (when the error voltage Verr falls below the second comparison reference voltage Vu2-). This causes the error voltage Verr to drop by the bias voltage Vr5. The resistance values ​​of the resistors R4 and R5 are set so that the error voltage Verr after the drop is smaller than the reference voltage Vstop.

[0054] The second comparison reference voltage Vu2- input to the inverting input terminal of the comparator U2 is not a constant value of the voltage V2, but is configured to be variable according to the output voltage Vu2o of the comparator U2 by connecting a resistor R6 and connecting the output side of the comparator U2 using a resistor R7. It is possible to generate a second comparison reference voltage that has a different value with respect to the error voltage Verr according to the output voltage Vu2o of the comparator U2.

[0055] (Operation Example) Next, an operation example of the power supply circuit 30B will be described with reference to Fig. 5. Fig. 5A shows fluctuations in the output current Io, Fig. 5B shows fluctuations in the output voltage Vo, Fig. 5C shows fluctuations in the error voltage Verr, and Fig. 5D shows fluctuations in the input current Iac.

[0056] Assume that the load 40 becomes lighter at time ta. As the load 40 becomes lighter, the output current Io decreases. When the output current Io decreases, the current required by the load 40 becomes smaller relative to the input current Iac of the PFC circuit 50, causing the output voltage Vo to increase. When the output voltage Vo increases, the divided voltage value input to the inverting input terminal of the error amplifier U1 increases and exceeds the first comparison reference voltage V1. Because the divided voltage value of the output voltage Vo is greater than the first comparison reference voltage V1, the error amplifier U1 draws in the error current signal on the electrical path ECB. This reduces the error voltage Verr. When the error voltage Verr decreases, the gate signal generation circuit 61 generates a gate signal to reduce the input current Iac. The generated gate signal is input to the gate terminal of the switching element Q1. The switching element Q1 operates in accordance with the gate signal input to the gate terminal, thereby reducing the input current Iac.

[0057] The error voltage Verr decreases, and at time tb, when the error voltage Verr falls below the second comparison reference voltage Vu2- (the upper dashed line in FIG. 5C ), the output voltage Vu2o of the comparator U2 goes low. This causes the bias voltage Vr5, which is the voltage across resistor R5, to go to zero. Furthermore, as the output voltage Vu2o of the comparator U2 goes low, the second comparison reference voltage Vu2- goes to the voltage value shown by the lower dashed line in FIG. 5C . Because the bias voltage Vr5 has gone to zero, the error voltage Verr drops by the same amount as the bias voltage Vr5. As the error voltage Verr drops by the amount of the bias voltage Vr5, the error voltage Verr becomes smaller than the reference voltage Vstop. This causes the gate signal generation circuit 61 to stop operating, and the switching element Q1 to turn off. This causes the input current Iac to go to zero. Subsequently, when the output voltage Vo decreases and the divided voltage input to the inverting input terminal of the error amplifier U1 falls below the first comparison reference voltage V1, the error amplifier U1 outputs an error current signal, causing the error voltage Verr to increase.

[0058] At time tc, when the error voltage Verr exceeds the second comparison reference voltage Vu2- (the lower dashed line in FIG. 5C), the output voltage Vu2o of the comparator U2 goes high. Furthermore, as the output voltage Vu2o of the comparator U2 goes high, the second comparison reference voltage Vu2- becomes the voltage value indicated by the upper dashed line in FIG. 5C. This generates a bias voltage Vr5 across the resistor R5. At this time, the error voltage Verr also increases by the same voltage as the bias voltage Vr5. As a result, the error voltage Verr becomes larger than the reference voltage Vstop, and the gate signal generation circuit 61 begins operating. Because the error voltage Verr increases significantly by the amount of the bias voltage Vr5, the gate signal generation circuit 61 generates a gate signal for the switching element Q1 so that a large input current Iac flows. As the input current Iac increases, the output voltage Vo increases. When the output voltage Vo rises, the divided voltage input to the inverting input terminal of the error amplifier U1 increases and exceeds the first comparison reference voltage V1. Because the divided voltage of the output voltage Vo is greater than the first comparison reference voltage V1, the error amplifier U1 draws in the error current signal on the electrical path ECB. This causes the error voltage Verr to decrease.

[0059] At time td, the operations at times tb and tc are repeated.

[0060] Assume that the load 40 becomes heavy at time te. At time te, the output current Io increases. As the output current Io increases, the current required by the load 40 increases relative to the input current Iac of the PFC circuit 50, causing the output voltage Vo to decrease. As the output voltage Vo decreases, the divided voltage value input to the inverting input terminal of the error amplifier U1 decreases and falls below the first comparison reference voltage V1. Because the divided voltage value of the output voltage Vo is smaller than the first comparison reference voltage V1, the error amplifier U1 outputs an error current signal to the electrical circuit ECB. This causes the error voltage Verr to increase.

[0061] Then, at time tf, when the error voltage Verr exceeds the second comparison reference voltage Vu2- (the lower dashed line in FIG. 5C), the output voltage Vu2o of the comparator U2 goes high, causing a bias voltage Vr5 to be generated across the resistor R5. At this time, the error voltage Verr also rises by the same voltage as the bias voltage Vr5. As a result, the error voltage Verr becomes larger than the reference voltage Vstop, and the gate signal generation circuit 61 begins operating. Because the error voltage Verr rises significantly by the amount of the bias voltage Vr5, the gate signal generation circuit 61 generates a gate signal for the switching element Q1 so that a large input current Iac flows. As the input current Iac increases, the output voltage Vo increases.

[0062] When the output voltage Vo increases, the divided voltage value input to the inverting input terminal of the error amplifier U1 increases and exceeds the first comparison reference voltage V1. Because the divided voltage value of the output voltage Vo is greater than the first comparison reference voltage V1, the error amplifier U1 draws in the error current signal on the electrical path ECB. This causes the error voltage Verr to decrease. When the error voltage Verr decreases, the gate signal generation circuit 61 generates a gate signal to reduce the input current Iac. The generated gate signal is input to the gate terminal of the switching element Q1. The switching element Q1 operates in response to the gate signal input to the gate terminal, thereby reducing the input current Iac. When the error voltage Verr balances with the output current Io before it falls below the second comparison reference voltage Vu2- (the upper dash-dot line in FIG. 5C ), the error voltage Verr and the input current Iac stabilize.

[0063] [Advantages Obtained by the Present Embodiment] In the present embodiment, when the load factor is small, the bias voltage Vr5 is appropriately applied to repeat the operation at time td, i.e., operation at a large load factor and its halt. This allows the operation at a small load factor, which reduces efficiency, to be skipped, thereby improving the conversion efficiency of the power supply circuit 30B. Furthermore, while the PFC circuit 50 tends to generate large harmonic currents when the load factor is small, the present embodiment eliminates the operation at a small load factor, thereby minimizing harmonic currents. Furthermore, since the operation is not limited to the phase angle of the AC voltage where the voltage is large, current distortion and the generation of harmonic currents are suppressed. This eliminates the risk of adverse effects on other electrical devices and the power transmission system (AC power line). Furthermore, the above-described advantages can be achieved without complex control, as there is no need to detect zero-crossings of the AC voltage or binary detection of the output voltage. Furthermore, the second comparison reference voltage Vu2- for the error voltage Verr can be changed according to the output voltage Vu2o, which is the output of the comparator U2. For example, if the second comparison reference voltage Vu2- is set to a fixed value (e.g., the lower dashed line in FIG. 5C), control will not be performed until the error voltage Verr drops significantly, resulting in operation similar to that of a typical power supply circuit. However, in this embodiment, the second comparison reference voltage Vu2- relative to the error voltage Verr can be changed in accordance with the output voltage Vu2o, which is the output of the comparator U2, thereby avoiding the above-mentioned inconvenience.

[0064] Second Embodiment Next, a second embodiment will be described. In the description of the second embodiment, the same or similar components as those in the above description will be denoted by the same reference numerals, and duplicated descriptions will be omitted as appropriate. Furthermore, unless otherwise specified, the matters described in the first embodiment can be applied to the second embodiment.

[0065] Although the power supply circuit 30B according to the first embodiment can improve the conversion efficiency, there are some points that need to be considered, which will be first described with reference to FIGS. 6A and 6B.

[0066] 6A and 6B are enlarged views of the transition of the error voltage Verr and the input current Iac of the power supply circuit 30B from time tb to time tc, respectively.

[0067] When the error voltage Verr rises and reaches the second comparison reference voltage Vu2- (e.g., the lower dashed line in FIG. 6A), the output voltage Vu2o of the comparator U2 goes high, generating a bias voltage Vr5 across the resistor R5. At this time, the error voltage Verr also rises by the same amount as the bias voltage Vr5, increasing the input current Iac. The timing at which the error voltage Verr coincides with the second comparison reference voltage Vu2- is uncertain and may occur near a high instantaneous value of the AC voltage. In this case, as shown in FIG. 6B, the input current Iac rises sharply, potentially resulting in harmonic components and noise from the coil or other components. This embodiment aims to address this issue.

[0068] FIG. 7 is a diagram showing an example of the circuit configuration of a power supply circuit (power supply circuit 30C) according to the second embodiment. The power supply circuit 30C has a configuration in which the input voltage Vac is input to the second comparison reference voltage Vu2-. This allows the input voltage Vac to be superimposed on the second comparison reference voltage Vu2-. Note that the input voltage Vac may be a signal obtained by dividing the input voltage Vac. For example, the power supply circuit 30C further includes a resistor R8 in addition to the configuration of the power supply circuit 30B. One end of the resistor R8 is connected to a connection point PJ between the input terminal TA and the PFC circuit 50. The other end of the resistor R8 is connected to a connection point PH.

[0069] FIG. 8 is a diagram illustrating an example of the operation of the power supply circuit 30C at the same timing as FIG. 6 . In the first embodiment, the second comparison reference voltage Vu2− takes two values ​​depending on the state of the output voltage Vu2o of the comparator U2. In contrast, in this embodiment, the second comparison reference voltage Vu2− takes a value obtained by superimposing the input voltage Vac, which has a full-wave rectified waveform (a mountain-shaped waveform indicated by the dashed-dotted line in FIG. 8A ). Due to the nature of the PFC circuit 50, the response speed of the error voltage Verr is approximately in phase with one cycle of the input. Therefore, when the error voltage Verr increases, the timing at which the error voltage Verr coincides with the second comparison reference voltage Vu2− is limited to a period near a phase angle where the instantaneous value of the AC voltage is small. This eliminates the sudden increase in the input current Iac shown in FIG. 6B , thereby suppressing the generation of harmonic components and audible noise from coils and the like.

[0070] <Third Embodiment> Next, a third embodiment will be described. In the description of the third embodiment, the same or similar components as those in the above description will be denoted by the same reference numerals, and duplicated descriptions will be omitted as appropriate. Furthermore, unless otherwise specified, the matters described in the first and second embodiments can be applied to the third embodiment.

[0071] The power supply circuit 30C according to the second embodiment can improve conversion efficiency and further suppress the generation of harmonic components and the generation of acoustic noise from coils, etc. Although the generation of harmonic components and the generation of acoustic noise from coils, etc. can be suppressed, there are some points that need to be considered. These points will be first described with reference to FIGS. 9A and 9B.

[0072] 9A and 9B are enlarged views of the transition of the error voltage Verr and the input current Iac of the power supply circuit 30C from time ta to time tb, respectively.

[0073] When the error voltage Verr decreases and reaches the second comparison reference voltage Vu2-, the error voltage Verr decreases significantly by the amount of the applied bias voltage Vr5. The error voltage Verr becomes smaller than the reference voltage Vstop, and the gate signal generation circuit 61 stops operating. As a result, the input current Iac becomes zero.

[0074] The timing at which the error voltage Verr coincides with the second reference voltage for comparison Vu2- is not fixed, and may occur near a high instantaneous value of the AC voltage. In this case, the input current Iac may suddenly decrease, possibly resulting in the inclusion of harmonic components or the generation of noise from the coil, etc. This embodiment is an embodiment that improves this point.

[0075] 10 is a diagram showing an example configuration of a power supply circuit (power supply circuit 30D) according to the third embodiment. In this embodiment, compared to the power supply circuit 30C according to the second embodiment, an inverted signal of the input voltage Vac is added to the second comparison reference voltage Vu2-. This makes it possible to superimpose an inverted signal of the input voltage Vac (e.g., a signal obtained by dividing the input voltage Vac) on the second comparison reference voltage Vu2-.

[0076] In addition to the configuration of the power supply circuit 30C, the power supply circuit 30D further includes resistors R9, R10, R11, R12, R13, R14, and R15, and an operational amplifier U3. Resistor R9 is connected in series with resistor R8. Specifically, one end of resistor R9 is connected to the other end of resistor R8, and the other end of resistor R9 is connected to a low-voltage side electrical path (not shown). One end of resistor R10 is connected to a connection point PK between resistors R8 and R9. The other end of resistor R10 is connected to connection point PH. One end of resistor R11 is connected to connection point PK. The other end of resistor R11 is connected to the inverting input terminal of operational amplifier U3. An electrical path ECD is connected to the output terminal of operational amplifier U3. Resistor R12 is connected between connection point PL between resistor R11 and the inverting input terminal of operational amplifier U3 and connection point PM in the electrical path ECD. Specifically, one end of the resistor R12 is connected to the connection point PL, and the other end of the resistor R12 is connected to the connection point PM.

[0077] A resistor R13 is connected to the electrical path ECD. Specifically, one end of the resistor R13 is connected to the output terminal of the operational amplifier U3. The other end of the resistor R13 is connected to a connection point PN between the resistor R10 and the connection point PH.

[0078] Resistors R14 and R15 are connected in series to connection point PG. Specifically, one end of resistor R14 is connected to connection point PG, and the other end of resistor R14 is connected to one end of resistor R15. The other end of resistor R15 is connected to a low-voltage side electrical path (not shown). A connection point PQ between resistors R14 and R15 is connected to the non-inverting input terminal of operational amplifier U3, and a resistance-divided voltage value formed by resistors R14 and R15 is input to the non-inverting input terminal of operational amplifier U3.

[0079] An example of the operation of the power supply circuit 30D will now be described. A full-wave rectified waveform of the input voltage Vac is present at the connection point PK. By setting the resistor-divider value of resistors R8 and R9 smaller than the resistance value of resistor R10, a full-wave rectified waveform can be obtained that is substantially unaffected by the second comparison reference voltage Vu2-. This full-wave rectified waveform is inverted and amplified by an inverting amplifier circuit composed of resistors R12, R13, and operational amplifier U3, and the inverted and amplified full-wave rectified waveform is added to the second comparison reference voltage Vu2-. The magnitude of the inverted and amplified full-wave rectified waveform can be set by the ratio of resistors R10 and R13. For example, by making the resistance value of resistor R13 smaller than the resistance value of resistor R10, the magnitude of the inverted and amplified full-wave rectified waveform can be increased. This increases the influence of the inverted amplification, and allows a waveform obtained by inverting the full-wave rectified waveform to be superimposed on the second comparison reference voltage Vu2-.

[0080] The magnitude of the output of the operational amplifier U3 is determined by the voltage division value of resistors R14 and R15. That is, when the output voltage Vu2o of the comparator U2 is low, the output of the operational amplifier U3, which constitutes an inverting amplifier circuit, is reduced. Furthermore, when the output voltage Vu2o of the comparator U2 is high, the output of the operational amplifier U3 is increased. As a result, when the output voltage Vu2o is low, a full-wave rectified AC waveform is superimposed on the second comparison reference voltage Vu2-. When the output voltage Vu2o is high, a waveform obtained by inverting and amplifying the full-wave rectified AC waveform is superimposed on the second comparison reference voltage Vu2-. That is, as in the second embodiment, when the error voltage Verr increases, the full-wave rectified AC waveform can be superimposed on the second comparison reference voltage Vu2-. Furthermore, in this embodiment, when the error voltage Verr decreases, a waveform obtained by inverting and amplifying the full-wave rectified AC waveform can be superimposed on the second comparison reference voltage Vu2-.

[0081] In the second embodiment, the second comparison reference voltage Vu2- assumes a value in phase with the instantaneous value of the input voltage Vac, whereas in the present embodiment, the second comparison reference voltage Vu2- assumes a value obtained by superimposing an inverted value of the input voltage Vac. As a result, as shown in FIG. 11 , when the error voltage Verr decreases, the timing at which the error voltage Verr coincides with the second comparison reference voltage Vu2- is limited to a phase angle (near the peak of the inverted waveform) where the instantaneous value of the AC voltage is small. Therefore, the sudden drop in the input current Iac shown in FIG. 9B is eliminated, thereby suppressing the generation of harmonic components and noise from coils, etc.

[0082] <Modifications> Although the embodiments of the present disclosure have been specifically described above, the contents of the present disclosure are not limited to the above-described embodiments, and various modifications based on the technical ideas of the present disclosure are possible.

[0083] It goes without saying that the circuit configurations described in the above embodiments are merely examples. Although the circuit configurations described in each embodiment are preferred, the circuit configurations according to each embodiment can be modified as appropriate to achieve the functions described in each embodiment.

[0084] The configurations, methods, steps, shapes, materials, and values ​​described in the above-described embodiments are merely examples, and different configurations, methods, steps, shapes, materials, and values ​​may be used as needed. The above-described embodiments and modifications can be combined as appropriate.

[0085] The present disclosure may also adopt the following configurations. (1) A power supply circuit comprising: a converter having at least a switching element that converts an AC voltage into a DC voltage and outputs the DC voltage; and a controller that generates a control signal that adjusts the output power of the converter based on a comparison result signal generated in response to a first comparison result, wherein a bias voltage is applied to the comparison result signal in response to a second comparison result. (2) The power supply circuit according to (1), wherein the controller has an error amplifier that obtains the first comparison result by comparing the output voltage of the converter with a first comparison reference voltage. (3) The power supply circuit according to (2), wherein the error amplifier increases the voltage of the comparison result signal by outputting a current when the output voltage of the converter is lower than the first comparison reference voltage, and decreases the voltage of the comparison result signal by drawing a current when the output voltage of the converter is higher than the first comparison reference voltage. (4) The power supply circuit according to any one of (1) to (3), wherein the controller outputs the control signal to the switching element so that the output power of the converter increases as the comparison result signal increases, and outputs the control signal to the switching element so that the output power of the converter decreases as the comparison result signal decreases. (5) The power supply circuit according to (4), wherein the controller stops outputting the control signal when the comparison result signal falls below an operation stop reference voltage. (6) The power supply circuit according to any one of (1) to (5), wherein the switching element is configured by a MOSFET, and the controller outputs the control signal to a gate terminal of the MOSFET. (7) The power supply circuit according to (2), further comprising a comparator, wherein the comparator obtains the second comparison result by comparing the comparison result signal with a second comparison reference voltage. (8) The power supply circuit according to (7), wherein the comparator generates the bias voltage when the comparison result signal is greater than the second comparison reference voltage, and does not generate the bias voltage when the comparison result signal is smaller than the second comparison reference voltage.(9) The power supply circuit according to (8), wherein when the comparison result signal increases and reaches the second comparison reference voltage, the voltage of the comparison result signal increases by the voltage of the bias voltage, and when the comparison result signal decreases and reaches the second comparison reference voltage, the voltage of the comparison result signal decreases by the voltage of the bias voltage. (10) The power supply circuit according to any of (7) to (9), wherein a capacitor and a resistor are connected in series to a current path connected to the output terminal of the error amplifier, and wherein an output terminal of the comparator is connected to a connection point between the capacitor and the resistor. (11) The power supply circuit according to any of (7) to (10), wherein the second comparison reference voltage is configured to change according to the output of the comparator. (12) The power supply circuit according to any of (7) to (11), wherein the AC voltage is superimposed on the second comparison reference voltage. (13) The power supply circuit according to any one of (7) to (12), wherein the AC voltage is inverted and superimposed on the second reference voltage for comparison. (14) An electric device having the power supply circuit according to any one of (1) to (13).

[0086] 1... Electrical device 30, 30A, 30B, 30C, 30D... Power supply circuit 50... PFC circuit 60... Control circuit 61... Gate signal generating circuit U1... Error amplifier U2... Comparator U3... Operational amplifier Q1... Switching element

Claims

1. A power supply circuit comprising: a converter having at least a switching element for converting an AC voltage into a DC voltage and outputting the DC voltage; and a controller for generating a control signal for adjusting the output power of the converter based on a comparison result signal generated in response to a first comparison result; and configured such that a bias voltage is applied to the comparison result signal in response to a second comparison result.

2. The power supply circuit according to claim 1, wherein the controller has an error amplifier that obtains the first comparison result by comparing the output voltage of the converter with a first comparison reference voltage.

3. The power supply circuit of claim 2, wherein the error amplifier increases the voltage of the comparison result signal by outputting a current when the output voltage of the converter falls below the first comparison reference voltage, and decreases the voltage of the comparison result signal by drawing a current when the output voltage of the converter exceeds the first comparison reference voltage.

4. The power supply circuit of claim 1, wherein the controller outputs the control signal to the switching element such that the output power of the converter increases as the comparison result signal increases, and outputs the control signal to the switching element such that the output power of the converter decreases as the comparison result signal decreases.

5. The power supply circuit according to claim 4, wherein the controller stops outputting the control signal when the comparison result signal falls below an operation stop reference voltage.

6. The power supply circuit according to claim 1, wherein the switching element is configured by a MOSFET, and the controller outputs the control signal to a gate terminal of the MOSFET.

7. The power supply circuit according to claim 2, further comprising a comparator, the comparator obtaining the second comparison result by comparing the comparison result signal with a second comparison reference voltage.

8. The power supply circuit according to claim 7, wherein the comparator generates the bias voltage when the comparison result signal is greater than the second comparison reference voltage, and does not generate the bias voltage when the comparison result signal is smaller than the second comparison reference voltage.

9. The power supply circuit according to claim 8, wherein when the comparison result signal increases and reaches the second comparison reference voltage, the voltage of the comparison result signal rises by the voltage of a bias voltage, and when the comparison result signal decreases and reaches the second comparison reference voltage, the voltage of the comparison result signal drops by the voltage of the bias voltage.

10. The power supply circuit according to claim 7, wherein a capacitor and a resistor are connected in series to an electric path connected to the output terminal of the error amplifier, and the output terminal of the comparator is connected to a connection point between the capacitor and the resistor.

11. The power supply circuit according to claim 7, wherein the second comparison reference voltage is configured to change according to the output of the comparator.

12. The power supply circuit according to claim 7, wherein the AC voltage is superimposed on the second comparative reference voltage.

13. The power supply circuit according to claim 7, wherein the AC voltage is inverted and superimposed on the second comparative reference voltage.

14. An electric device having the power supply circuit of claim 1.

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