Computation device and data transfer method

Abstract

A computation device (10) configures an array of virtual PEs (12B) so that the rows and / or the columns are in reverse order in relation to an array of real PEs (12A), and continuously arranges data with respect to the real PEs (12A) and the virtual PEs (12B). Furthermore, the computation device (10) transfers the data in the order of the arrangement of the data by transferring data among the virtual PEs (12B) in a direction different from the data transfer among the real PEs (12A).

Description

Arithmetic device and data movement method CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Application No. 2023-154064, filed on September 21, 2023, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a computing device and a data movement method.

[0003] A computing device has been developed that is composed of a plurality of processors arranged in an array (two-dimensionally).

[0004] In such computing devices, there is a demand for improved data processing speed. For example, Patent Document 1 describes a computing device including a first plurality of processing cores arranged in an array and a second plurality of processing cores arranged in an array. A subset of the first plurality of processing cores included in this computing device is disposed between a data processing circuit and the second plurality of processing cores.

[0005] U.S. Pat. No. 1,086,574

[0006] FIG. 20 is a schematic diagram of a conventional arithmetic device 100 in which processors (Processing Elements, hereinafter referred to as "PEs") 102 are arranged in an array. Note that (0, 0) and the like written in each PE 102 indicate the coordinates of each PE 102, with x=0 representing the first column and being described below as column 0, and y=0 representing the first row and being described below as row 0. Reference numeral 104 denotes wiring for inputting and outputting data between PEs 102 and between PEs 102 and external memory 106. In the conventional arithmetic device 100, data is arranged in each PE 102 in order, for example, starting with the top-left PE 102 whose coordinates are (0, 0).

[0007] Here, when processing data items greater than the number of PEs 102, it is not possible to allocate all of the data items to the PEs 102. For example, if the width of the PEs 102 is 4 and processing is performed using data immediately to the right of data held in the rightmost PE 102 in column 3 (hereinafter referred to as "data adjacent to the edge"), the data adjacent to the edge must be transferred from the external memory 106 on the side of the PE 102 in column 0, which is the opposite edge. In such a data transfer, the distance traveled by the data adjacent to the edge is long, and processing takes time.

[0008] Furthermore, when placing required data in advance in PEs 102 rather than placing one piece of data in each PE 102, typically, the data immediately to the right of the right-most PE 102 is placed in the left-most PE 102 (x=0), and the data immediately to the right of that is placed in the PE 102 immediately to the right of the left-most PE 102 (x=1). In other words, if the arrangement of data before being placed in PEs 102 is represented by two-dimensional coordinates (X, Y), data to be placed in PEs 102 when there are four data arranged vertically and horizontally is placed at the PE 102 position (x, y) = (X remainder when dividing X by 4, Y remainder when dividing Y by 4). In this case, the data adjacent to the end needs to be transferred from the PE 102 at the opposite end, and the movement distance is long, which takes time for processing.

[0009] The present disclosure aims to provide a computing device and a data movement method that can efficiently process a larger amount of data than the number of processors arranged in line.

[0010] A computing device according to one aspect of the present disclosure is a computing device having a plurality of processors, in which the arrangement of virtual processors is set so that at least one of the rows and columns is in reverse order based on the arrangement of the real processors, data is arranged consecutively between the real processors and the virtual processors, and data is moved between the virtual processors in a direction different from the data movement between the real processors, thereby moving the data in the order in which the data is arranged.

[0011] In the arithmetic device of this configuration, the array of virtual processors is set so that at least one of the rows and columns is in reverse order relative to the array of real processors. Data is then sequentially allocated to the real processors and the virtual processors. The virtual processor is physically located at the same position as the real processor corresponding to the set array, and stores and moves data. Data set as a virtual processor is stored in a register provided in the corresponding processor at the same coordinates. In other words, of multiple consecutive data pieces, the remaining data after being allocated to the real processor is folded back and allocated to the virtual processor. Then, by moving the real processors and the virtual processors together in the same direction, data can be moved in the order of data allocation. In this case, the direction of movement of the virtual processor is physically different from that of the real processor.

[0012] In this configuration, data held in a register of a processor is stored in normal or reverse order when input from an external device. For example, if the arrangement of data before being allocated to a processor is represented by two-dimensional coordinates (X, Y), the (x, y) of the data to be allocated to a processor when there are four rows and four columns is as follows: If the quotient of X divided by 4 is even, x = "remainder when X is divided by 4," and if the quotient of X divided by 4 is odd, x = "3 - (remainder when X is divided by 4)." Furthermore, if the quotient of Y divided by 4 is even, y = "remainder when Y is divided by 4," and if the quotient of Y divided by 4 is odd, y = "3 - (remainder when Y is divided by 4)." The data represented by (X, Y) is then allocated to one processor located at the calculated (x, y).

[0013] As a result, data that could not be held in a real processor in the past is set in a virtual processor and moved from the virtual processor to the real processor, so that the real processor can input data over a shorter distance. Also, because data is moved from the virtual processor to the real processor, data processing can be continued without data input / output between external memory and the processor. Therefore, with this configuration, it is possible to efficiently process data that is greater than the number of processors lined up.

[0014] In the above-described arithmetic device, data to be moved from a register included in the real processor may be set in the corresponding virtual processor together with the real processor.

[0015] The above-described arithmetic device may further include a first wiring for transferring data between the real processors and a second wiring for transferring data between the virtual processors, the first wiring and the second wiring transferring the data in different directions. This allows data transfer between the real processors and the virtual processors to be performed in a single process. Alternatively, the second wiring may not be provided, and data may be transferred between the virtual processors in multiple steps using only the real processors and the first wiring, with data being transferred in different directions.

[0016] In the above-mentioned arithmetic device, in order to perform a convolution operation using a group of processors in which a plurality of the processors are arranged two-dimensionally, the virtual processors may be set to be arranged around the real processors, and data of interest may be set to the real processors and data surrounding the data of interest to the virtual processors. The data of interest is data at the center of the convolution operation and is also data surrounding the data of interest as viewed from other processors.

[0017] In the above-mentioned computing device, the real processor located at a corner of the processor group may have at least three movement circuits that move data between the real processor and three of the virtual processors, including in a diagonal direction, and the real processor located at a side of the processor group excluding the corner may have at least one movement circuit that moves data between the real processor and one of the virtual processors.

[0018] In the above-described arithmetic device, the real processor may include eight transfer circuits for transferring data between the real processor and the eight virtual processors, including those in the up, down, left, right and diagonal directions.

[0019] In the above-mentioned arithmetic device, when data is input to the real processor from an external memory, the real processor may move the data to the virtual processor, reverse the order of the data, and store the data in a register provided in the processor.

[0020] In the above-mentioned arithmetic device, data may be input from an external memory to the processors located at the ends and the processors located inside of the real processors arranged two-dimensionally, and the real processors may move the array of data input from the ends and the inside to the virtual processor in reverse order.

[0021] In the above-described computing device, the real processor and the virtual processor may be set as a continuous one-dimensional array, and one-dimensional data may be arranged continuously in the real processor and the virtual processor.

[0022] In the above-described arithmetic device, the processor may arrange the one-dimensional data in a forward or reverse order alternately for each row or column of the processors arranged two-dimensionally.

[0023] In the above-mentioned arithmetic device, the real processor and the virtual processor may divide the input data into a plurality of pieces of data each having a predetermined number of bits, and arrange the data, and move each piece of data divided by the predetermined number of bits.

[0024] In the above-described arithmetic device, the processor may arrange the divided data in a forward or reverse order with the bit positions alternately arranged for each of the two-dimensionally arranged processors.

[0025] A data movement method of one aspect of the present disclosure is a data movement method for a computing device having multiple processors, in which an arrangement of virtual processors is set so that at least one of the rows and columns is in reverse order based on the arrangement of the real processors, data is arranged consecutively in the real processors and the virtual processors, and data is moved between the virtual processors in a direction different from the data movement between the real processors, thereby moving the data in the order of the data arrangement.

[0026] According to the present disclosure, it is possible to efficiently process a larger amount of data than the number of processors arranged in line.

[0027] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which Fig. 1 is a schematic configuration diagram of a computing device according to an embodiment, Fig. 2 is a schematic diagram showing real PEs and virtual PEs according to an embodiment, Fig. 3 is a schematic diagram showing the order of data input to PEs according to an embodiment, Fig. 4 is a schematic diagram showing data movement in the computing device according to an embodiment, Fig. 5 is a schematic diagram showing data movement in the computing device according to an embodiment, Fig. 6 is a schematic diagram showing data movement in the computing device according to an embodiment, Fig. 7 is a schematic diagram showing the relationship between a target data group and a required data group when performing a convolution operation according to an embodiment, Fig. 8 is a schematic diagram showing the setting of a group of real PEs and a group of virtual PEs when performing a convolution operation according to an embodiment, Fig. 9 is a schematic diagram showing a case where a target data group is moved rightward in the convolution operation according to an embodiment, and Fig. 10 is a schematic diagram showing a case where a target data group is moved rightward and downward in the convolution operation according to an embodiment. 11 is a schematic diagram showing data input from an external memory to the arithmetic device of the embodiment, FIG. 12 is a schematic diagram showing data output from the arithmetic device of the embodiment to an external memory, FIG. 13 is a schematic diagram showing a form in which data is input from an end and an inside of a group of real PEs of the embodiment, FIG. 14 is a schematic diagram of real PEs and virtual PEs of the embodiment arranged one-dimensionally, FIG. 15 is a schematic diagram of one-dimensional data input to the arithmetic device of the embodiment, FIG. 16 is a schematic diagram showing data movement of one-dimensional data in the arithmetic device of the embodiment, FIG. 17 is a schematic diagram showing data movement of one-dimensional data in the arithmetic device of the embodiment, FIG. 18 is a schematic diagram showing data movement of one-dimensional data in the arithmetic device of the embodiment, FIG. 19 is a schematic diagram showing data movement involving SIMD processing of the embodiment, and FIG. 20 is a schematic diagram of a conventional arithmetic device.

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the embodiments described below are examples of how the present disclosure may be implemented, and the present disclosure is not limited to the specific configurations described below. When implementing the present disclosure, specific configurations according to the embodiments may be appropriately adopted.

[0029] FIG. 1 is a schematic diagram of a computing device 10 according to this embodiment.

[0030] The arithmetic device 10 is configured with a plurality of PEs (Processing Elements) 12. Note that, in the example of Fig. 1, a total of 16 PEs 12 are arranged two-dimensionally in four rows and four columns, but the arithmetic device 10 may include any number of PEs 12 as long as they are arranged in a plurality of dimensions. Furthermore, the plurality of PEs 12 may not only be arranged two-dimensionally (in an array), but may also be arranged in a multi-dimensional manner of three or more dimensions, as will be described later.

[0031] The PE 12 of this embodiment includes an arithmetic circuit and a register.

[0032] The arithmetic circuits perform various arithmetic operations, such as ==, !=, >, >=, <, <=, >>, <<, or, and, min, max, clip, add, sub, mul, div, mod, and macc. The arithmetic circuit that performs the arithmetic operation can be selected appropriately by the arithmetic device 10. In the arithmetic device 10 of this embodiment, one PE 12 may include multiple arithmetic circuits, and one PE 12 may select multiple different arithmetic operations or multiple identical arithmetic operations from among multiple prepared arithmetic operations, and perform the arithmetic operations simultaneously. Furthermore, by each PE 12 performing a different arithmetic operation, the arithmetic device 10 may perform multiple different arithmetic operations simultaneously.

[0033] A register is a storage unit that holds (stores) data. For example, an arithmetic circuit performs arithmetic processing on the data held in the register, and the register holds the arithmetic result. Note that the PE 12 may include multiple registers.

[0034] The arithmetic device 10 is capable of various processes such as data movement and calculation for each PE 12. However, if settings are made for each PE 12 by a program, the amount of programming increases.

[0035] Therefore, the operation for executing the required function of the arithmetic device 10 may be set in advance or by data for each PE 12, and different operations may be performed for each PE 12 according to the requirements of the function. Note that this data is setting data input to the PE 12 and is different from data that moves between PEs 12. This eliminates the need to set the operation for each PE 12 by program, and reduces the amount of programming required for the arithmetic device 10 to function.

[0036] Each PE 12 also includes a transfer circuit for transferring data to another adjacent PE 12. Data transfer settings such as the direction and timing at which the transfer circuit transfers data to another PE 12 are also set in advance or by data.

[0037] The PE 12 acquires data from the external memory 16 via the wiring 14 and stores it in a register. The PEs 12 are electrically connected by wiring 14A and 14B for data movement between adjacent PEs 12. Even if the wiring 14 between PEs 12 is not shown in other figures, the PEs 12 and the external memory 16, and adjacent PEs 12 are connected by the wiring 14. In this embodiment, data movement is a concept that also includes copying of data. The wiring 14A and 14B will be described in detail later.

[0038] Here, the arithmetic device 10 of this embodiment will be described in detail with reference to FIG. 2. In FIG. 2, x represents a column coordinate (column number), and y represents a row coordinate (row number). In the arithmetic device 10 of this embodiment, as shown in FIG. 2, the arrangement of the virtual PEs 12 is set so that the columns are in reverse order with respect to the arrangement of the real PEs 12. In the following description, the real PEs 12 are also referred to as real PEs 12A, and a group of real PEs 12A is referred to as a real PE group 20A. The virtual PEs 12 are also referred to as virtual PEs 12B, and a group of virtual PEs 12B is referred to as a virtual PE group 20B. That is, in the example of FIG. 2, a virtual PE group 20B is set adjacent to the real PE group 20A, with the columns in reverse order.

[0039] The real PE 12A is the same as the PE 12 shown in FIG. 1 , and its arithmetic circuit performs various operations on input data. On the other hand, the virtual PE 12B is a PE 12 that does not actually exist, and therefore does not perform any operations. The real PE 12A and the virtual PE 12B at the same coordinates (row and column numbers) are in a corresponding relationship. That is, the virtual PE 12B is physically located at the same position as the real PE 12A corresponding to the set array, and holds and moves data. The data set in the virtual PE 12B is held in a register of the corresponding PE 12 at the same coordinates.

[0040] The data to be moved from the register provided in the PE 12 is set in the real PE 12A and the corresponding virtual PE 12B. At this time, a circuit may be provided that can set data in the real PE 12A and the corresponding virtual PE 12B at the same time.

[0041] Specifically, when a plurality of data items are held in the registers of the PE 12 and a group of data items of interest is to be processed, the data items of interest are set in the shift circuit of the real PE 12A. Then, the peripheral data items are set (copied) from the registers to the shift circuit of the virtual PE 12B at once, so that the data items can be shifted at once. As a result, even if the group of data items of interest changes to the group of data one item to the right, the same processing can be performed on a different group of data by setting (copying) the data from the register. In other words, the data is not stored in the virtual PE 12B from the beginning.

[0042] Note that data held in the registers of the PE 12 of this embodiment is held in normal or reverse order when input from the outside. For example, if the arrangement of data before being allocated to the PE 12 is represented by two-dimensional coordinates (X, Y), the (x, y) of the data to be allocated to the PE 12 when four pieces are arranged vertically and horizontally is as follows: If the quotient of X divided by 4 is even, x = "remainder when X is divided by 4", and if the quotient of X divided by 4 is odd, x = "3 - (remainder when X is divided by 4)". Furthermore, if the quotient of Y divided by 4 is even, y = "remainder when Y is divided by 4", and if the quotient of Y divided by 4 is odd, y = "3 - (remainder when Y is divided by 4)". Then, the data represented by (X, Y) is allocated to one PE 12 located at the calculated (x, y).

[0043] 3 shows the order of data input from the external memory 16 to each PE 12. The x and y coordinates in Fig. 3 correspond to the columns and rows of the PE 12. As shown in Fig. 3, the x and y coordinates alternate between forward and reverse order, such as "0" to "3", "3" to "0", and "0" to "3", and correspondingly, the data is input to the PE 12 row by row (two-dimensionally).

[0044] The state in which the data shown in Fig. 3 is allocated to the real PE 12A and the virtual PE 12B is the numerical values ​​in the real PE 12A and the virtual PE 12B in Fig. 2. As shown in Fig. 2, in the arithmetic device 10 of this embodiment, data is allocated consecutively for each row in the real PE 12A and the virtual PE 12B.

[0045] 2 and 3, the real PE 12A from (0,0) to (3,0) sets data of "00" to "03", and the virtual PE 12B from (3,0) to (0,0) in the reverse order sets data of "04" to "07". That is, the PE 12 turns the continuous data at the end of the string, sets the data before the turn as the data of the real PE 12A, and sets the data after the turn as the data of the virtual PE 12B.

[0046] In this way, the arithmetic device 10 of this embodiment allocates data consecutively to the real PE 12A and the virtual PE 12B. The arithmetic device 10 then moves data between the virtual PEs 12B in a direction different from the data movement between the real PEs 12A, thereby moving the data in the data arrangement order. Then, by moving the real PE 12A and the virtual PE 12B together in the same direction, it becomes possible to move the data in the data arrangement order. In this case, the movement direction of the virtual PE 12B is physically different from that of the real PE 12A.

[0047] 4 to 6 are schematic diagrams showing data movement in the arithmetic device 10 of this embodiment. FIG. 4 shows a state after one data item has been moved to the left from the data arrangement state of FIG. 2, and a state after two data items have been moved. Data movement is performed simultaneously in one direction in the data arrangement order in all PEs 12. Note that while data simultaneously moves from (3,0) to (0,0) in the real PE 12A, data simultaneously moves from (0,0) to (3,0) in the virtual PE 12B. That is, data moves in the virtual PE 12B in the opposite direction to the arrangement order in the real PE 12A.

[0048] For this reason, the arithmetic device 10 of this embodiment includes wiring 14A and 14B between the PEs 12. The wiring 14A is a wiring 14 for moving data between real PEs 12A. The wiring 14B is a wiring 14 for moving data between virtual PEs 12B. The wiring 14A and the wiring 14B move data in different directions (opposite directions). By moving data using the wiring 14A and 14B in this manner, data movement between real PEs 12A and data movement between virtual PEs 12B can be performed simultaneously. Note that the arithmetic device 10 of this embodiment does not include the wiring 14B, and data movement between virtual PEs 12B may also be performed using only the wiring 14A, with data being moved in different directions in multiple steps.

[0049] In order to move data between real PEs 12A and between virtual PEs 12B in different directions, the PE 12 includes a move circuit used to move data between real PEs 12A and a move circuit used to move data between virtual PEs 12B. These move circuits may not only enable data movement between real PEs 12A or virtual PEs 12B adjacent to each other above, below, left, or right, but also between real PEs 12A or virtual PEs 12B adjacent to each other in diagonal directions.

[0050] Furthermore, the data to be set in the virtual PE 12B in column 3 is actually held in a register of the PE 12 in column 3. Therefore, data movement from the virtual PE 12B in column 3, which is at the end of the column, to the real PE 12A in column 3 is performed within the real PE 12A. Therefore, the PE 12 located at the end of the column is provided with a movement circuit for moving data within itself.

[0051] Here, for example, when the real PE 12A of column 3 performs an arithmetic process by referring to data "04," "14," "24," and "34" adjacent to the data it holds, conventionally, the real PE 12A of column 3 would acquire these pieces of data from the external memory 16 each time. In such a case, the real PE 12A of column 3 would need to acquire the data from the external memory 16 via the real PEs 12A of columns 0 to 2, which takes time to acquire the data. Also, referring to FIG. 20 , when necessary data is allocated to the PEs 102 in advance rather than allocating one piece of data to the PE 102, typically, the data adjacent to the right of the rightmost PE 102 is allocated to the leftmost PE 102 (x=0), and the data adjacent to that is allocated to the PE 102 immediately to the right of the leftmost PE 102 (x=1). In other words, if the arrangement of data before being placed in PE 102 is expressed as two-dimensional coordinates (X, Y), when there are four PEs arranged vertically and horizontally, the data to be placed in PE 102 is placed in PE 102 where (x, y) = (remainder when X is divided by 4, remainder when Y is divided by 4). In this case, data next to the edge needs to be transferred from PE 102 on the opposite edge, and the movement distance is long, which takes time for processing.

[0052] In contrast to this, in this embodiment, as shown in FIG. 4, the real PE 12A in column 3 acquires data from the virtual PE 12B in column 3 adjacent thereto, so the data acquisition time is shorter than in the conventional case.

[0053] Furthermore, after one data item is moved, the data is moved to the left, and data items "08", "18", "28", and "38" are newly allocated to the virtual PE 12B of column 0 in accordance with the data arrangement order shown in Fig. 3. Furthermore, after two data items are moved, the virtual PE 12B of column 0 becomes empty without holding any data.

[0054] 5, the data is moved to the left, and data "09", "19", "29", and "39" are newly allocated to the virtual PE 12B of column 1 in accordance with the data arrangement order shown in FIG. 3. Meanwhile, the virtual PE 12B of column 0 becomes empty without holding any data. Furthermore, after moving four positions, as the data is moved to the left, the virtual PEs 12B of column 0 and 1 become empty without holding any data.

[0055] Although not shown in the figure, after moving five positions, the data moves leftward and data "0a", "1a", "2a", and "3a" are newly allocated to the virtual PE 12B in column 2. On the other hand, the virtual PEs 12B in columns 0 and 1 become empty without holding any data. Furthermore, after moving six positions, as the data moves leftward, the virtual PEs 12B in columns 0 to 2 become empty without holding any data.

[0056] After seven shifts as shown in FIG. 6, the data is shifted to the left, and data "0b", "1b", "2b", and "3b" are newly allocated to the virtual PE 12B in the third column.

[0057] After moving eight positions, the data moves leftward, and data "0f" to "0c", "1f" to "1c", "2f" to "2c", and "3f" to "3c" are arranged in the virtual PE 12B of columns 3 to 0 in accordance with the data arrangement order shown in Fig. 3. After this, the data continues to move leftward in the same manner as above, but no new data is arranged.

[0058] As described above, in the arithmetic device 10 of this embodiment, the arrangement of the virtual PE 12B is set so that at least one of the rows and columns is in reverse order with respect to the arrangement of the real PE 12A. Then, in the arithmetic device 10, data is consecutively allocated to the real PE 12A and the virtual PE 12B. The data set as the virtual PE 12B is held in a register provided in the PE 12 corresponding to the virtual PE 12B. That is, of the consecutive multiple pieces of data, the remaining data after being allocated to the real PE 12A is folded back and allocated to the virtual PE 12B. Then, by moving data between the virtual PEs 12B in a direction different from the data movement between the real PEs 12A, it is possible to move data in the order of data arrangement.

[0059] As a result, data that could not be held in the real PE 12A in the past is set in the virtual PE 12B and moved from the virtual PE 12B to the real PE 12A, so that the data can be input to the real PE 12A over a shorter movement distance. Also, because the data moves from the virtual PE 12B to the real PE 12A, continuous data processing is possible without performing data input / output between the external memory 16 and the PE 12. Therefore, the arithmetic device 10 of this embodiment can efficiently process data that is greater than the number of PEs 12 arranged side by side.

[0060] In this embodiment, the virtual PE group 20B is set in a column-reversed order, but this is not limiting, and as described above, it is sufficient that at least one of the rows and columns of the virtual PE group 20B is reversed. That is, the virtual PE group 20B may be set in a row-reversed order, or both the rows and columns may be reversed.

[0061] (Application to Convolution Operation) With reference to FIGS. 7 to 10, a case where the above embodiment is applied to a convolution operation will be described.

[0062] FIG. 7 is a schematic diagram showing the relationship between the data used in the convolution operation of this embodiment and the PEs 12. In the example of FIG. 7, the arithmetic device 10 includes 16 PEs 12 (four rows and four columns). The central data group, "44" to "47," "54" to "57," "64" to "67," and "74" to "77," is the data of interest that is the target of the convolution operation. The data of interest is the data at the center of the convolution operation and, from the perspective of the other PEs 12, is also the data surrounding the data of interest. In the data group surrounding the central data group, the data within the inner dashed dotted line is the data required for the 3×3 convolution operation, and the data within the outer dashed dotted line is the data required for the 5×5 convolution operation.

[0063] In the arithmetic device 10 of this embodiment, in order to perform a convolution operation using a group of PEs (a group of real PEs 20A) in which PEs 12 are arranged two-dimensionally, a virtual PE 12B is set to be arranged around a real PE 12A. Then, data of interest is set in the real PE 12A, and necessary data, which is data around the data of interest, is set in the virtual PE 12B.

[0064] FIG. 8 shows the settings of the real PE group 20A and the virtual PE group 20B in this embodiment. In the example of FIG. 8, the area within the dashed lines surrounding (0,0) to (0,3) and (0,0) to (3,0) is the real PE group 20A. The area surrounding the real PE group 20A is the virtual PE group 20B. Note that the virtual PE group 12B (virtual PEs 12B with six sides) within the dashed line adjacent to the real PE group 20A in one row and one column is set with data required for a 3×3 convolution operation. The virtual PE group 12B (virtual PEs 12B with eight sides) within the dashed line adjacent to the real PE group 20A in two rows and two columns is set with data required for a 5×5 convolution operation. Then, the PE 12 wraps around the data as described above, and allocates the data of the real PE 12A and the virtual PE 12B at the same coordinates.

[0065] 9 is a schematic diagram illustrating a case where a data group of interest is shifted to the right in the convolution calculation of this embodiment. In FIG. 9, the virtual PE 12B is represented by a dashed line, and the virtual PE 12B is illustrated so as to partially overlap the corresponding real PE 12A. The PE 12 holds data of the real PE 12A and the virtual PE 12B, which have the same coordinates. For example, the PE 12 at (0, 0) holds data "44" of the real PE 12A and data "43" of the virtual PE 12B.

[0066] In the first movement for moving the data group of interest to the right, the data held by the real PE 12A in each row is moved to the real PE 12A in the adjacent column to the right. Also, the data held by the virtual PE 12B in each row is moved to the real PE 12A in the adjacent column to the left. In this way, data movement between real PEs 12A and data movement between virtual PEs 12B are performed in opposite directions. Note that the data movement from the virtual PE 12B with column number 0 to the real PE 12A with column number 0 is actually data movement within the PE 12 with column number 0.

[0067] 8, all of the data movements described in Fig. 9 are from left to right. The second movement for moving the data group of interest to the right is similar to the first movement, in which data held by a real PE 12A in each row moves to a real PE 12A in the adjacent column to the right, and data moves from the virtual PE 12B in column 0 to the real PE 12A in column 0.

[0068] 10 is a schematic diagram illustrating a case where a data group of interest is moved to the right and downward (diagonally downward right) in the convolution calculation of this embodiment. In FIG. 10, the PE 12 holds data of a real PE 12A and a virtual PE 12B that are at the same coordinates. That is, the PE 12 holds data of the real PE 12A and data of the virtual PE 12B that overlaps the left side, the upper side, and the upper left side of the real PE 12A. For example, the PE 12 at (0,0) holds data "44" of the real PE 12A and data "33", "34", and "43" of the virtual PE 12B.

[0069] In the first movement for moving the data group of interest rightward and downward (diagonally downward to the right), the data held by the real PE 12A is moved to the real PE 12A diagonally downward to the right. Furthermore, data held by the virtual PE 12B to the left is moved to the real PEs 12A at (1,0), (2,0), and (3,0). Data held by the virtual PE 12B above is moved to the real PEs 12A at (0,1), (0,2), and (0,3).

[0070] Also, the data "33" of the virtual PE 12B at (0,0) is moved to the real PE 12A at (0,0).

[0071] The data "32" of the virtual PE 12B at (1,0) is moved to the virtual PE 12B at (0,0) on the left, and the data "42" of the virtual PE 12B at (1,0) is moved to the virtual PE 12B at (0,1) diagonally downward to the left.

[0072] The data "24" of the virtual PE 12B at (0,1) is moved to the virtual PE 12B at (1,0) located to the upper right, and the data "23" of the virtual PE 12B at (0,1) is moved to the virtual PE 12B at (0,0) located above.

[0073] The data "22" of the virtual PE12B at (1,1) is moved to the virtual PE12B at (0,0) located in the upper left, the data "25" of the virtual PE12B at (1,1) is moved to the virtual PE12B at (2,0) located in the upper right, and the data "52" of the virtual PE12B at (1,1) is moved to the virtual PE12B at (0,2) located in the lower left.

[0074] In this way, data between real PEs 12A moves in a diagonally downward right direction, while data between virtual PEs 12B moves in a direction different from the data movement between real PEs 12A. Note that, with reference to Fig. 8, all of the data movements described in Fig. 10 are data movements in a diagonally downward right direction.

[0075] The second move is similar to the first move, and the data held by the real PE 12A is moved to the real PE 12A diagonally to the lower right. Then, data held by the virtual PE 12B to the left is moved to the real PEs 12A at (1,0), (2,0), and (3,0). Data held by the virtual PE 12B above is moved to the real PEs 12A at (0,1), (0,2), and (0,3). Data is moved from the virtual PE 12B at (0,0) to the real PE 12A at (0,0).

[0076] As described above, the arithmetic device 10 of this embodiment is configured to place the virtual PE 12B around the real PE 12A in order to perform a convolution operation using the real PE group 20A. Then, data of interest is set in the real PE 12A, and necessary data, which is data surrounding the data of interest, is set in the virtual PE 12B. This eliminates the need to prepare a PE 12 for holding the necessary data in order to perform the convolution operation, and shortens the data movement path.

[0077] Furthermore, once the data movement direction between real PEs 12A is determined, the data movement direction between virtual PEs 12B is also determined, so the data movement setting between virtual PEs 12B may be determined in conjunction with the data movement setting between real PEs 12A.

[0078] Here, among the PEs 12 of this embodiment, a real PE 12A located at a corner of the real PE group 20A includes at least three move circuits that perform data movement between the real PE 12A and three virtual PEs 12B, including those located diagonally. Also, a real PE 12A located at a side of the real PE group 20A other than the corner includes at least one move circuit that performs data movement between the real PE 12A and one virtual PE 12B.

[0079] 8, for example, the real PE 12A (0,0) located in the upper left corner of the real PE group 20A moves data between it and the three virtual PEs 12B (0,0). Therefore, the real PE 12A (0,0) has at least three move circuits to move data between it and the three virtual PEs 12B (0,0). The same applies to the real PEs 12A (0,3) at the bottom left, (3,0) at the top right, and (3,3) at the bottom right.

[0080] Furthermore, the real PE 12A (0,1) located on the left side of the real PE group 20A (excluding the corners) moves data between itself and the one virtual PE 12B (0,1) located to the left. For this reason, the real PE 12A (0,1) has at least one move circuit for moving data between itself and the one virtual PE 12B (0,1). The same applies to the real PEs 12A (0,2) on the left, (1,0) and (2,0) above, (3,1) and (3,2) on the right, and (1,3) and (2,3) below.

[0081] Similarly, referring to the case of performing a 5x5 convolution operation in Figure 8, the real PE 12A located in the upper left corner of the real PE group 20A is not only (0,0), but also (1,0), (0,1), and (1,1), which are two PE 12 widths. Therefore, these real PEs 12A each have at least three move circuits to move data between them and the three virtual PEs 12B. The same applies to the real PEs 12A at the bottom left (0,2), (1,2), (0,3), and (1,3), the top right (2,0), (3,0), (2,1), and (3,1), and the bottom right (2,2), (3,2), (2,3), and (3,3).

[0082] Similarly to the corners, the sides of the actual PE group 20A, excluding the corners, have a width of two PEs 12. However, in the case of PEs 12 with a width of four, all PEs 12 correspond to the corners, and therefore no PEs 12 are included in the side portions.

[0083] Furthermore, when a large amount of peripheral data is required, such as in a 7x7 or 9x9 convolution operation, the number of virtual PEs 12B and shift circuits may be increased. In this case, the width of the PE 12 is increased to more than four.

[0084] On the other hand, in order to enable data movement between a larger number of virtual PEs 12B, the real PE 12A may be provided with eight movement circuits for moving data between eight virtual PEs 12B, including those in the up, down, left, right, and diagonal directions.

[0085] Furthermore, the shift circuit that moves data between the real PE 12A and the virtual PE 12B does not have to be provided in all real PEs 12A. The shift circuit may be provided only in real PEs 12A that have virtual PEs 12B at the same coordinates. In other words, real PEs 12A that do not have virtual PEs 12B at the same coordinates do not have a shift circuit for moving data between them and the virtual PE 12B. For example, when only the 3×3 convolution operation in FIG. 8 is performed, the central (1,1), (2,1), (1,2), and (2,2) correspond to real PEs 12A that do not have virtual PEs 12B.

[0086] (Data Input / Output Between External Memory and PE) Hereinafter, data input / output between the external memory 16 and the PE 12 will be described.

[0087] In this embodiment, when data is input from external memory 16 to real PE12A (PE12), the arithmetic device 10 moves the data from real PE12A to virtual PE12B, reversing the arrangement, and stores the data in a register provided in PE12.

[0088] FIG. 11 is a schematic diagram showing data input from the external memory 16 to the arithmetic device 10 according to this embodiment. In FIG. 11 , the PE 12 within the dashed line is the real PE 12A, and the PE 12 within the dashed line is the virtual PE 12B. The virtual PE group 20B1 receives data from the real PE 12A, causing the rows (vertical direction in FIG. 11 ) to be reversed, and the data is stored in a register provided in the PE 12. The virtual PE group 20B2 receives data from the real PE 12A, causing the columns (horizontal direction in FIG. 11 ) to be reversed, and the data is stored in a register provided in the PE 12. That is, the virtual PE 12B performs a process of folding back the data input from the external memory 16, stores the unfolded data in a register provided in the PE 12, and also stores the folded data in a register provided in the PE 12. Furthermore, when reversing the order of data in both rows and columns, the data is first moved to the virtual PE group 20B1, then moved to the real PE 12A at the same coordinates, and then moved to the virtual PE group 20B2.

[0089] 11 , as an example, data (data group) is input from the external memory 16 to the real PE 12A (PE 12) in row 3, and each real PE 12A stores the data in normal order. Then, the real PE 12A moves data of the input data for which the rows are to be reversed to the virtual PE group 20B1, thereby reversing the row order and storing the data in a register provided in the PE 12. Furthermore, the real PE 12A moves data of the input data for which the columns are to be reversed to the virtual PE group 20B2, thereby reversing the column order and storing the data in a register provided in the PE 12.

[0090] As an example, after the first data group is input to the real PE 12A from the external memory 16, when the second data group is being input, the real PE 12A may move the first input data group to the virtual PE 12B. In this way, the real PE 12A may simultaneously perform the input of the data groups and the process of reversing the order of the data groups.

[0091] 11, the register provided in the PE 12 holds data in which the rows are reversed or data in which the columns are reversed, but the same applies when the virtual PE 12B holds data in which both the rows and columns are reversed. Also, although the external memory 16 is arranged at the bottom, it may be arranged at the top, left, or right, and different data may be input from all directions at the same time.

[0092] FIG. 12 is a schematic diagram showing data output from the arithmetic unit 10 to the external memory 16 according to this embodiment.

[0093] The data output process from the arithmetic unit 10 to the external memory 16 is the reverse of the data input process described above. That is, data is set from a register provided in the PE 12 to the virtual PE 12B, and the data is moved from the virtual PE 12B to the real PE 12A to reverse the data arrangement, thereby restoring the data arrangement to normal order. The real PE 12A then outputs the data, which has been restored to normal order, to the external memory 16. Note that the real PE 12A may perform the process of restoring the data to normal order by moving data from the virtual PE 12B while outputting the data to the external memory 16. Furthermore, although the external memory 16 is arranged above, it may also be located below, to the left, or to the right, and different data may also be output in all directions at the same time.

[0094] 13 is a schematic diagram showing a form in which data is input from the end and the inside of the real PE group 20A. As shown in Fig. 13, among the real PEs 12A arranged two-dimensionally, data may be input from the intermediate external memory 18 to the real PEs 12A located at the end and the real PEs 12A located at the inside, and the real PEs 12A may move the data input from the end and the inside to the virtual PE 12B, thereby reversing the data arrangement.

[0095] 13, the real PE 12A is virtually divided into four real PE groups 20A1 to 20A4, and the number of real PEs 12A included in each of the virtually divided real PE groups 20A1 to 20A4 is the same.

[0096] 13 , data corresponding to the real PE group 20A1 is input from the intermediate external memory 18A to the real PEs 12A at (0,1) and (1,1). Data corresponding to the real PE group 20A2 is input from the intermediate external memory 18B to the real PEs 12A at (2,1) and (3,1). Data corresponding to the real PE group 20A3 is input from the intermediate external memory 18C to the real PEs 12A at (0,3) and (1,3). Data corresponding to the real PE group 20A4 is input from the intermediate external memory 18D to the real PEs 12A at (2,3) and (3,3). Then, in the real PE groups 20A1 to 22A4, the input data groups are moved to the corresponding virtual PE groups 20B1 and 20B2, thereby reversing the data order.

[0097] Here, when the rows of data are reversed, the data moved to the virtual PE 12B of row 0 is the data that was input to the real PE 12A of row 3 before the reversal, and the data moved to the virtual PE 12B of row 1 is the data that was input to the real PE 12A of row 2 before the reversal. Therefore, when the rows are in normal order, the intermediate external memories 18A, 18B input the data of row 0 and row 1 to be held in the real PE 12A, and when the rows are in reverse order, they input the data of row 2 and row 3 to the real PE 12A. Then, the real PE 12A reverses the row order by moving the data of row 2 and row 3 to the virtual PE 12B.

[0098] Furthermore, when the rows are to be arranged in forward order, the intermediate external memories 18C and 18D input the data of row numbers 2 and 3 to be held in the real PE 12A, and when the rows are to be arranged in reverse order, the intermediate external memories 18C and 18D input the data of row numbers 0 and 1 to the real PE 12A. Then, the real PE 12A reverses the row order by moving the data of row numbers 0 and 1 to the virtual PE 12B.

[0099] Similarly, in the case of columns, the intermediate external memories 18A, 18C input the data of column numbers 0 and 1 to be held in the real PE 12A when the columns are to be in normal order, and input the data of column numbers 2 and 3 to the real PE 12A when the columns are to be in reverse order. The real PE 12A then reverses the order of the columns by moving the data of column numbers 2 and 3 to the virtual PE 12B. Furthermore, the intermediate external memories 18B, 18D input the data of column numbers 2 and 3 to be held in the real PE 12A, and input the data of column numbers 0 and 1 to the real PE 12A when the columns are to be in reverse order. The real PE 12A then reverses the order of the columns by moving the data of column numbers 0 and 1 to the virtual PE 12B.

[0100] Note that instead of inputting data corresponding to the arrangement of the virtual PE 12B from the intermediate external memories 18A to 18D to the real PE 12A as described above, the data may be input from the intermediate external memories 18A to 18D to the real PE 12A, and then the real PE 12A may move the data to the virtual PE 12B, thereby reversing the order of the data, as shown in FIG. 11 . To achieve this, when reversing the rows, it is necessary to change row numbers 0 and 1 of the real PE 12A to row numbers 2 and 3, and row numbers 2 and 3 to row numbers 0 and 1. Therefore, in order to reverse the order simultaneously with the input, an additional shift circuit is required so that the shift can be performed simultaneously. The same can be done when reversing the columns.

[0101] When data is output from the real PE 12A to the intermediate external memories 18A to 18D, the reverse processing of the data input processing is performed, and the reversed order data is returned to the normal order and output.

[0102] 13, there are four intermediate external memories 18, but for example, the calculation device 10 may have more intermediate external memories 18 so that data can be input to the real PE 12A from two or more of them, and more data may be input and output simultaneously for each finer group of PEs 12. Furthermore, while the external memories 16 are arranged above and below, they may also be arranged above, below, left, or right, and different data may also be input and output simultaneously in all directions.

[0103] (Processing for One-Dimensional Data) Data input to the arithmetic device 10 of this embodiment may be one-dimensional continuous data (hereinafter referred to as "one-dimensional data"). Therefore, in the arithmetic device 10 of this embodiment, the real PE 12A and the virtual PE 12B are set as a continuous one-dimensional array, and the one-dimensional data is arranged continuously in the real PE 12A and the virtual PE 12B.

[0104] As shown in FIG. 14 , the arithmetic device 10 of this embodiment starts with the real PE 12A at (0,0) in the real PE group 20A. The real PE 12A at (3,0) and the real PE 12A at (3,1), which are at the ends of the column, perform row data movement, the real PE 12A at (0,1) and the real PE 12A at (0,2) on the opposite side perform row data movement, and the real PE 12A at (3,2) and the real PE 12A at (3,3) on the further opposite side perform row data movement, and the other real PEs 12A perform column data movement only. The virtual PE group 20B also performs similar data movement, enabling data movement between the real PE 12A at (0,3) and the virtual PE 12B. With this setting, the arithmetic device 10 of this embodiment arranges the real PEs 12A and the virtual PEs 12B in a continuous one-dimensional array.

[0105] 15 shows the arrangement order of data input from the external memory 16 to each PE 12. In FIG. 3, x represents the column number, and y represents the row number. Furthermore, "data" is an example of a value input to the PE 12, and is one-dimensional data consisting of multiple consecutive pieces of data. Note that FIG. 14 also shows a state in which the data shown in FIG. 15 is arranged in the real PE 12A and the virtual PE 12B.

[0106] 16 to 18 are schematic diagrams showing data movement in the arithmetic device 10 of the embodiment. FIG. 16 shows a state after one data item has been moved from the data arrangement state of FIG. 14 and a state after two data items have been moved. Data movement is performed in the order of consecutive data arrangement. Note that, in the arrangement order of the PEs 12, for example, data moves from (0, 3) to (0, 0) in the real PE 12A, while data moves from (0, 0) to (0, 3) in the virtual PE 12B. In other words, data moves in the virtual PE 12B in the opposite direction to the arrangement order of the real PE 12A.

[0107] Furthermore, after one data item has been moved, data "20" is newly allocated to the virtual PE 12B at (0, 0) along with the data movement. Furthermore, after two data items have been moved, the virtual PE 12B at (0, 0) becomes empty without holding any data.

[0108] 17, after three data movements, data "21" is newly allocated to the virtual PE 12B at (1,0) and the virtual PE 12B at (0,0) remains empty without holding any data. By repeating this data movement, after seven data movements, data "23" is newly added to the virtual PE 12B at (3,0) and the virtual PEs 12B at (0,1) to (0,2) become empty.

[0109] 18, data "2f" is newly added to the virtual PE 12B at (0, 3) along with the data movement, and the virtual PEs 12B other than (0, 3) become empty. After 32 data pieces are moved, data "30" to "3f" are newly added to the virtual PE 12B along with the data movement.

[0110] Note that the one-dimensional arrangement of the real PEs 12A and the virtual PEs 12B shown in Figure 14 and the like is an example and is not limited to this. In Figure 14 and the like, the real PEs 12A and the virtual PEs 12B are arranged one-dimensionally by arranging them horizontally and then changing the vertical arrangement when the horizontal arrangement is filled, but they may also be arranged one-dimensionally by arranging them vertically and then changing the horizontal arrangement when the vertical arrangement is filled. Furthermore, they may be arranged so that a real PE 12A other than the real PE 12A at (0,0) is at the head, such as the real PE 12A at (3,0).

[0111] As described above, in this embodiment, the one-dimensional data held by the PEs 12 is alternately arranged in forward or reverse order for each row of the two-dimensionally arranged PEs 12. This allows the arithmetic device 10 of this embodiment to move data arranged in multiple PEs 12 between the PEs 12 as one-dimensional data. Note that, although the example of FIG. 14 shows that the data is moved by column, when moving by row, the data held by the PEs 12 is alternately arranged in forward or reverse order for each column of the two-dimensionally arranged PEs 12.

[0112] Furthermore, in this embodiment in which the PEs 12 are arranged one-dimensionally, similar to the "data input / output between external memory and PEs" in the embodiment in which the PEs 12 are arranged two-dimensionally, when data is input, the data is input from the external memory 16 or the intermediate external memory 18 and moved to the virtual PE 12B in reverse order. When data is output, the reverse process of the data input process is performed, the reversed data is returned to normal order, and the data is output to the external memory 16 or the intermediate external memory 18.

[0113] (Application of SIMD Processing) In this embodiment, the real PE 12A and the virtual PE 12B divide input data into a plurality of data pieces each having a predetermined number of bits, arrange the data, and move each data piece divided by the predetermined number of bits.

[0114] In this embodiment, the PE 12 performs parallel processing using single instruction multiple data (SIMD) processing to simultaneously perform calculations and transfers on multiple pieces of data divided by a predetermined number of bits within one PE 12. In the following, data divided by a predetermined number of bits is also referred to as divided data.

[0115] In this embodiment, as an example, 128-bit data is input to the PE 12, and the PE 12 divides the data into 32-bit chunks and stores them in a register. That is, the PE 12 stores four 32-bit pieces of divided data in a register. The example of FIG. 19 shows a state in which the PEs 12 are set as a continuous one-dimensional array, and one PE 12 stores four pieces of divided data in order from the most significant 32 bits to the least significant 32 bits. The least significant 32 bits of the divided data of each PE 12 are arranged so as to be continuous with the most significant 32 bits of the divided data of another PE 12 adjacent to the right (the PE 12 with a larger column number).

[0116] 19, the divided data held by the PE 12 in row 0 moves leftward toward the PE 12 in (0,0). Therefore, the upper 32 bits of the divided data of the PE 12 to the right move to the position of the lower 32 bits of the divided data held by the PE 12 in row 0. Meanwhile, the divided data held by the PE 12 in row 1 moves rightward. Therefore, the lower 32 bits of the divided data of the PE 12 to the left move to the position of the upper 32 bits of the divided data held by the PE 12 in row 1. Note that the PE 12 is provided with a shift circuit for shifting the divided data within the PE 12.

[0117] To achieve the one-dimensional data movement described above, in the example of Fig. 19, the data arrangement in odd-numbered rows is reversed relative to the even-numbered rows. That is, the divided data is arranged in reverse order in each PE 12 in odd-numbered rows. In Fig. 19, for example, in the PE 12 in row 1, column 2 (2,1), the front data "14" is arranged in the lower 32 bits, and the rear data "17" is arranged in the upper 32 bits.

[0118] Furthermore, the PEs 12 at the ends of each row, except for the PE 12 at (0,0), are capable of moving data with the PE 12 in the row (above or below). Therefore, the lower 32 bits of the divided data of the PE 12 at (3,1) are moved to the position of the lower 32 bits of the divided data of the PE 12 at (3,0).

[0119] As described above, in this embodiment, the plurality of divided data held by the PEs 12 are alternately arranged in forward or reverse order for each row of the two-dimensionally arranged PEs 12. This allows the arithmetic device 10 of this embodiment to move the divided data arranged in the plurality of PEs 12 between the PEs 12 as one-dimensional data. Note that, in the example of FIG. 19 , the divided data is moved by column, but when moving by row, the plurality of divided data held by the PEs 12 are alternately arranged in forward or reverse order for each column of the two-dimensionally arranged PEs 12.

[0120] Furthermore, so that the same bit is transferred between different PEs 12, the bit positions of the multiple divided data held by the PEs 12 may be arranged alternately in normal or reverse order for each PE 12. In this case, when data is input from the outside, it is held in normal or reverse order, and when the data is output to the outside, it is returned to normal order and output, but the order may be reversed all at once by providing a switching circuit in the PE 12 that reverses the bit positions.

[0121] 19 shows the arrangement of a plurality of divided data items in the real PE 12A, but the arrangement of the divided data items in the virtual PE 12B is similar, and data items are arranged contiguously between the real PE 12A and the virtual PE 12B. The data movement described above is performed on the plurality of divided data items arranged in the real PE 12A and the virtual PE 12B.

[0122] 19 , each PE 12 may hold the divided data in a two-dimensional manner, for example, in two rows and two columns, instead of holding the divided data in one row and four columns. In this case, the divided data held two-dimensionally within the PE 12 is arranged alternately in forward or reverse order for each row or column. This allows the arithmetic device 10 of this embodiment to move the divided data arranged in multiple PEs 12 between the PEs 12 as one-dimensional data.

[0123] Furthermore, the number of rows and the number of columns of divided data within one PE 12 may be arbitrarily determined and moved according to the number of bits and the number of divisions of the data input to the PE 12. Furthermore, although the above description is for moving divided data one-dimensionally, to move divided data two-dimensionally, processing of divided data and processing of two-dimensional data movement may be combined.

[0124] Although the present disclosure has been described using the above-mentioned embodiments, the technical scope of the present disclosure is not limited to the scope described in the above-mentioned embodiments. Various modifications or improvements can be made to the above-mentioned embodiments without departing from the gist of the disclosure, and such modifications or improvements are also included in the technical scope of the present disclosure.

[0125] In the above embodiments, the data is arranged from left to right from the PE 12 at (0,0) to the PE 12 at (3,0), but the present disclosure is not limited to this. For example, the data may be arranged from top to bottom, or from right to left, or from bottom to top.

[0126] In order to perform data transfer at a higher speed, data transfer using the real PE 12A and the virtual PE 12B may be multiplexed.

[0127] Furthermore, instead of a two-dimensional array of PEs 12 that moves data only up, down, left, and right, data may be moved diagonally or in multiple dimensions, such as three or four dimensions. A multidimensional array of PEs 12 means that the PEs 12 are represented in a multidimensional coordinate system that includes two dimensions indicating the up, down, left, and right directions (X and Y directions) as well as other directions (such as the ZW direction). In a multidimensional array, PEs 12 can input and output data between adjacent PEs 12 in the X and Y directions, and can also input and output data between adjacent PEs 12 in other dimensions, such as the ZW direction. When PEs 12 are arranged in three or more dimensions, each PE 12 is connected to the PEs 12 in the X, Y, and ZW directions by wiring 14A and 14B.

[0128] Next, the features of the present invention will be described as follows.

[0129] (Aspect 1) An arithmetic device (10) comprising a plurality of processors (12), wherein an arrangement of virtual processors (12B) is set so that at least one of rows and columns is in reverse order with respect to the arrangement of the real processors (12A), and data is arranged consecutively in the real processors and the virtual processors, and the data is moved in the arrangement order of the data by moving data between the virtual processors in a direction different from the data movement between the real processors. (Aspect 2) The arithmetic device according to Aspect 1, wherein data to be moved from a register included in the processor is set in the corresponding virtual processor together with the real processor. (Aspect 3) The arithmetic device according to Aspect 1 or Aspect 2, comprising first wiring (14A) for moving data between the real processors and second wiring (14B) for moving data between the virtual processors, and wherein the first wiring and the second wiring move the data in different directions. (Aspect 4) The arithmetic device according to any one of Aspects 1 to 3, wherein the virtual processors are configured to be arranged around the real processors in order to perform a convolution operation using a processor group in which a plurality of the processors are arranged two-dimensionally, and wherein data of interest is set to the real processors and data surrounding the data of interest is set to the virtual processors. (Aspect 5) The arithmetic device according to Aspect 4, wherein the real processor located at a corner of the processor group comprises at least three shift circuits that perform data transfer between the real processors and three of the virtual processors, including in a diagonal direction, and the real processor located at a side of the processor group excluding the corner, comprises at least one shift circuit that performs data transfer between the real processors and one of the virtual processors. (Aspect 6) The arithmetic device according to Aspect 4, wherein the real processor comprises eight shift circuits that perform data transfer between the real processors and eight of the virtual processors, including in up, down, left, right, and diagonal directions. (Aspect 7) The arithmetic device according to any one of Aspects 1 to 6, wherein when data is input to the real processor from an external memory (16), the real processor moves the data to the virtual processor, reverses the order of the data, and a register included in the processor holds the data.(Aspect 8) The arithmetic device according to Aspect 7, wherein data is input from an external memory to an edge-located processor and an internal-located processor of the real processors arranged in a two-dimensional configuration, and the real processor reverses the order of the data input from the edge and the internal processors and moves the data to the virtual processor in reverse order. (Aspect 9) The arithmetic device according to any one of Aspects 1 to 8, wherein the real processors and the virtual processors are set as a contiguous one-dimensional array, and one-dimensional data is arranged contiguous in the real processors and the virtual processors. (Aspect 10) The arithmetic device according to Aspect 9, wherein the processor arranges the one-dimensional data alternately in forward order or reverse order for each row or column of the two-dimensionally arranged processors. (Aspect 11) The arithmetic device according to any one of Aspects 1 to 10, wherein the real processor and the virtual processor divide the input data into a plurality of data pieces every predetermined number of bits and arrange them, and move each of the data pieces divided by the predetermined number of bits. (Aspect 12) The arithmetic device according to Aspect 11, wherein the processor arranges the divided data in forward or reverse order with bit positions alternating for each of the processors arranged two-dimensionally. (Aspect 13) A data movement method for an arithmetic device having a plurality of processors, comprising: setting an arrangement of virtual processors so that at least one of rows and columns is in reverse order with respect to an arrangement of the real processors as a reference, arranging data consecutively in the real processors and the virtual processors, and moving the data between the virtual processors in a direction different from the data movement between the real processors, thereby moving the data in the arrangement order of the data.

Claims

1. A computing device (10) having a plurality of processors (12), wherein an arrangement of a virtual processor (12B) is set so that at least one of the rows and columns is in reverse order based on the arrangement of the real processors (12A), data is arranged consecutively in the real processors and the virtual processors, and data is moved between the virtual processors in a direction different from the data movement between the real processors, thereby moving the data in the order of the data arrangement.

2. The arithmetic device according to claim 1, further comprising: a register for transferring data from said real processor to said corresponding virtual processor.

3. The arithmetic device according to claim 1 or 2, further comprising a first wiring (14A) for moving data between the real processors and a second wiring (14B) for moving data between the virtual processors, wherein the first wiring and the second wiring move the data in different directions.

4. A computing device as claimed in claim 1 or claim 2, which is configured to arrange the virtual processors around the real processors in order to perform convolution operations using a group of processors in which a plurality of the processors are arranged two-dimensionally, and which sets data of interest in the real processors and sets data surrounding the data of interest in the virtual processors.

5. The computing device according to claim 4, wherein the real processor located at a corner of the processor group has at least three movement circuits for moving data between the real processor and three of the virtual processors including a diagonal direction, and the real processor located at a side excluding the corner of the processor group has at least one movement circuit for moving data between one of the virtual processors.

6. The arithmetic device according to claim 4, wherein the real processor comprises eight movement circuits for performing data movement between the real processor and the eight virtual processors including up, down, left, right and diagonal directions.

7. The arithmetic device according to claim 1 or 2, wherein when data is input to the real processor from an external memory (16), the real processor moves the data to the virtual processor and reverses the order of the data, and the data is held in a register provided in the processor.

8. The arithmetic device according to claim 7, wherein data is input from an external memory to the processors located at the ends and the processors located inside of the real processors arranged in a two-dimensional configuration, and the real processors reverse the order of the data input from the ends and the inside, and transfer the data to the virtual processor in reverse order.

9. The arithmetic device according to claim 1 or 2, wherein the real processor and the virtual processor are set as a continuous one-dimensional array, and one-dimensional data is arranged contiguously in the real processor and the virtual processor.

10. The arithmetic device according to claim 9, wherein the processor arranges the one-dimensional data in normal or reverse order alternately for each row or column of the processor arranged two-dimensionally.

11. The arithmetic device according to claim 1 or 2, wherein the real processor and the virtual processor divide input data into a plurality of pieces of data each having a predetermined number of bits, arrange the data, and move each piece of data divided by the predetermined number of bits.

12. The arithmetic device according to claim 11, wherein the processor arranges the divided data in a forward or reverse order such that bit positions alternate for each of the two-dimensionally arranged processors.

13. A data movement method for an arithmetic device having a plurality of processors, comprising: setting an arrangement of virtual processors so that at least one of the rows and columns is in reverse order based on the arrangement of the real processors; data is arranged consecutively in the real processors and the virtual processors; and data is moved between the virtual processors in a direction different from the data movement between the real processors, thereby moving the data in the data arrangement order.

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